[U-Boot] [PATCH v2 1/2] drivers/reset: support rockchip reset drivers
From: Elaine Zhang zhangqing@rock-chips.com
Create driver to support all Rockchip SoCs soft reset. Example of usage: i2c driver: ret = reset_get_by_name(dev, "i2c", &reset_ctl); if (ret) { error("reset_get_by_name() failed: %d\n", ret); }
reset_assert(&reset_ctl); udelay(50); reset_deassert(&reset_ctl);
i2c dts node: resets = <&cru SRST_P_I2C1>, <&cru SRST_I2C1>; reset-names = "p_i2c", "i2c";
Signed-off-by: Elaine Zhang zhangqing@rock-chips.com Signed-off-by: Kever Yang kever.yang@rock-chips.com ---
Changes in v2: - fix Kconfig more than 80 length - use MACRO for reset bits in one reg - use rkclr/set_reg for reg access - add rockchip_reset_bind() - use dev_read_addr_size() instead of fdtdec_
drivers/reset/Kconfig | 9 +++ drivers/reset/Makefile | 1 + drivers/reset/reset-rockchip.c | 133 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 143 insertions(+) create mode 100644 drivers/reset/reset-rockchip.c
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index ce46e27..97a78d7 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -74,4 +74,13 @@ config AST2500_RESET resets that are supported by watchdog. The main limitation though is that some reset signals, like I2C or MISC reset multiple devices.
+config RESET_ROCKCHIP + bool "Reset controller driver for Rockchip SoCs" + depends on DM_RESET && CLK + default y + help + Support for reset controller on rockchip SoC. The main limitation + though is that some reset signals, like I2C or MISC reset multiple + devices. + endmenu diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 252cefe..7d7e080 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -12,3 +12,4 @@ obj-$(CONFIG_TEGRA186_RESET) += tegra186-reset.o obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o obj-$(CONFIG_AST2500_RESET) += ast2500-reset.o +obj-$(CONFIG_RESET_ROCKCHIP) += reset-rockchip.o diff --git a/drivers/reset/reset-rockchip.c b/drivers/reset/reset-rockchip.c new file mode 100644 index 0000000..01047a2 --- /dev/null +++ b/drivers/reset/reset-rockchip.c @@ -0,0 +1,133 @@ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <dm.h> +#include <reset-uclass.h> +#include <linux/io.h> +#include <asm/arch/hardware.h> +#include <dm/lists.h> +/* + * Each reg has 16 bits reset signal for devices + * Note: Not including rk2818 and older SoCs + */ +#define ROCKCHIP_RESET_NUM_IN_REG 16 + +struct rockchip_reset_priv { + void __iomem *base; + /* Rockchip reset reg locate at cru controller */ + u32 reset_reg_offset; + /* Rockchip reset reg number */ + u32 reset_reg_num; +}; + +static int rockchip_reset_request(struct reset_ctl *reset_ctl) +{ + struct rockchip_reset_priv *priv = dev_get_priv(reset_ctl->dev); + + debug("%s(reset_ctl=%p) (dev=%p, id=%lu) (reg_num=%d)\n", __func__, + reset_ctl, reset_ctl->dev, reset_ctl->id, priv->reset_reg_num); + + if (reset_ctl->id / ROCKCHIP_RESET_NUM_IN_REG >= priv->reset_reg_num) + return -EINVAL; + + return 0; +} + +static int rockchip_reset_free(struct reset_ctl *reset_ctl) +{ + debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl, + reset_ctl->dev, reset_ctl->id); + + return 0; +} + +static int rockchip_reset_assert(struct reset_ctl *reset_ctl) +{ + struct rockchip_reset_priv *priv = dev_get_priv(reset_ctl->dev); + int bank = reset_ctl->id / ROCKCHIP_RESET_NUM_IN_REG; + int offset = reset_ctl->id % ROCKCHIP_RESET_NUM_IN_REG; + + debug("%s(reset_ctl=%p) (dev=%p, id=%lu) (reg_addr=%p)\n", __func__, + reset_ctl, reset_ctl->dev, reset_ctl->id, + priv->base + (bank * 4)); + + rk_setreg(priv->base + (bank * 4), BIT(offset)); + + return 0; +} + +static int rockchip_reset_deassert(struct reset_ctl *reset_ctl) +{ + struct rockchip_reset_priv *priv = dev_get_priv(reset_ctl->dev); + int bank = reset_ctl->id / ROCKCHIP_RESET_NUM_IN_REG; + int offset = reset_ctl->id % ROCKCHIP_RESET_NUM_IN_REG; + + debug("%s(reset_ctl=%p) (dev=%p, id=%lu) (reg_addr=%p)\n", __func__, + reset_ctl, reset_ctl->dev, reset_ctl->id, + priv->base + (bank * 4)); + + rk_clrreg(priv->base + (bank * 4), BIT(offset)); + + return 0; +} + +struct reset_ops rockchip_reset_ops = { + .request = rockchip_reset_request, + .free = rockchip_reset_free, + .rst_assert = rockchip_reset_assert, + .rst_deassert = rockchip_reset_deassert, +}; + +static int rockchip_reset_probe(struct udevice *dev) +{ + struct rockchip_reset_priv *priv = dev_get_priv(dev); + fdt_addr_t addr; + fdt_size_t size; + + addr = dev_read_addr_size(dev, "reg", &size); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + if ((priv->reset_reg_offset == 0) && (priv->reset_reg_num == 0)) + return -EINVAL; + + addr += priv->reset_reg_offset; + priv->base = ioremap(addr, size); + + debug("%s(base=%p) (reg_offset=%x, reg_num=%d)\n", __func__, + priv->base, priv->reset_reg_offset, priv->reset_reg_num); + + return 0; +} + +int rockchip_reset_bind(struct udevice *pdev, u32 reg_offset, u32 reg_number) +{ + struct udevice *rst_dev; + struct rockchip_reset_priv *priv; + int ret; + + ret = device_bind_driver_to_node(pdev, "rockchip_reset", "reset", + dev_ofnode(pdev), &rst_dev); + if (ret) { + debug("Warning: No rockchip reset driver: ret=%d\n", ret); + return ret; + } + priv = malloc(sizeof(struct rockchip_reset_priv)); + priv->reset_reg_offset = reg_offset; + priv->reset_reg_num = reg_number; + rst_dev->priv = priv; + + return 0; +} + +U_BOOT_DRIVER(rockchip_reset) = { + .name = "rockchip_reset", + .id = UCLASS_RESET, + .probe = rockchip_reset_probe, + .ops = &rockchip_reset_ops, + .priv_auto_alloc_size = sizeof(struct rockchip_reset_priv), +};
From: Elaine Zhang zhangqing@rock-chips.com
Bind rockchip reset to clock-controller with rockchip_reset_bind().
Signed-off-by: Elaine Zhang zhangqing@rock-chips.com Signed-off-by: Kever Yang kever.yang@rock-chips.com ---
Changes in v2: - use rockchip_reset_bind() to bind reset driver.
arch/arm/include/asm/arch-rockchip/clock.h | 10 ++++++++++ drivers/clk/rockchip/clk_rk3036.c | 6 ++++++ drivers/clk/rockchip/clk_rk3188.c | 6 ++++++ drivers/clk/rockchip/clk_rk322x.c | 6 ++++++ drivers/clk/rockchip/clk_rk3288.c | 6 ++++++ drivers/clk/rockchip/clk_rk3328.c | 6 ++++++ drivers/clk/rockchip/clk_rk3368.c | 6 ++++++ drivers/clk/rockchip/clk_rk3399.c | 19 +++++++++++++++++++ drivers/clk/rockchip/clk_rv1108.c | 6 ++++++ 9 files changed, 71 insertions(+)
diff --git a/arch/arm/include/asm/arch-rockchip/clock.h b/arch/arm/include/asm/arch-rockchip/clock.h index 736b260..5264111 100644 --- a/arch/arm/include/asm/arch-rockchip/clock.h +++ b/arch/arm/include/asm/arch-rockchip/clock.h @@ -85,4 +85,14 @@ void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf);
int rockchip_get_clk(struct udevice **devp);
+/* + * rockchip_reset_bind() - Bind soft reset device as child of clock device + * + * @pdev: clock udevice + * @reg_offset: the first offset in cru for softreset registers + * @reg_number: the reg numbers of softreset registers + * @return 0 success, or error value + */ +int rockchip_reset_bind(struct udevice *pdev, u32 reg_offset, u32 reg_number); + #endif diff --git a/drivers/clk/rockchip/clk_rk3036.c b/drivers/clk/rockchip/clk_rk3036.c index 280ebb9..a718a08 100644 --- a/drivers/clk/rockchip/clk_rk3036.c +++ b/drivers/clk/rockchip/clk_rk3036.c @@ -332,6 +332,7 @@ static int rk3036_clk_bind(struct udevice *dev) int ret; struct udevice *sys_child; struct sysreset_reg *priv; + u32 offset;
/* The reset driver does not have a device node, so bind it here */ ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset", @@ -347,6 +348,11 @@ static int rk3036_clk_bind(struct udevice *dev) sys_child->priv = priv; }
+ offset = offsetof(struct rk3036_cru, cru_softrst_con[0]); + ret = rockchip_reset_bind(dev, offset, 9); + if (ret) + debug("Warning: software reset driver bind faile\n"); + return 0; }
diff --git a/drivers/clk/rockchip/clk_rk3188.c b/drivers/clk/rockchip/clk_rk3188.c index fca6899..6f24538 100644 --- a/drivers/clk/rockchip/clk_rk3188.c +++ b/drivers/clk/rockchip/clk_rk3188.c @@ -575,6 +575,7 @@ static int rk3188_clk_bind(struct udevice *dev) int ret; struct udevice *sys_child; struct sysreset_reg *priv; + u32 offset;
/* The reset driver does not have a device node, so bind it here */ ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset", @@ -590,6 +591,11 @@ static int rk3188_clk_bind(struct udevice *dev) sys_child->priv = priv; }
+ offset = offsetof(struct rk3188_cru, cru_softrst_con[0]); + ret = rockchip_reset_bind(dev, offset, 9); + if (ret) + debug("Warning: software reset driver bind faile\n"); + return 0; }
diff --git a/drivers/clk/rockchip/clk_rk322x.c b/drivers/clk/rockchip/clk_rk322x.c index ff52b55..1fc4e9e 100644 --- a/drivers/clk/rockchip/clk_rk322x.c +++ b/drivers/clk/rockchip/clk_rk322x.c @@ -387,6 +387,7 @@ static int rk322x_clk_bind(struct udevice *dev) int ret; struct udevice *sys_child; struct sysreset_reg *priv; + u32 offset;
/* The reset driver does not have a device node, so bind it here */ ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset", @@ -402,6 +403,11 @@ static int rk322x_clk_bind(struct udevice *dev) sys_child->priv = priv; }
+ offset = offsetof(struct rk322x_cru, cru_softrst_con[0]); + ret = rockchip_reset_bind(dev, offset, 9); + if (ret) + debug("Warning: software reset driver bind faile\n"); + return 0; }
diff --git a/drivers/clk/rockchip/clk_rk3288.c b/drivers/clk/rockchip/clk_rk3288.c index ac53239..e456bd0 100644 --- a/drivers/clk/rockchip/clk_rk3288.c +++ b/drivers/clk/rockchip/clk_rk3288.c @@ -861,6 +861,7 @@ static int rk3288_clk_bind(struct udevice *dev) int ret; struct udevice *sys_child; struct sysreset_reg *priv; + u32 offset;
/* The reset driver does not have a device node, so bind it here */ ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset", @@ -876,6 +877,11 @@ static int rk3288_clk_bind(struct udevice *dev) sys_child->priv = priv; }
+ offset = offsetof(struct rk3288_cru, cru_softrst_con[0]); + ret = rockchip_reset_bind(dev, offset, 12); + if (ret) + debug("Warning: software reset driver bind faile\n"); + return 0; }
diff --git a/drivers/clk/rockchip/clk_rk3328.c b/drivers/clk/rockchip/clk_rk3328.c index 4d522a7..8563c72 100644 --- a/drivers/clk/rockchip/clk_rk3328.c +++ b/drivers/clk/rockchip/clk_rk3328.c @@ -599,6 +599,7 @@ static int rk3328_clk_bind(struct udevice *dev) int ret; struct udevice *sys_child; struct sysreset_reg *priv; + u32 offset;
/* The reset driver does not have a device node, so bind it here */ ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset", @@ -614,6 +615,11 @@ static int rk3328_clk_bind(struct udevice *dev) sys_child->priv = priv; }
+ offset = offsetof(struct rk3328_cru, softrst_con[0]); + ret = rockchip_reset_bind(dev, offset, 12); + if (ret) + debug("Warning: software reset driver bind faile\n"); + return ret; }
diff --git a/drivers/clk/rockchip/clk_rk3368.c b/drivers/clk/rockchip/clk_rk3368.c index bfeef39..c9449ed 100644 --- a/drivers/clk/rockchip/clk_rk3368.c +++ b/drivers/clk/rockchip/clk_rk3368.c @@ -528,6 +528,7 @@ static int rk3368_clk_bind(struct udevice *dev) int ret; struct udevice *sys_child; struct sysreset_reg *priv; + u32 offset;
/* The reset driver does not have a device node, so bind it here */ ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset", @@ -543,6 +544,11 @@ static int rk3368_clk_bind(struct udevice *dev) sys_child->priv = priv; }
+ offset = offsetof(struct rk3368_cru, softrst_con[0]); + ret = rockchip_reset_bind(dev, offset, 15); + if (ret) + debug("Warning: software reset driver bind faile\n"); + return ret; }
diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index 2e85ac7..97d2fcc 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -1031,6 +1031,7 @@ static int rk3399_clk_bind(struct udevice *dev) int ret; struct udevice *sys_child; struct sysreset_reg *priv; + u32 offset;
/* The reset driver does not have a device node, so bind it here */ ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset", @@ -1046,6 +1047,11 @@ static int rk3399_clk_bind(struct udevice *dev) sys_child->priv = priv; }
+ offset = offsetof(struct rk3399_cru, softrst_con[0]); + ret = rockchip_reset_bind(dev, offset, 21); + if (ret) + debug("Warning: software reset driver bind faile\n"); + return 0; }
@@ -1221,6 +1227,18 @@ static int rk3399_pmuclk_ofdata_to_platdata(struct udevice *dev) return 0; }
+static int rk3399_pmuclk_bind(struct udevice *dev) +{ + int ret = 0; + + offset = offsetof(struct rk3399_pmucru, pmucru_softrst_con[0]); + ret = rockchip_reset_bind(dev, offset, 2); + if (ret) + debug("Warning: software reset driver bind faile\n"); + + return 0; +} + static const struct udevice_id rk3399_pmuclk_ids[] = { { .compatible = "rockchip,rk3399-pmucru" }, { } @@ -1234,6 +1252,7 @@ U_BOOT_DRIVER(rockchip_rk3399_pmuclk) = { .ofdata_to_platdata = rk3399_pmuclk_ofdata_to_platdata, .ops = &rk3399_pmuclk_ops, .probe = rk3399_pmuclk_probe, + .bind = rk3399_pmuclk_bind, #if CONFIG_IS_ENABLED(OF_PLATDATA) .platdata_auto_alloc_size = sizeof(struct rk3399_pmuclk_plat), #endif diff --git a/drivers/clk/rockchip/clk_rv1108.c b/drivers/clk/rockchip/clk_rv1108.c index a119548..0f0a18f 100644 --- a/drivers/clk/rockchip/clk_rv1108.c +++ b/drivers/clk/rockchip/clk_rv1108.c @@ -225,6 +225,7 @@ static int rv1108_clk_bind(struct udevice *dev) int ret; struct udevice *sys_child; struct sysreset_reg *priv; + u32 offset;
/* The reset driver does not have a device node, so bind it here */ ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset", @@ -240,6 +241,11 @@ static int rv1108_clk_bind(struct udevice *dev) sys_child->priv = priv; }
+ offset = offsetof(struct rk3368_cru, softrst_con[0]); + ret = rockchip_reset_bind(dev, offset, 13); + if (ret) + debug("Warning: software reset driver bind faile\n"); + return 0; }
From: Elaine Zhang zhangqing@rock-chips.com
Bind rockchip reset to clock-controller with rockchip_reset_bind().
Signed-off-by: Elaine Zhang zhangqing@rock-chips.com Signed-off-by: Kever Yang kever.yang@rock-chips.com
Changes in v2:
- use rockchip_reset_bind() to bind reset driver.
arch/arm/include/asm/arch-rockchip/clock.h | 10 ++++++++++ drivers/clk/rockchip/clk_rk3036.c | 6 ++++++ drivers/clk/rockchip/clk_rk3188.c | 6 ++++++ drivers/clk/rockchip/clk_rk322x.c | 6 ++++++ drivers/clk/rockchip/clk_rk3288.c | 6 ++++++ drivers/clk/rockchip/clk_rk3328.c | 6 ++++++ drivers/clk/rockchip/clk_rk3368.c | 6 ++++++ drivers/clk/rockchip/clk_rk3399.c | 19 +++++++++++++++++++ drivers/clk/rockchip/clk_rv1108.c | 6 ++++++ 9 files changed, 71 insertions(+)
Acked-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
From: Elaine Zhang zhangqing@rock-chips.com
Bind rockchip reset to clock-controller with rockchip_reset_bind().
Signed-off-by: Elaine Zhang zhangqing@rock-chips.com Signed-off-by: Kever Yang kever.yang@rock-chips.com Acked-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
Changes in v2:
- use rockchip_reset_bind() to bind reset driver.
arch/arm/include/asm/arch-rockchip/clock.h | 10 ++++++++++ drivers/clk/rockchip/clk_rk3036.c | 6 ++++++ drivers/clk/rockchip/clk_rk3188.c | 6 ++++++ drivers/clk/rockchip/clk_rk322x.c | 6 ++++++ drivers/clk/rockchip/clk_rk3288.c | 6 ++++++ drivers/clk/rockchip/clk_rk3328.c | 6 ++++++ drivers/clk/rockchip/clk_rk3368.c | 6 ++++++ drivers/clk/rockchip/clk_rk3399.c | 19 +++++++++++++++++++ drivers/clk/rockchip/clk_rv1108.c | 6 ++++++ 9 files changed, 71 insertions(+)
Reviewed-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
From: Elaine Zhang zhangqing@rock-chips.com
Create driver to support all Rockchip SoCs soft reset. Example of usage: i2c driver: ret = reset_get_by_name(dev, "i2c", &reset_ctl); if (ret) { error("reset_get_by_name() failed: %d\n", ret); }
reset_assert(&reset_ctl); udelay(50); reset_deassert(&reset_ctl);
i2c dts node: resets = <&cru SRST_P_I2C1>, <&cru SRST_I2C1>; reset-names = "p_i2c", "i2c";
Signed-off-by: Elaine Zhang zhangqing@rock-chips.com Signed-off-by: Kever Yang kever.yang@rock-chips.com
Changes in v2:
- fix Kconfig more than 80 length
- use MACRO for reset bits in one reg
- use rkclr/set_reg for reg access
- add rockchip_reset_bind()
- use dev_read_addr_size() instead of fdtdec_
drivers/reset/Kconfig | 9 +++ drivers/reset/Makefile | 1 + drivers/reset/reset-rockchip.c | 133 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 143 insertions(+) create mode 100644 drivers/reset/reset-rockchip.c
Acked-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
From: Elaine Zhang zhangqing@rock-chips.com
Create driver to support all Rockchip SoCs soft reset. Example of usage: i2c driver: ret = reset_get_by_name(dev, "i2c", &reset_ctl); if (ret) { error("reset_get_by_name() failed: %d\n", ret); }
reset_assert(&reset_ctl); udelay(50); reset_deassert(&reset_ctl);
i2c dts node: resets = <&cru SRST_P_I2C1>, <&cru SRST_I2C1>; reset-names = "p_i2c", "i2c";
Signed-off-by: Elaine Zhang zhangqing@rock-chips.com Signed-off-by: Kever Yang kever.yang@rock-chips.com Acked-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
Changes in v2:
- fix Kconfig more than 80 length
- use MACRO for reset bits in one reg
- use rkclr/set_reg for reg access
- add rockchip_reset_bind()
- use dev_read_addr_size() instead of fdtdec_
drivers/reset/Kconfig | 9 +++ drivers/reset/Makefile | 1 + drivers/reset/reset-rockchip.c | 133 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 143 insertions(+) create mode 100644 drivers/reset/reset-rockchip.c
Reviewed-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
Kever,
This series causes build-breakage (even outside of the rockchip targets)... See https://travis-ci.org/ptomsich/u-boot-rockchip/builds/308522589
Please fix and resubmit. Also: did you test this using buildman or travis?
Thanks, Philipp.
On 28 Nov 2017, at 11:06, Philipp Tomsich philipp.tomsich@theobroma-systems.com wrote:
From: Elaine Zhang zhangqing@rock-chips.com
Create driver to support all Rockchip SoCs soft reset. Example of usage: i2c driver: ret = reset_get_by_name(dev, "i2c", &reset_ctl); if (ret) { error("reset_get_by_name() failed: %d\n", ret); }
reset_assert(&reset_ctl); udelay(50); reset_deassert(&reset_ctl);
i2c dts node: resets = <&cru SRST_P_I2C1>, <&cru SRST_I2C1>; reset-names = "p_i2c", "i2c";
Signed-off-by: Elaine Zhang zhangqing@rock-chips.com Signed-off-by: Kever Yang kever.yang@rock-chips.com Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com mailto:philipp.tomsich@theobroma-systems.com>
Changes in v2:
- fix Kconfig more than 80 length
- use MACRO for reset bits in one reg
- use rkclr/set_reg for reg access
- add rockchip_reset_bind()
- use dev_read_addr_size() instead of fdtdec_
drivers/reset/Kconfig | 9 +++ drivers/reset/Makefile | 1 + drivers/reset/reset-rockchip.c | 133 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 143 insertions(+) create mode 100644 drivers/reset/reset-rockchip.c
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com mailto:philipp.tomsich@theobroma-systems.com> _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de mailto:U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot https://lists.denx.de/listinfo/u-boot
Philipp,
On 11/29/2017 03:49 AM, Dr. Philipp Tomsich wrote:
Kever,
This series causes build-breakage (even outside of the rockchip targets)... See https://travis-ci.org/ptomsich/u-boot-rockchip/builds/308522589
I'm not understand this error, sometimes I also met this, which depends on the build system. The asm/arch is a link to asm/arch-rockchip which is dynamic generated by build system, is there a option to make sure the build system generate the link before build the c source? +drivers/reset/reset-rockchip.c:11:31: fatal error: asm/arch/hardware.h: No such file or directory
Please fix and resubmit. Also: did you test this using buildman or travis?
I use buildman, but no expperience with travis.
Thanks, - Kever
Thanks, Philipp.
On 28 Nov 2017, at 11:06, Philipp Tomsich <philipp.tomsich@theobroma-systems.com mailto:philipp.tomsich@theobroma-systems.com> wrote:
From: Elaine Zhang <zhangqing@rock-chips.com mailto:zhangqing@rock-chips.com>
Create driver to support all Rockchip SoCs soft reset. Example of usage: i2c driver: ret = reset_get_by_name(dev, "i2c", &reset_ctl); if (ret) { error("reset_get_by_name() failed: %d\n", ret); }
reset_assert(&reset_ctl); udelay(50); reset_deassert(&reset_ctl);
i2c dts node: resets = <&cru SRST_P_I2C1>, <&cru SRST_I2C1>; reset-names = "p_i2c", "i2c";
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com mailto:zhangqing@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com mailto:kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com
mailto:philipp.tomsich@theobroma-systems.com>
Changes in v2:
- fix Kconfig more than 80 length
- use MACRO for reset bits in one reg
- use rkclr/set_reg for reg access
- add rockchip_reset_bind()
- use dev_read_addr_size() instead of fdtdec_
drivers/reset/Kconfig | 9 +++ drivers/reset/Makefile | 1 + drivers/reset/reset-rockchip.c | 133 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 143 insertions(+) create mode 100644 drivers/reset/reset-rockchip.c
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com mailto:philipp.tomsich@theobroma-systems.com> _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de mailto:U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
On 4 Dec 2017, at 02:04, Kever Yang kever.yang@rock-chips.com wrote:
Philipp,
On 11/29/2017 03:49 AM, Dr. Philipp Tomsich wrote:
Kever,
This series causes build-breakage (even outside of the rockchip targets)... See https://travis-ci.org/ptomsich/u-boot-rockchip/builds/308522589 https://travis-ci.org/ptomsich/u-boot-rockchip/builds/308522589
I'm not understand this error, sometimes I also met this, which depends on the build system. The asm/arch is a link to asm/arch-rockchip which is dynamic generated by build system, is there a option to make sure the build system generate the link before build the c source? +drivers/reset/reset-rockchip.c:11:31: fatal error: asm/arch/hardware.h: No such file or directory
Please fix and resubmit. Also: did you test this using buildman or travis?
I use buildman, but no expperience with travis.
This reproduces with buildman for me. I wonder what difference in our setups causes this not to show up on your end… Also: why is reset-rockchip.o even being built for the evb-ast2500 target?
ptomsich@android:~/u-boot-rockchip$ tools/buildman/buildman arm11 Building current source for 11 boards (4 threads, 1 job per thread) arm: + evb-ast2500 +drivers/reset/reset-rockchip.c:11:31: fatal error: asm/arch/hardware.h: No such file or directory + #include <asm/arch/hardware.h> + ^ +compilation terminated. +make[3]: *** [drivers/reset/reset-rockchip.o] Error 1 +make[2]: *** [drivers/reset] Error 2 +make[1]: *** [drivers] Error 2 +make: *** [sub-make] Error 2 arm: + rpi +arch/arm/dts/bcm2835-rpi-a-plus.dtb: Warning (phys_property): Missing property '#phy-cells' in node /phy or bad phandle (referred from /soc/usb@7e980000:phys[0]) +arch/arm/dts/bcm2835-rpi-a.dtb: Warning (phys_property): Missing property '#phy-cells' in node /phy or bad phandle (referred from /soc/usb@7e980000:phys[0]) +arch/arm/dts/bcm2835-rpi-b-plus.dtb: Warning (phys_property): Missing property '#phy-cells' in node /phy or bad phandle (referred from /soc/usb@7e980000:phys[0]) +arch/arm/dts/bcm2835-rpi-b-rev2.dtb: Warning (phys_property): Missing property '#phy-cells' in node /phy or bad phandle (referred from /soc/usb@7e980000:phys[0]) +arch/arm/dts/bcm2835-rpi-b.dtb: Warning (phys_property): Missing property '#phy-cells' in node /phy or bad phandle (referred from /soc/usb@7e980000:phys[0]) +arch/arm/dts/bcm2836-rpi-2-b.dtb: Warning (phys_property): Missing property '#phy-cells' in node /phy or bad phandle (referred from /soc/usb@7e980000:phys[0]) +arch/arm/dts/bcm2837-rpi-3-b.dtb: Warning (phys_property): Missing property '#phy-cells' in node /phy or bad phandle (referred from /soc/usb@7e980000:phys[0]) 9 1 1 /11 0:00:07 : mx31pdk
Thanks,
- Kever
Thanks, Philipp.
On 28 Nov 2017, at 11:06, Philipp Tomsich <philipp.tomsich@theobroma-systems.com mailto:philipp.tomsich@theobroma-systems.com> wrote:
From: Elaine Zhang <zhangqing@rock-chips.com mailto:zhangqing@rock-chips.com>
Create driver to support all Rockchip SoCs soft reset. Example of usage: i2c driver: ret = reset_get_by_name(dev, "i2c", &reset_ctl); if (ret) { error("reset_get_by_name() failed: %d\n", ret); }
reset_assert(&reset_ctl); udelay(50); reset_deassert(&reset_ctl);
i2c dts node: resets = <&cru SRST_P_I2C1>, <&cru SRST_I2C1>; reset-names = "p_i2c", "i2c";
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com mailto:zhangqing@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com mailto:kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com mailto:philipp.tomsich@theobroma-systems.com>
Changes in v2:
- fix Kconfig more than 80 length
- use MACRO for reset bits in one reg
- use rkclr/set_reg for reg access
- add rockchip_reset_bind()
- use dev_read_addr_size() instead of fdtdec_
drivers/reset/Kconfig | 9 +++ drivers/reset/Makefile | 1 + drivers/reset/reset-rockchip.c | 133 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 143 insertions(+) create mode 100644 drivers/reset/reset-rockchip.c
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com mailto:philipp.tomsich@theobroma-systems.com> _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de mailto:U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot https://lists.denx.de/listinfo/u-boot
On 8 Dec 2017, at 14:27, Dr. Philipp Tomsich philipp.tomsich@theobroma-systems.com wrote:
On 4 Dec 2017, at 02:04, Kever Yang <kever.yang@rock-chips.com mailto:kever.yang@rock-chips.com> wrote:
Philipp,
On 11/29/2017 03:49 AM, Dr. Philipp Tomsich wrote:
Kever,
This series causes build-breakage (even outside of the rockchip targets)... See https://travis-ci.org/ptomsich/u-boot-rockchip/builds/308522589 https://travis-ci.org/ptomsich/u-boot-rockchip/builds/308522589
I'm not understand this error, sometimes I also met this, which depends on the build system. The asm/arch is a link to asm/arch-rockchip which is dynamic generated by build system, is there a option to make sure the build system generate the link before build the c source? +drivers/reset/reset-rockchip.c:11:31: fatal error: asm/arch/hardware.h: No such file or directory
Please fix and resubmit. Also: did you test this using buildman or travis?
I use buildman, but no expperience with travis.
You might want to check your buildman configuration, as the following should have been caught by buildman on your end...
The following snippet from the patch
@@ -1221,6 +1227,18 @@ static int rk3399_pmuclk_ofdata_to_platdata(struct udevice *dev) return 0; }
+static int rk3399_pmuclk_bind(struct udevice *dev) +{ + int ret = 0; + + offset = offsetof(struct rk3399_pmucru, pmucru_softrst_con[0]); + ret = rockchip_reset_bind(dev, offset, 2); + if (ret) + debug("Warning: software reset driver bind faile\n"); + + return 0; +} +
results in the buildman failure (due to offset not being declared):
aarch64: + firefly-rk3399 +drivers/clk/rockchip/clk_rk3399.c: In function 'rk3399_pmuclk_bind': +drivers/clk/rockchip/clk_rk3399.c:1234:2: error: 'offset' undeclared (first use in this function); did you mean 'off_t'? + offset = offsetof(struct rk3399_pmucru, pmucru_softrst_con[0]); + ^~~~~~ + off_t +drivers/clk/rockchip/clk_rk3399.c:1234:2: note: each undeclared identifier is reported only once for each function it appears in +make[4]: *** [drivers/clk/rockchip/clk_rk3399.o] Error 1 +make[3]: *** [drivers/clk/rockchip] Error 2 +make[2]: *** [drivers/clk] Error 2 +make[1]: *** [drivers] Error 2 +make: *** [sub-make] Error 2
Thanks, Philipp.
Thanks,
- Kever
Thanks, Philipp.
On 28 Nov 2017, at 11:06, Philipp Tomsich <philipp.tomsich@theobroma-systems.com mailto:philipp.tomsich@theobroma-systems.com> wrote:
From: Elaine Zhang <zhangqing@rock-chips.com mailto:zhangqing@rock-chips.com>
Create driver to support all Rockchip SoCs soft reset. Example of usage: i2c driver: ret = reset_get_by_name(dev, "i2c", &reset_ctl); if (ret) { error("reset_get_by_name() failed: %d\n", ret); }
reset_assert(&reset_ctl); udelay(50); reset_deassert(&reset_ctl);
i2c dts node: resets = <&cru SRST_P_I2C1>, <&cru SRST_I2C1>; reset-names = "p_i2c", "i2c";
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com mailto:zhangqing@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com mailto:kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com mailto:philipp.tomsich@theobroma-systems.com>
Changes in v2:
- fix Kconfig more than 80 length
- use MACRO for reset bits in one reg
- use rkclr/set_reg for reg access
- add rockchip_reset_bind()
- use dev_read_addr_size() instead of fdtdec_
drivers/reset/Kconfig | 9 +++ drivers/reset/Makefile | 1 + drivers/reset/reset-rockchip.c | 133 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 143 insertions(+) create mode 100644 drivers/reset/reset-rockchip.c
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com mailto:philipp.tomsich@theobroma-systems.com> _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de mailto:U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot https://lists.denx.de/listinfo/u-boot
participants (3)
-
Dr. Philipp Tomsich -
Kever Yang -
Philipp Tomsich