imx8qxp: deneb board fails with current HEAD
Hello Peng,
I just rebased my current work on siemens deneb board with current master:
* d5cab0d6ad - (HEAD -> master, origin/master, origin/WIP/15Oct2024, origin/HEAD) Revert "Makefile: Drop SPL_FIT_GENERATOR / SPL_FIT_SOURCE support" changes (vor 3 Stunden) <Tom Rini>
And see: """ U-Boot SPL 2024.10-01044-g91b1263d96d9 (Oct 16 2024 - 07:10:25 +0200) Normal Boot Trying to boot from MMC1 __imx8_clk_enable(Invalid clk ID #0) fsl_esdhc usdhc@5b010000: Failed to enable clks: -22 __imx8_clk_enable(Invalid clk ID #0) fsl_esdhc usdhc@5b010000: Failed to enable clks: -22 spl: could not initialize mmc. error: -22 SPL: failed to boot from all boot devices ### ERROR ### Please RESET the board ### """
Looking around the changes I found your commit:
commit 76332fae769acbba49751827ce126b0cb1014b48 Author: Peng Fan peng.fan@nxp.com Date: Tue Oct 1 21:07:53 2024 +0800
mmc: fsl_esdhc_imx: Enable AHB/IPG clk with clk bulk API
With partition reset supported for i.MX8QM/QXP/95 and etc, when linux mmc runtime suspended, the mmc clks are gated off. While at same time system controller reset Cortex-A cores because of various reasons( WDOG timeout and etc), with SPL run again, only enable PER clk is not enough, also need to enable AHB/IPG clk, here use clk bulk API to enable all the clocks.
Signed-off-by: Peng Fan peng.fan@nxp.com
reverting it, and board boots fine again!
May you have an idea? I try to look deeper soon.
(A fast look as I wondered about clk id 0):
./include/dt-bindings/clock/imx8qxp-clock.h #define IMX8QXP_CLK_DUMMY 0
and ./arch/arm/dts/fsl-imx8dx.dtsi 512 usdhc2: usdhc@5b020000 { 513 compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc"; [...] 517 clocks = <&clk IMX8QXP_SDHC1_IPG_CLK>, 518 <&clk IMX8QXP_SDHC1_CLK>, 519 <&clk IMX8QXP_CLK_DUMMY>; 520 clock-names = "ipg", "per", "ahb";
So this explains ID 0 ... and with drivers/clk/imx/clk-imx8qxp.c 242 int __imx8_clk_enable(struct clk *clk, bool enable) 243 { [...] 250 switch (clk->id) { 251 case IMX8QXP_I2C0_CLK:
no entry for IMX8QXP_CLK_DUMMY ...
So I wonder how this can work ...
Thanks!
bye, Heiko [1] U-Boot SPL 2024.10-01045-g0a08358303ba (Oct 16 2024 - 07:18:23 +0200) Normal Boot Trying to boot from MMC1 Primary set selected Load image from MMC/SD 0x47800
U-Boot 2024.10-01045-g0a08358303ba (Oct 16 2024 - 07:18:23 +0200) ##v01.06
CPU: NXP i.MX8QXP RevC A35 at 1200 MHz at 31C Model: Siemens CXG3 Board: Capricorn Build: SCFW 042ba867, SECO-FW c9de51c0, ATF 2ba2c83 Boot: MMC0 Reset cause: POR DRAM: 2 GiB HW Version: v04.03 Core: 94 devices, 23 uclasses, devicetree: separate WDT: Started scu-wdt without servicing (60s timeout) MMC: FSL_SDHC: 0 Loading Environment from MMC... *** Warning - bad CRC, using default environment
Reading from MMC(0)... In: serial@5a080000 Out: serial@5a080000 Err: serial@5a080000 ERROR: PCA9552 probe failed I2C LED init failed Net: eth1: ethernet@5b050000 [PRIME] Autobooting in 3 seconds, press "<Esc><Esc>" to stop U-Boot# U-Boot#
Hi Heiko,
Subject: imx8qxp: deneb board fails with current HEAD
Hello Peng,
I just rebased my current work on siemens deneb board with current master:
- d5cab0d6ad - (HEAD -> master, origin/master, origin/WIP/15Oct2024,
origin/HEAD) Revert "Makefile: Drop SPL_FIT_GENERATOR / SPL_FIT_SOURCE support" changes (vor 3 Stunden) <Tom Rini>
My bad. I had a patch in my local, this should resolve the issue you met.
From 3e5f8ad6cb93b9538852230d01c01b52d5c1c9d1 Mon Sep 17 00:00:00 2001 From: Peng Fan peng.fan@nxp.com Date: Fri, 11 Oct 2024 19:57:49 +0800 Subject: [PATCH] clk: imx8: Add dummy clk
There is a dummy clk entry for i.MX8QM/QXP, so add the dummy clk enable and get rate. Otherwise "__imx8_clk_enable(Invalid clk ID #0)".
Fixes: 76332fae769 ("mmc: fsl_esdhc_imx: Enable AHB/IPG clk with clk bulk API") Signed-off-by: Peng Fan peng.fan@nxp.com --- drivers/clk/imx/clk-imx8qm.c | 4 ++++ drivers/clk/imx/clk-imx8qxp.c | 4 ++++ 2 files changed, 8 insertions(+)
diff --git a/drivers/clk/imx/clk-imx8qm.c b/drivers/clk/imx/clk-imx8qm.c index 62fed7e3e32..466d71786cf 100644 --- a/drivers/clk/imx/clk-imx8qm.c +++ b/drivers/clk/imx/clk-imx8qm.c @@ -48,6 +48,8 @@ ulong imx8_clk_get_rate(struct clk *clk) debug("%s(#%lu)\n", __func__, clk->id);
switch (clk->id) { + case IMX8QM_CLK_DUMMY: + return 0; case IMX8QM_A53_DIV: resource = SC_R_A53; pm_clk = SC_PM_CLK_CPU; @@ -264,6 +266,8 @@ int __imx8_clk_enable(struct clk *clk, bool enable) debug("%s(#%lu)\n", __func__, clk->id);
switch (clk->id) { + case IMX8QM_CLK_DUMMY: + return 0; case IMX8QM_I2C0_IPG_CLK: case IMX8QM_I2C0_CLK: case IMX8QM_I2C0_DIV: diff --git a/drivers/clk/imx/clk-imx8qxp.c b/drivers/clk/imx/clk-imx8qxp.c index 18bdc08971b..79098623bc8 100644 --- a/drivers/clk/imx/clk-imx8qxp.c +++ b/drivers/clk/imx/clk-imx8qxp.c @@ -51,6 +51,8 @@ ulong imx8_clk_get_rate(struct clk *clk) debug("%s(#%lu)\n", __func__, clk->id);
switch (clk->id) { + case IMX8QXP_CLK_DUMMY: + return 0; case IMX8QXP_A35_DIV: resource = SC_R_A35; pm_clk = SC_PM_CLK_CPU; @@ -248,6 +250,8 @@ int __imx8_clk_enable(struct clk *clk, bool enable) debug("%s(#%lu)\n", __func__, clk->id);
switch (clk->id) { + case IMX8QXP_CLK_DUMMY: + return 0; case IMX8QXP_I2C0_CLK: case IMX8QXP_I2C0_IPG_CLK: resource = SC_R_I2C_0;
Hello Peng,
On 16.10.24 08:11, Peng Fan wrote:
Hi Heiko,
Subject: imx8qxp: deneb board fails with current HEAD
Hello Peng,
I just rebased my current work on siemens deneb board with current master:
- d5cab0d6ad - (HEAD -> master, origin/master, origin/WIP/15Oct2024,
origin/HEAD) Revert "Makefile: Drop SPL_FIT_GENERATOR / SPL_FIT_SOURCE support" changes (vor 3 Stunden) <Tom Rini>
My bad. I had a patch in my local, this should resolve the issue you met.
No problem!
From 3e5f8ad6cb93b9538852230d01c01b52d5c1c9d1 Mon Sep 17 00:00:00 2001 From: Peng Fan peng.fan@nxp.com Date: Fri, 11 Oct 2024 19:57:49 +0800 Subject: [PATCH] clk: imx8: Add dummy clk
There is a dummy clk entry for i.MX8QM/QXP, so add the dummy clk enable and get rate. Otherwise "__imx8_clk_enable(Invalid clk ID #0)".
Fixes: 76332fae769 ("mmc: fsl_esdhc_imx: Enable AHB/IPG clk with clk bulk API") Signed-off-by: Peng Fan peng.fan@nxp.com
drivers/clk/imx/clk-imx8qm.c | 4 ++++ drivers/clk/imx/clk-imx8qxp.c | 4 ++++ 2 files changed, 8 insertions(+)
diff --git a/drivers/clk/imx/clk-imx8qm.c b/drivers/clk/imx/clk-imx8qm.c index 62fed7e3e32..466d71786cf 100644 --- a/drivers/clk/imx/clk-imx8qm.c +++ b/drivers/clk/imx/clk-imx8qm.c @@ -48,6 +48,8 @@ ulong imx8_clk_get_rate(struct clk *clk) debug("%s(#%lu)\n", __func__, clk->id);
switch (clk->id) {
case IMX8QM_CLK_DUMMY:return 0; case IMX8QM_A53_DIV: resource = SC_R_A53; pm_clk = SC_PM_CLK_CPU;@@ -264,6 +266,8 @@ int __imx8_clk_enable(struct clk *clk, bool enable) debug("%s(#%lu)\n", __func__, clk->id);
switch (clk->id) {
case IMX8QM_CLK_DUMMY:return 0; case IMX8QM_I2C0_IPG_CLK: case IMX8QM_I2C0_CLK: case IMX8QM_I2C0_DIV:diff --git a/drivers/clk/imx/clk-imx8qxp.c b/drivers/clk/imx/clk-imx8qxp.c index 18bdc08971b..79098623bc8 100644 --- a/drivers/clk/imx/clk-imx8qxp.c +++ b/drivers/clk/imx/clk-imx8qxp.c @@ -51,6 +51,8 @@ ulong imx8_clk_get_rate(struct clk *clk) debug("%s(#%lu)\n", __func__, clk->id);
switch (clk->id) {
case IMX8QXP_CLK_DUMMY:return 0; case IMX8QXP_A35_DIV: resource = SC_R_A35; pm_clk = SC_PM_CLK_CPU;@@ -248,6 +250,8 @@ int __imx8_clk_enable(struct clk *clk, bool enable) debug("%s(#%lu)\n", __func__, clk->id);
switch (clk->id) {
case IMX8QXP_CLK_DUMMY:return 0; case IMX8QXP_I2C0_CLK: case IMX8QXP_I2C0_IPG_CLK: resource = SC_R_I2C_0;
Heh, yes, that what I thought after I had sended my EMail... but wondering why we use a dummy here and not like it is in linux:
clocks = <&sdhc0_lpcg IMX_LPCG_CLK_4>, <&sdhc0_lpcg IMX_LPCG_CLK_5>, <&sdhc0_lpcg IMX_LPCG_CLK_0>; clock-names = "ipg", "ahb", "per";
?
Do you plan to send this patch?
bye, Heiko
Subject: Re: imx8qxp: deneb board fails with current HEAD
Hello Peng,
On 16.10.24 08:11, Peng Fan wrote:
Hi Heiko,
Subject: imx8qxp: deneb board fails with current HEAD
Hello Peng,
I just rebased my current work on siemens deneb board with current master:
- d5cab0d6ad - (HEAD -> master, origin/master,
origin/WIP/15Oct2024,
origin/HEAD) Revert "Makefile: Drop SPL_FIT_GENERATOR / SPL_FIT_SOURCE support" changes (vor
3
Stunden) <Tom Rini>
My bad. I had a patch in my local, this should resolve the issue you
met.
No problem!
From 3e5f8ad6cb93b9538852230d01c01b52d5c1c9d1 Mon Sep 17
00:00:00
2001 From: Peng Fan peng.fan@nxp.com Date: Fri, 11 Oct 2024 19:57:49 +0800 Subject: [PATCH] clk: imx8: Add dummy clk
There is a dummy clk entry for i.MX8QM/QXP, so add the dummy clk enable and get rate. Otherwise "__imx8_clk_enable(Invalid clk ID #0)".
Fixes: 76332fae769 ("mmc: fsl_esdhc_imx: Enable AHB/IPG clk with
clk
bulk API") Signed-off-by: Peng Fan peng.fan@nxp.com
drivers/clk/imx/clk-imx8qm.c | 4 ++++ drivers/clk/imx/clk-imx8qxp.c | 4 ++++ 2 files changed, 8 insertions(+)
diff --git a/drivers/clk/imx/clk-imx8qm.c b/drivers/clk/imx/clk-imx8qm.c index 62fed7e3e32..466d71786cf
100644
--- a/drivers/clk/imx/clk-imx8qm.c +++ b/drivers/clk/imx/clk-imx8qm.c @@ -48,6 +48,8 @@ ulong imx8_clk_get_rate(struct clk *clk) debug("%s(#%lu)\n", __func__, clk->id);
switch (clk->id) {
case IMX8QM_CLK_DUMMY:return 0; case IMX8QM_A53_DIV: resource = SC_R_A53; pm_clk = SC_PM_CLK_CPU; @@ -264,6 +266,8 @@ int__imx8_clk_enable(struct clk *clk, bool enable) debug("%s(#%lu)\n", __func__, clk->id);
switch (clk->id) {
case IMX8QM_CLK_DUMMY:return 0; case IMX8QM_I2C0_IPG_CLK: case IMX8QM_I2C0_CLK: case IMX8QM_I2C0_DIV:diff --git a/drivers/clk/imx/clk-imx8qxp.c b/drivers/clk/imx/clk-imx8qxp.c index 18bdc08971b..79098623bc8
100644
--- a/drivers/clk/imx/clk-imx8qxp.c +++ b/drivers/clk/imx/clk-imx8qxp.c @@ -51,6 +51,8 @@ ulong imx8_clk_get_rate(struct clk *clk) debug("%s(#%lu)\n", __func__, clk->id);
switch (clk->id) {
case IMX8QXP_CLK_DUMMY:return 0; case IMX8QXP_A35_DIV: resource = SC_R_A35; pm_clk = SC_PM_CLK_CPU; @@ -248,6 +250,8 @@ int__imx8_clk_enable(struct clk *clk, bool enable) debug("%s(#%lu)\n", __func__, clk->id);
switch (clk->id) {
case IMX8QXP_CLK_DUMMY:return 0; case IMX8QXP_I2C0_CLK: case IMX8QXP_I2C0_IPG_CLK: resource = SC_R_I2C_0;Heh, yes, that what I thought after I had sended my EMail... but wondering why we use a dummy here and not like it is in linux:
clocks = <&sdhc0_lpcg IMX_LPCG_CLK_4>, <&sdhc0_lpcg IMX_LPCG_CLK_5>, <&sdhc0_lpcg IMX_LPCG_CLK_0>; clock-names = "ipg", "ahb", "per";?
The current U-Boot support for i.MX8 not reuse the device tree from kernel. The device tree diverges.
Do you plan to send this patch?
You mean "[PATCH] clk: imx8: Add dummy clk"? I could post it out. But If you wanna to add more stuff, feel free to take it over and do that.
I not have plan to sync the DTB for i.MX8.
Regards, Peng.
bye, Heiko -- DENX Software Engineering GmbH, Managing Director: Erika Unter HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-52 Fax: +49-8142-66989-80 Email: hs@denx.de
Hello Peng,
On 16.10.24 08:33, Peng Fan wrote:
Subject: Re: imx8qxp: deneb board fails with current HEAD
Hello Peng,
On 16.10.24 08:11, Peng Fan wrote:
Hi Heiko,
Subject: imx8qxp: deneb board fails with current HEAD
Hello Peng,
I just rebased my current work on siemens deneb board with current master:
- d5cab0d6ad - (HEAD -> master, origin/master,
origin/WIP/15Oct2024,
origin/HEAD) Revert "Makefile: Drop SPL_FIT_GENERATOR / SPL_FIT_SOURCE support" changes (vor
3
Stunden) <Tom Rini>
My bad. I had a patch in my local, this should resolve the issue you
met.
No problem!
From 3e5f8ad6cb93b9538852230d01c01b52d5c1c9d1 Mon Sep 17
00:00:00
2001 From: Peng Fan peng.fan@nxp.com Date: Fri, 11 Oct 2024 19:57:49 +0800 Subject: [PATCH] clk: imx8: Add dummy clk
There is a dummy clk entry for i.MX8QM/QXP, so add the dummy clk enable and get rate. Otherwise "__imx8_clk_enable(Invalid clk ID #0)".
Fixes: 76332fae769 ("mmc: fsl_esdhc_imx: Enable AHB/IPG clk with
clk
bulk API") Signed-off-by: Peng Fan peng.fan@nxp.com
drivers/clk/imx/clk-imx8qm.c | 4 ++++ drivers/clk/imx/clk-imx8qxp.c | 4 ++++ 2 files changed, 8 insertions(+)
diff --git a/drivers/clk/imx/clk-imx8qm.c b/drivers/clk/imx/clk-imx8qm.c index 62fed7e3e32..466d71786cf
100644
--- a/drivers/clk/imx/clk-imx8qm.c +++ b/drivers/clk/imx/clk-imx8qm.c @@ -48,6 +48,8 @@ ulong imx8_clk_get_rate(struct clk *clk) debug("%s(#%lu)\n", __func__, clk->id);
switch (clk->id) {
case IMX8QM_CLK_DUMMY:return 0; case IMX8QM_A53_DIV: resource = SC_R_A53; pm_clk = SC_PM_CLK_CPU; @@ -264,6 +266,8 @@ int__imx8_clk_enable(struct clk *clk, bool enable) debug("%s(#%lu)\n", __func__, clk->id);
switch (clk->id) {
case IMX8QM_CLK_DUMMY:return 0; case IMX8QM_I2C0_IPG_CLK: case IMX8QM_I2C0_CLK: case IMX8QM_I2C0_DIV:diff --git a/drivers/clk/imx/clk-imx8qxp.c b/drivers/clk/imx/clk-imx8qxp.c index 18bdc08971b..79098623bc8
100644
--- a/drivers/clk/imx/clk-imx8qxp.c +++ b/drivers/clk/imx/clk-imx8qxp.c @@ -51,6 +51,8 @@ ulong imx8_clk_get_rate(struct clk *clk) debug("%s(#%lu)\n", __func__, clk->id);
switch (clk->id) {
case IMX8QXP_CLK_DUMMY:return 0; case IMX8QXP_A35_DIV: resource = SC_R_A35; pm_clk = SC_PM_CLK_CPU; @@ -248,6 +250,8 @@ int__imx8_clk_enable(struct clk *clk, bool enable) debug("%s(#%lu)\n", __func__, clk->id);
switch (clk->id) {
case IMX8QXP_CLK_DUMMY:return 0; case IMX8QXP_I2C0_CLK: case IMX8QXP_I2C0_IPG_CLK: resource = SC_R_I2C_0;Heh, yes, that what I thought after I had sended my EMail... but wondering why we use a dummy here and not like it is in linux:
clocks = <&sdhc0_lpcg IMX_LPCG_CLK_4>, <&sdhc0_lpcg IMX_LPCG_CLK_5>, <&sdhc0_lpcg IMX_LPCG_CLK_0>; clock-names = "ipg", "ahb", "per";?
The current U-Boot support for i.MX8 not reuse the device tree from kernel. The device tree diverges.
Yes, I know...
Do you plan to send this patch?
You mean "[PATCH] clk: imx8: Add dummy clk"?
Yes.
I could post it out. But If you wanna to add more stuff, feel free to take it over and do that.
Please post it, thanks! You can add my
Reviewed-by: Heiko Schocher hs@denx.de
When posted, I will test it.
I not have plan to sync the DTB for i.MX8.
bye, Heiko
Regards, Peng.
bye, Heiko -- DENX Software Engineering GmbH, Managing Director: Erika Unter HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-52 Fax: +49-8142-66989-80 Email: hs@denx.de
participants (2)
-
Heiko Schocher -
Peng Fan