On 29/05/2024 07:33, Sumit Garg wrote:

Hi Neil,

On Tue, 28 May 2024 at 14:02, Neil Armstrong neil.armstrong@linaro.org wrote:

...

Add support for bias-pull-down as an alternate of bias-pull-up.

nit: s/alternate/alternative/

...

Signed-off-by: Neil Armstrong neil.armstrong@linaro.org

drivers/pinctrl/qcom/pinctrl-qcom.c | 1 + 1 file changed, 1 insertion(+)

diff --git a/drivers/pinctrl/qcom/pinctrl-qcom.c b/drivers/pinctrl/qcom/pinctrl-qcom.c index 3c3336e7635..4f4e9a83949 100644 --- a/drivers/pinctrl/qcom/pinctrl-qcom.c +++ b/drivers/pinctrl/qcom/pinctrl-qcom.c @@ -44,6 +44,7 @@ static const struct pinconf_param msm_conf_params[] = { { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 2 }, { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 }, { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 3 },

•   { "bias-pull-down", PIN_CONFIG_BIAS_PULL_UP, 1 },
  

Did you mean PIN_CONFIG_BIAS_PULL_DOWN here instead?

Nop, I use the same flag but with the "1" argument instead of "3" which does set a pull-down.

Neil

-Sumit

...

     { "output-high", PIN_CONFIG_OUTPUT, 1, },
     { "output-low", PIN_CONFIG_OUTPUT, 0, },

};

-- 2.34.1

On Tue, 28 May 2024 at 14:02, Neil Armstrong neil.armstrong@linaro.org wrote:

In order to help setup pin configuration for special pins (UFS, SDCard), introduce the msm_special_pin_data struct largely inspired from the Linux conterpart but with only U-Boot required fields.

This struct is added to the pins_data to allow specifying the special pins data for each SoC.

Signed-off-by: Neil Armstrong neil.armstrong@linaro.org

arch/arm/mach-snapdragon/include/mach/gpio.h | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-)

Reviewed-by: Sumit Garg sumit.garg@linaro.org

-Sumit

diff --git a/arch/arm/mach-snapdragon/include/mach/gpio.h b/arch/arm/mach-snapdragon/include/mach/gpio.h index 53c6ae06490..cc8f405e20b 100644 --- a/arch/arm/mach-snapdragon/include/mach/gpio.h +++ b/arch/arm/mach-snapdragon/include/mach/gpio.h @@ -10,11 +10,25 @@ #include <asm/types.h> #include <stdbool.h>

+struct msm_special_pin_data {

•   char *name;
  

•   u32 ctl_reg;
  

•   u32 io_reg;
  

•   unsigned pull_bit:5;
  

•   unsigned drv_bit:5;
  

•   unsigned oe_bit:5;
  

•   unsigned in_bit:5;
  

•   unsigned out_bit:5;
  

+};

struct msm_pin_data { int pin_count; const unsigned int *pin_offsets;

•   /* Index of first special pin, these are ignored for now */
    unsigned int special_pins_start;
  

•   const struct msm_special_pin_data *special_pins_data;
  

};

static inline u32 qcom_pin_offset(const unsigned int *offs, unsigned int selector)

-- 2.34.1

On Tue, 28 May 2024 at 14:02, Neil Armstrong neil.armstrong@linaro.org wrote:

Use the previously introduced msm_special_pin_data to setup the special pins configuration if the SoC driver have them specified.

Signed-off-by: Neil Armstrong neil.armstrong@linaro.org

drivers/pinctrl/qcom/pinctrl-qcom.c | 37 +++++++++++++++++++++++++++++++++++-- 1 file changed, 35 insertions(+), 2 deletions(-)

Reviewed-by: Sumit Garg sumit.garg@linaro.org

-Sumit

diff --git a/drivers/pinctrl/qcom/pinctrl-qcom.c b/drivers/pinctrl/qcom/pinctrl-qcom.c index 4f4e9a83949..26a3fba194a 100644 --- a/drivers/pinctrl/qcom/pinctrl-qcom.c +++ b/drivers/pinctrl/qcom/pinctrl-qcom.c @@ -103,14 +103,47 @@ static int msm_pinmux_set(struct udevice *dev, unsigned int pin_selector, return 0; }

+static int msm_pinconf_set_special(struct msm_pinctrl_priv *priv, unsigned int pin_selector,

•                              unsigned int param, unsigned int argument)
  

+{

•   unsigned int offset = pin_selector - priv->data->pin_data.special_pins_start;
  

•   const struct msm_special_pin_data *data;
  

•   if (!priv->data->pin_data.special_pins_data)
  

•           return 0;
  

•   data = &priv->data->pin_data.special_pins_data[offset];
  

•   switch (param) {
  

•   case PIN_CONFIG_DRIVE_STRENGTH:
  

•           argument = (argument / 2) - 1;
  

•           clrsetbits_le32(priv->base + data->ctl_reg,
  

•                           GENMASK(2, 0) << data->drv_bit,
  

•                           argument << data->drv_bit);
  

•           break;
  

•   case PIN_CONFIG_BIAS_DISABLE:
  

•           clrbits_le32(priv->base + data->ctl_reg,
  

•                        TLMM_GPIO_PULL_MASK << data->pull_bit);
  

•           break;
  

•   case PIN_CONFIG_BIAS_PULL_UP:
  

•           clrsetbits_le32(priv->base + data->ctl_reg,
  

•                           TLMM_GPIO_PULL_MASK << data->pull_bit,
  

•                           argument << data->pull_bit);
  

•           break;
  

•   default:
  

•           return 0;
  

•   }
  

•   return 0;
  

+}

static int msm_pinconf_set(struct udevice *dev, unsigned int pin_selector, unsigned int param, unsigned int argument) { struct msm_pinctrl_priv *priv = dev_get_priv(dev);

•   /* Always NOP for special pins */
    if (qcom_is_special_pin(&priv->data->pin_data, pin_selector))
  

•           return 0;
  

•           return msm_pinconf_set_special(priv, pin_selector, param, argument);
  
    switch (param) {
    case PIN_CONFIG_DRIVE_STRENGTH:
  
  

-- 2.34.1

On Tue, 28 May 2024 at 14:02, Neil Armstrong neil.armstrong@linaro.org wrote:

Add the special pins configuration data to allow setup the bias of the UFS and SDCard pins on the SM8550 SoC.

Signed-off-by: Neil Armstrong neil.armstrong@linaro.org

drivers/pinctrl/qcom/pinctrl-sm8550.c | 42 ++++++++++++++++++++++++++++------- 1 file changed, 34 insertions(+), 8 deletions(-)

Reviewed-by: Sumit Garg sumit.garg@linaro.org

-Sumit

diff --git a/drivers/pinctrl/qcom/pinctrl-sm8550.c b/drivers/pinctrl/qcom/pinctrl-sm8550.c index 7265cb73404..c65dfe0435e 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8550.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8550.c @@ -18,6 +18,37 @@ static const struct pinctrl_function msm_pinctrl_functions[] = { {"gpio", 0}, };

+#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \

•   {                                               \
  

•           .name = pg_name,                        \
  

•           .ctl_reg = ctl,                         \
  

•           .io_reg = 0,                            \
  

•           .pull_bit = pull,                       \
  

•           .drv_bit = drv,                         \
  

•           .oe_bit = -1,                           \
  

•           .in_bit = -1,                           \
  

•           .out_bit = -1,                          \
  

•   }
  

+#define UFS_RESET(pg_name, ctl, io) \

•   {                                               \
  

•           .name = pg_name,                        \
  

•           .ctl_reg = ctl,                         \
  

•           .io_reg = io,                           \
  

•           .pull_bit = 3,                          \
  

•           .drv_bit = 0,                           \
  

•           .oe_bit = -1,                           \
  

•           .in_bit = -1,                           \
  

•           .out_bit = 0,                           \
  

•   }
  

+static const struct msm_special_pin_data msm_special_pins_data[] = {

•   [0] = UFS_RESET("ufs_reset", 0xde000, 0xde004),
  

•   [1] = SDC_QDSD_PINGROUP("sdc2_clk", 0xd6000, 14, 6),
  

•   [2] = SDC_QDSD_PINGROUP("sdc2_cmd", 0xd6000, 11, 3),
  

•   [3] = SDC_QDSD_PINGROUP("sdc2_data", 0xd6000, 9, 0),
  

+};

static const char *sm8550_get_function_name(struct udevice *dev, unsigned int selector) { @@ -27,15 +58,9 @@ static const char *sm8550_get_function_name(struct udevice *dev, static const char *sm8550_get_pin_name(struct udevice *dev, unsigned int selector) {

•   static const char *special_pins_names[] = {
  

•           "ufs_reset",
  

•           "sdc2_clk",
  

•           "sdc2_cmd",
  

•           "sdc2_data",
  

•   };
  

•   if (selector >= 210 && selector <= 213)
  

•           snprintf(pin_name, MAX_PIN_NAME_LEN, special_pins_names[selector - 210]);
  

•           snprintf(pin_name, MAX_PIN_NAME_LEN,
  

•                    msm_special_pins_data[selector - 210].name);
    else
            snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector);
  
  

@@ -52,6 +77,7 @@ static struct msm_pinctrl_data sm8550_data = { .pin_data = { .pin_count = 214, .special_pins_start = 210,

•           .special_pins_data = msm_special_pins_data,
    },
    .functions_count = ARRAY_SIZE(msm_pinctrl_functions),
    .get_function_name = sm8550_get_function_name,
  
  

-- 2.34.1

On Tue, 28 May 2024 at 14:02, Neil Armstrong neil.armstrong@linaro.org wrote:

Add the special pins configuration data to allow setup the bias of the UFS and SDCard pins on the SM8650 SoC.

Signed-off-by: Neil Armstrong neil.armstrong@linaro.org

drivers/pinctrl/qcom/pinctrl-sm8650.c | 42 ++++++++++++++++++++++++++++------- 1 file changed, 34 insertions(+), 8 deletions(-)

Reviewed-by: Sumit Garg sumit.garg@linaro.org

-Sumit

diff --git a/drivers/pinctrl/qcom/pinctrl-sm8650.c b/drivers/pinctrl/qcom/pinctrl-sm8650.c index d6cc1bbdda8..58fc94e71ac 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8650.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8650.c @@ -18,6 +18,37 @@ static const struct pinctrl_function msm_pinctrl_functions[] = { {"gpio", 0}, };

+#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \

•   {                                               \
  

•           .name = pg_name,                        \
  

•           .ctl_reg = ctl,                         \
  

•           .io_reg = 0,                            \
  

•           .pull_bit = pull,                       \
  

•           .drv_bit = drv,                         \
  

•           .oe_bit = -1,                           \
  

•           .in_bit = -1,                           \
  

•           .out_bit = -1,                          \
  

•   }
  

+#define UFS_RESET(pg_name, ctl, io) \

•   {                                               \
  

•           .name = pg_name,                        \
  

•           .ctl_reg = ctl,                         \
  

•           .io_reg = io,                           \
  

•           .pull_bit = 3,                          \
  

•           .drv_bit = 0,                           \
  

•           .oe_bit = -1,                           \
  

•           .in_bit = -1,                           \
  

•           .out_bit = 0,                           \
  

•   }
  

+static const struct msm_special_pin_data msm_special_pins_data[] = {

•   [0] = UFS_RESET("ufs_reset", 0xde004, 0xdf000),
  

•   [1] = SDC_QDSD_PINGROUP("sdc2_clk", 0xd6000, 14, 6),
  

•   [2] = SDC_QDSD_PINGROUP("sdc2_cmd", 0xd6000, 11, 3),
  

•   [3] = SDC_QDSD_PINGROUP("sdc2_data", 0xd6000, 9, 0),
  

+};

static const char *sm8650_get_function_name(struct udevice *dev, unsigned int selector) { @@ -27,15 +58,9 @@ static const char *sm8650_get_function_name(struct udevice *dev, static const char *sm8650_get_pin_name(struct udevice *dev, unsigned int selector) {

•   static const char *special_pins_names[] = {
  

•           "ufs_reset",
  

•           "sdc2_clk",
  

•           "sdc2_cmd",
  

•           "sdc2_data",
  

•   };
  

•   if (selector >= 210 && selector <= 213)
  

•           snprintf(pin_name, MAX_PIN_NAME_LEN, special_pins_names[selector - 210]);
  

•           snprintf(pin_name, MAX_PIN_NAME_LEN,
  

•                    msm_special_pins_data[selector - 210].name);
    else
            snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector);
  
  

@@ -52,6 +77,7 @@ static struct msm_pinctrl_data sm8650_data = { .pin_data = { .pin_count = 214, .special_pins_start = 210,

•           .special_pins_data = msm_special_pins_data,
    },
    .functions_count = ARRAY_SIZE(msm_pinctrl_functions),
    .get_function_name = sm8650_get_function_name,
  
  

-- 2.34.1