[U-Boot] [PATCH] 85xx if NUM_CPUS>1, print cpu number
Signed-off-by: Ed Swarthout Ed.Swarthout@freescale.com --- cpu/mpc85xx/cpu.c | 5 +++++ 1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index 67e81c0..bc7d092 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -98,7 +98,12 @@ int checkcpu (void) #endif minor = SVR_MIN(svr);
+#if (CONFIG_NUM_CPUS > 1) + volatile ccsr_pic_t *pic = (void *)(CFG_MPC85xx_PIC_ADDR); + printf("CPU%d: ", pic->whoami); +#else puts("CPU: "); +#endif
cpu = identify_cpu(ver); if (cpu) {
Signed-off-by: Ed Swarthout Ed.Swarthout@freescale.com --- drivers/pci/fsl_pci_init.c | 17 +++++++++++++++-- 1 files changed, 15 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index bb2813f..38a16e5 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c @@ -168,8 +168,21 @@ fsl_pci_init(struct pci_controller *hose) }
#ifndef CONFIG_PCI_NOSCAN - printf (" Scanning PCI bus %02x\n", hose->current_busno); - hose->last_busno = pci_hose_scan_bus(hose,hose->current_busno); + pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &temp8); + + /* Programming Interface (PCI_CLASS_PROG) + * 0 == pci host or pcie root-complex, + * 1 == pci agent or pcie end-point + */ + if (!temp8) { + printf(" Scanning PCI bus %02x\n", + hose->current_busno); + hose->last_busno = pci_hose_scan_bus(hose, hose->current_busno); + } else { + debug(" Not scanning PCI bus %02x. PI=%x\n", + hose->current_busno, temp8); + hose->last_busno = hose->current_busno; + }
if ( bridge ) { /* update limit regs and subordinate busno */ pciauto_postscan_setup_bridge(hose, dev, hose->last_busno);
Signed-off-by: Ed Swarthout Ed.Swarthout@freescale.com --- board/freescale/common/pixis.c | 4 ++++ 1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/board/freescale/common/pixis.c b/board/freescale/common/pixis.c index b5a0e84..8192bb3 100644 --- a/board/freescale/common/pixis.c +++ b/board/freescale/common/pixis.c @@ -453,7 +453,9 @@ pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) */ if ((p_cf && !(p_cf_sysclk && p_cf_corepll && p_cf_mpxpll)) || unknown_param) { +#ifdef CFG_LONGHELP puts(cmdtp->help); +#endif return 1; }
@@ -483,7 +485,9 @@ pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) if (!(set_px_sysclk(sysclk) && set_px_corepll(corepll) && set_px_mpxpll(mpxpll))) { +#ifdef CFG_LONGHELP puts(cmdtp->help); +#endif return 1; } read_from_px_regs(1);
Signed-off-by: Ed Swarthout Ed.Swarthout@freescale.com --- Makefile | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/Makefile b/Makefile index 7c13ce8..25ba4e5 100644 --- a/Makefile +++ b/Makefile @@ -243,9 +243,11 @@ endif ifeq ($(CPU),mpc85xx) LIBS += drivers/qe/qe.a LIBS += cpu/mpc8xxx/ddr/libddr.a +TAG_SUBDIRS += cpu/mpc8xxx endif ifeq ($(CPU),mpc86xx) LIBS += cpu/mpc8xxx/ddr/libddr.a +TAG_SUBDIRS += cpu/mpc8xxx endif LIBS += drivers/rtc/librtc.a LIBS += drivers/serial/libserial.a
On Wed, Oct 8, 2008 at 11:38 PM, Ed Swarthout Ed.Swarthout@freescale.com wrote:
Signed-off-by: Ed Swarthout Ed.Swarthout@freescale.com
Applied to 85xx-next
On Wed, Oct 8, 2008 at 11:38 PM, Ed Swarthout Ed.Swarthout@freescale.com wrote:
Signed-off-by: Ed Swarthout Ed.Swarthout@freescale.com
Applied to 85xx-next
On Wed, Oct 8, 2008 at 11:38 PM, Ed Swarthout Ed.Swarthout@freescale.com wrote:
Signed-off-by: Ed Swarthout Ed.Swarthout@freescale.com
Acked-by: Andy Fleming afleming@freescale.com
On Mon, 2008-10-13 at 14:14 -0500, Andy Fleming wrote:
On Wed, Oct 8, 2008 at 11:38 PM, Ed Swarthout Ed.Swarthout@freescale.com wrote:
Signed-off-by: Ed Swarthout Ed.Swarthout@freescale.com
Acked-by: Andy Fleming afleming@freescale.com
When agent/end-point, I thought the CPU must enable inbound PCI configuration cycles by poking the PBFR Register (offset 0x44) for PCI, or the Configuration Ready Register (offset 0x4b0 for PCIe) after configuring its own inbound BARs. I believe without these PCI config writes, the agent/end-point device will not be able to be enumerated by the PCI/PCIe host/root-comples as any config cycle to the device will be retried.
Would it make sense to add the unlocking of inbound PCI configuration cycles with this patch, or as a separate one? I have some basic code to do this, but wasn't sure of a clean way to determine if an interface is PCI or PCIe to determine how the interface should be unlocked (ie, the patch is a bit "dirty":).
Best, Peter
From: Peter Tyser [mailto:ptyser@xes-inc.com]
When agent/end-point, I thought the CPU must enable inbound PCI configuration cycles by poking the PBFR Register (offset 0x44) for PCI, or the Configuration Ready Register (offset 0x4b0 for PCIe) after configuring its own inbound BARs.
That is true if any of the CPUs are allowed to boot immediately after hreset. If all the CPUs have boot-holdoff set, hardware will enable inbound config.
I believe without these PCI config writes, the agent/end-point device will not be able to be enumerated by the PCI/PCIe host/root-comples as any config cycle to the device will be retried.
True.
Would it make sense to add the unlocking of inbound PCI configuration cycles with this patch, or as a separate one?
Separate.
Are there use cases where this should not be done in u-boot, but postponed until Linux is booted?
I have some basic code to do this, but wasn't sure of a clean way to determine if an interface is PCI or PCIe to determine how the interface should be unlocked (ie, the patch is a bit "dirty":).
I'm not sure of the best way for this determination. It looks like a non-zero value for the "PCI Express Capability ID Register" at 4c can be use to detect PCIe.
-Ed
Dear Ed Swarthout,
In message 1223527082-17061-2-git-send-email-Ed.Swarthout@freescale.com you wrote:
Signed-off-by: Ed Swarthout Ed.Swarthout@freescale.com
drivers/pci/fsl_pci_init.c | 17 +++++++++++++++-- 1 files changed, 15 insertions(+), 2 deletions(-)
Applied, thanks.
Best regards,
Wolfgang Denk
On Wed, Oct 8, 2008 at 11:37 PM, Ed Swarthout Ed.Swarthout@freescale.com wrote:
Signed-off-by: Ed Swarthout Ed.Swarthout@freescale.com
Applied to 85xx-next
participants (5)
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Andy Fleming -
Ed Swarthout -
Peter Tyser -
Swarthout Edward L
-
Wolfgang Denk