[U-Boot] [PATCH v2 0/22] x86: Add bare support for Intel Minnowboard Max
This series adds support for the Intel Minnowboard Max (called Minnowmax for short). Along the way a few refactors and additions are made:
- The Intel Firmware Support Package support is moved from queensbay to a common location - PCI support for XHCI is added - A few tweaks are made to the PCI support - Support for the debug UART (early debug output) is provided - The microcode tool now also supports reading in header files
This board has been lightly tested. The following seem to work:
- USB2 on the blue port (not USB3), e.g. for keyboard - Ethernet - HDMI out and console - UART - uSD card - SPI
SATA is detected but I have not attached a drive to try it. USB3 shows signs of life but does not detect a USB stick, and crashes when trying to use a USB Ethernet adaptor.
For SPI some parts cannot be read and others cannot be written. This seems to be a feature of the Intel hardware configuration. It may be possible to fix this using the SPI registers but I cannot work out how / lost interest trying. So far, addresses from 500000 to 700000 can be used.
I have not tried the ICH GPIO driver but it likely needs work before it will function. I2C is not supported as there is currently no U-Boot driver for this.
The zboot command can be used to start a bzImage kernel. Verified boot is supported - use mkimage to sign images as described in this walk-through: doc/uImage.FIT/beaglebone_vboot.txt
Boot time is grim: - 1423ms to set up display (Intel FSP) - 454ms to scan AHCI (when no devices are connected) - ~1000ms to power up and start cache-as-RAM init (Intel FSP) (this is not benchmarked, may be inaccurate) - ~950ms to set up memory and initial machine configuration (Intel FSP) (this is not benchmarked, may be inaccurate)
So it takes over 4 seconds to get to booting a kernel.
Implementing the Memory Reference Code (MRC) cache should improve this slightly (perhaps a reduction of 500-1000ms). This cache is implemented for ivybridge so that code needs to be moved into a generic x86 directory and plumbed into the FSP code. This has not been done in this series. Also the video and SATA/AHCI can be disabled if preferred.
It is also possible to run as a coreboot payload. See the instructions in README.x86 for this. In this case video does not work since coreboot does not pass through the VESA display information.
To support the single-core 1GB variant, changes would need to be made to arch/x86/cpu/baytrail/fsp_configs.c to select different values for the memory. The microcode update may need to change also.
This series is available at u-boot-x86 branch minnow-working.
Changes in v2: - Fix missing spaces (code style nit) - Add another comment in pci_find_class() - Fix README typos - Rename MMCONF_BASE_ADDRESS to PCIE_ECAM_BASE - Adjust the Kconfig help according to Bin's comments - Rename pci_rom_emul_t to pci_rom_emul - Move MMC code into a new pci_mmc.c file - Remove setup_early_uart() function prototype - Remove duplicate prototype of setup_early_uart() - Document how to change the SPI speed with ifdtool - Move CONFIG_SYS_CACHELINE_SIZE to the board CONFIG file - Add comment about FSP setting PCIE_ECAM_BASE - Put baytrail Kconfig in alphabetical order - Remove superfluous check for CONFIG_DEBUG_UART in setup_early_uart() - Fix compatible string for SPI flash - Remove commented-out DEBUG_UART_CLOCK baud rate - Rename 'Coreboot' to 'coreboot' in README.x86
Simon Glass (22): x86: Enhance the microcode tool to support header files as input pci: Add a function to find a device by class x86: pci: Add PCI IDs for Minnowboard Max x86: video: Enable video for Minnowboard Max usb: pci: Use pci_find_class() to find the device usb: pci: Add XHCI driver for PCI x86: Add an option to enabling building a ROM file x86: Rename MMCONF_BASE_ADDRESS and make it common across x86 x86: video: Allow video ROM execution to fall back to the other method x86: bootstage: Add time measurement for vesa start-up x86: Move common FSP code into a common location x86: Adjust the FSP types slightly x86: Make CAR and DRAM FSP code common x86: mmc: Move common FSP functions into a common file x86: Remove unnecessary casts and fix comment typos x86: Allow FSP Kconfig settings for all x86 x86: Allow a UART to be set up before the FSP is ready x86: spi: Support ValleyView in ICH SPI driver scsi: bootstage: Measure time taken to scan the bus x86: Enable bootstage features x86: Add some documentation on how to port U-Boot on x86 x86: Add support for Intel Minnowboard Max
Makefile | 5 +- arch/x86/Kconfig | 67 + arch/x86/cpu/Makefile | 1 + arch/x86/cpu/baytrail/Kconfig | 9 + arch/x86/cpu/baytrail/Makefile | 10 + arch/x86/cpu/baytrail/early_uart.c | 78 + arch/x86/cpu/baytrail/fsp_configs.c | 156 + arch/x86/cpu/baytrail/pci.c | 47 + arch/x86/cpu/baytrail/valleyview.c | 38 + arch/x86/cpu/ivybridge/gma.c | 3 +- arch/x86/cpu/ivybridge/sdram.c | 2 +- arch/x86/cpu/queensbay/Kconfig | 38 - arch/x86/cpu/queensbay/Makefile | 4 +- arch/x86/cpu/queensbay/fsp_configs.c | 2 +- arch/x86/cpu/queensbay/tnc.c | 29 +- arch/x86/cpu/queensbay/tnc_pci.c | 17 +- arch/x86/cpu/queensbay/topcliff.c | 33 +- arch/x86/dts/Makefile | 3 +- arch/x86/dts/microcode/m0130673322.dtsi | 3284 ++++++++++++++++++++ arch/x86/dts/minnowmax.dts | 45 + arch/x86/dts/serial.dtsi | 2 +- arch/x86/include/asm/arch-baytrail/fsp/azalia.h | 39 + arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h | 95 + arch/x86/include/asm/arch-baytrail/gpio.h | 13 + arch/x86/include/asm/arch-ivybridge/sandybridge.h | 2 +- arch/x86/include/asm/arch-queensbay/fsp/fsp_vpd.h | 2 - .../include/asm/{arch-queensbay => }/fsp/fsp_api.h | 6 +- .../asm/{arch-queensbay => }/fsp/fsp_bootmode.h | 0 .../include/asm/{arch-queensbay => }/fsp/fsp_ffs.h | 0 .../include/asm/{arch-queensbay => }/fsp/fsp_fv.h | 0 .../include/asm/{arch-queensbay => }/fsp/fsp_hob.h | 0 .../asm/{arch-queensbay => }/fsp/fsp_infoheader.h | 0 .../asm/{arch-queensbay => }/fsp/fsp_platform.h | 0 .../asm/{arch-queensbay => }/fsp/fsp_support.h | 6 +- .../asm/{arch-queensbay => }/fsp/fsp_types.h | 0 arch/x86/include/asm/u-boot-x86.h | 3 + arch/x86/lib/Makefile | 1 + arch/x86/lib/cmd_hob.c | 2 +- arch/x86/lib/fsp/Makefile | 10 + .../{cpu/queensbay/tnc_car.S => lib/fsp/fsp_car.S} | 0 arch/x86/lib/fsp/fsp_common.c | 55 + .../queensbay/tnc_dram.c => lib/fsp/fsp_dram.c} | 2 +- arch/x86/{cpu/queensbay => lib/fsp}/fsp_support.c | 20 +- board/google/chromebook_link/Kconfig | 3 +- board/intel/minnowmax/Kconfig | 30 + board/intel/minnowmax/MAINTAINERS | 6 + board/intel/minnowmax/Makefile | 7 + board/intel/minnowmax/minnowmax.c | 32 + board/intel/minnowmax/start.S | 9 + common/cmd_scsi.c | 2 + configs/minnowmax_defconfig | 13 + doc/README.x86 | 121 +- drivers/mmc/Makefile | 1 + drivers/mmc/pci_mmc.c | 42 + drivers/pci/pci.c | 43 + drivers/pci/pci_rom.c | 32 +- drivers/spi/ich.c | 56 +- drivers/spi/ich.h | 11 +- drivers/usb/host/Makefile | 1 + drivers/usb/host/ehci-pci.c | 53 +- drivers/usb/host/xhci-pci.c | 60 + drivers/video/vesa_fb.c | 9 +- include/bootstage.h | 1 + include/configs/minnowmax.h | 72 + include/configs/x86-common.h | 3 + include/mmc.h | 14 + include/pci.h | 3 +- include/pci_ids.h | 5 + include/pci_rom.h | 15 +- tools/microcode-tool.py | 90 +- 70 files changed, 4608 insertions(+), 255 deletions(-) create mode 100644 arch/x86/cpu/baytrail/Kconfig create mode 100644 arch/x86/cpu/baytrail/Makefile create mode 100644 arch/x86/cpu/baytrail/early_uart.c create mode 100644 arch/x86/cpu/baytrail/fsp_configs.c create mode 100644 arch/x86/cpu/baytrail/pci.c create mode 100644 arch/x86/cpu/baytrail/valleyview.c create mode 100644 arch/x86/dts/microcode/m0130673322.dtsi create mode 100644 arch/x86/dts/minnowmax.dts create mode 100644 arch/x86/include/asm/arch-baytrail/fsp/azalia.h create mode 100644 arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h create mode 100644 arch/x86/include/asm/arch-baytrail/gpio.h rename arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_api.h (88%) rename arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_bootmode.h (100%) rename arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_ffs.h (100%) rename arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_fv.h (100%) rename arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_hob.h (100%) rename arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_infoheader.h (100%) rename arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_platform.h (100%) rename arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_support.h (98%) rename arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_types.h (100%) create mode 100644 arch/x86/lib/fsp/Makefile rename arch/x86/{cpu/queensbay/tnc_car.S => lib/fsp/fsp_car.S} (100%) create mode 100644 arch/x86/lib/fsp/fsp_common.c rename arch/x86/{cpu/queensbay/tnc_dram.c => lib/fsp/fsp_dram.c} (98%) rename arch/x86/{cpu/queensbay => lib/fsp}/fsp_support.c (96%) create mode 100644 board/intel/minnowmax/Kconfig create mode 100644 board/intel/minnowmax/MAINTAINERS create mode 100644 board/intel/minnowmax/Makefile create mode 100644 board/intel/minnowmax/minnowmax.c create mode 100644 board/intel/minnowmax/start.S create mode 100644 configs/minnowmax_defconfig create mode 100644 drivers/mmc/pci_mmc.c create mode 100644 drivers/usb/host/xhci-pci.c create mode 100644 include/configs/minnowmax.h
Sometimes microcode is delivered as a header file. Allow the tool to support this as well as collecting multiple microcode blocks into a single update.
Signed-off-by: Simon Glass sjg@chromium.org Tested-by: Bin Meng bmeng.cn@gmail.com ---
Changes in v2: None
tools/microcode-tool.py | 90 ++++++++++++++++++++++++++++++++++++++----------- 1 file changed, 70 insertions(+), 20 deletions(-)
diff --git a/tools/microcode-tool.py b/tools/microcode-tool.py index 003716d..71c2e91 100755 --- a/tools/microcode-tool.py +++ b/tools/microcode-tool.py @@ -76,6 +76,35 @@ def ParseFile(fname): microcodes[name] = Microcode(name, data) return date, license_text, microcodes
+def ParseHeaderFiles(fname_list): + """Parse a list of header files and return the component parts + + Args: + fname_list: List of files to parse + Returns: + date: String containing date from the file's header + license_text: List of text lines for the license file + microcodes: List of Microcode objects from the file + """ + microcodes = {} + license_text = [] + date = '' + name = None + for fname in fname_list: + name = os.path.basename(fname).lower() + name = os.path.splitext(name)[0] + data = [] + with open(fname) as fd: + for line in fd: + line = line.rstrip() + + # Omit anything after the last comma + words = line.split(',')[:-1] + data += [word + ',' for word in words] + microcodes[name] = Microcode(name, data) + return date, license_text, microcodes + + def List(date, microcodes, model): """List the available microcode chunks
@@ -129,13 +158,13 @@ def FindMicrocode(microcodes, model): break return found, tried
-def CreateFile(date, license_text, mcode, outfile): +def CreateFile(date, license_text, mcodes, outfile): """Create a microcode file in U-Boot's .dtsi format
Args: date: String containing date of original microcode file license: List of text lines for the license file - mcode: Microcode object to write + mcodes: Microcode objects to write (normally only 1) outfile: Filename to write to ('-' for stdout) """ out = '''/*%s @@ -159,15 +188,22 @@ intel,processor-flags = <%#x>; data = <%s \t>;''' words = '' - for i in range(len(mcode.words)): - if not (i & 3): - words += '\n' - val = mcode.words[i] - # Change each word so it will be little-endian in the FDT - # This data is needed before RAM is available on some platforms so we - # cannot do an endianness swap on boot. - val = struct.unpack("<I", struct.pack(">I", val))[0] - words += '\t%#010x' % val + add_comments = len(mcodes) > 1 + for mcode in mcodes: + if add_comments: + words += '\n/* %s */' % mcode.name + for i in range(len(mcode.words)): + if not (i & 3): + words += '\n' + val = mcode.words[i] + # Change each word so it will be little-endian in the FDT + # This data is needed before RAM is available on some platforms so + # we cannot do an endianness swap on boot. + val = struct.unpack("<I", struct.pack(">I", val))[0] + words += '\t%#010x' % val + + # Use the first microcode for the headers + mcode = mcodes[0]
# Take care to avoid adding a space before a tab text = '' @@ -187,8 +223,8 @@ data = <%s print >> sys.stderr, "Creating directory '%s'" % MICROCODE_DIR os.makedirs(MICROCODE_DIR) outfile = os.path.join(MICROCODE_DIR, mcode.name + '.dtsi') - print >> sys.stderr, "Writing microcode for '%s' to '%s'" % ( - mcode.name, outfile) + print >> sys.stderr, "Writing microcode for '%s' to '%s'" % ( + ', '.join([mcode.name for mcode in mcodes]), outfile) with open(outfile, 'w') as fd: print >> fd, out % tuple(args)
@@ -198,8 +234,12 @@ def MicrocodeTool(): parser = OptionParser() parser.add_option('-d', '--mcfile', type='string', action='store', help='Name of microcode.dat file') + parser.add_option('-H', '--headerfile', type='string', action='append', + help='Name of .h file containing microcode') parser.add_option('-m', '--model', type='string', action='store', - help='Model name to extract') + help="Model name to extract ('all' for all)") + parser.add_option('-M', '--multiple', type='string', action='store', + help="Allow output of multiple models") parser.add_option('-o', '--outfile', type='string', action='store', help='Filename to use for output (- for stdout), default is' ' %s/<name>.dtsi' % MICROCODE_DIR) @@ -224,9 +264,14 @@ def MicrocodeTool(): if cmd not in commands: parser.error("Unknown command '%s'" % cmd)
- if not options.mcfile: - parser.error('You must specify a microcode file') - date, license_text, microcodes = ParseFile(options.mcfile) + if (not not options.mcfile) != (not not options.mcfile): + parser.error("You must specify either header files or a microcode file, not both") + if options.headerfile: + date, license_text, microcodes = ParseHeaderFiles(options.headerfile) + elif options.mcfile: + date, license_text, microcodes = ParseFile(options.mcfile) + else: + parser.error('You must specify a microcode file (or header files)')
if cmd == 'list': List(date, microcodes, options.model) @@ -236,16 +281,21 @@ def MicrocodeTool(): if not options.model: parser.error('You must specify a model to create') model = options.model.lower() - mcode_list, tried = FindMicrocode(microcodes, model) + if options.model == 'all': + options.multiple = True + mcode_list = microcodes.values() + tried = [] + else: + mcode_list, tried = FindMicrocode(microcodes, model) if not mcode_list: parser.error("Unknown model '%s' (%s) - try 'list' to list" % (model, ', '.join(tried))) - if len(mcode_list) > 1: + if not options.multiple and len(mcode_list) > 1: parser.error("Ambiguous model '%s' (%s) matched %s - try 'list' " "to list or specify a particular file" % (model, ', '.join(tried), ', '.join([m.name for m in mcode_list]))) - CreateFile(date, license_text, mcode_list[0], options.outfile) + CreateFile(date, license_text, mcode_list, options.outfile) else: parser.error("Unknown command '%s'" % cmd)
On 27 January 2015 at 21:13, Simon Glass sjg@chromium.org wrote:
Sometimes microcode is delivered as a header file. Allow the tool to support this as well as collecting multiple microcode blocks into a single update.
Signed-off-by: Simon Glass sjg@chromium.org Tested-by: Bin Meng bmeng.cn@gmail.com
Changes in v2: None
tools/microcode-tool.py | 90 ++++++++++++++++++++++++++++++++++++++----------- 1 file changed, 70 insertions(+), 20 deletions(-)
Applied to u-boot-x86.
There is an existing function prototype in the header file but it is not implemented. Implement something similar.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: - Fix missing spaces (code style nit) - Add another comment in pci_find_class()
drivers/pci/pci.c | 43 +++++++++++++++++++++++++++++++++++++++++++ include/pci.h | 3 +-- 2 files changed, 44 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 950a247..0210e41 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -15,6 +15,7 @@ #include <common.h>
#include <command.h> +#include <errno.h> #include <asm/processor.h> #include <asm/io.h> #include <pci.h> @@ -236,6 +237,48 @@ pci_dev_t pci_find_devices(struct pci_device_id *ids, int index) return -1; }
+pci_dev_t pci_find_class(uint find_class, int index) +{ + int bus; + int devnum; + pci_dev_t bdf; + uint32_t class; + + for (bus = 0; bus <= pci_last_busno(); bus++) { + for (devnum = 0; devnum < PCI_MAX_PCI_DEVICES - 1; devnum++) { + pci_read_config_dword(PCI_BDF(bus, devnum, 0), + PCI_CLASS_REVISION, &class); + if (class >> 16 == 0xffff) + continue; + + for (bdf = PCI_BDF(bus, devnum, 0); + bdf <= PCI_BDF(bus, devnum, + PCI_MAX_PCI_FUNCTIONS - 1); + bdf += PCI_BDF(0, 0, 1)) { + pci_read_config_dword(bdf, PCI_CLASS_REVISION, + &class); + class >>= 8; + + if (class != find_class) + continue; + /* + * Decrement the index. We want to return the + * correct device, so index is 0 for theh first + * matching device, 1 for the second, etc. + */ + if (index) { + index--; + continue; + } + /* Return index'th controller. */ + return bdf; + } + } + } + + return -ENODEV; +} + pci_dev_t pci_find_device(unsigned int vendor, unsigned int device, int index) { struct pci_device_id ids[2] = { {}, {0, 0} }; diff --git a/include/pci.h b/include/pci.h index 4fbb8f6..004a048 100644 --- a/include/pci.h +++ b/include/pci.h @@ -644,8 +644,7 @@ extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev);
extern pci_dev_t pci_find_device (unsigned int vendor, unsigned int device, int index); extern pci_dev_t pci_find_devices (struct pci_device_id *ids, int index); -extern pci_dev_t pci_find_class(int wanted_class, int wanted_sub_code, - int wanted_prog_if, int index); +pci_dev_t pci_find_class(unsigned int find_class, int index);
extern int pci_hose_config_device(struct pci_controller *hose, pci_dev_t dev,
Hi Simon,
On Wed, Jan 28, 2015 at 1:13 PM, Simon Glass sjg@chromium.org wrote:
There is an existing function prototype in the header file but it is not implemented. Implement something similar.
Signed-off-by: Simon Glass sjg@chromium.org
Reviewed-by: Bin Meng bmeng.cn@gmail.com
One typo below and I think you can fix it before applying.
Changes in v2:
- Fix missing spaces (code style nit)
- Add another comment in pci_find_class()
drivers/pci/pci.c | 43 +++++++++++++++++++++++++++++++++++++++++++ include/pci.h | 3 +-- 2 files changed, 44 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 950a247..0210e41 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -15,6 +15,7 @@ #include <common.h>
#include <command.h> +#include <errno.h> #include <asm/processor.h> #include <asm/io.h> #include <pci.h> @@ -236,6 +237,48 @@ pci_dev_t pci_find_devices(struct pci_device_id *ids, int index) return -1; }
+pci_dev_t pci_find_class(uint find_class, int index) +{
int bus;int devnum;pci_dev_t bdf;uint32_t class;for (bus = 0; bus <= pci_last_busno(); bus++) {for (devnum = 0; devnum < PCI_MAX_PCI_DEVICES - 1; devnum++) {pci_read_config_dword(PCI_BDF(bus, devnum, 0),PCI_CLASS_REVISION, &class);if (class >> 16 == 0xffff)continue;for (bdf = PCI_BDF(bus, devnum, 0);bdf <= PCI_BDF(bus, devnum,PCI_MAX_PCI_FUNCTIONS - 1);bdf += PCI_BDF(0, 0, 1)) {pci_read_config_dword(bdf, PCI_CLASS_REVISION,&class);class >>= 8;if (class != find_class)continue;/** Decrement the index. We want to return the* correct device, so index is 0 for theh first
theh -> the
* matching device, 1 for the second, etc.*/if (index) {index--;continue;}/* Return index'th controller. */return bdf;}}}return -ENODEV;+}
pci_dev_t pci_find_device(unsigned int vendor, unsigned int device, int index) { struct pci_device_id ids[2] = { {}, {0, 0} }; diff --git a/include/pci.h b/include/pci.h index 4fbb8f6..004a048 100644 --- a/include/pci.h +++ b/include/pci.h @@ -644,8 +644,7 @@ extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev);
extern pci_dev_t pci_find_device (unsigned int vendor, unsigned int device, int index); extern pci_dev_t pci_find_devices (struct pci_device_id *ids, int index); -extern pci_dev_t pci_find_class(int wanted_class, int wanted_sub_code,
int wanted_prog_if, int index);+pci_dev_t pci_find_class(unsigned int find_class, int index);
extern int pci_hose_config_device(struct pci_controller *hose, pci_dev_t dev, --
Regards, Bin
On 27 January 2015 at 22:30, Bin Meng bmeng.cn@gmail.com wrote:
Hi Simon,
On Wed, Jan 28, 2015 at 1:13 PM, Simon Glass sjg@chromium.org wrote:
There is an existing function prototype in the header file but it is not implemented. Implement something similar.
Signed-off-by: Simon Glass sjg@chromium.org
Reviewed-by: Bin Meng bmeng.cn@gmail.com
One typo below and I think you can fix it before applying.
Changes in v2:
- Fix missing spaces (code style nit)
- Add another comment in pci_find_class()
drivers/pci/pci.c | 43 +++++++++++++++++++++++++++++++++++++++++++ include/pci.h | 3 +-- 2 files changed, 44 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 950a247..0210e41 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -15,6 +15,7 @@ #include <common.h>
#include <command.h> +#include <errno.h> #include <asm/processor.h> #include <asm/io.h> #include <pci.h> @@ -236,6 +237,48 @@ pci_dev_t pci_find_devices(struct pci_device_id *ids, int index) return -1; }
+pci_dev_t pci_find_class(uint find_class, int index) +{
int bus;int devnum;pci_dev_t bdf;uint32_t class;for (bus = 0; bus <= pci_last_busno(); bus++) {for (devnum = 0; devnum < PCI_MAX_PCI_DEVICES - 1; devnum++) {pci_read_config_dword(PCI_BDF(bus, devnum, 0),PCI_CLASS_REVISION, &class);if (class >> 16 == 0xffff)continue;for (bdf = PCI_BDF(bus, devnum, 0);bdf <= PCI_BDF(bus, devnum,PCI_MAX_PCI_FUNCTIONS - 1);bdf += PCI_BDF(0, 0, 1)) {pci_read_config_dword(bdf, PCI_CLASS_REVISION,&class);class >>= 8;if (class != find_class)continue;/** Decrement the index. We want to return the* correct device, so index is 0 for theh firsttheh -> the
* matching device, 1 for the second, etc.*/if (index) {index--;continue;}/* Return index'th controller. */return bdf;}}}return -ENODEV;+}
pci_dev_t pci_find_device(unsigned int vendor, unsigned int device, int index) { struct pci_device_id ids[2] = { {}, {0, 0} }; diff --git a/include/pci.h b/include/pci.h index 4fbb8f6..004a048 100644 --- a/include/pci.h +++ b/include/pci.h @@ -644,8 +644,7 @@ extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev);
extern pci_dev_t pci_find_device (unsigned int vendor, unsigned int device, int index); extern pci_dev_t pci_find_devices (struct pci_device_id *ids, int index); -extern pci_dev_t pci_find_class(int wanted_class, int wanted_sub_code,
int wanted_prog_if, int index);+pci_dev_t pci_find_class(unsigned int find_class, int index);
extern int pci_hose_config_device(struct pci_controller *hose, pci_dev_t dev, --
Regards, Bin
Fixed, applied to u-boot-x86.
This board includes a few IDs we have not seen before.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---
Changes in v2: None
include/pci_ids.h | 5 +++++ 1 file changed, 5 insertions(+)
diff --git a/include/pci_ids.h b/include/pci_ids.h index 26f4748..1012abe 100644 --- a/include/pci_ids.h +++ b/include/pci_ids.h @@ -1346,6 +1346,7 @@
#define PCI_VENDOR_ID_REALTEK 0x10ec #define PCI_DEVICE_ID_REALTEK_8139 0x8139 +#define PCI_DEVICE_ID_REALTEK_8168 0x8168
#define PCI_VENDOR_ID_XILINX 0x10ee #define PCI_DEVICE_ID_RME_DIGI96 0x3fc0 @@ -2594,6 +2595,10 @@ #define PCI_DEVICE_ID_INTEL_I960 0x0960 #define PCI_DEVICE_ID_INTEL_I960RM 0x0962 #define PCI_DEVICE_ID_INTEL_CENTERTON_ILB 0x0c60 +#define PCI_DEVICE_ID_INTEL_VALLEYVIEW_SDIO 0x0f15 +#define PCI_DEVICE_ID_INTEL_VALLEYVIEW_SDCARD 0x0f16 +#define PCI_DEVICE_ID_INTEL_VALLEYVIEW_LPC 0x0f1c +#define PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA 0x0f23 #define PCI_DEVICE_ID_INTEL_82541ER 0x1078 #define PCI_DEVICE_ID_INTEL_82541GI_LF 0x107c #define PCI_DEVICE_ID_INTEL_82542 0x1000
On 27 January 2015 at 21:13, Simon Glass sjg@chromium.org wrote:
This board includes a few IDs we have not seen before.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com
Changes in v2: None
include/pci_ids.h | 5 +++++ 1 file changed, 5 insertions(+)
Applied to u-boot-x86.
This board uses a new PCI ID.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---
Changes in v2: None
drivers/video/vesa_fb.c | 1 + 1 file changed, 1 insertion(+)
diff --git a/drivers/video/vesa_fb.c b/drivers/video/vesa_fb.c index 3dacafd..3a0fea2 100644 --- a/drivers/video/vesa_fb.c +++ b/drivers/video/vesa_fb.c @@ -23,6 +23,7 @@ struct pci_device_id vesa_video_ids[] = { { .vendor = 0x1002, .device = 0x5159 }, { .vendor = 0x1002, .device = 0x4752 }, { .vendor = 0x1002, .device = 0x5452 }, + { .vendor = 0x8086, .device = 0x0f31 }, {}, };
On 27 January 2015 at 21:13, Simon Glass sjg@chromium.org wrote:
This board uses a new PCI ID.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com
Changes in v2: None
drivers/video/vesa_fb.c | 1 + 1 file changed, 1 insertion(+)
Applied to u-boot-x86.
Use the new utility function instead of local code.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---
Changes in v2: None
drivers/usb/host/ehci-pci.c | 53 +-------------------------------------------- 1 file changed, 1 insertion(+), 52 deletions(-)
diff --git a/drivers/usb/host/ehci-pci.c b/drivers/usb/host/ehci-pci.c index 991b199..b9eabc5 100644 --- a/drivers/usb/host/ehci-pci.c +++ b/drivers/usb/host/ehci-pci.c @@ -34,57 +34,6 @@ static struct pci_device_id ehci_pci_ids[] = { {0, 0} }; #else -static pci_dev_t ehci_find_class(int index) -{ - int bus; - int devnum; - pci_dev_t bdf; - uint32_t class; - - for (bus = 0; bus <= pci_last_busno(); bus++) { - for (devnum = 0; devnum < PCI_MAX_PCI_DEVICES-1; devnum++) { - pci_read_config_dword(PCI_BDF(bus, devnum, 0), - PCI_CLASS_REVISION, &class); - if (class >> 16 == 0xffff) - continue; - - for (bdf = PCI_BDF(bus, devnum, 0); - bdf <= PCI_BDF(bus, devnum, - PCI_MAX_PCI_FUNCTIONS - 1); - bdf += PCI_BDF(0, 0, 1)) { - pci_read_config_dword(bdf, PCI_CLASS_REVISION, - &class); - class >>= 8; - /* - * Here be dragons! In case we have multiple - * PCI EHCI controllers, this function will - * be called multiple times as well. This - * function will scan the PCI busses, always - * starting from bus 0, device 0, function 0, - * until it finds an USB controller. The USB - * stack gives us an 'index' of a controller - * that is currently being registered, which - * is a number, starting from 0 and growing - * in ascending order as controllers are added. - * To avoid probing the same controller in tne - * subsequent runs of this function, we will - * skip 'index - 1' detected controllers and - * report the index'th controller. - */ - if (class != PCI_CLASS_SERIAL_USB_EHCI) - continue; - if (index) { - index--; - continue; - } - /* Return index'th controller. */ - return bdf; - } - } - } - - return -ENODEV; -} #endif
/* @@ -102,7 +51,7 @@ int ehci_hcd_init(int index, enum usb_init_type init, #ifdef CONFIG_PCI_EHCI_DEVICE pdev = pci_find_devices(ehci_pci_ids, CONFIG_PCI_EHCI_DEVICE); #else - pdev = ehci_find_class(index); + pdev = pci_find_class(PCI_CLASS_SERIAL_USB_EHCI, index); #endif if (pdev < 0) { printf("EHCI host controller not found\n");
On 27 January 2015 at 21:13, Simon Glass sjg@chromium.org wrote:
Use the new utility function instead of local code.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com
Changes in v2: None
drivers/usb/host/ehci-pci.c | 53 +-------------------------------------------- 1 file changed, 1 insertion(+), 52 deletions(-)
Applied to u-boot-x86.
Add a driver which locates the available XHCI controllers on the PCI bus and makes them available.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---
Changes in v2: None
drivers/usb/host/Makefile | 1 + drivers/usb/host/xhci-pci.c | 60 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 61 insertions(+) create mode 100644 drivers/usb/host/xhci-pci.c
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile index c11b551..66d6e9a 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile @@ -47,6 +47,7 @@ obj-$(CONFIG_USB_XHCI) += xhci.o xhci-mem.o xhci-ring.o obj-$(CONFIG_USB_XHCI_KEYSTONE) += xhci-keystone.o obj-$(CONFIG_USB_XHCI_EXYNOS) += xhci-exynos5.o obj-$(CONFIG_USB_XHCI_OMAP) += xhci-omap.o +obj-$(CONFIG_USB_XHCI_PCI) += xhci-pci.o
# designware obj-$(CONFIG_USB_DWC2) += dwc2.o diff --git a/drivers/usb/host/xhci-pci.c b/drivers/usb/host/xhci-pci.c new file mode 100644 index 0000000..361fcce --- /dev/null +++ b/drivers/usb/host/xhci-pci.c @@ -0,0 +1,60 @@ +/* + * Copyright (c) 2015, Google, Inc + * Written by Simon Glass sjg@chromium.org + * All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <errno.h> +#include <pci.h> +#include <usb.h> + +#include "xhci.h" + +/* + * Create the appropriate control structures to manage a new XHCI host + * controller. + */ +int xhci_hcd_init(int index, struct xhci_hccr **ret_hccr, + struct xhci_hcor **ret_hcor) +{ + struct xhci_hccr *hccr; + struct xhci_hcor *hcor; + pci_dev_t pdev; + uint32_t cmd; + int len; + + pdev = pci_find_class(PCI_CLASS_SERIAL_USB_XHCI, index); + if (pdev < 0) { + printf("XHCI host controller not found\n"); + return -1; + } + + hccr = (struct xhci_hccr *)pci_map_bar(pdev, + PCI_BASE_ADDRESS_0, PCI_REGION_MEM); + len = HC_LENGTH(xhci_readl(&hccr->cr_capbase)); + hcor = (struct xhci_hcor *)((uint32_t)hccr + len); + + debug("XHCI-PCI init hccr 0x%x and hcor 0x%x hc_length %d\n", + (uint32_t)hccr, (uint32_t)hcor, len); + + *ret_hccr = hccr; + *ret_hcor = hcor; + + /* enable busmaster */ + pci_read_config_dword(pdev, PCI_COMMAND, &cmd); + cmd |= PCI_COMMAND_MASTER; + pci_write_config_dword(pdev, PCI_COMMAND, cmd); + + return 0; +} + +/* + * Destroy the appropriate control structures corresponding * to the XHCI host + * controller + */ +void xhci_hcd_stop(int index) +{ +}
On 27 January 2015 at 21:13, Simon Glass sjg@chromium.org wrote:
Add a driver which locates the available XHCI controllers on the PCI bus and makes them available.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com
Changes in v2: None
drivers/usb/host/Makefile | 1 + drivers/usb/host/xhci-pci.c | 60 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 61 insertions(+) create mode 100644 drivers/usb/host/xhci-pci.c
Applied to u-boot-x86.
Rather than requiring the Makefile to be modified, provide a build option to enable the ROM to be built.
We cannot do this by default since it requires binary blobs. Without these the build will fail.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: - Fix README typos
Makefile | 5 +++-- doc/README.x86 | 10 ++++++---- 2 files changed, 9 insertions(+), 6 deletions(-)
diff --git a/Makefile b/Makefile index a876f1f..c6e4ad1 100644 --- a/Makefile +++ b/Makefile @@ -729,8 +729,9 @@ ALL-$(CONFIG_SPL) += $(CONFIG_SPL_TARGET:"%"=%) endif ALL-$(CONFIG_REMAKE_ELF) += u-boot.elf
-# We can't do this yet due to the need for binary blobs -# ALL-$(CONFIG_X86_RESET_VECTOR) += u-boot.rom +ifneq ($(BUILD_ROM),) +ALL-$(CONFIG_X86_RESET_VECTOR) += u-boot.rom +endif
# enable combined SPL/u-boot/dtb rules for tegra ifneq ($(CONFIG_TEGRA),) diff --git a/doc/README.x86 b/doc/README.x86 index 7df8cc5..ddfd75e 100644 --- a/doc/README.x86 +++ b/doc/README.x86 @@ -51,9 +51,11 @@ Building ROM version of U-Boot (hereafter referred to as u-boot.rom) is a little bit tricky, as generally it requires several binary blobs which are not shipped in the U-Boot source tree. Due to this reason, the u-boot.rom build is not turned on by default in the U-Boot source tree. Firstly, you need turn it -on by uncommenting the following line in the main U-Boot Makefile: +on by enabling the ROM build:
-# ALL-$(CONFIG_X86_RESET_VECTOR) += u-boot.rom +$ export BUILD_ROM=y + +This tells the Makefile to build u-boot.rom as a target.
Link-specific instructions:
@@ -126,11 +128,11 @@ Make sure 0x1110000 matches CONFIG_SYS_TEXT_BASE and 0x1110015 matches the symbol address of _start (in arch/x86/cpu/start.S).
If you want to use ELF as the coreboot payload, change U-Boot configuration to -use CONFIG_OF_EMBED. +use CONFIG_OF_EMBED instead of CONFIG_OF_SEPARATE.
CPU Microcode ------------- -Modern CPU usually requires a special bit stream called microcode [5] to be +Modern CPUs usually require a special bit stream called microcode [5] to be loaded on the processor after power up in order to function properly. U-Boot has already integrated these as hex dumps in the source tree.
On Wed, Jan 28, 2015 at 1:13 PM, Simon Glass sjg@chromium.org wrote:
Rather than requiring the Makefile to be modified, provide a build option to enable the ROM to be built.
We cannot do this by default since it requires binary blobs. Without these the build will fail.
Signed-off-by: Simon Glass sjg@chromium.org
Changes in v2:
- Fix README typos
Makefile | 5 +++-- doc/README.x86 | 10 ++++++---- 2 files changed, 9 insertions(+), 6 deletions(-)
diff --git a/Makefile b/Makefile index a876f1f..c6e4ad1 100644 --- a/Makefile +++ b/Makefile @@ -729,8 +729,9 @@ ALL-$(CONFIG_SPL) += $(CONFIG_SPL_TARGET:"%"=%) endif ALL-$(CONFIG_REMAKE_ELF) += u-boot.elf
-# We can't do this yet due to the need for binary blobs -# ALL-$(CONFIG_X86_RESET_VECTOR) += u-boot.rom +ifneq ($(BUILD_ROM),) +ALL-$(CONFIG_X86_RESET_VECTOR) += u-boot.rom +endif
# enable combined SPL/u-boot/dtb rules for tegra ifneq ($(CONFIG_TEGRA),) diff --git a/doc/README.x86 b/doc/README.x86 index 7df8cc5..ddfd75e 100644 --- a/doc/README.x86 +++ b/doc/README.x86 @@ -51,9 +51,11 @@ Building ROM version of U-Boot (hereafter referred to as u-boot.rom) is a little bit tricky, as generally it requires several binary blobs which are not shipped in the U-Boot source tree. Due to this reason, the u-boot.rom build is not turned on by default in the U-Boot source tree. Firstly, you need turn it -on by uncommenting the following line in the main U-Boot Makefile: +on by enabling the ROM build:
-# ALL-$(CONFIG_X86_RESET_VECTOR) += u-boot.rom +$ export BUILD_ROM=y
+This tells the Makefile to build u-boot.rom as a target.
Link-specific instructions:
@@ -126,11 +128,11 @@ Make sure 0x1110000 matches CONFIG_SYS_TEXT_BASE and 0x1110015 matches the symbol address of _start (in arch/x86/cpu/start.S).
If you want to use ELF as the coreboot payload, change U-Boot configuration to -use CONFIG_OF_EMBED. +use CONFIG_OF_EMBED instead of CONFIG_OF_SEPARATE.
CPU Microcode
-Modern CPU usually requires a special bit stream called microcode [5] to be +Modern CPUs usually require a special bit stream called microcode [5] to be loaded on the processor after power up in order to function properly. U-Boot has already integrated these as hex dumps in the source tree.
--
Reviewed-by: Bin Meng bmeng.cn@gmail.com
On 27 January 2015 at 21:32, Bin Meng bmeng.cn@gmail.com wrote:
On Wed, Jan 28, 2015 at 1:13 PM, Simon Glass sjg@chromium.org wrote:
Rather than requiring the Makefile to be modified, provide a build option to enable the ROM to be built.
We cannot do this by default since it requires binary blobs. Without these the build will fail.
Signed-off-by: Simon Glass sjg@chromium.org
Changes in v2:
- Fix README typos
Makefile | 5 +++-- doc/README.x86 | 10 ++++++---- 2 files changed, 9 insertions(+), 6 deletions(-)
diff --git a/Makefile b/Makefile index a876f1f..c6e4ad1 100644 --- a/Makefile +++ b/Makefile @@ -729,8 +729,9 @@ ALL-$(CONFIG_SPL) += $(CONFIG_SPL_TARGET:"%"=%) endif ALL-$(CONFIG_REMAKE_ELF) += u-boot.elf
-# We can't do this yet due to the need for binary blobs -# ALL-$(CONFIG_X86_RESET_VECTOR) += u-boot.rom +ifneq ($(BUILD_ROM),) +ALL-$(CONFIG_X86_RESET_VECTOR) += u-boot.rom +endif
# enable combined SPL/u-boot/dtb rules for tegra ifneq ($(CONFIG_TEGRA),) diff --git a/doc/README.x86 b/doc/README.x86 index 7df8cc5..ddfd75e 100644 --- a/doc/README.x86 +++ b/doc/README.x86 @@ -51,9 +51,11 @@ Building ROM version of U-Boot (hereafter referred to as u-boot.rom) is a little bit tricky, as generally it requires several binary blobs which are not shipped in the U-Boot source tree. Due to this reason, the u-boot.rom build is not turned on by default in the U-Boot source tree. Firstly, you need turn it -on by uncommenting the following line in the main U-Boot Makefile: +on by enabling the ROM build:
-# ALL-$(CONFIG_X86_RESET_VECTOR) += u-boot.rom +$ export BUILD_ROM=y
+This tells the Makefile to build u-boot.rom as a target.
Link-specific instructions:
@@ -126,11 +128,11 @@ Make sure 0x1110000 matches CONFIG_SYS_TEXT_BASE and 0x1110015 matches the symbol address of _start (in arch/x86/cpu/start.S).
If you want to use ELF as the coreboot payload, change U-Boot configuration to -use CONFIG_OF_EMBED. +use CONFIG_OF_EMBED instead of CONFIG_OF_SEPARATE.
CPU Microcode
-Modern CPU usually requires a special bit stream called microcode [5] to be +Modern CPUs usually require a special bit stream called microcode [5] to be loaded on the processor after power up in order to function properly. U-Boot has already integrated these as hex dumps in the source tree.
--
Reviewed-by: Bin Meng bmeng.cn@gmail.com
Applied to u-boot-x86.
This setting will be used by more than just ivybridge so make it common.
Also rename it to PCIE_ECAM_BASE which is a more descriptive name.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: - Rename MMCONF_BASE_ADDRESS to PCIE_ECAM_BASE - Adjust the Kconfig help according to Bin's comments
arch/x86/Kconfig | 14 ++++++++++++++ arch/x86/cpu/ivybridge/sdram.c | 2 +- arch/x86/include/asm/arch-ivybridge/sandybridge.h | 2 +- board/google/chromebook_link/Kconfig | 3 +-- 4 files changed, 17 insertions(+), 4 deletions(-)
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 90e828a..bda7a0e 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -356,4 +356,18 @@ source "board/google/chromebook_link/Kconfig"
source "board/intel/crownbay/Kconfig"
+config PCIE_ECAM_BASE + hex + default 0xe0000000 + help + This is the memory-mapped address of PCI configuration space, which + is only available through the Enhanced Configuration Access + Mechanism (ECAM) with PCI Express. It can be set up almost + anywhere. Before it is set up, it is possible to access PCI + configuration space through I/O access, but memory access is more + convenient. Using this, PCI can be scanned and configured. This + should be set to a region that does not conflict with memory + assigned to PCI devices - i.e. the memory and prefetch regions, as + passed to pci_set_region(). + endmenu diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c index 4963448..766b385 100644 --- a/arch/x86/cpu/ivybridge/sdram.c +++ b/arch/x86/cpu/ivybridge/sdram.c @@ -757,7 +757,7 @@ int dram_init(void) .mchbar = DEFAULT_MCHBAR, .dmibar = DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, + .pciexbar = CONFIG_PCIE_ECAM_BASE, .smbusbar = SMBUS_IO_BASE, .wdbbar = 0x4000000, .wdbsize = 0x1000, diff --git a/arch/x86/include/asm/arch-ivybridge/sandybridge.h b/arch/x86/include/asm/arch-ivybridge/sandybridge.h index cf7457f..c960525 100644 --- a/arch/x86/include/asm/arch-ivybridge/sandybridge.h +++ b/arch/x86/include/asm/arch-ivybridge/sandybridge.h @@ -43,7 +43,7 @@ #define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ #define DEFAULT_RCBABASE 0xfed1c000 /* 4 KB per PCIe device */ -#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS +#define DEFAULT_PCIEXBAR CONFIG_PCIE_ECAM_BASE
/* Device 0:0.0 PCI configuration space (Host Bridge) */ #define EPBAR 0x40 diff --git a/board/google/chromebook_link/Kconfig b/board/google/chromebook_link/Kconfig index 33a31f3..ea45472 100644 --- a/board/google/chromebook_link/Kconfig +++ b/board/google/chromebook_link/Kconfig @@ -22,8 +22,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MARK_GRAPHICS_MEM_WRCOMB select BOARD_ROMSIZE_KB_8192
-config MMCONF_BASE_ADDRESS - hex +config PCIE_ECAM_BASE default 0xf0000000
config EARLY_POST_CROS_EC
On Wed, Jan 28, 2015 at 1:13 PM, Simon Glass sjg@chromium.org wrote:
This setting will be used by more than just ivybridge so make it common.
Also rename it to PCIE_ECAM_BASE which is a more descriptive name.
Signed-off-by: Simon Glass sjg@chromium.org
Reviewed-by: Bin Meng bmeng.cn@gmail.com
Please see one minor issue below.
Changes in v2:
- Rename MMCONF_BASE_ADDRESS to PCIE_ECAM_BASE
- Adjust the Kconfig help according to Bin's comments
arch/x86/Kconfig | 14 ++++++++++++++ arch/x86/cpu/ivybridge/sdram.c | 2 +- arch/x86/include/asm/arch-ivybridge/sandybridge.h | 2 +- board/google/chromebook_link/Kconfig | 3 +-- 4 files changed, 17 insertions(+), 4 deletions(-)
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 90e828a..bda7a0e 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -356,4 +356,18 @@ source "board/google/chromebook_link/Kconfig"
source "board/intel/crownbay/Kconfig"
+config PCIE_ECAM_BASE
hexdefault 0xe0000000
Need make 'default' aligned. Sorry I did not point it out in the v1 review. You can fix it when applying.
helpThis is the memory-mapped address of PCI configuration space, whichis only available through the Enhanced Configuration AccessMechanism (ECAM) with PCI Express. It can be set up almostanywhere. Before it is set up, it is possible to access PCIconfiguration space through I/O access, but memory access is moreconvenient. Using this, PCI can be scanned and configured. Thisshould be set to a region that does not conflict with memoryassigned to PCI devices - i.e. the memory and prefetch regions, aspassed to pci_set_region().endmenu diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c index 4963448..766b385 100644 --- a/arch/x86/cpu/ivybridge/sdram.c +++ b/arch/x86/cpu/ivybridge/sdram.c @@ -757,7 +757,7 @@ int dram_init(void) .mchbar = DEFAULT_MCHBAR, .dmibar = DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR,
.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
.pciexbar = CONFIG_PCIE_ECAM_BASE, .smbusbar = SMBUS_IO_BASE, .wdbbar = 0x4000000, .wdbsize = 0x1000,diff --git a/arch/x86/include/asm/arch-ivybridge/sandybridge.h b/arch/x86/include/asm/arch-ivybridge/sandybridge.h index cf7457f..c960525 100644 --- a/arch/x86/include/asm/arch-ivybridge/sandybridge.h +++ b/arch/x86/include/asm/arch-ivybridge/sandybridge.h @@ -43,7 +43,7 @@ #define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ #define DEFAULT_RCBABASE 0xfed1c000 /* 4 KB per PCIe device */ -#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS +#define DEFAULT_PCIEXBAR CONFIG_PCIE_ECAM_BASE
/* Device 0:0.0 PCI configuration space (Host Bridge) */ #define EPBAR 0x40 diff --git a/board/google/chromebook_link/Kconfig b/board/google/chromebook_link/Kconfig index 33a31f3..ea45472 100644 --- a/board/google/chromebook_link/Kconfig +++ b/board/google/chromebook_link/Kconfig @@ -22,8 +22,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MARK_GRAPHICS_MEM_WRCOMB select BOARD_ROMSIZE_KB_8192
-config MMCONF_BASE_ADDRESS
hex+config PCIE_ECAM_BASE default 0xf0000000
config EARLY_POST_CROS_EC
Regards, Bin
On 27 January 2015 at 22:36, Bin Meng bmeng.cn@gmail.com wrote:
On Wed, Jan 28, 2015 at 1:13 PM, Simon Glass sjg@chromium.org wrote:
This setting will be used by more than just ivybridge so make it common.
Also rename it to PCIE_ECAM_BASE which is a more descriptive name.
Signed-off-by: Simon Glass sjg@chromium.org
Reviewed-by: Bin Meng bmeng.cn@gmail.com
Please see one minor issue below.
Changes in v2:
- Rename MMCONF_BASE_ADDRESS to PCIE_ECAM_BASE
- Adjust the Kconfig help according to Bin's comments
arch/x86/Kconfig | 14 ++++++++++++++ arch/x86/cpu/ivybridge/sdram.c | 2 +- arch/x86/include/asm/arch-ivybridge/sandybridge.h | 2 +- board/google/chromebook_link/Kconfig | 3 +-- 4 files changed, 17 insertions(+), 4 deletions(-)
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 90e828a..bda7a0e 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -356,4 +356,18 @@ source "board/google/chromebook_link/Kconfig"
source "board/intel/crownbay/Kconfig"
+config PCIE_ECAM_BASE
hexdefault 0xe0000000Need make 'default' aligned. Sorry I did not point it out in the v1 review. You can fix it when applying.
Fixed.
Applied to u-boot-x86.
If the BIOS emulator is not available, allow use of native execution if available, and vice versa. This can be controlled by the caller.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---
Changes in v2: - Rename pci_rom_emul_t to pci_rom_emul
arch/x86/cpu/ivybridge/gma.c | 3 ++- drivers/pci/pci_rom.c | 32 +++++++++++++++++++++++++------- drivers/video/vesa_fb.c | 6 +++--- include/pci_rom.h | 15 +++++++++++++-- 4 files changed, 43 insertions(+), 13 deletions(-)
diff --git a/arch/x86/cpu/ivybridge/gma.c b/arch/x86/cpu/ivybridge/gma.c index 6cf9654..821ea25 100644 --- a/arch/x86/cpu/ivybridge/gma.c +++ b/arch/x86/cpu/ivybridge/gma.c @@ -758,7 +758,8 @@ int gma_func0_init(pci_dev_t dev, struct pci_controller *hose,
#ifdef CONFIG_VIDEO start = get_timer(0); - ret = pci_run_vga_bios(dev, int15_handler, false); + ret = pci_run_vga_bios(dev, int15_handler, PCI_ROM_USE_NATIVE | + PCI_ROM_ALLOW_FALLBACK); debug("BIOS ran in %lums\n", get_timer(start)); #endif /* Post VBIOS init */ diff --git a/drivers/pci/pci_rom.c b/drivers/pci/pci_rom.c index eb76591..0796179 100644 --- a/drivers/pci/pci_rom.c +++ b/drivers/pci/pci_rom.c @@ -228,11 +228,12 @@ int vbe_get_video_info(struct graphic_device *gdev) #endif }
-int pci_run_vga_bios(pci_dev_t dev, int (*int15_handler)(void), bool emulate) +int pci_run_vga_bios(pci_dev_t dev, int (*int15_handler)(void), int exec_method) { struct pci_rom_header *rom, *ram; int vesa_mode = -1; uint16_t class; + bool emulate; int ret;
/* Only execute VGA ROMs */ @@ -262,6 +263,29 @@ int pci_run_vga_bios(pci_dev_t dev, int (*int15_handler)(void), bool emulate) vesa_mode = CONFIG_FRAMEBUFFER_VESA_MODE; #endif debug("Selected vesa mode %#x\n", vesa_mode); + + if (exec_method & PCI_ROM_USE_NATIVE) { +#ifdef CONFIG_X86 + emulate = false; +#else + if (!(exec_method & PCI_ROM_ALLOW_FALLBACK)) { + printf("BIOS native execution is only available on x86\n"); + return -ENOSYS; + } + emulate = true; +#endif + } else { +#ifdef CONFIG_BIOSEMU + emulate = true; +#else + if (!(exec_method & PCI_ROM_ALLOW_FALLBACK)) { + printf("BIOS emulation not available - see CONFIG_BIOSEMU\n"); + return -ENOSYS; + } + emulate = false; +#endif + } + if (emulate) { #ifdef CONFIG_BIOSEMU BE_VGAInfo *info; @@ -274,9 +298,6 @@ int pci_run_vga_bios(pci_dev_t dev, int (*int15_handler)(void), bool emulate) vesa_mode, &mode_info); if (ret) return ret; -#else - printf("BIOS emulation not available - see CONFIG_BIOSEMU\n"); - return -ENOSYS; #endif } else { #ifdef CONFIG_X86 @@ -284,9 +305,6 @@ int pci_run_vga_bios(pci_dev_t dev, int (*int15_handler)(void), bool emulate)
bios_run_on_x86(dev, (unsigned long)ram, vesa_mode, &mode_info); -#else - printf("BIOS native execution is only available on x86\n"); - return -ENOSYS; #endif } debug("Final vesa mode %#x\n", mode_info.video_mode); diff --git a/drivers/video/vesa_fb.c b/drivers/video/vesa_fb.c index 3a0fea2..9164f8d 100644 --- a/drivers/video/vesa_fb.c +++ b/drivers/video/vesa_fb.c @@ -42,8 +42,8 @@ void *video_hw_init(void) printf("no card detected\n"); return NULL; } - printf("bdf %x\n", dev); - ret = pci_run_vga_bios(dev, NULL, true); + ret = pci_run_vga_bios(dev, NULL, PCI_ROM_USE_NATIVE | + PCI_ROM_ALLOW_FALLBACK); if (ret) { printf("failed to run video BIOS: %d\n", ret); return NULL; @@ -59,7 +59,7 @@ void *video_hw_init(void) sprintf(gdev->modeIdent, "%dx%dx%d", gdev->winSizeX, gdev->winSizeY, bits_per_pixel); printf("%s\n", gdev->modeIdent); - debug("Framex buffer at %x\n", gdev->pciBase); + debug("Frame buffer at %x\n", gdev->pciBase);
return (void *)gdev; } diff --git a/include/pci_rom.h b/include/pci_rom.h index 4ba36eb..2f1665d 100644 --- a/include/pci_rom.h +++ b/include/pci_rom.h @@ -33,14 +33,25 @@ struct pci_rom_data { uint16_t reserved_2; };
+/* + * Determines which execution method is used and whether we allow falling back + * to the other if the requested method is not available. + */ +enum pci_rom_emul { + PCI_ROM_EMULATE = 0 << 0, + PCI_ROM_USE_NATIVE = 1 << 0, + PCI_ROM_ALLOW_FALLBACK = 1 << 1, +}; + /** * pci_run_vga_bios() - Run the VGA BIOS in an x86 PC * * @dev: Video device containing the BIOS * @int15_handler: Function to call to handle int 0x15 - * @emulate: true to use the x86 emulator, false to run native + * @exec_method: flags from enum pci_rom_emul */ -int pci_run_vga_bios(pci_dev_t dev, int (*int15_handler)(void), bool emulate); +int pci_run_vga_bios(pci_dev_t dev, int (*int15_handler)(void), + int exec_method);
/** * board_map_oprom_vendev() - map several PCI IDs to the one the ROM expects
On 27 January 2015 at 21:13, Simon Glass sjg@chromium.org wrote:
If the BIOS emulator is not available, allow use of native execution if available, and vice versa. This can be controlled by the caller.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com
Changes in v2:
- Rename pci_rom_emul_t to pci_rom_emul
arch/x86/cpu/ivybridge/gma.c | 3 ++- drivers/pci/pci_rom.c | 32 +++++++++++++++++++++++++------- drivers/video/vesa_fb.c | 6 +++--- include/pci_rom.h | 15 +++++++++++++-- 4 files changed, 43 insertions(+), 13 deletions(-)
Applied to u-boot-x86.
Since we must run a PCI BIOS ROM, and this can take a calamitous amount of time, measure it using bootstage.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---
Changes in v2: None
drivers/video/vesa_fb.c | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/drivers/video/vesa_fb.c b/drivers/video/vesa_fb.c index 9164f8d..47f824a 100644 --- a/drivers/video/vesa_fb.c +++ b/drivers/video/vesa_fb.c @@ -42,8 +42,10 @@ void *video_hw_init(void) printf("no card detected\n"); return NULL; } + bootstage_start(BOOTSTAGE_ID_ACCUM_LCD, "vesa display"); ret = pci_run_vga_bios(dev, NULL, PCI_ROM_USE_NATIVE | PCI_ROM_ALLOW_FALLBACK); + bootstage_accum(BOOTSTAGE_ID_ACCUM_LCD); if (ret) { printf("failed to run video BIOS: %d\n", ret); return NULL;
On 27 January 2015 at 21:13, Simon Glass sjg@chromium.org wrote:
Since we must run a PCI BIOS ROM, and this can take a calamitous amount of time, measure it using bootstage.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com
Changes in v2: None
drivers/video/vesa_fb.c | 2 ++ 1 file changed, 2 insertions(+)
Applied to u-boot-x86.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com Tested-by: Bin Meng bmeng.cn@gmail.com ---
Changes in v2: None
arch/x86/cpu/queensbay/Makefile | 2 +- arch/x86/cpu/queensbay/fsp_configs.c | 2 +- arch/x86/cpu/queensbay/tnc.c | 2 +- arch/x86/cpu/queensbay/tnc_dram.c | 2 +- arch/x86/cpu/queensbay/tnc_pci.c | 2 +- arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_api.h | 0 arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_bootmode.h | 0 arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_ffs.h | 0 arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_fv.h | 0 arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_hob.h | 0 arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_infoheader.h | 0 arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_platform.h | 0 arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_support.h | 2 +- arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_types.h | 0 arch/x86/lib/Makefile | 1 + arch/x86/lib/cmd_hob.c | 2 +- arch/x86/lib/fsp/Makefile | 7 +++++++ arch/x86/{cpu/queensbay => lib/fsp}/fsp_support.c | 2 +- 18 files changed, 16 insertions(+), 8 deletions(-) rename arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_api.h (100%) rename arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_bootmode.h (100%) rename arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_ffs.h (100%) rename arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_fv.h (100%) rename arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_hob.h (100%) rename arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_infoheader.h (100%) rename arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_platform.h (100%) rename arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_support.h (99%) rename arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_types.h (100%) create mode 100644 arch/x86/lib/fsp/Makefile rename arch/x86/{cpu/queensbay => lib/fsp}/fsp_support.c (99%)
diff --git a/arch/x86/cpu/queensbay/Makefile b/arch/x86/cpu/queensbay/Makefile index 2c2ec01..b3e7d87 100644 --- a/arch/x86/cpu/queensbay/Makefile +++ b/arch/x86/cpu/queensbay/Makefile @@ -5,5 +5,5 @@ #
obj-y += tnc_car.o tnc_dram.o tnc.o topcliff.o -obj-y += fsp_configs.o fsp_support.o +obj-y += fsp_configs.o obj-$(CONFIG_PCI) += tnc_pci.o diff --git a/arch/x86/cpu/queensbay/fsp_configs.c b/arch/x86/cpu/queensbay/fsp_configs.c index af28e45..78bc966 100644 --- a/arch/x86/cpu/queensbay/fsp_configs.c +++ b/arch/x86/cpu/queensbay/fsp_configs.c @@ -6,7 +6,7 @@ */
#include <common.h> -#include <asm/arch/fsp/fsp_support.h> +#include <asm/fsp/fsp_support.h>
void update_fsp_upd(struct upd_region *fsp_upd) { diff --git a/arch/x86/cpu/queensbay/tnc.c b/arch/x86/cpu/queensbay/tnc.c index 8637cdc..f9b3bfa 100644 --- a/arch/x86/cpu/queensbay/tnc.c +++ b/arch/x86/cpu/queensbay/tnc.c @@ -9,7 +9,7 @@ #include <asm/pci.h> #include <asm/post.h> #include <asm/arch/tnc.h> -#include <asm/arch/fsp/fsp_support.h> +#include <asm/fsp/fsp_support.h> #include <asm/processor.h>
static void unprotect_spi_flash(void) diff --git a/arch/x86/cpu/queensbay/tnc_dram.c b/arch/x86/cpu/queensbay/tnc_dram.c index df79a39..4c0a7c8 100644 --- a/arch/x86/cpu/queensbay/tnc_dram.c +++ b/arch/x86/cpu/queensbay/tnc_dram.c @@ -5,7 +5,7 @@ */
#include <common.h> -#include <asm/arch/fsp/fsp_support.h> +#include <asm/fsp/fsp_support.h> #include <asm/e820.h> #include <asm/post.h>
diff --git a/arch/x86/cpu/queensbay/tnc_pci.c b/arch/x86/cpu/queensbay/tnc_pci.c index 39bff49..9b0b725 100644 --- a/arch/x86/cpu/queensbay/tnc_pci.c +++ b/arch/x86/cpu/queensbay/tnc_pci.c @@ -7,7 +7,7 @@ #include <common.h> #include <pci.h> #include <asm/pci.h> -#include <asm/arch/fsp/fsp_support.h> +#include <asm/fsp/fsp_support.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/arch/x86/include/asm/arch-queensbay/fsp/fsp_api.h b/arch/x86/include/asm/fsp/fsp_api.h similarity index 100% rename from arch/x86/include/asm/arch-queensbay/fsp/fsp_api.h rename to arch/x86/include/asm/fsp/fsp_api.h diff --git a/arch/x86/include/asm/arch-queensbay/fsp/fsp_bootmode.h b/arch/x86/include/asm/fsp/fsp_bootmode.h similarity index 100% rename from arch/x86/include/asm/arch-queensbay/fsp/fsp_bootmode.h rename to arch/x86/include/asm/fsp/fsp_bootmode.h diff --git a/arch/x86/include/asm/arch-queensbay/fsp/fsp_ffs.h b/arch/x86/include/asm/fsp/fsp_ffs.h similarity index 100% rename from arch/x86/include/asm/arch-queensbay/fsp/fsp_ffs.h rename to arch/x86/include/asm/fsp/fsp_ffs.h diff --git a/arch/x86/include/asm/arch-queensbay/fsp/fsp_fv.h b/arch/x86/include/asm/fsp/fsp_fv.h similarity index 100% rename from arch/x86/include/asm/arch-queensbay/fsp/fsp_fv.h rename to arch/x86/include/asm/fsp/fsp_fv.h diff --git a/arch/x86/include/asm/arch-queensbay/fsp/fsp_hob.h b/arch/x86/include/asm/fsp/fsp_hob.h similarity index 100% rename from arch/x86/include/asm/arch-queensbay/fsp/fsp_hob.h rename to arch/x86/include/asm/fsp/fsp_hob.h diff --git a/arch/x86/include/asm/arch-queensbay/fsp/fsp_infoheader.h b/arch/x86/include/asm/fsp/fsp_infoheader.h similarity index 100% rename from arch/x86/include/asm/arch-queensbay/fsp/fsp_infoheader.h rename to arch/x86/include/asm/fsp/fsp_infoheader.h diff --git a/arch/x86/include/asm/arch-queensbay/fsp/fsp_platform.h b/arch/x86/include/asm/fsp/fsp_platform.h similarity index 100% rename from arch/x86/include/asm/arch-queensbay/fsp/fsp_platform.h rename to arch/x86/include/asm/fsp/fsp_platform.h diff --git a/arch/x86/include/asm/arch-queensbay/fsp/fsp_support.h b/arch/x86/include/asm/fsp/fsp_support.h similarity index 99% rename from arch/x86/include/asm/arch-queensbay/fsp/fsp_support.h rename to arch/x86/include/asm/fsp/fsp_support.h index ebdbd03..6329cfe 100644 --- a/arch/x86/include/asm/arch-queensbay/fsp/fsp_support.h +++ b/arch/x86/include/asm/fsp/fsp_support.h @@ -16,7 +16,7 @@ #include "fsp_platform.h" #include "fsp_infoheader.h" #include "fsp_bootmode.h" -#include "fsp_vpd.h" +#include <asm/arch/fsp/fsp_vpd.h>
struct shared_data { struct fsp_header *fsp_hdr; diff --git a/arch/x86/include/asm/arch-queensbay/fsp/fsp_types.h b/arch/x86/include/asm/fsp/fsp_types.h similarity index 100% rename from arch/x86/include/asm/arch-queensbay/fsp/fsp_types.h rename to arch/x86/include/asm/fsp/fsp_types.h diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile index 32d7b98..c17f7f0 100644 --- a/arch/x86/lib/Makefile +++ b/arch/x86/lib/Makefile @@ -25,6 +25,7 @@ obj-y += string.o obj-$(CONFIG_SYS_X86_TSC_TIMER) += tsc_timer.o obj-$(CONFIG_VIDEO_VGA) += video.o obj-$(CONFIG_CMD_ZBOOT) += zimage.o +obj-$(CONFIG_HAVE_FSP) += fsp/
extra-$(CONFIG_USE_PRIVATE_LIBGCC) := lib.a
diff --git a/arch/x86/lib/cmd_hob.c b/arch/x86/lib/cmd_hob.c index a0ef037..915746a 100644 --- a/arch/x86/lib/cmd_hob.c +++ b/arch/x86/lib/cmd_hob.c @@ -7,7 +7,7 @@ #include <common.h> #include <command.h> #include <linux/compiler.h> -#include <asm/arch/fsp/fsp_support.h> +#include <asm/fsp/fsp_support.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/arch/x86/lib/fsp/Makefile b/arch/x86/lib/fsp/Makefile new file mode 100644 index 0000000..1b9b0e2 --- /dev/null +++ b/arch/x86/lib/fsp/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (C) 2015 Google, Inc +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += fsp_support.o diff --git a/arch/x86/cpu/queensbay/fsp_support.c b/arch/x86/lib/fsp/fsp_support.c similarity index 99% rename from arch/x86/cpu/queensbay/fsp_support.c rename to arch/x86/lib/fsp/fsp_support.c index aed3e2b..f6ae85a 100644 --- a/arch/x86/cpu/queensbay/fsp_support.c +++ b/arch/x86/lib/fsp/fsp_support.c @@ -6,7 +6,7 @@ */
#include <common.h> -#include <asm/arch/fsp/fsp_support.h> +#include <asm/fsp/fsp_support.h> #include <asm/post.h>
/**
On 27 January 2015 at 21:13, Simon Glass sjg@chromium.org wrote:
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com Tested-by: Bin Meng bmeng.cn@gmail.com
Changes in v2: None
Applied to u-boot-x86.
On 28 January 2015 at 16:44, Simon Glass sjg@chromium.org wrote:
On 27 January 2015 at 21:13, Simon Glass sjg@chromium.org wrote:
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com Tested-by: Bin Meng bmeng.cn@gmail.com
Changes in v2: None
Applied to u-boot-x86.
I had to change the Makefile slightly to only include this when CONFIG_X86 is defined.
- Simon
To avoid casts, find_fsp_header() should return a pointer. Add asmlinkage to two API functions which use that convention. UPD_TERMINATOR is common so move it into a common file.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com Tested-by: Bin Meng bmeng.cn@gmail.com ---
Changes in v2: None
arch/x86/include/asm/arch-queensbay/fsp/fsp_vpd.h | 2 -- arch/x86/include/asm/fsp/fsp_api.h | 6 ++++-- arch/x86/include/asm/fsp/fsp_support.h | 4 +++- arch/x86/lib/fsp/fsp_support.c | 4 ++-- 4 files changed, 9 insertions(+), 7 deletions(-)
diff --git a/arch/x86/include/asm/arch-queensbay/fsp/fsp_vpd.h b/arch/x86/include/asm/arch-queensbay/fsp/fsp_vpd.h index bce58b1..3c57558 100644 --- a/arch/x86/include/asm/arch-queensbay/fsp/fsp_vpd.h +++ b/arch/x86/include/asm/arch-queensbay/fsp/fsp_vpd.h @@ -10,8 +10,6 @@ #ifndef __VPDHEADER_H__ #define __VPDHEADER_H__
-#define UPD_TERMINATOR 0x55AA - struct __packed upd_region { u64 sign; /* Offset 0x0000 */ u64 reserved; /* Offset 0x0008 */ diff --git a/arch/x86/include/asm/fsp/fsp_api.h b/arch/x86/include/asm/fsp/fsp_api.h index a9d7156..2d34d13 100644 --- a/arch/x86/include/asm/fsp/fsp_api.h +++ b/arch/x86/include/asm/fsp/fsp_api.h @@ -8,6 +8,8 @@ #ifndef __FSP_API_H__ #define __FSP_API_H__
+#include <linux/linkage.h> + /* * FspInit continuation function prototype. * Control will be returned to this callback function after FspInit API call. @@ -47,9 +49,9 @@ struct fsp_notify_params { };
/* FspInit API function prototype */ -typedef u32 (*fsp_init_f)(struct fsp_init_params *params); +typedef asmlinkage u32 (*fsp_init_f)(struct fsp_init_params *params);
/* FspNotify API function prototype */ -typedef u32 (*fsp_notify_f)(struct fsp_notify_params *params); +typedef asmlinkage u32 (*fsp_notify_f)(struct fsp_notify_params *params);
#endif diff --git a/arch/x86/include/asm/fsp/fsp_support.h b/arch/x86/include/asm/fsp/fsp_support.h index 6329cfe..c6c7dc0 100644 --- a/arch/x86/include/asm/fsp/fsp_support.h +++ b/arch/x86/include/asm/fsp/fsp_support.h @@ -26,6 +26,8 @@ struct shared_data {
#define FSP_LOWMEM_BASE 0x100000UL #define FSP_HIGHMEM_BASE 0x100000000ULL +#define UPD_TERMINATOR 0x55AA +
/** * FSP Continuation assembly helper routine @@ -61,7 +63,7 @@ void fsp_continue(struct shared_data *shared_data, u32 status, * * @retval: the offset of FSP header. If signature is invalid, returns 0. */ -u32 find_fsp_header(void); +struct fsp_header *find_fsp_header(void);
/** * FSP initialization wrapper function. diff --git a/arch/x86/lib/fsp/fsp_support.c b/arch/x86/lib/fsp/fsp_support.c index f6ae85a..bf37807 100644 --- a/arch/x86/lib/fsp/fsp_support.c +++ b/arch/x86/lib/fsp/fsp_support.c @@ -30,7 +30,7 @@ static bool compare_guid(const struct efi_guid *guid1, return false; }
-u32 __attribute__((optimize("O0"))) find_fsp_header(void) +struct fsp_header *__attribute__((optimize("O0"))) find_fsp_header(void) { /* * This function may be called before the a stack is established, @@ -84,7 +84,7 @@ u32 __attribute__((optimize("O0"))) find_fsp_header(void) fsp = 0; }
- return (u32)fsp; + return (struct fsp_header *)fsp; }
void fsp_continue(struct shared_data *shared_data, u32 status, void *hob_list)
On 27 January 2015 at 21:13, Simon Glass sjg@chromium.org wrote:
To avoid casts, find_fsp_header() should return a pointer. Add asmlinkage to two API functions which use that convention. UPD_TERMINATOR is common so move it into a common file.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com Tested-by: Bin Meng bmeng.cn@gmail.com
Changes in v2: None
Applied to u-boot-x86.
For now this code seems to be the same for all FSP platforms. Make it common until we see what differences are required.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com Tested-by: Bin Meng bmeng.cn@gmail.com ---
Changes in v2: None
arch/x86/cpu/queensbay/Makefile | 2 +- arch/x86/lib/fsp/Makefile | 2 ++ arch/x86/{cpu/queensbay/tnc_car.S => lib/fsp/fsp_car.S} | 0 arch/x86/{cpu/queensbay/tnc_dram.c => lib/fsp/fsp_dram.c} | 0 4 files changed, 3 insertions(+), 1 deletion(-) rename arch/x86/{cpu/queensbay/tnc_car.S => lib/fsp/fsp_car.S} (100%) rename arch/x86/{cpu/queensbay/tnc_dram.c => lib/fsp/fsp_dram.c} (100%)
diff --git a/arch/x86/cpu/queensbay/Makefile b/arch/x86/cpu/queensbay/Makefile index b3e7d87..d8761fd 100644 --- a/arch/x86/cpu/queensbay/Makefile +++ b/arch/x86/cpu/queensbay/Makefile @@ -4,6 +4,6 @@ # SPDX-License-Identifier: GPL-2.0+ #
-obj-y += tnc_car.o tnc_dram.o tnc.o topcliff.o obj-y += fsp_configs.o +obj-y += tnc.o topcliff.o obj-$(CONFIG_PCI) += tnc_pci.o diff --git a/arch/x86/lib/fsp/Makefile b/arch/x86/lib/fsp/Makefile index 1b9b0e2..3a2bac0 100644 --- a/arch/x86/lib/fsp/Makefile +++ b/arch/x86/lib/fsp/Makefile @@ -4,4 +4,6 @@ # SPDX-License-Identifier: GPL-2.0+ #
+obj-y += fsp_car.o +obj-y += fsp_dram.o obj-y += fsp_support.o diff --git a/arch/x86/cpu/queensbay/tnc_car.S b/arch/x86/lib/fsp/fsp_car.S similarity index 100% rename from arch/x86/cpu/queensbay/tnc_car.S rename to arch/x86/lib/fsp/fsp_car.S diff --git a/arch/x86/cpu/queensbay/tnc_dram.c b/arch/x86/lib/fsp/fsp_dram.c similarity index 100% rename from arch/x86/cpu/queensbay/tnc_dram.c rename to arch/x86/lib/fsp/fsp_dram.c
On 27 January 2015 at 21:13, Simon Glass sjg@chromium.org wrote:
For now this code seems to be the same for all FSP platforms. Make it common until we see what differences are required.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com Tested-by: Bin Meng bmeng.cn@gmail.com
Changes in v2: None
Applied to u-boot-x86.
Since these board functions seem to be the same for all boards which use FSP, move them into a common file. We can adjust this later if future FSPs need more flexibility.
This creates a generic PCI MMC device.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: - Move MMC code into a new pci_mmc.c file - Remove setup_early_uart() function prototype
arch/x86/cpu/queensbay/tnc.c | 27 ------------------- arch/x86/cpu/queensbay/tnc_pci.c | 15 ----------- arch/x86/cpu/queensbay/topcliff.c | 33 +++-------------------- arch/x86/lib/fsp/Makefile | 1 + arch/x86/lib/fsp/fsp_common.c | 55 +++++++++++++++++++++++++++++++++++++++ drivers/mmc/Makefile | 1 + drivers/mmc/pci_mmc.c | 42 ++++++++++++++++++++++++++++++ include/mmc.h | 14 ++++++++++ 8 files changed, 116 insertions(+), 72 deletions(-) create mode 100644 arch/x86/lib/fsp/fsp_common.c create mode 100644 drivers/mmc/pci_mmc.c
diff --git a/arch/x86/cpu/queensbay/tnc.c b/arch/x86/cpu/queensbay/tnc.c index f9b3bfa..30ab725 100644 --- a/arch/x86/cpu/queensbay/tnc.c +++ b/arch/x86/cpu/queensbay/tnc.c @@ -43,30 +43,3 @@ int arch_cpu_init(void)
return 0; } - -int print_cpuinfo(void) -{ - post_code(POST_CPU_INFO); - return default_print_cpuinfo(); -} - -void reset_cpu(ulong addr) -{ - /* cold reset */ - outb(0x06, PORT_RESET); -} - -void board_final_cleanup(void) -{ - u32 status; - - /* call into FspNotify */ - debug("Calling into FSP (notify phase INIT_PHASE_BOOT): "); - status = fsp_notify(NULL, INIT_PHASE_BOOT); - if (status != FSP_SUCCESS) - debug("fail, error code %x\n", status); - else - debug("OK\n"); - - return; -} diff --git a/arch/x86/cpu/queensbay/tnc_pci.c b/arch/x86/cpu/queensbay/tnc_pci.c index 9b0b725..6c291f9 100644 --- a/arch/x86/cpu/queensbay/tnc_pci.c +++ b/arch/x86/cpu/queensbay/tnc_pci.c @@ -44,18 +44,3 @@ void board_pci_setup_hose(struct pci_controller *hose)
hose->region_count = 4; } - -int board_pci_post_scan(struct pci_controller *hose) -{ - u32 status; - - /* call into FspNotify */ - debug("Calling into FSP (notify phase INIT_PHASE_PCI): "); - status = fsp_notify(NULL, INIT_PHASE_PCI); - if (status != FSP_SUCCESS) - debug("fail, error code %x\n", status); - else - debug("OK\n"); - - return 0; -} diff --git a/arch/x86/cpu/queensbay/topcliff.c b/arch/x86/cpu/queensbay/topcliff.c index b01422a..9faf1b9 100644 --- a/arch/x86/cpu/queensbay/topcliff.c +++ b/arch/x86/cpu/queensbay/topcliff.c @@ -5,43 +5,16 @@ */
#include <common.h> -#include <errno.h> -#include <malloc.h> -#include <pci.h> +#include <mmc.h> #include <pci_ids.h> -#include <sdhci.h>
static struct pci_device_id mmc_supported[] = { { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SDIO_0 }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SDIO_1 }, - { } };
int cpu_mmc_init(bd_t *bis) { - struct sdhci_host *mmc_host; - pci_dev_t devbusfn; - u32 iobase; - int ret; - int i; - - for (i = 0; i < ARRAY_SIZE(mmc_supported); i++) { - devbusfn = pci_find_devices(mmc_supported, i); - if (devbusfn == -1) - return -ENODEV; - - mmc_host = (struct sdhci_host *)malloc(sizeof(struct sdhci_host)); - if (!mmc_host) - return -ENOMEM; - - mmc_host->name = "Topcliff SDHCI"; - pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &iobase); - mmc_host->ioaddr = (void *)iobase; - mmc_host->quirks = 0; - ret = add_sdhci(mmc_host, 0, 0); - if (ret) - return ret; - } - - return 0; + return pci_mmc_init("Topcliff SDHCI", mmc_supported, + ARRAY_SIZE(mmc_supported)); } diff --git a/arch/x86/lib/fsp/Makefile b/arch/x86/lib/fsp/Makefile index 3a2bac0..5b12c12 100644 --- a/arch/x86/lib/fsp/Makefile +++ b/arch/x86/lib/fsp/Makefile @@ -5,5 +5,6 @@ #
obj-y += fsp_car.o +obj-y += fsp_common.o obj-y += fsp_dram.o obj-y += fsp_support.o diff --git a/arch/x86/lib/fsp/fsp_common.c b/arch/x86/lib/fsp/fsp_common.c new file mode 100644 index 0000000..f668259 --- /dev/null +++ b/arch/x86/lib/fsp/fsp_common.c @@ -0,0 +1,55 @@ +/* + * Copyright (C) 2014, Bin Meng bmeng.cn@gmail.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <errno.h> +#include <asm/io.h> +#include <asm/post.h> +#include <asm/processor.h> +#include <asm/fsp/fsp_support.h> + +int print_cpuinfo(void) +{ + post_code(POST_CPU_INFO); + return default_print_cpuinfo(); +} + +void reset_cpu(ulong addr) +{ + /* cold reset */ + outb(0x06, PORT_RESET); +} + + +int board_pci_post_scan(struct pci_controller *hose) +{ + u32 status; + + /* call into FspNotify */ + debug("Calling into FSP (notify phase INIT_PHASE_PCI): "); + status = fsp_notify(NULL, INIT_PHASE_PCI); + if (status != FSP_SUCCESS) + debug("fail, error code %x\n", status); + else + debug("OK\n"); + + return 0; +} + +void board_final_cleanup(void) +{ + u32 status; + + /* call into FspNotify */ + debug("Calling into FSP (notify phase INIT_PHASE_BOOT): "); + status = fsp_notify(NULL, INIT_PHASE_BOOT); + if (status != FSP_SUCCESS) + debug("fail, error code %x\n", status); + else + debug("OK\n"); + + return; +} diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index 4ba5878..8d42437 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -24,6 +24,7 @@ obj-$(CONFIG_MVEBU_MMC) += mvebu_mmc.o obj-$(CONFIG_MXC_MMC) += mxcmmc.o obj-$(CONFIG_MXS_MMC) += mxsmmc.o obj-$(CONFIG_OMAP_HSMMC) += omap_hsmmc.o +obj-$(CONFIG_PCI) += pci_mmc.o obj-$(CONFIG_PXA_MMC_GENERIC) += pxa_mmc_gen.o obj-$(CONFIG_SUPPORT_EMMC_RPMB) += rpmb.o obj-$(CONFIG_S3C_SDI) += s3c_sdi.o diff --git a/drivers/mmc/pci_mmc.c b/drivers/mmc/pci_mmc.c new file mode 100644 index 0000000..dc78bcb --- /dev/null +++ b/drivers/mmc/pci_mmc.c @@ -0,0 +1,42 @@ +/* + * Copyright (C) 2015, Google, Inc + * Copyright (C) 2014, Bin Meng bmeng.cn@gmail.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <errno.h> +#include <malloc.h> +#include <sdhci.h> +#include <asm/pci.h> + +int pci_mmc_init(const char *name, struct pci_device_id mmc_supported[], + int num_ids) +{ + struct sdhci_host *mmc_host; + pci_dev_t devbusfn; + u32 iobase; + int ret; + int i; + + for (i = 0; i < num_ids; i++) { + devbusfn = pci_find_devices(mmc_supported, i); + if (devbusfn == -1) + return -ENODEV; + + mmc_host = malloc(sizeof(struct sdhci_host)); + if (!mmc_host) + return -ENOMEM; + + mmc_host->name = (char *)name; + pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &iobase); + mmc_host->ioaddr = (void *)iobase; + mmc_host->quirks = 0; + ret = add_sdhci(mmc_host, 0, 0); + if (ret) + return ret; + } + + return 0; +} diff --git a/include/mmc.h b/include/mmc.h index 09101e2..e5c3a76 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -438,6 +438,20 @@ int board_mmc_init(bd_t *bis); int cpu_mmc_init(bd_t *bis); int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr);
+struct pci_device_id; + +/** + * pci_mmc_init() - set up PCI MMC devices + * + * This finds all the matching PCI IDs and sets them up as MMC devices. + * + * @name: Name to use for devices + * @mmc_supported: PCI IDs to search for + * @num_ids: Number of elements in @mmc_supported + */ +int pci_mmc_init(const char *name, struct pci_device_id mmc_supported[], + int num_ids); + /* Set block count limit because of 16 bit register limit on some hardware*/ #ifndef CONFIG_SYS_MMC_MAX_BLK_COUNT #define CONFIG_SYS_MMC_MAX_BLK_COUNT 65535
On Wed, Jan 28, 2015 at 1:13 PM, Simon Glass sjg@chromium.org wrote:
Since these board functions seem to be the same for all boards which use FSP, move them into a common file. We can adjust this later if future FSPs need more flexibility.
This creates a generic PCI MMC device.
Signed-off-by: Simon Glass sjg@chromium.org
Changes in v2:
- Move MMC code into a new pci_mmc.c file
- Remove setup_early_uart() function prototype
arch/x86/cpu/queensbay/tnc.c | 27 ------------------- arch/x86/cpu/queensbay/tnc_pci.c | 15 ----------- arch/x86/cpu/queensbay/topcliff.c | 33 +++-------------------- arch/x86/lib/fsp/Makefile | 1 + arch/x86/lib/fsp/fsp_common.c | 55 +++++++++++++++++++++++++++++++++++++++ drivers/mmc/Makefile | 1 + drivers/mmc/pci_mmc.c | 42 ++++++++++++++++++++++++++++++ include/mmc.h | 14 ++++++++++ 8 files changed, 116 insertions(+), 72 deletions(-) create mode 100644 arch/x86/lib/fsp/fsp_common.c create mode 100644 drivers/mmc/pci_mmc.c
diff --git a/arch/x86/cpu/queensbay/tnc.c b/arch/x86/cpu/queensbay/tnc.c index f9b3bfa..30ab725 100644 --- a/arch/x86/cpu/queensbay/tnc.c +++ b/arch/x86/cpu/queensbay/tnc.c @@ -43,30 +43,3 @@ int arch_cpu_init(void)
return 0;}
-int print_cpuinfo(void) -{
post_code(POST_CPU_INFO);return default_print_cpuinfo();-}
-void reset_cpu(ulong addr) -{
/* cold reset */outb(0x06, PORT_RESET);-}
-void board_final_cleanup(void) -{
u32 status;/* call into FspNotify */debug("Calling into FSP (notify phase INIT_PHASE_BOOT): ");status = fsp_notify(NULL, INIT_PHASE_BOOT);if (status != FSP_SUCCESS)debug("fail, error code %x\n", status);elsedebug("OK\n");return;-} diff --git a/arch/x86/cpu/queensbay/tnc_pci.c b/arch/x86/cpu/queensbay/tnc_pci.c index 9b0b725..6c291f9 100644 --- a/arch/x86/cpu/queensbay/tnc_pci.c +++ b/arch/x86/cpu/queensbay/tnc_pci.c @@ -44,18 +44,3 @@ void board_pci_setup_hose(struct pci_controller *hose)
hose->region_count = 4;}
-int board_pci_post_scan(struct pci_controller *hose) -{
u32 status;/* call into FspNotify */debug("Calling into FSP (notify phase INIT_PHASE_PCI): ");status = fsp_notify(NULL, INIT_PHASE_PCI);if (status != FSP_SUCCESS)debug("fail, error code %x\n", status);elsedebug("OK\n");return 0;-} diff --git a/arch/x86/cpu/queensbay/topcliff.c b/arch/x86/cpu/queensbay/topcliff.c index b01422a..9faf1b9 100644 --- a/arch/x86/cpu/queensbay/topcliff.c +++ b/arch/x86/cpu/queensbay/topcliff.c @@ -5,43 +5,16 @@ */
#include <common.h> -#include <errno.h> -#include <malloc.h> -#include <pci.h> +#include <mmc.h> #include <pci_ids.h> -#include <sdhci.h>
static struct pci_device_id mmc_supported[] = { { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SDIO_0 }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SDIO_1 },
{ }};
int cpu_mmc_init(bd_t *bis) {
struct sdhci_host *mmc_host;pci_dev_t devbusfn;u32 iobase;int ret;int i;for (i = 0; i < ARRAY_SIZE(mmc_supported); i++) {devbusfn = pci_find_devices(mmc_supported, i);if (devbusfn == -1)return -ENODEV;mmc_host = (struct sdhci_host *)malloc(sizeof(struct sdhci_host));if (!mmc_host)return -ENOMEM;mmc_host->name = "Topcliff SDHCI";pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &iobase);mmc_host->ioaddr = (void *)iobase;mmc_host->quirks = 0;ret = add_sdhci(mmc_host, 0, 0);if (ret)return ret;}return 0;
return pci_mmc_init("Topcliff SDHCI", mmc_supported,ARRAY_SIZE(mmc_supported));} diff --git a/arch/x86/lib/fsp/Makefile b/arch/x86/lib/fsp/Makefile index 3a2bac0..5b12c12 100644 --- a/arch/x86/lib/fsp/Makefile +++ b/arch/x86/lib/fsp/Makefile @@ -5,5 +5,6 @@ #
obj-y += fsp_car.o +obj-y += fsp_common.o obj-y += fsp_dram.o obj-y += fsp_support.o diff --git a/arch/x86/lib/fsp/fsp_common.c b/arch/x86/lib/fsp/fsp_common.c new file mode 100644 index 0000000..f668259 --- /dev/null +++ b/arch/x86/lib/fsp/fsp_common.c @@ -0,0 +1,55 @@ +/*
- Copyright (C) 2014, Bin Meng bmeng.cn@gmail.com
- SPDX-License-Identifier: GPL-2.0+
- */
+#include <common.h> +#include <errno.h> +#include <asm/io.h> +#include <asm/post.h> +#include <asm/processor.h> +#include <asm/fsp/fsp_support.h>
+int print_cpuinfo(void) +{
post_code(POST_CPU_INFO);return default_print_cpuinfo();+}
+void reset_cpu(ulong addr) +{
/* cold reset */outb(0x06, PORT_RESET);+}
+int board_pci_post_scan(struct pci_controller *hose) +{
u32 status;/* call into FspNotify */debug("Calling into FSP (notify phase INIT_PHASE_PCI): ");status = fsp_notify(NULL, INIT_PHASE_PCI);if (status != FSP_SUCCESS)debug("fail, error code %x\n", status);elsedebug("OK\n");return 0;+}
+void board_final_cleanup(void) +{
u32 status;/* call into FspNotify */debug("Calling into FSP (notify phase INIT_PHASE_BOOT): ");status = fsp_notify(NULL, INIT_PHASE_BOOT);if (status != FSP_SUCCESS)debug("fail, error code %x\n", status);elsedebug("OK\n");return;+} diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index 4ba5878..8d42437 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -24,6 +24,7 @@ obj-$(CONFIG_MVEBU_MMC) += mvebu_mmc.o obj-$(CONFIG_MXC_MMC) += mxcmmc.o obj-$(CONFIG_MXS_MMC) += mxsmmc.o obj-$(CONFIG_OMAP_HSMMC) += omap_hsmmc.o +obj-$(CONFIG_PCI) += pci_mmc.o obj-$(CONFIG_PXA_MMC_GENERIC) += pxa_mmc_gen.o obj-$(CONFIG_SUPPORT_EMMC_RPMB) += rpmb.o obj-$(CONFIG_S3C_SDI) += s3c_sdi.o diff --git a/drivers/mmc/pci_mmc.c b/drivers/mmc/pci_mmc.c new file mode 100644 index 0000000..dc78bcb --- /dev/null +++ b/drivers/mmc/pci_mmc.c @@ -0,0 +1,42 @@ +/*
- Copyright (C) 2015, Google, Inc
- Copyright (C) 2014, Bin Meng bmeng.cn@gmail.com
- SPDX-License-Identifier: GPL-2.0+
- */
+#include <common.h> +#include <errno.h> +#include <malloc.h> +#include <sdhci.h> +#include <asm/pci.h>
+int pci_mmc_init(const char *name, struct pci_device_id mmc_supported[],
int num_ids)+{
struct sdhci_host *mmc_host;pci_dev_t devbusfn;u32 iobase;int ret;int i;for (i = 0; i < num_ids; i++) {devbusfn = pci_find_devices(mmc_supported, i);if (devbusfn == -1)return -ENODEV;mmc_host = malloc(sizeof(struct sdhci_host));if (!mmc_host)return -ENOMEM;mmc_host->name = (char *)name;pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &iobase);mmc_host->ioaddr = (void *)iobase;mmc_host->quirks = 0;ret = add_sdhci(mmc_host, 0, 0);if (ret)return ret;}return 0;+} diff --git a/include/mmc.h b/include/mmc.h index 09101e2..e5c3a76 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -438,6 +438,20 @@ int board_mmc_init(bd_t *bis); int cpu_mmc_init(bd_t *bis); int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr);
+struct pci_device_id;
+/**
- pci_mmc_init() - set up PCI MMC devices
- This finds all the matching PCI IDs and sets them up as MMC devices.
- @name: Name to use for devices
- @mmc_supported: PCI IDs to search for
- @num_ids: Number of elements in @mmc_supported
- */
+int pci_mmc_init(const char *name, struct pci_device_id mmc_supported[],
int num_ids);/* Set block count limit because of 16 bit register limit on some hardware*/ #ifndef CONFIG_SYS_MMC_MAX_BLK_COUNT
#define CONFIG_SYS_MMC_MAX_BLK_COUNT 65535
Reviewed-by: Bin Meng bmeng.cn@gmail.com Tested-by: Bin Meng bmeng.cn@gmail.com
On 27 January 2015 at 21:56, Bin Meng bmeng.cn@gmail.com wrote:
On Wed, Jan 28, 2015 at 1:13 PM, Simon Glass sjg@chromium.org wrote:
Since these board functions seem to be the same for all boards which use FSP, move them into a common file. We can adjust this later if future FSPs need more flexibility.
This creates a generic PCI MMC device.
Signed-off-by: Simon Glass sjg@chromium.org
Changes in v2:
- Move MMC code into a new pci_mmc.c file
- Remove setup_early_uart() function prototype
arch/x86/cpu/queensbay/tnc.c | 27 ------------------- arch/x86/cpu/queensbay/tnc_pci.c | 15 ----------- arch/x86/cpu/queensbay/topcliff.c | 33 +++-------------------- arch/x86/lib/fsp/Makefile | 1 + arch/x86/lib/fsp/fsp_common.c | 55 +++++++++++++++++++++++++++++++++++++++ drivers/mmc/Makefile | 1 + drivers/mmc/pci_mmc.c | 42 ++++++++++++++++++++++++++++++ include/mmc.h | 14 ++++++++++ 8 files changed, 116 insertions(+), 72 deletions(-) create mode 100644 arch/x86/lib/fsp/fsp_common.c create mode 100644 drivers/mmc/pci_mmc.c
[snip]
Reviewed-by: Bin Meng bmeng.cn@gmail.com Tested-by: Bin Meng bmeng.cn@gmail.com
Applied to u-boot-x86.
Tidy up the FSP support code a little.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---
Changes in v2: None
arch/x86/lib/fsp/fsp_support.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/x86/lib/fsp/fsp_support.c b/arch/x86/lib/fsp/fsp_support.c index bf37807..8b639f7 100644 --- a/arch/x86/lib/fsp/fsp_support.c +++ b/arch/x86/lib/fsp/fsp_support.c @@ -124,25 +124,25 @@ void fsp_init(u32 stack_top, u32 boot_mode, void *nvs_buf) struct fsp_init_params *params_ptr; struct upd_region *fsp_upd;
- fsp_hdr = (struct fsp_header *)find_fsp_header(); + fsp_hdr = find_fsp_header(); if (fsp_hdr == NULL) { /* No valid FSP info header was found */ panic("Invalid FSP header"); }
- fsp_upd = (struct upd_region *)&shared_data.fsp_upd; + fsp_upd = &shared_data.fsp_upd; memset(&rt_buf, 0, sizeof(struct fspinit_rtbuf));
/* Reserve a gap in stack top */ rt_buf.common.stack_top = (u32 *)stack_top - 32; rt_buf.common.boot_mode = boot_mode; - rt_buf.common.upd_data = (struct upd_region *)fsp_upd; + rt_buf.common.upd_data = fsp_upd;
/* Get VPD region start */ fsp_vpd = (struct vpd_region *)(fsp_hdr->img_base + fsp_hdr->cfg_region_off);
- /* Verifify the VPD data region is valid */ + /* Verify the VPD data region is valid */ assert((fsp_vpd->img_rev == VPD_IMAGE_REV) && (fsp_vpd->sign == VPD_IMAGE_ID));
@@ -150,7 +150,7 @@ void fsp_init(u32 stack_top, u32 boot_mode, void *nvs_buf) memcpy(fsp_upd, (void *)(fsp_hdr->img_base + fsp_vpd->upd_offset), sizeof(struct upd_region));
- /* Verifify the UPD data region is valid */ + /* Verify the UPD data region is valid */ assert(fsp_upd->terminator == UPD_TERMINATOR);
/* Override any UPD setting if required */
On 27 January 2015 at 21:13, Simon Glass sjg@chromium.org wrote:
Tidy up the FSP support code a little.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com
Changes in v2: None
arch/x86/lib/fsp/fsp_support.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-)
Applied to u-boot-x86.
While queensbay is the first chip with these settings, others will want to use them too. Make them common.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---
Changes in v2: None
arch/x86/Kconfig | 38 ++++++++++++++++++++++++++++++++++++++ arch/x86/cpu/queensbay/Kconfig | 38 -------------------------------------- 2 files changed, 38 insertions(+), 38 deletions(-)
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index bda7a0e..1b7955b 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -344,6 +344,44 @@ config TSC_FREQ_IN_MHZ help The running frequency in MHz of Time-Stamp Counter (TSC).
+config HAVE_FSP + bool "Add an Firmware Support Package binary" + help + Select this option to add an Firmware Support Package binary to + the resulting U-Boot image. It is a binary blob which U-Boot uses + to set up SDRAM and other chipset specific initialization. + + Note: Without this binary U-Boot will not be able to set up its + SDRAM so will not boot. + +config FSP_FILE + string "Firmware Support Package binary filename" + depends on HAVE_FSP + default "fsp.bin" + help + The filename of the file to use as Firmware Support Package binary + in the board directory. + +config FSP_ADDR + hex "Firmware Support Package binary location" + depends on HAVE_FSP + default 0xfffc0000 + help + FSP is not Position Independent Code (PIC) and the whole FSP has to + be rebased if it is placed at a location which is different from the + perferred base address specified during the FSP build. Use Intel's + Binary Configuration Tool (BCT) to do the rebase. + + The default base address of 0xfffc0000 indicates that the binary must + be located at offset 0xc0000 from the beginning of a 1MB flash device. + +config FSP_TEMP_RAM_ADDR + hex + default 0x2000000 + help + Stack top address which is used in FspInit after DRAM is ready and + CAR is disabled. + source "arch/x86/cpu/coreboot/Kconfig"
source "arch/x86/cpu/ivybridge/Kconfig" diff --git a/arch/x86/cpu/queensbay/Kconfig b/arch/x86/cpu/queensbay/Kconfig index f6b5201..397e599 100644 --- a/arch/x86/cpu/queensbay/Kconfig +++ b/arch/x86/cpu/queensbay/Kconfig @@ -11,44 +11,6 @@ config INTEL_QUEENSBAY
if INTEL_QUEENSBAY
-config HAVE_FSP - bool "Add an Firmware Support Package binary" - help - Select this option to add an Firmware Support Package binary to - the resulting U-Boot image. It is a binary blob which U-Boot uses - to set up SDRAM and other chipset specific initialization. - - Note: Without this binary U-Boot will not be able to set up its - SDRAM so will not boot. - -config FSP_FILE - string "Firmware Support Package binary filename" - depends on HAVE_FSP - default "fsp.bin" - help - The filename of the file to use as Firmware Support Package binary - in the board directory. - -config FSP_ADDR - hex "Firmware Support Package binary location" - depends on HAVE_FSP - default 0xfffc0000 - help - FSP is not Position Independent Code (PIC) and the whole FSP has to - be rebased if it is placed at a location which is different from the - perferred base address specified during the FSP build. Use Intel's - Binary Configuration Tool (BCT) to do the rebase. - - The default base address of 0xfffc0000 indicates that the binary must - be located at offset 0xc0000 from the beginning of a 1MB flash device. - -config FSP_TEMP_RAM_ADDR - hex - default 0x2000000 - help - Stack top address which is used in FspInit after DRAM is ready and - CAR is disabled. - config HAVE_CMC bool "Add a Chipset Micro Code state machine binary" help
On 27 January 2015 at 21:13, Simon Glass sjg@chromium.org wrote:
While queensbay is the first chip with these settings, others will want to use them too. Make them common.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com
Changes in v2: None
arch/x86/Kconfig | 38 ++++++++++++++++++++++++++++++++++++++ arch/x86/cpu/queensbay/Kconfig | 38 -------------------------------------- 2 files changed, 38 insertions(+), 38 deletions(-)
Applied to u-boot-x86.
Since the FSP is a black box it helps to have some sort of debugging available to check its inputs. If the debug UART is in use, set it up after CAR is available.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: - Remove duplicate prototype of setup_early_uart()
arch/x86/include/asm/u-boot-x86.h | 3 +++ arch/x86/lib/fsp/fsp_support.c | 4 ++++ 2 files changed, 7 insertions(+)
diff --git a/arch/x86/include/asm/u-boot-x86.h b/arch/x86/include/asm/u-boot-x86.h index b98afa8..5d7dff5 100644 --- a/arch/x86/include/asm/u-boot-x86.h +++ b/arch/x86/include/asm/u-boot-x86.h @@ -45,6 +45,9 @@ ulong board_get_usable_ram_top(ulong total_size); void dram_init_banksize(void); int default_print_cpuinfo(void);
+/* Set up a UART which can be used with printch(), printhex8(), etc. */ +int setup_early_uart(void); + void setup_pcat_compatibility(void);
void isa_unmap_rom(u32 addr); diff --git a/arch/x86/lib/fsp/fsp_support.c b/arch/x86/lib/fsp/fsp_support.c index 8b639f7..5f96da1 100644 --- a/arch/x86/lib/fsp/fsp_support.c +++ b/arch/x86/lib/fsp/fsp_support.c @@ -124,6 +124,10 @@ void fsp_init(u32 stack_top, u32 boot_mode, void *nvs_buf) struct fsp_init_params *params_ptr; struct upd_region *fsp_upd;
+#ifdef CONFIG_DEBUG_UART + setup_early_uart(); +#endif + fsp_hdr = find_fsp_header(); if (fsp_hdr == NULL) { /* No valid FSP info header was found */
On Wed, Jan 28, 2015 at 1:13 PM, Simon Glass sjg@chromium.org wrote:
Since the FSP is a black box it helps to have some sort of debugging available to check its inputs. If the debug UART is in use, set it up after CAR is available.
Signed-off-by: Simon Glass sjg@chromium.org
Changes in v2:
- Remove duplicate prototype of setup_early_uart()
arch/x86/include/asm/u-boot-x86.h | 3 +++ arch/x86/lib/fsp/fsp_support.c | 4 ++++ 2 files changed, 7 insertions(+)
diff --git a/arch/x86/include/asm/u-boot-x86.h b/arch/x86/include/asm/u-boot-x86.h index b98afa8..5d7dff5 100644 --- a/arch/x86/include/asm/u-boot-x86.h +++ b/arch/x86/include/asm/u-boot-x86.h @@ -45,6 +45,9 @@ ulong board_get_usable_ram_top(ulong total_size); void dram_init_banksize(void); int default_print_cpuinfo(void);
+/* Set up a UART which can be used with printch(), printhex8(), etc. */ +int setup_early_uart(void);
void setup_pcat_compatibility(void);
void isa_unmap_rom(u32 addr); diff --git a/arch/x86/lib/fsp/fsp_support.c b/arch/x86/lib/fsp/fsp_support.c index 8b639f7..5f96da1 100644 --- a/arch/x86/lib/fsp/fsp_support.c +++ b/arch/x86/lib/fsp/fsp_support.c @@ -124,6 +124,10 @@ void fsp_init(u32 stack_top, u32 boot_mode, void *nvs_buf) struct fsp_init_params *params_ptr; struct upd_region *fsp_upd;
+#ifdef CONFIG_DEBUG_UART
setup_early_uart();+#endif
fsp_hdr = find_fsp_header(); if (fsp_hdr == NULL) { /* No valid FSP info header was found */--
Reviewed-by: Bin Meng bmeng.cn@gmail.com
On 27 January 2015 at 21:57, Bin Meng bmeng.cn@gmail.com wrote:
On Wed, Jan 28, 2015 at 1:13 PM, Simon Glass sjg@chromium.org wrote:
Since the FSP is a black box it helps to have some sort of debugging available to check its inputs. If the debug UART is in use, set it up after CAR is available.
Signed-off-by: Simon Glass sjg@chromium.org
Changes in v2:
- Remove duplicate prototype of setup_early_uart()
[snip]
--
Reviewed-by: Bin Meng bmeng.cn@gmail.com
Applied to u-boot-x86.
The base address is found in a different way and the protection bit is also in a different place. Otherwise it is very similar.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: None
drivers/spi/ich.c | 56 ++++++++++++++++++++++++++++++++++++++++--------------- drivers/spi/ich.h | 11 ++++++----- 2 files changed, 47 insertions(+), 20 deletions(-)
diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c index fdff158..da85779 100644 --- a/drivers/spi/ich.c +++ b/drivers/spi/ich.c @@ -7,6 +7,7 @@ */
#include <common.h> +#include <errno.h> #include <malloc.h> #include <spi.h> #include <pci.h> @@ -21,6 +22,7 @@ struct ich_ctlr { pci_dev_t dev; /* PCI device number */ int ich_version; /* Controller version, 7 or 9 */ + bool use_sbase; /* Use SBASE instead of RCB */ int ichspi_lock; int locked; uint8_t *opmenu; @@ -145,7 +147,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, * ICH 7 SPI controller only supports array read command * and byte program command for SST flash */ - if (ctlr.ich_version == 7) { + if (ctlr.ich_version == 7 || ctlr.use_sbase) { ich->slave.op_mode_rx = SPI_OPM_RX_AS; ich->slave.op_mode_tx = SPI_OPM_TX_BP; } @@ -181,7 +183,8 @@ static int get_ich_version(uint16_t device_id) if ((device_id >= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN && device_id <= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX) || (device_id >= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN && - device_id <= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX)) + device_id <= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX) || + device_id == PCI_DEVICE_ID_INTEL_VALLEYVIEW_LPC) return 9;
return 0; @@ -204,14 +207,14 @@ static int ich9_can_do_33mhz(pci_dev_t dev) return speed == 1; }
-static int ich_find_spi_controller(pci_dev_t *devp, int *ich_versionp) +static int ich_find_spi_controller(struct ich_ctlr *ich) { int last_bus = pci_last_busno(); int bus;
if (last_bus == -1) { debug("No PCI busses?\n"); - return -1; + return -ENODEV; }
for (bus = 0; bus <= last_bus; bus++) { @@ -225,24 +228,33 @@ static int ich_find_spi_controller(pci_dev_t *devp, int *ich_versionp) device_id = ids >> 16;
if (vendor_id == PCI_VENDOR_ID_INTEL) { - *devp = dev; - *ich_versionp = get_ich_version(device_id); - return 0; + ich->dev = dev; + ich->ich_version = get_ich_version(device_id); + if (device_id == PCI_DEVICE_ID_INTEL_VALLEYVIEW_LPC) + ich->use_sbase = true; + return ich->ich_version == 0 ? -ENODEV : 0; } }
debug("ICH SPI: No ICH found.\n"); - return -1; + return -ENODEV; }
static int ich_init_controller(struct ich_ctlr *ctlr) { uint8_t *rcrb; /* Root Complex Register Block */ uint32_t rcba; /* Root Complex Base Address */ + uint32_t sbase_addr; + uint8_t *sbase;
pci_read_config_dword(ctlr->dev, 0xf0, &rcba); /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable. */ rcrb = (uint8_t *)(rcba & 0xffffc000); + + /* SBASE is similar */ + pci_read_config_dword(ctlr->dev, 0x54, &sbase_addr); + sbase = (uint8_t *)(sbase_addr & 0xfffffe00); + if (ctlr->ich_version == 7) { struct ich7_spi_regs *ich7_spi;
@@ -262,7 +274,10 @@ static int ich_init_controller(struct ich_ctlr *ctlr) } else if (ctlr->ich_version == 9) { struct ich9_spi_regs *ich9_spi;
- ich9_spi = (struct ich9_spi_regs *)(rcrb + 0x3800); + if (ctlr->use_sbase) + ich9_spi = (struct ich9_spi_regs *)sbase; + else + ich9_spi = (struct ich9_spi_regs *)(rcrb + 0x3800); ctlr->ichspi_lock = ich_readw(&ich9_spi->hsfs) & HSFS_FLOCKDN; ctlr->opmenu = ich9_spi->opmenu; ctlr->menubytes = sizeof(ich9_spi->opmenu); @@ -282,12 +297,13 @@ static int ich_init_controller(struct ich_ctlr *ctlr) ctlr->ich_version); return -1; } - debug("ICH SPI: Version %d detected\n", ctlr->ich_version);
/* Work out the maximum speed we can support */ ctlr->max_speed = 20000000; if (ctlr->ich_version == 9 && ich9_can_do_33mhz(ctlr->dev)) ctlr->max_speed = 33000000; + debug("ICH SPI: Version %d detected at %p, speed %ld\n", + ctlr->ich_version, ctlr->base, ctlr->max_speed);
ich_set_bbar(ctlr, 0);
@@ -298,7 +314,7 @@ void spi_init(void) { uint8_t bios_cntl;
- if (ich_find_spi_controller(&ctlr.dev, &ctlr.ich_version)) { + if (ich_find_spi_controller(&ctlr)) { printf("ICH SPI: Cannot find device\n"); return; } @@ -312,10 +328,20 @@ void spi_init(void) * Disable the BIOS write protect so write commands are allowed. On * v9, deassert SMM BIOS Write Protect Disable. */ - pci_read_config_byte(ctlr.dev, 0xdc, &bios_cntl); - if (ctlr.ich_version == 9) - bios_cntl &= ~(1 << 5); - pci_write_config_byte(ctlr.dev, 0xdc, bios_cntl | 0x1); + if (ctlr.use_sbase) { + struct ich9_spi_regs *ich9_spi; + + ich9_spi = (struct ich9_spi_regs *)ctlr.base; + bios_cntl = ich_readb(&ich9_spi->bcr); + bios_cntl &= ~(1 << 5); /* clear Enable InSMM_STS (EISS) */ + bios_cntl |= 1; /* Write Protect Disable (WPD) */ + ich_writeb(bios_cntl, &ich9_spi->bcr); + } else { + pci_read_config_byte(ctlr.dev, 0xdc, &bios_cntl); + if (ctlr.ich_version == 9) + bios_cntl &= ~(1 << 5); + pci_write_config_byte(ctlr.dev, 0xdc, bios_cntl | 0x1); + } }
int spi_claim_bus(struct spi_slave *slave) diff --git a/drivers/spi/ich.h b/drivers/spi/ich.h index d2e4b85..1419b23 100644 --- a/drivers/spi/ich.h +++ b/drivers/spi/ich.h @@ -37,18 +37,19 @@ struct ich9_spi_regs { uint8_t opmenu[8]; /* 0x98 */ uint32_t bbar; uint8_t _reserved3[12]; - uint32_t fdoc; + uint32_t fdoc; /* 0xb0 */ uint32_t fdod; uint8_t _reserved4[8]; - uint32_t afc; + uint32_t afc; /* 0xc0 */ uint32_t lvscc; uint32_t uvscc; uint8_t _reserved5[4]; - uint32_t fpb; + uint32_t fpb; /* 0xd0 */ uint8_t _reserved6[28]; - uint32_t srdl; + uint32_t srdl; /* 0xf0 */ uint32_t srdc; - uint32_t srd; + uint32_t scs; + uint32_t bcr; } __packed;
enum {
On Wed, Jan 28, 2015 at 1:13 PM, Simon Glass sjg@chromium.org wrote:
The base address is found in a different way and the protection bit is also in a different place. Otherwise it is very similar.
Signed-off-by: Simon Glass sjg@chromium.org
Changes in v2: None
drivers/spi/ich.c | 56 ++++++++++++++++++++++++++++++++++++++++--------------- drivers/spi/ich.h | 11 ++++++----- 2 files changed, 47 insertions(+), 20 deletions(-)
diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c index fdff158..da85779 100644 --- a/drivers/spi/ich.c +++ b/drivers/spi/ich.c @@ -7,6 +7,7 @@ */
#include <common.h> +#include <errno.h> #include <malloc.h> #include <spi.h> #include <pci.h> @@ -21,6 +22,7 @@ struct ich_ctlr { pci_dev_t dev; /* PCI device number */ int ich_version; /* Controller version, 7 or 9 */
bool use_sbase; /* Use SBASE instead of RCB */ int ichspi_lock; int locked; uint8_t *opmenu;@@ -145,7 +147,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, * ICH 7 SPI controller only supports array read command * and byte program command for SST flash */
if (ctlr.ich_version == 7) {
if (ctlr.ich_version == 7 || ctlr.use_sbase) { ich->slave.op_mode_rx = SPI_OPM_RX_AS; ich->slave.op_mode_tx = SPI_OPM_TX_BP; }@@ -181,7 +183,8 @@ static int get_ich_version(uint16_t device_id) if ((device_id >= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN && device_id <= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX) || (device_id >= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN &&
device_id <= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX))
device_id <= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX) ||device_id == PCI_DEVICE_ID_INTEL_VALLEYVIEW_LPC) return 9; return 0;@@ -204,14 +207,14 @@ static int ich9_can_do_33mhz(pci_dev_t dev) return speed == 1; }
-static int ich_find_spi_controller(pci_dev_t *devp, int *ich_versionp) +static int ich_find_spi_controller(struct ich_ctlr *ich) { int last_bus = pci_last_busno(); int bus;
if (last_bus == -1) { debug("No PCI busses?\n");
return -1;
return -ENODEV; } for (bus = 0; bus <= last_bus; bus++) {@@ -225,24 +228,33 @@ static int ich_find_spi_controller(pci_dev_t *devp, int *ich_versionp) device_id = ids >> 16;
if (vendor_id == PCI_VENDOR_ID_INTEL) {
*devp = dev;*ich_versionp = get_ich_version(device_id);return 0;
ich->dev = dev;ich->ich_version = get_ich_version(device_id);if (device_id == PCI_DEVICE_ID_INTEL_VALLEYVIEW_LPC)ich->use_sbase = true;return ich->ich_version == 0 ? -ENODEV : 0; } } debug("ICH SPI: No ICH found.\n");
return -1;
return -ENODEV;}
static int ich_init_controller(struct ich_ctlr *ctlr) { uint8_t *rcrb; /* Root Complex Register Block */ uint32_t rcba; /* Root Complex Base Address */
uint32_t sbase_addr;uint8_t *sbase; pci_read_config_dword(ctlr->dev, 0xf0, &rcba); /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable. */ rcrb = (uint8_t *)(rcba & 0xffffc000);/* SBASE is similar */pci_read_config_dword(ctlr->dev, 0x54, &sbase_addr);sbase = (uint8_t *)(sbase_addr & 0xfffffe00);if (ctlr->ich_version == 7) { struct ich7_spi_regs *ich7_spi;@@ -262,7 +274,10 @@ static int ich_init_controller(struct ich_ctlr *ctlr) } else if (ctlr->ich_version == 9) { struct ich9_spi_regs *ich9_spi;
ich9_spi = (struct ich9_spi_regs *)(rcrb + 0x3800);
if (ctlr->use_sbase)ich9_spi = (struct ich9_spi_regs *)sbase;elseich9_spi = (struct ich9_spi_regs *)(rcrb + 0x3800); ctlr->ichspi_lock = ich_readw(&ich9_spi->hsfs) & HSFS_FLOCKDN; ctlr->opmenu = ich9_spi->opmenu; ctlr->menubytes = sizeof(ich9_spi->opmenu);@@ -282,12 +297,13 @@ static int ich_init_controller(struct ich_ctlr *ctlr) ctlr->ich_version); return -1; }
debug("ICH SPI: Version %d detected\n", ctlr->ich_version); /* Work out the maximum speed we can support */ ctlr->max_speed = 20000000; if (ctlr->ich_version == 9 && ich9_can_do_33mhz(ctlr->dev)) ctlr->max_speed = 33000000;
debug("ICH SPI: Version %d detected at %p, speed %ld\n",ctlr->ich_version, ctlr->base, ctlr->max_speed); ich_set_bbar(ctlr, 0);@@ -298,7 +314,7 @@ void spi_init(void) { uint8_t bios_cntl;
if (ich_find_spi_controller(&ctlr.dev, &ctlr.ich_version)) {
if (ich_find_spi_controller(&ctlr)) { printf("ICH SPI: Cannot find device\n"); return; }@@ -312,10 +328,20 @@ void spi_init(void) * Disable the BIOS write protect so write commands are allowed. On * v9, deassert SMM BIOS Write Protect Disable. */
pci_read_config_byte(ctlr.dev, 0xdc, &bios_cntl);if (ctlr.ich_version == 9)bios_cntl &= ~(1 << 5);pci_write_config_byte(ctlr.dev, 0xdc, bios_cntl | 0x1);
if (ctlr.use_sbase) {struct ich9_spi_regs *ich9_spi;ich9_spi = (struct ich9_spi_regs *)ctlr.base;bios_cntl = ich_readb(&ich9_spi->bcr);bios_cntl &= ~(1 << 5); /* clear Enable InSMM_STS (EISS) */bios_cntl |= 1; /* Write Protect Disable (WPD) */ich_writeb(bios_cntl, &ich9_spi->bcr);} else {pci_read_config_byte(ctlr.dev, 0xdc, &bios_cntl);if (ctlr.ich_version == 9)bios_cntl &= ~(1 << 5);pci_write_config_byte(ctlr.dev, 0xdc, bios_cntl | 0x1);}}
int spi_claim_bus(struct spi_slave *slave) diff --git a/drivers/spi/ich.h b/drivers/spi/ich.h index d2e4b85..1419b23 100644 --- a/drivers/spi/ich.h +++ b/drivers/spi/ich.h @@ -37,18 +37,19 @@ struct ich9_spi_regs { uint8_t opmenu[8]; /* 0x98 */ uint32_t bbar; uint8_t _reserved3[12];
uint32_t fdoc;
uint32_t fdoc; /* 0xb0 */ uint32_t fdod; uint8_t _reserved4[8];
uint32_t afc;
uint32_t afc; /* 0xc0 */ uint32_t lvscc; uint32_t uvscc; uint8_t _reserved5[4];
uint32_t fpb;
uint32_t fpb; /* 0xd0 */ uint8_t _reserved6[28];
uint32_t srdl;
uint32_t srdl; /* 0xf0 */ uint32_t srdc;
uint32_t srd;
uint32_t scs;uint32_t bcr;} __packed;
enum {
Reviewed-by: Bin Meng bmeng.cn@gmail.com
On some hardware this time can be significant. Add bootstage support for measuring this. The result can be obtained using 'bootstage report' or passed on to the Linux via the device tree.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---
Changes in v2: None
common/cmd_scsi.c | 2 ++ include/bootstage.h | 1 + 2 files changed, 3 insertions(+)
diff --git a/common/cmd_scsi.c b/common/cmd_scsi.c index cbc107e..a0a62eb 100644 --- a/common/cmd_scsi.c +++ b/common/cmd_scsi.c @@ -217,8 +217,10 @@ void scsi_init(void) (busdevfunc >> 8) & 0x7); } #endif + bootstage_start(BOOTSTAGE_ID_ACCUM_SCSI, "ahci"); scsi_low_level_init(busdevfunc); scsi_scan(1); + bootstage_accum(BOOTSTAGE_ID_ACCUM_SCSI); } #endif
diff --git a/include/bootstage.h b/include/bootstage.h index df13ab2..6b7588d 100644 --- a/include/bootstage.h +++ b/include/bootstage.h @@ -194,6 +194,7 @@ enum bootstage_id { BOOTSTAGE_ID_MAIN_CPU_READY,
BOOTSTAGE_ID_ACCUM_LCD, + BOOTSTAGE_ID_ACCUM_SCSI,
/* a few spare for the user, from here */ BOOTSTAGE_ID_USER,
On 27 January 2015 at 21:13, Simon Glass sjg@chromium.org wrote:
On some hardware this time can be significant. Add bootstage support for measuring this. The result can be obtained using 'bootstage report' or passed on to the Linux via the device tree.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com
Changes in v2: None
common/cmd_scsi.c | 2 ++ include/bootstage.h | 1 + 2 files changed, 3 insertions(+)
Applied to u-boot-x86.
Allow measuring of boot time using bootstage.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com Tested-by: Bin Meng bmeng.cn@gmail.com ---
Changes in v2: None
include/configs/x86-common.h | 3 +++ 1 file changed, 3 insertions(+)
diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h index ecedfc3..66d4894 100644 --- a/include/configs/x86-common.h +++ b/include/configs/x86-common.h @@ -245,6 +245,9 @@ #define CONFIG_BOOTP_GATEWAY #define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTSTAGE +#define CONFIG_CMD_BOOTSTAGE + #define CONFIG_CMD_USB
#define CONFIG_EXTRA_ENV_SETTINGS \
On 27 January 2015 at 21:13, Simon Glass sjg@chromium.org wrote:
Allow measuring of boot time using bootstage.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com Tested-by: Bin Meng bmeng.cn@gmail.com
Changes in v2: None
include/configs/x86-common.h | 3 +++ 1 file changed, 3 insertions(+)
Applied to u-boot-x86.
Some information has been gleaned on tools and procedures for porting U-Boot to different x86 platforms. Add a few notes to start things off.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---
Changes in v2: - Document how to change the SPI speed with ifdtool
doc/README.x86 | 64 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 64 insertions(+)
diff --git a/doc/README.x86 b/doc/README.x86 index ddfd75e..a9105f8 100644 --- a/doc/README.x86 +++ b/doc/README.x86 @@ -164,6 +164,70 @@ mtrr - List and set the Memory Type Range Registers (MTRR). These are used to mode to use. U-Boot sets up some reasonable values but you can adjust then with this command.
+Development Flow +---------------- + +These notes are for those who want to port U-Boot to a new x86 platform. + +Since x86 CPUs boot from SPI flash, a SPI flash emulator is a good investment. +The Dediprog em100 can be used on Linux. The em100 tool is available here: + + http://review.coreboot.org/p/em100.git + +On Minnowboard Max the following command line can be used: + + sudo em100 -s -p LOW -d u-boot.rom -c W25Q64DW -r + +A suitable clip for connecting over the SPI flash chip is here: + + http://www.dediprog.com/pd/programmer-accessories/EM-TC-8 + +This allows you to override the SPI flash contents for development purposes. +Typically you can write to the em100 in around 1200ms, considerably faster +than programming the real flash device each time. The only important +limitation of the em100 is that it only supports SPI bus speeds up to 20MHz. +This means that images must be set to boot with that speed. This is an +Intel-specific feature - e.g. tools/ifttool has an option to set the SPI +speed in the SPI descriptor region. + +If your chip/board uses an Intel Firmware Support Package (FSP) it is fairly +easy to fit it in. You can follow the Minnowboard Max implementation, for +example. Hopefully you will just need to create new files similar to those +in arch/x86/cpu/baytrail which provide Bay Trail support. + +If you are not using an FSP you have more freedom and more responsibility. +The ivybridge support works this way, although it still uses a ROM for +graphics and still has binary blobs containing Intel code. You should aim to +support all important peripherals on your platform including video and storage. +Use the device tree for configuration where possible. + +For the microcode you can create a suitable device tree file using the +microcode tool: + + ./tools/microcode-tool -d microcode.dat create <model> + +or if you only have header files and not the full Intel microcode.dat database: + + ./tools/microcode-tool -H BAY_TRAIL_FSP_KIT/Microcode/M0130673322.h \ + -H BAY_TRAIL_FSP_KIT/Microcode/M0130679901.h \ + create all + +These are written to arch/x86/dts/microcode/ by default. + +Note that it is possible to just add the micrcode for your CPU if you know its +model. U-Boot prints this information when it starts + + CPU: x86_64, vendor Intel, device 30673h + +so here we can use the M0130673322 file. + +If you platform can display POST codes on two little 7-segment displays on +the board, then you can use post_code() calls from C or assembler to monitor +boot progress. This can be good for debugging. + +If not, you can try to get serial working as early as possible. The early +debug serial port may be useful here. See setup_early_uart() for an example. + TODO List --------- - Audio
uOn 27 January 2015 at 21:13, Simon Glass sjg@chromium.org wrote:
Some information has been gleaned on tools and procedures for porting U-Boot to different x86 platforms. Add a few notes to start things off.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com
Changes in v2:
- Document how to change the SPI speed with ifdtool
doc/README.x86 | 64 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 64 insertions(+)
Applied to u-boot-x86.
This is a relatively low-cost x86 board in a small form factor. The main peripherals are uSD, USB, HDMI, Ethernet and SATA. It uses an Atom 3800 series CPU. So far only the dual core 2GB variant is supported.
This uses the existing FSP support. Binary blobs are required to make this board work. The microcode update is included as a patch (all 3000 lines of it).
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: - Move CONFIG_SYS_CACHELINE_SIZE to the board CONFIG file - Add comment about FSP setting PCIE_ECAM_BASE - Put baytrail Kconfig in alphabetical order - Remove superfluous check for CONFIG_DEBUG_UART in setup_early_uart() - Fix compatible string for SPI flash - Remove commented-out DEBUG_UART_CLOCK baud rate - Rename 'Coreboot' to 'coreboot' in README.x86
arch/x86/Kconfig | 15 + arch/x86/cpu/Makefile | 1 + arch/x86/cpu/baytrail/Kconfig | 9 + arch/x86/cpu/baytrail/Makefile | 10 + arch/x86/cpu/baytrail/early_uart.c | 78 + arch/x86/cpu/baytrail/fsp_configs.c | 156 + arch/x86/cpu/baytrail/pci.c | 47 + arch/x86/cpu/baytrail/valleyview.c | 38 + arch/x86/dts/Makefile | 3 +- arch/x86/dts/microcode/m0130673322.dtsi | 3284 ++++++++++++++++++++++ arch/x86/dts/minnowmax.dts | 45 + arch/x86/dts/serial.dtsi | 2 +- arch/x86/include/asm/arch-baytrail/fsp/azalia.h | 39 + arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h | 95 + arch/x86/include/asm/arch-baytrail/gpio.h | 13 + board/intel/minnowmax/Kconfig | 30 + board/intel/minnowmax/MAINTAINERS | 6 + board/intel/minnowmax/Makefile | 7 + board/intel/minnowmax/minnowmax.c | 32 + board/intel/minnowmax/start.S | 9 + configs/minnowmax_defconfig | 13 + doc/README.x86 | 47 +- include/configs/minnowmax.h | 72 + 23 files changed, 4044 insertions(+), 7 deletions(-) create mode 100644 arch/x86/cpu/baytrail/Kconfig create mode 100644 arch/x86/cpu/baytrail/Makefile create mode 100644 arch/x86/cpu/baytrail/early_uart.c create mode 100644 arch/x86/cpu/baytrail/fsp_configs.c create mode 100644 arch/x86/cpu/baytrail/pci.c create mode 100644 arch/x86/cpu/baytrail/valleyview.c create mode 100644 arch/x86/dts/microcode/m0130673322.dtsi create mode 100644 arch/x86/dts/minnowmax.dts create mode 100644 arch/x86/include/asm/arch-baytrail/fsp/azalia.h create mode 100644 arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h create mode 100644 arch/x86/include/asm/arch-baytrail/gpio.h create mode 100644 board/intel/minnowmax/Kconfig create mode 100644 board/intel/minnowmax/MAINTAINERS create mode 100644 board/intel/minnowmax/Makefile create mode 100644 board/intel/minnowmax/minnowmax.c create mode 100644 board/intel/minnowmax/start.S create mode 100644 configs/minnowmax_defconfig create mode 100644 include/configs/minnowmax.h
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 1b7955b..3e0d809 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -41,6 +41,17 @@ config TARGET_CROWNBAY Intel Platform Controller Hub EG20T, other system components and peripheral connectors for PCIe/SATA/USB/LAN/SD/UART/Audio/LVDS.
+config TARGET_MINNOWMAX + bool "Support Intel Minnowboard MAX" + help + This is the Intel Minnowboard MAX. It contains an Atom E3800 + processor in a small form factor with Ethernet, micro-SD, USB 2, + USB 3, SATA, serial console, some GPIOs and HDMI 1.3 video out. + It requires some binary blobs - see README.x86 for details. + + Note that PCIE_ECAM_BASE is set up by the FSP so the value used + by U-Boot matches that value. + endchoice
config RAMBASE @@ -382,6 +393,8 @@ config FSP_TEMP_RAM_ADDR Stack top address which is used in FspInit after DRAM is ready and CAR is disabled.
+source "arch/x86/cpu/baytrail/Kconfig" + source "arch/x86/cpu/coreboot/Kconfig"
source "arch/x86/cpu/ivybridge/Kconfig" @@ -394,6 +407,8 @@ source "board/google/chromebook_link/Kconfig"
source "board/intel/crownbay/Kconfig"
+source "board/intel/minnowmax/Kconfig" + config PCIE_ECAM_BASE hex default 0xe0000000 diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile index 62e43c0..5acf8bb 100644 --- a/arch/x86/cpu/Makefile +++ b/arch/x86/cpu/Makefile @@ -12,6 +12,7 @@ extra-y = start.o obj-$(CONFIG_X86_RESET_VECTOR) += resetvec.o start16.o obj-y += interrupts.o cpu.o call64.o
+obj-$(CONFIG_INTEL_BAYTRAIL) += baytrail/ obj-$(CONFIG_SYS_COREBOOT) += coreboot/ obj-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += ivybridge/ obj-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += ivybridge/ diff --git a/arch/x86/cpu/baytrail/Kconfig b/arch/x86/cpu/baytrail/Kconfig new file mode 100644 index 0000000..e86cc01 --- /dev/null +++ b/arch/x86/cpu/baytrail/Kconfig @@ -0,0 +1,9 @@ +# +# Copyright (C) 2015 Google, Inc +# +# SPDX-License-Identifier: GPL-2.0+ +# + +config INTEL_BAYTRAIL + bool + select HAVE_FSP diff --git a/arch/x86/cpu/baytrail/Makefile b/arch/x86/cpu/baytrail/Makefile new file mode 100644 index 0000000..8914e8b --- /dev/null +++ b/arch/x86/cpu/baytrail/Makefile @@ -0,0 +1,10 @@ +# +# Copyright (C) 2015 Google, Inc +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += early_uart.o +obj-y += fsp_configs.o +obj-y += pci.o +obj-y += valleyview.o diff --git a/arch/x86/cpu/baytrail/early_uart.c b/arch/x86/cpu/baytrail/early_uart.c new file mode 100644 index 0000000..0144323 --- /dev/null +++ b/arch/x86/cpu/baytrail/early_uart.c @@ -0,0 +1,78 @@ +/* + * Copyright (C) 2015 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <debug_uart.h> +#include <errno.h> +#include <asm/io.h> + +#define PCI_DEV_CONFIG(segbus, dev, fn) ( \ + (((segbus) & 0xfff) << 20) | \ + (((dev) & 0x1f) << 15) | \ + (((fn) & 0x07) << 12)) + +/* Platform Controller Unit */ +#define LPC_DEV 0x1f +#define LPC_FUNC 0 + +/* Enable UART */ +#define UART_CONT 0x80 + +/* SCORE Pad definitions */ +#define UART_RXD_PAD 82 +#define UART_TXD_PAD 83 + +/* Pad base: PAD_CONF0[n]= PAD_BASE + 16 * n */ +#define GPSCORE_PAD_BASE (IO_BASE_ADDRESS + IO_BASE_OFFSET_GPSCORE) + +/* IO Memory */ +#define IO_BASE_ADDRESS 0xfed0c000 +#define IO_BASE_OFFSET_GPSCORE 0x0000 +#define IO_BASE_OFFSET_GPNCORE 0x1000 +#define IO_BASE_OFFSET_GPSSUS 0x2000 +#define IO_BASE_SIZE 0x4000 + +static inline unsigned int score_pconf0(int pad_num) +{ + return GPSCORE_PAD_BASE + pad_num * 16; +} + +static void score_select_func(int pad, int func) +{ + uint32_t reg; + uint32_t pconf0_addr = score_pconf0(pad); + + reg = readl(pconf0_addr); + reg &= ~0x7; + reg |= func & 0x7; + writel(reg, pconf0_addr); +} + +static void pci_write_config32(int dev, unsigned int where, u32 value) +{ + unsigned long addr; + + addr = CONFIG_PCIE_ECAM_BASE | dev | (where & ~3); + writel(value, addr); +} + +/* This can be called after memory-mapped PCI is working */ +int setup_early_uart(void) +{ + /* Enable the legacy UART hardware. */ + pci_write_config32(PCI_DEV_CONFIG(0, LPC_DEV, LPC_FUNC), UART_CONT, 1); + + /* + * Set up the pads to the UART function. This allows the signals to + * leave the chip + */ + score_select_func(UART_RXD_PAD, 1); + score_select_func(UART_TXD_PAD, 1); + + debug_uart_init(); + + return 0; +} diff --git a/arch/x86/cpu/baytrail/fsp_configs.c b/arch/x86/cpu/baytrail/fsp_configs.c new file mode 100644 index 0000000..86b6926 --- /dev/null +++ b/arch/x86/cpu/baytrail/fsp_configs.c @@ -0,0 +1,156 @@ +/* + * Copyright (C) 2013, Intel Corporation + * Copyright (C) 2014, Bin Meng bmeng.cn@gmail.com + * + * SPDX-License-Identifier: Intel + */ + +#include <common.h> +#include <asm/arch/fsp/azalia.h> +#include <asm/fsp/fsp_support.h> + +/* ALC262 Verb Table - 10EC0262 */ +static const uint32_t verb_table_data13[] = { + /* Pin Complex (NID 0x11) */ + 0x01171cf0, + 0x01171d11, + 0x01171e11, + 0x01171f41, + /* Pin Complex (NID 0x12) */ + 0x01271cf0, + 0x01271d11, + 0x01271e11, + 0x01271f41, + /* Pin Complex (NID 0x14) */ + 0x01471c10, + 0x01471d40, + 0x01471e01, + 0x01471f01, + /* Pin Complex (NID 0x15) */ + 0x01571cf0, + 0x01571d11, + 0x01571e11, + 0x01571f41, + /* Pin Complex (NID 0x16) */ + 0x01671cf0, + 0x01671d11, + 0x01671e11, + 0x01671f41, + /* Pin Complex (NID 0x18) */ + 0x01871c20, + 0x01871d98, + 0x01871ea1, + 0x01871f01, + /* Pin Complex (NID 0x19) */ + 0x01971c21, + 0x01971d98, + 0x01971ea1, + 0x01971f02, + /* Pin Complex (NID 0x1A) */ + 0x01a71c2f, + 0x01a71d30, + 0x01a71e81, + 0x01a71f01, + /* Pin Complex */ + 0x01b71c1f, + 0x01b71d40, + 0x01b71e21, + 0x01b71f02, + /* Pin Complex */ + 0x01c71cf0, + 0x01c71d11, + 0x01c71e11, + 0x01c71f41, + /* Pin Complex */ + 0x01d71c01, + 0x01d71dc6, + 0x01d71e14, + 0x01d71f40, + /* Pin Complex */ + 0x01e71cf0, + 0x01e71d11, + 0x01e71e11, + 0x01e71f41, + /* Pin Complex */ + 0x01f71cf0, + 0x01f71d11, + 0x01f71e11, + 0x01f71f41, +}; + +/* + * This needs to be in ROM since if we put it in CAR, FSP init loses it when + * it drops CAR. + * + * TODO(sjg@chromium.org): Move to device tree when FSP allows it + * + * VerbTable: (RealTek ALC262) + * Revision ID = 0xFF, support all steps + * Codec Verb Table For AZALIA + * Codec Address: CAd value (0/1/2) + * Codec Vendor: 0x10EC0262 + */ +static const struct pch_azalia_verb_table azalia_verb_table[] = { + { + { + 0x10ec0262, + 0x0000, + 0xff, + 0x01, + 0x000b, + 0x0002, + }, + verb_table_data13 + } +}; + +const struct pch_azalia_config azalia_config = { + .pme_enable = 1, + .docking_supported = 1, + .docking_attached = 0, + .hdmi_codec_enable = 1, + .azalia_v_ci_enable = 1, + .rsvdbits = 0, + .azalia_verb_table_num = 1, + .azalia_verb_table = azalia_verb_table, + .reset_wait_timer_us = 300 +}; + +void update_fsp_upd(struct upd_region *fsp_upd) +{ + struct memory_down_data *mem; + + /* + * Configure everything here to avoid the poor hard-pressed user + * needing to run Intel's binary configuration tool. It may also allow + * us to support the 1GB single core variant easily. + * + * TODO(sjg@chromium.org): Move to device tree + */ + fsp_upd->mrc_init_tseg_size = 8; + fsp_upd->mrc_init_mmio_size = 0x800; + fsp_upd->emmc_boot_mode = 0xff; + fsp_upd->enable_sdio = 1; + fsp_upd->enable_sdcard = 1; + fsp_upd->enable_hsuart0 = 1; + fsp_upd->azalia_config_ptr = (uint32_t)&azalia_config; + fsp_upd->enable_i2_c0 = 0; + fsp_upd->enable_i2_c2 = 0; + fsp_upd->enable_i2_c3 = 0; + fsp_upd->enable_i2_c4 = 0; + fsp_upd->enable_xhci = 0; + fsp_upd->igd_render_standby = 1; + + mem = &fsp_upd->memory_params; + mem->enable_memory_down = 1; + mem->dram_speed = 1; + mem->dimm_width = 1; + mem->dimm_density = 2; + mem->dimm_tcl = 0xb; + mem->dimm_trpt_rcd = 0xb; + mem->dimm_twr = 0xc; + mem->dimm_twtr = 6; + mem->dimm_trrd = 6; + mem->dimm_trtp = 6; + mem->dimm_tfaw = 0x14; +} diff --git a/arch/x86/cpu/baytrail/pci.c b/arch/x86/cpu/baytrail/pci.c new file mode 100644 index 0000000..7032c97 --- /dev/null +++ b/arch/x86/cpu/baytrail/pci.c @@ -0,0 +1,47 @@ +/* + * Copyright (C) 2014, Bin Meng bmeng.cn@gmail.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <debug_uart.h> +#include <pci.h> +#include <asm/pci.h> +#include <asm/fsp/fsp_support.h> + +DECLARE_GLOBAL_DATA_PTR; + +void board_pci_setup_hose(struct pci_controller *hose) +{ + hose->first_busno = 0; + hose->last_busno = 0; + + /* PCI memory space */ + pci_set_region(hose->regions + 0, + CONFIG_PCI_MEM_BUS, + CONFIG_PCI_MEM_PHYS, + CONFIG_PCI_MEM_SIZE, + PCI_REGION_MEM); + + /* PCI IO space */ + pci_set_region(hose->regions + 1, + CONFIG_PCI_IO_BUS, + CONFIG_PCI_IO_PHYS, + CONFIG_PCI_IO_SIZE, + PCI_REGION_IO); + + pci_set_region(hose->regions + 2, + CONFIG_PCI_PREF_BUS, + CONFIG_PCI_PREF_PHYS, + CONFIG_PCI_PREF_SIZE, + PCI_REGION_PREFETCH); + + pci_set_region(hose->regions + 3, + 0, + 0, + gd->ram_size, + PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); + + hose->region_count = 4; +} diff --git a/arch/x86/cpu/baytrail/valleyview.c b/arch/x86/cpu/baytrail/valleyview.c new file mode 100644 index 0000000..a3e837d --- /dev/null +++ b/arch/x86/cpu/baytrail/valleyview.c @@ -0,0 +1,38 @@ +/* + * Copyright (C) 2014, Bin Meng bmeng.cn@gmail.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <mmc.h> +#include <pci_ids.h> +#include <asm/post.h> + +static struct pci_device_id mmc_supported[] = { + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SDIO }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SDCARD }, +}; + +int cpu_mmc_init(bd_t *bis) +{ + printf("mmc init\n"); + return pci_mmc_init("ValleyView SDHCI", mmc_supported, + ARRAY_SIZE(mmc_supported)); +} + +int arch_cpu_init(void) +{ + int ret; + + post_code(POST_CPU_INIT); +#ifdef CONFIG_SYS_X86_TSC_TIMER + timer_set_base(rdtsc()); +#endif + + ret = x86_cpu_init_f(); + if (ret) + return ret; + + return 0; +} diff --git a/arch/x86/dts/Makefile b/arch/x86/dts/Makefile index 97ed884..4e0171a 100644 --- a/arch/x86/dts/Makefile +++ b/arch/x86/dts/Makefile @@ -1,5 +1,6 @@ dtb-y += chromebook_link.dtb \ - crownbay.dtb + crownbay.dtb \ + minnowmax.dtb
targets += $(dtb-y)
diff --git a/arch/x86/dts/microcode/m0130673322.dtsi b/arch/x86/dts/microcode/m0130673322.dtsi new file mode 100644 index 0000000..90bf2fb --- /dev/null +++ b/arch/x86/dts/microcode/m0130673322.dtsi @@ -0,0 +1,3284 @@ +/* + * --- + * This is a device tree fragment. Use #include to add these properties to a + * node. + * + * Date: + */ + +compatible = "intel,microcode"; +intel,header-version = <1>; +intel,update-revision = <0x322>; +intel,date-code = <0x4012014>; +intel,processor-signature = <0x30673>; +intel,checksum = <0x17b0d914>; +intel,loader-revision = <1>; +intel,processor-flags = <0x1>; + +/* The first 48-bytes are the public header which repeats the above data */ +data = < + 0x01000000 0x22030000 0x14200104 0x73060300 + 0x14d9b017 0x01000000 0x01000000 0xd0cb0000 + 0x00cc0000 0x00000000 0x00000000 0x00000000 + 0x00000000 0xa1000000 0x01000200 0x22030000 + 0x00000000 0x00000000 0x31031420 0x11320000 + 0x01000000 0x73060300 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0xf4320000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x0ae10178 0x7c98f9d1 0x41962d85 0x19391270 + 0xcf3c0336 0xc1f13d6f 0xe46abaf6 0x3b65ca6b + 0xdb666815 0x5a17bfc4 0x4fca009d 0x099ae8b3 + 0x198e2c7d 0x7c665bbf 0xc07a1a7a 0x7dbcee26 + 0x867296b2 0xc885b6ce 0xe602baff 0x68544b14 + 0xc928c400 0x3add156d 0x531946f9 0x92a03216 + 0xda352322 0xd967ee1f 0x3c5170a7 0xf6de834e + 0x5a2ed8b3 0x9fb8f050 0x450de17f 0xfd5ef070 + 0x4954575f 0xa3a071ab 0xb56e2afb 0xe2b48302 + 0x6655a958 0x57c9a438 0x1b2f688a 0x09309bc4 + 0x0be95612 0x529c1633 0xc48515d9 0x29eb78df + 0x9933409f 0xda58dea9 0x58c805fd 0xbc110f5a + 0x40780ec0 0x6ad59bb3 0xc7387fb8 0x591c1490 + 0xf9335932 0x32130e0b 0xef4b3c96 0xacd903f2 + 0x5b362539 0xe7f85529 0xcb17c41f 0xe7e440d8 + 0xfaf7e925 0x969b76fb 0x5edab8c7 0xf00012e8 + 0x121c2971 0xe5b18959 0xadfd07c0 0x1f09c9d7 + 0x9781006a 0x39550073 0x6c438b6d 0x436f60bc + 0x11000000 0x8514b971 0x40df7b4a 0x6a6b7285 + 0x7978ef59 0x319bddf5 0x04c68e5a 0xe1c28b10 + 0x172f63dc 0x306fb95d 0x31d881e8 0x69f8e08d + 0x617a99e1 0x1ab6b574 0x2951fa5b 0xcc7e3e94 + 0xff379d19 0x5c035dec 0xe28ed726 0x22b8a5ac + 0xd08b3ac5 0x45c03b9e 0xcea4083c 0xc26758aa + 0xbe7cf81e 0x43d898f3 0x5c45a635 0xc9cac095 + 0xb89aea20 0x2c02b40e 0xe3a8b48d 0xeabfb60e + 0x776ed2a9 0x080ae6d5 0x7f64b1df 0x00e40ee6 + 0x0f1c10f4 0x792e5423 0x787f5459 0x63a8b02c + 0x3fd6a255 0x049cae26 0x0949f5ff 0x9aebb236 + 0xecc01775 0x91b57b84 0xe0e45ea3 0x5a8bf79e + 0x356a843a 0x2406795f 0x8aaae5d8 0x6a8c877c + 0xa8b2b8f4 0x04cf8f49 0x422d9e2c 0xf09f9896 + 0xe9b92215 0x9c98fb44 0x88556b7f 0x519d6f4c + 0x9e8a016b 0xcb18d16c 0x419b4ee7 0x080b49c8 + 0xc51b875e 0x46aabc9c 0x262d27eb 0x93ea189d + 0xdd0da69d 0x3e5b17e8 0xcc78509a 0x00b07e6e + 0x363d5a70 0x64572070 0x8a84abc4 0x1cb03838 + 0x965fd76a 0x540aafc9 0x83a91654 0x1a722e67 + 0x4bf98ce1 0x2b3c2ff9 0x972cebd4 0xf3a68395 + 0x2613e422 0xf8d031d7 0xb1c79a0f 0xfd44f65b + 0xa7012a9b 0xd9a15a60 0xc311fc0c 0x6f52f878 + 0x3d68381d 0xd2a035d7 0xb790c50e 0x9f1e5010 + 0x41877064 0xa9d1e4ae 0xfe9abbd5 0x60c2c748 + 0x8167e5ad 0x022dbfb3 0x75abe483 0x51c37170 + 0x09b8590d 0xc1bb323d 0x2c7336b1 0xd4d0d49b + 0xc7f6152b 0x7919d596 0x1e1ff62e 0xc49604a0 + 0x33857369 0xeaa3f382 0x98b8cd86 0x176e1bf3 + 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0x6f3c9f7f + 0x34cf42d1 0xc1027cbb 0xde67c065 0xe0a229af + 0xfc8bd2e8 0xd62ca176 0x8bfb76b2 0x54a1388f + 0xe0650bb6 0x6d60682b 0xe16cf130 0xbd7c3ca2 + 0xea642814 0xa25f4d44 0x27013786 0x7316aa38 + 0x571511c8 0xf1b6b789 0xb7bfe72b 0x8fd2652c + 0xbfc7771a 0x51a2e551 0x3bd738c2 0x2698b495 + 0xec69a196 0xd5ecb5c4 0x9bd3224c 0x6d9ab4cf + 0x326c9942 0x4d711191 0xde9be50a 0xa980ca0b + 0xe8e59dd0 0x4439e4ae 0x35de914d 0xee499a84 + 0xd1ca0c9d 0xfe6ee96d 0x5b1f4fd0 0xabf0621a + 0x0c8220c7 0xcb6dbb1e 0xa5116036 0xe858d3c3 + 0x728e3a56 0x3b33e818 0xbe2643c1 0x497bbcc7 + 0xeb369828 0x9a4a01be 0x8c7e72a6 0xaf052f25 + 0x8d3ca85b 0x4703e55e 0x45647d4c 0x86d1e3e8 + 0x40ab59f9 0x3259b195 0xf979a147 0xb8961870 + 0x88b024f9 0x366e26bc 0xd6811525 0x252910c2 + 0x4223a20e 0x7fc971a3 0x4a639bf3 0xb6550c3b + 0xfe05e552 0xbdc98897 0x509923ff 0xf51a5abc + 0xc6cc0891 0x61cdac05 0x03a68664 0x1b80cc76 + 0xe18d8ee1 0x798bb4d2 0xd7769bf9 0x9ab4c02d + 0x7484774b 0xa9ee2c8b 0x87d34c85 0x15697682 + 0x9f6a4a55 0x9d7a731c 0x10014d6a 0xb9798070 + 0xd42f79cb 0x89db59b3 0xd5b0a0b6 0xf60864a5 + 0x2d6fb084 0x1cb607b2 0x48232701 0x9310cbc6 + 0x5bc81c98 0x6b25016c 0x2014b99d 0x0836e60b + 0x0addbc4c 0x3b8bac7c 0x8d95ac77 0x1d56c3c7 + 0x58333104 0x3d6eb719 0x676eb951 0xd5c2d1a3 + 0x239dae86 0x92181ab8 0xbdde9741 0x7995d452 + 0xe0020661 0x2f80c8b7 0xeedcd4fc 0xe4bde175 + 0xb98fdf78 0x84b9228f 0x78ecb4f3 0xe99e5d46 + 0xa33b9b96 0xe2cbc71c 0xc19e2146 0xdc0ee758 + 0x2d8f8767 0x2036685b 0x149df155 0x2e7ab376 + 0xb13b4266 0xf5c8a3b0 0x02ca1e19 0x1badd81b + 0xb9c1832a 0x73b31f75 0x69979b55 0x567070a2 + 0x2edeb3dc 0x26b55921 0x461df49f 0xc1aba883 + 0x25d6faec 0x5260e9bf 0xa8ccdd4c 0x04291961 + 0xfaf7a1b8 0xbc2d36e3 0xd6c86385 0x2757fbb9 + 0x62c7107c 0x87dac461 0x0c006454 0x0e971e49 + 0x4749afca 0x7f1fb389 0xdc0b69d3 0xc69fab09 + 0x12c372c9 0x78480a51 0x8ab03a94 0xb37022ca + 0x1d00e893 0x0989de45 0x8c819503 0x8e0e1c06 + 0x11cfef86 0x3c2386a6 0x66c0e6c8 0x1befa478 + 0xd2e7a4a7 0x9a8b5917 0x2cfa1816 0xaf7e6c7a + 0xd6c9f0ff 0x1aada3e0 0xbe36a471 0x5a91f3c7 + 0x6c61ea95 0x5246ef7c 0x20bc86c4 0xcfd87abd + 0xdc61f595 0x8310a684 0x0477e35c 0xe59e776f + 0xfa403863 0xdaf7bcb1 0xd6084825 0xb90bb047 + 0xeb9ff684 0x7223fbca 0x6b4af987 0x6b2553f8 + 0xdaabc6d2 0x82e2ebc3 0xa7c1c054 0x667eb0a7 + 0x53a0c7d4 0x3fcba743 0x38170187 0x2a2e5830 + 0xee134608 0xcd6e0112 0xac0831f9 0x9537d532 + 0x1e176b9c 0xe3fcb69f 0x17a2eee9 0xa9e6467f + 0xbf6b0246 0x6a08c0fb 0x7fb943b6 0xb8f67c0e + 0x2b3b4ffc 0xb155d20c 0x4eb5de53 0xf078715b + >; diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts new file mode 100644 index 0000000..8f34369 --- /dev/null +++ b/arch/x86/dts/minnowmax.dts @@ -0,0 +1,45 @@ +/* + * Copyright (C) 2014, Bin Meng bmeng.cn@gmail.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +/include/ "skeleton.dtsi" +/include/ "serial.dtsi" + +/ { + model = "Intel Minnowboard Max"; + compatible = "intel,minnowmax", "intel,baytrail"; + + aliases { + serial0 = &serial; + }; + + config { + silent_console = <0>; + }; + + chosen { + stdout-path = "/serial"; + }; + + spi { + #address-cells = <1>; + #size-cells = <0>; + compatible = "intel,ich"; + spi-flash@0 { + reg = <0>; + compatible = "sst,25vf016b", "spi-flash"; + memory-map = <0xff800000 0x00800000>; + }; + }; + + microcode { + update@0 { +#include "microcode/m0130673322.dtsi" + }; + }; + +}; diff --git a/arch/x86/dts/serial.dtsi b/arch/x86/dts/serial.dtsi index 9b097f4..6865eed 100644 --- a/arch/x86/dts/serial.dtsi +++ b/arch/x86/dts/serial.dtsi @@ -1,5 +1,5 @@ / { - serial { + serial: serial { compatible = "x86-uart"; reg = <0x3f8 8>; reg-shift = <0>; diff --git a/arch/x86/include/asm/arch-baytrail/fsp/azalia.h b/arch/x86/include/asm/arch-baytrail/fsp/azalia.h new file mode 100644 index 0000000..d96a20f --- /dev/null +++ b/arch/x86/include/asm/arch-baytrail/fsp/azalia.h @@ -0,0 +1,39 @@ +/* + * Copyright (C) 2013, Intel Corporation + * Copyright (C) 2015 Google, Inc + * + * SPDX-License-Identifier: Intel + */ + +#ifndef _FSP_AZALIA_H_ +#define _FSP_AZALIA_H_ + +struct __packed pch_azalia_verb_table_header { + uint32_t vendor_device_id; + uint16_t sub_system_id; + uint8_t revision_id; /* 0xff applies to all steppings */ + uint8_t front_panel_support; + uint16_t number_of_rear_jacks; + uint16_t number_of_front_jacks; +}; + +struct __packed pch_azalia_verb_table { + struct pch_azalia_verb_table_header verb_table_header; + const uint32_t *verb_table_data; +}; + +struct __packed pch_azalia_config { + uint8_t pme_enable:1; + uint8_t docking_supported:1; + uint8_t docking_attached:1; + uint8_t hdmi_codec_enable:1; + uint8_t azalia_v_ci_enable:1; + uint8_t rsvdbits:3; + /* number of verb tables provided by platform */ + uint8_t azalia_verb_table_num; + const struct pch_azalia_verb_table *azalia_verb_table; + /* delay timer after azalia reset */ + uint16_t reset_wait_timer_us; +}; + +#endif diff --git a/arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h b/arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h new file mode 100644 index 0000000..82862f6 --- /dev/null +++ b/arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h @@ -0,0 +1,95 @@ +/* + * Copyright (C) 2013, Intel Corporation + * Copyright (C) 2015 Google, Inc + * + * SPDX-License-Identifier: Intel + */ + +#ifndef __FSP_VPD_H +#define __FSP_VPD_H + +struct memory_down_data { + uint8_t enable_memory_down; + uint8_t dram_speed; + uint8_t dram_type; + uint8_t dimm_0_enable; + uint8_t dimm_1_enable; + uint8_t dimm_width; + uint8_t dimm_density; + uint8_t dimm_bus_width; + uint8_t dimm_sides; /* Ranks Per dimm_ */ + uint8_t dimm_tcl; /* tCL */ + /* tRP and tRCD in DRAM clk - 5:12.5ns, 6:15ns, etc. */ + uint8_t dimm_trpt_rcd; + uint8_t dimm_twr; /* tWR in DRAM clk */ + uint8_t dimm_twtr; /* tWTR in DRAM clk */ + uint8_t dimm_trrd; /* tRRD in DRAM clk */ + uint8_t dimm_trtp; /* tRTP in DRAM clk */ + uint8_t dimm_tfaw; /* tFAW in DRAM clk */ +}; + +struct __packed upd_region { + uint64_t signature; /* Offset 0x0000 */ + uint8_t reserved0[24]; /* Offset 0x0008 */ + uint16_t mrc_init_tseg_size; /* Offset 0x0020 */ + uint16_t mrc_init_mmio_size; /* Offset 0x0022 */ + uint8_t mrc_init_spd_addr1; /* Offset 0x0024 */ + uint8_t mrc_init_spd_addr2; /* Offset 0x0025 */ + uint8_t emmc_boot_mode; /* Offset 0x0026 */ + uint8_t enable_sdio; /* Offset 0x0027 */ + uint8_t enable_sdcard; /* Offset 0x0028 */ + uint8_t enable_hsuart0; /* Offset 0x0029 */ + uint8_t enable_hsuart1; /* Offset 0x002a */ + uint8_t enable_spi; /* Offset 0x002b */ + uint8_t reserved1; /* Offset 0x002c */ + uint8_t enable_sata; /* Offset 0x002d */ + uint8_t sata_mode; /* Offset 0x002e */ + uint8_t enable_azalia; /* Offset 0x002f */ + uint32_t azalia_config_ptr; /* Offset 0x0030 */ + uint8_t enable_xhci; /* Offset 0x0034 */ + uint8_t enable_lpe; /* Offset 0x0035 */ + uint8_t lpss_sio_enable_pci_mode; /* Offset 0x0036 */ + uint8_t enable_dma0; /* Offset 0x0037 */ + uint8_t enable_dma1; /* Offset 0x0038 */ + uint8_t enable_i2_c0; /* Offset 0x0039 */ + uint8_t enable_i2_c1; /* Offset 0x003a */ + uint8_t enable_i2_c2; /* Offset 0x003b */ + uint8_t enable_i2_c3; /* Offset 0x003c */ + uint8_t enable_i2_c4; /* Offset 0x003d */ + uint8_t enable_i2_c5; /* Offset 0x003e */ + uint8_t enable_i2_c6; /* Offset 0x003f */ + uint8_t enable_pwm0; /* Offset 0x0040 */ + uint8_t enable_pwm1; /* Offset 0x0041 */ + uint8_t enable_hsi; /* Offset 0x0042 */ + uint8_t igd_dvmt50_pre_alloc; /* Offset 0x0043 */ + uint8_t aperture_size; /* Offset 0x0044 */ + uint8_t gtt_size; /* Offset 0x0045 */ + uint32_t serial_debug_port_address; /* Offset 0x0046 */ + uint8_t serial_debug_port_type; /* Offset 0x004a */ + uint8_t mrc_debug_msg; /* Offset 0x004b */ + uint8_t isp_enable; /* Offset 0x004c */ + uint8_t scc_enable_pci_mode; /* Offset 0x004d */ + uint8_t igd_render_standby; /* Offset 0x004e */ + uint8_t txe_uma_enable; /* Offset 0x004f */ + uint8_t os_selection; /* Offset 0x0050 */ + uint8_t emmc45_ddr50_enabled; /* Offset 0x0051 */ + uint8_t emmc45_hs200_enabled; /* Offset 0x0052 */ + uint8_t emmc45_retune_timer_value; /* Offset 0x0053 */ + uint8_t unused_upd_space1[156]; /* Offset 0x0054 */ + struct memory_down_data memory_params; /* Offset 0x00f0 */ + uint16_t terminator; /* Offset 0x0100 */ +}; + +#define VPD_IMAGE_ID 0x3157454956594C56 /* 'VLYVIEW1' */ +#define VPD_IMAGE_REV 0x00000303 + +struct __packed vpd_region { + uint64_t sign; /* Offset 0x0000 */ + uint32_t img_rev; /* Offset 0x0008 */ + uint32_t upd_offset; /* Offset 0x000c */ + uint8_t unused[16]; /* Offset 0x0010 */ + uint32_t fsp_res_memlen; /* Offset 0x0020 */ + uint8_t platform_type; /* Offset 0x0024 */ + uint8_t enable_secure_boot; /* Offset 0x0025 */ +}; +#endif diff --git a/arch/x86/include/asm/arch-baytrail/gpio.h b/arch/x86/include/asm/arch-baytrail/gpio.h new file mode 100644 index 0000000..ab4e059 --- /dev/null +++ b/arch/x86/include/asm/arch-baytrail/gpio.h @@ -0,0 +1,13 @@ +/* + * Copyright (C) 2014, Bin Meng bmeng.cn@gmail.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _X86_ARCH_GPIO_H_ +#define _X86_ARCH_GPIO_H_ + +/* Where in config space is the register that points to the GPIO registers? */ +#define PCI_CFG_GPIOBASE 0x44 + +#endif /* _X86_ARCH_GPIO_H_ */ diff --git a/board/intel/minnowmax/Kconfig b/board/intel/minnowmax/Kconfig new file mode 100644 index 0000000..d9e370a --- /dev/null +++ b/board/intel/minnowmax/Kconfig @@ -0,0 +1,30 @@ +if TARGET_MINNOWMAX + +config SYS_BOARD + default "minnowmax" + +config SYS_VENDOR + default "intel" + +config SYS_SOC + default "baytrail" + +config SYS_CONFIG_NAME + default "minnowmax" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select X86_RESET_VECTOR + select INTEL_BAYTRAIL + select BOARD_ROMSIZE_KB_8192 + +config PCIE_ECAM_BASE + default 0xe0000000 + +config DEBUG_UART_BASE + default 0x3f8 + +config DEBUG_UART_CLOCK + default 1843200 + +endif diff --git a/board/intel/minnowmax/MAINTAINERS b/board/intel/minnowmax/MAINTAINERS new file mode 100644 index 0000000..d655761 --- /dev/null +++ b/board/intel/minnowmax/MAINTAINERS @@ -0,0 +1,6 @@ +CircuitCo Minnowboard Max +M: Simon Glass sjg@chromium.org +S: Maintained +F: board/intel/minnowmax +F: include/configs/minnowmax.h +F: configs/minnowmax_defconfig diff --git a/board/intel/minnowmax/Makefile b/board/intel/minnowmax/Makefile new file mode 100644 index 0000000..1a61432 --- /dev/null +++ b/board/intel/minnowmax/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (C) 2015, Google, Inc +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += minnowmax.o start.o diff --git a/board/intel/minnowmax/minnowmax.c b/board/intel/minnowmax/minnowmax.c new file mode 100644 index 0000000..6e82b16 --- /dev/null +++ b/board/intel/minnowmax/minnowmax.c @@ -0,0 +1,32 @@ +/* + * Copyright (C) 2015, Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/ibmpc.h> +#include <asm/pnp_def.h> +#include <netdev.h> +#include <smsc_lpc47m.h> + +#define SERIAL_DEV PNP_DEV(0x2e, 4) + +DECLARE_GLOBAL_DATA_PTR; + +int board_early_init_f(void) +{ + lpc47m_enable_serial(SERIAL_DEV, UART0_BASE); + + return 0; +} + +void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio) +{ + return; +} + +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} diff --git a/board/intel/minnowmax/start.S b/board/intel/minnowmax/start.S new file mode 100644 index 0000000..2c941a4 --- /dev/null +++ b/board/intel/minnowmax/start.S @@ -0,0 +1,9 @@ +/* + * Copyright (C) 2015, Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +.globl early_board_init +early_board_init: + jmp early_board_init_ret diff --git a/configs/minnowmax_defconfig b/configs/minnowmax_defconfig new file mode 100644 index 0000000..7bc9085 --- /dev/null +++ b/configs/minnowmax_defconfig @@ -0,0 +1,13 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xfff00000" +CONFIG_X86=y +CONFIG_TARGET_MINNOWMAX=y +CONFIG_OF_CONTROL=y +CONFIG_OF_SEPARATE=y +CONFIG_DEFAULT_DEVICE_TREE="minnowmax" +CONFIG_VIDEO_X86=y +CONFIG_FRAMEBUFFER_SET_VESA_MODE=y +CONFIG_FRAMEBUFFER_VESA_MODE_11A=y +CONFIG_DEBUG_UART_NS16550=y +CONFIG_DEBUG_UART=y +CONFIG_MMCONF_BASE_ADDRESS=0xe0000000 +CONFIG_HAVE_INTEL_ME=y diff --git a/doc/README.x86 b/doc/README.x86 index a9105f8..c699b79 100644 --- a/doc/README.x86 +++ b/doc/README.x86 @@ -18,11 +18,11 @@ U-Boot supports running as a coreboot [1] payload on x86. So far only Link on other x86 boards since coreboot deals with most of the low-level details.
U-Boot also supports booting directly from x86 reset vector without coreboot, -aka raw support or bare support. Currently Link and Intel Crown Bay board -support running U-Boot 'bare metal'. +aka raw support or bare support. Currently Link, Intel Crown Bay and Intel +Minnowboard Max support running U-Boot 'bare metal'.
-As for loading OS, U-Boot supports directly booting a 32-bit or 64-bit Linux -kernel as part of a FIT image. It also supports a compressed zImage. +As for loading an OS, U-Boot supports directly booting a 32-bit or 64-bit +Linux kernel as part of a FIT image. It also supports a compressed zImage.
Build Instructions ------------------ @@ -47,7 +47,7 @@ Change the 'Board configuration file' and 'Board Device Tree Source (dts) file' to point to a new board. You can also change the Cache-As-RAM (CAR) related settings here if the default values do not fit your new board.
-Building ROM version of U-Boot (hereafter referred to as u-boot.rom) is a +Building a ROM version of U-Boot (hereafter referred to as u-boot.rom) is a little bit tricky, as generally it requires several binary blobs which are not shipped in the U-Boot source tree. Due to this reason, the u-boot.rom build is not turned on by default in the U-Boot source tree. Firstly, you need turn it @@ -110,6 +110,33 @@ Now you can build U-Boot and obtain u-boot.rom $ make crownbay_defconfig $ make all
+ +Intel Minnowboard Max instructions: + +This uses as FSP as with Crown Bay, except it is for the Atom E3800 series. +Download this and get the .fd file (BAYTRAIL_FSP_GOLD_003_16-SEP-2014.fd at +the time of writing). Put it in the board directory: +board/intel/minnowmax/fsp.bin + +Obtain the VGA RAM (Vga.dat at the time of writing) and put it into the same +directory: board/intel/minnowmax/vga.bin + +You still need two more binary blobs. These come from the sample SPI image +provided in the FSP (SPI.bin at the time of writing). + +Use ifdtool in the U-Boot tools directory to extract the images from that +file, for example: + + $ ./tools/ifdtool -x BayleyBay/SPI.bin + $ cp flashregion_2_intel_me.bin board/intel/minnowmax/me.bin + $ cp flashregion_0_flashdescriptor.bin board/intel/minnowmax/descriptor.bin + +Now you can build U-Boot and obtain u-boot.rom + +$ make minnowmax_defconfig +$ make all + + Test with coreboot ------------------ For testing U-Boot as the coreboot payload, there are things that need be paid @@ -130,6 +157,16 @@ symbol address of _start (in arch/x86/cpu/start.S). If you want to use ELF as the coreboot payload, change U-Boot configuration to use CONFIG_OF_EMBED instead of CONFIG_OF_SEPARATE.
+To enable video you must enable these options in coreboot: + + - Set framebuffer graphics resolution (1280x1024 32k-color (1:5:5)) + - Keep VESA framebuffer + +At present it seems that for Minnowboard Max, coreboot does not pass through +the video information correctly (it always says the resolution is 0x0). This +works correctly for link though. + + CPU Microcode ------------- Modern CPUs usually require a special bit stream called microcode [5] to be diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h new file mode 100644 index 0000000..823e051 --- /dev/null +++ b/include/configs/minnowmax.h @@ -0,0 +1,72 @@ +/* + * Copyright (C) 2015 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <configs/x86-common.h> + +#define CONFIG_SYS_MONITOR_LEN (1 << 20) +#define CONFIG_BOARD_EARLY_INIT_F + +#define CONFIG_NR_DRAM_BANKS 1 + +#define CONFIG_X86_SERIAL +#define CONFIG_SMSC_LPC47M + +#define CONFIG_PCI_MEM_BUS 0xd0000000 +#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS +#define CONFIG_PCI_MEM_SIZE 0x10000000 + +#define CONFIG_PCI_PREF_BUS 0xc0000000 +#define CONFIG_PCI_PREF_PHYS CONFIG_PCI_PREF_BUS +#define CONFIG_PCI_PREF_SIZE 0x10000000 + +#define CONFIG_PCI_IO_BUS 0x2000 +#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS +#define CONFIG_PCI_IO_SIZE 0xe000 + +#define CONFIG_SYS_EARLY_PCI_INIT +#define CONFIG_PCI_PNP +#define CONFIG_RTL8169 +#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,vga,serial\0" \ + "stdout=vga,serial\0" \ + "stderr=vga,serial\0" + +#define CONFIG_SCSI_DEV_LIST \ + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA} +#define CONFIG_SPI_FLASH_SST + +#define CONFIG_MMC +#define CONFIG_SDHCI +#define CONFIG_GENERIC_MMC +#define CONFIG_MMC_SDMA +#define CONFIG_CMD_MMC + +#undef CONFIG_USB_MAX_CONTROLLER_COUNT +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 + +#define CONFIG_X86_OPTION_ROM_FILE vga.bin +#define CONFIG_X86_OPTION_ROM_ADDR 0xfff90000 + +#ifndef CONFIG_SYS_COREBOOT +#define CONFIG_VIDEO_VESA +#endif +#define VIDEO_IO_OFFSET 0 +#define CONFIG_X86EMU_RAW_IO +#define CONFIG_VGA_AS_SINGLE_DEVICE + +#define CONFIG_FIT_SIGNATURE +#define CONFIG_RSA + +/* Avoid a warning in the Realtek Ethernet driver */ +#define CONFIG_SYS_CACHELINE_SIZE 16 + +#endif /* __CONFIG_H */
On Wed, Jan 28, 2015 at 1:13 PM, Simon Glass sjg@chromium.org wrote:
This is a relatively low-cost x86 board in a small form factor. The main peripherals are uSD, USB, HDMI, Ethernet and SATA. It uses an Atom 3800 series CPU. So far only the dual core 2GB variant is supported.
This uses the existing FSP support. Binary blobs are required to make this board work. The microcode update is included as a patch (all 3000 lines of it).
Signed-off-by: Simon Glass sjg@chromium.org
Changes in v2:
- Move CONFIG_SYS_CACHELINE_SIZE to the board CONFIG file
- Add comment about FSP setting PCIE_ECAM_BASE
- Put baytrail Kconfig in alphabetical order
- Remove superfluous check for CONFIG_DEBUG_UART in setup_early_uart()
- Fix compatible string for SPI flash
- Remove commented-out DEBUG_UART_CLOCK baud rate
- Rename 'Coreboot' to 'coreboot' in README.x86
Reviewed-by: Bin Meng bmeng.cn@gmail.com
[snip]
Regards, Bin
On 27 January 2015 at 22:13, Bin Meng bmeng.cn@gmail.com wrote:
On Wed, Jan 28, 2015 at 1:13 PM, Simon Glass sjg@chromium.org wrote:
This is a relatively low-cost x86 board in a small form factor. The main peripherals are uSD, USB, HDMI, Ethernet and SATA. It uses an Atom 3800 series CPU. So far only the dual core 2GB variant is supported.
This uses the existing FSP support. Binary blobs are required to make this board work. The microcode update is included as a patch (all 3000 lines of it).
Signed-off-by: Simon Glass sjg@chromium.org
Changes in v2:
- Move CONFIG_SYS_CACHELINE_SIZE to the board CONFIG file
- Add comment about FSP setting PCIE_ECAM_BASE
- Put baytrail Kconfig in alphabetical order
- Remove superfluous check for CONFIG_DEBUG_UART in setup_early_uart()
- Fix compatible string for SPI flash
- Remove commented-out DEBUG_UART_CLOCK baud rate
- Rename 'Coreboot' to 'coreboot' in README.x86
Reviewed-by: Bin Meng bmeng.cn@gmail.com
(Rebased on top of upstream/master, so no longer has debug_uart and this code was dropped for now)
Applied to u-boot-x86.
Hi Simon and Bin (sorry for bringing this back from the dead),
But I have a question about fsp_configs.c down below:
On 01/27 22:13, Simon Glass wrote: ------------->8---------------
diff --git a/arch/x86/cpu/baytrail/fsp_configs.c b/arch/x86/cpu/baytrail/fsp_configs.c new file mode 100644 index 0000000..86b6926 --- /dev/null +++ b/arch/x86/cpu/baytrail/fsp_configs.c @@ -0,0 +1,156 @@ +/*
- Copyright (C) 2013, Intel Corporation
- Copyright (C) 2014, Bin Meng bmeng.cn@gmail.com
- SPDX-License-Identifier: Intel
- */
+#include <common.h> +#include <asm/arch/fsp/azalia.h> +#include <asm/fsp/fsp_support.h>
+/* ALC262 Verb Table - 10EC0262 */ +static const uint32_t verb_table_data13[] = {
- /* Pin Complex (NID 0x11) */
- 0x01171cf0,
- 0x01171d11,
- 0x01171e11,
- 0x01171f41,
- /* Pin Complex (NID 0x12) */
- 0x01271cf0,
- 0x01271d11,
- 0x01271e11,
- 0x01271f41,
- /* Pin Complex (NID 0x14) */
- 0x01471c10,
- 0x01471d40,
- 0x01471e01,
- 0x01471f01,
- /* Pin Complex (NID 0x15) */
- 0x01571cf0,
- 0x01571d11,
- 0x01571e11,
- 0x01571f41,
- /* Pin Complex (NID 0x16) */
- 0x01671cf0,
- 0x01671d11,
- 0x01671e11,
- 0x01671f41,
- /* Pin Complex (NID 0x18) */
- 0x01871c20,
- 0x01871d98,
- 0x01871ea1,
- 0x01871f01,
- /* Pin Complex (NID 0x19) */
- 0x01971c21,
- 0x01971d98,
- 0x01971ea1,
- 0x01971f02,
- /* Pin Complex (NID 0x1A) */
- 0x01a71c2f,
- 0x01a71d30,
- 0x01a71e81,
- 0x01a71f01,
- /* Pin Complex */
- 0x01b71c1f,
- 0x01b71d40,
- 0x01b71e21,
- 0x01b71f02,
- /* Pin Complex */
- 0x01c71cf0,
- 0x01c71d11,
- 0x01c71e11,
- 0x01c71f41,
- /* Pin Complex */
- 0x01d71c01,
- 0x01d71dc6,
- 0x01d71e14,
- 0x01d71f40,
- /* Pin Complex */
- 0x01e71cf0,
- 0x01e71d11,
- 0x01e71e11,
- 0x01e71f41,
- /* Pin Complex */
- 0x01f71cf0,
- 0x01f71d11,
- 0x01f71e11,
- 0x01f71f41,
+};
+/*
- This needs to be in ROM since if we put it in CAR, FSP init loses it when
- it drops CAR.
- TODO(sjg@chromium.org): Move to device tree when FSP allows it
- VerbTable: (RealTek ALC262)
- Revision ID = 0xFF, support all steps
- Codec Verb Table For AZALIA
- Codec Address: CAd value (0/1/2)
- Codec Vendor: 0x10EC0262
- */
+static const struct pch_azalia_verb_table azalia_verb_table[] = {
- {
{0x10ec0262,0x0000,0xff,0x01,0x000b,0x0002,},verb_table_data13- }
+};
+const struct pch_azalia_config azalia_config = {
- .pme_enable = 1,
- .docking_supported = 1,
- .docking_attached = 0,
- .hdmi_codec_enable = 1,
- .azalia_v_ci_enable = 1,
- .rsvdbits = 0,
- .azalia_verb_table_num = 1,
- .azalia_verb_table = azalia_verb_table,
- .reset_wait_timer_us = 300
+};
+void update_fsp_upd(struct upd_region *fsp_upd) +{
- struct memory_down_data *mem;
- /*
* Configure everything here to avoid the poor hard-pressed user* needing to run Intel's binary configuration tool. It may also allow* us to support the 1GB single core variant easily.** TODO(sjg@chromium.org): Move to device tree*/- fsp_upd->mrc_init_tseg_size = 8;
- fsp_upd->mrc_init_mmio_size = 0x800;
- fsp_upd->emmc_boot_mode = 0xff;
- fsp_upd->enable_sdio = 1;
- fsp_upd->enable_sdcard = 1;
- fsp_upd->enable_hsuart0 = 1;
- fsp_upd->azalia_config_ptr = (uint32_t)&azalia_config;
- fsp_upd->enable_i2_c0 = 0;
- fsp_upd->enable_i2_c2 = 0;
- fsp_upd->enable_i2_c3 = 0;
- fsp_upd->enable_i2_c4 = 0;
- fsp_upd->enable_xhci = 0;
- fsp_upd->igd_render_standby = 1;
- mem = &fsp_upd->memory_params;
- mem->enable_memory_down = 1;
- mem->dram_speed = 1;
- mem->dimm_width = 1;
- mem->dimm_density = 2;
- mem->dimm_tcl = 0xb;
- mem->dimm_trpt_rcd = 0xb;
- mem->dimm_twr = 0xc;
- mem->dimm_twtr = 6;
- mem->dimm_trrd = 6;
- mem->dimm_trtp = 6;
- mem->dimm_tfaw = 0x14;
+}
I am trying to move this fsp upd to use device tree as I am trying to create a patch set to add the Intel Valley Island E38xx board (which uses a SODIMM rather than memory down). In doing so, I've found that global data doesn't seem to be available when update_fsp_upd() is called and generally it seems that gd->fdt_blob is used to get a reference to the flattened device tree.
I'm not super familiar with device tree, but I was attempting to use fdtdec_next_compatible(gd->fdt_blob, 0, COMPAT_INTEL_BAYTRAIL_FSP) in a similar way that Quark does in my patchset (I've properly created the COMPAT_INTEL_BAYTRAIL_FSP define and some device tree nodes in my dts file). When I call fdtdec_next_compatible() the board does something which I'm unable to debug (Valley Island does not have the early UART pins connected so I have no early UART capability) but things just seem to stop.
In manually tracing the calls which lead to update_fsp_upd(), it seems that we haven't yet set up global data, so it makes sense that I can't reference it. But the device tree should be available in NOR flash or in some other way which we can access in order to get the FSP UPD settings.
Is there a simple way to access the device tree while it's still in NOR flash so I can avoid using gd? Or can global data be setup prior to calling update_fsp_upd() (I believe we're still in CAR at this point)? Or am I misunderstanding something basic here?
Did you have a rough outline of how this could be moved to device tree?
Thanks for your help! -Andrew
Hi Andrew,
On 26 May 2015 at 13:52, Andrew Bradford andrew@bradfordembedded.com wrote:
Hi Simon and Bin (sorry for bringing this back from the dead),
But I have a question about fsp_configs.c down below:
On 01/27 22:13, Simon Glass wrote: ------------->8---------------
diff --git a/arch/x86/cpu/baytrail/fsp_configs.c b/arch/x86/cpu/baytrail/fsp_configs.c new file mode 100644 index 0000000..86b6926 --- /dev/null +++ b/arch/x86/cpu/baytrail/fsp_configs.c @@ -0,0 +1,156 @@ +/*
- Copyright (C) 2013, Intel Corporation
- Copyright (C) 2014, Bin Meng bmeng.cn@gmail.com
- SPDX-License-Identifier: Intel
- */
+#include <common.h> +#include <asm/arch/fsp/azalia.h> +#include <asm/fsp/fsp_support.h>
+/* ALC262 Verb Table - 10EC0262 */ +static const uint32_t verb_table_data13[] = {
/* Pin Complex (NID 0x11) */0x01171cf0,0x01171d11,0x01171e11,0x01171f41,/* Pin Complex (NID 0x12) */0x01271cf0,0x01271d11,0x01271e11,0x01271f41,/* Pin Complex (NID 0x14) */0x01471c10,0x01471d40,0x01471e01,0x01471f01,/* Pin Complex (NID 0x15) */0x01571cf0,0x01571d11,0x01571e11,0x01571f41,/* Pin Complex (NID 0x16) */0x01671cf0,0x01671d11,0x01671e11,0x01671f41,/* Pin Complex (NID 0x18) */0x01871c20,0x01871d98,0x01871ea1,0x01871f01,/* Pin Complex (NID 0x19) */0x01971c21,0x01971d98,0x01971ea1,0x01971f02,/* Pin Complex (NID 0x1A) */0x01a71c2f,0x01a71d30,0x01a71e81,0x01a71f01,/* Pin Complex */0x01b71c1f,0x01b71d40,0x01b71e21,0x01b71f02,/* Pin Complex */0x01c71cf0,0x01c71d11,0x01c71e11,0x01c71f41,/* Pin Complex */0x01d71c01,0x01d71dc6,0x01d71e14,0x01d71f40,/* Pin Complex */0x01e71cf0,0x01e71d11,0x01e71e11,0x01e71f41,/* Pin Complex */0x01f71cf0,0x01f71d11,0x01f71e11,0x01f71f41,+};
+/*
- This needs to be in ROM since if we put it in CAR, FSP init loses it when
- it drops CAR.
- TODO(sjg@chromium.org): Move to device tree when FSP allows it
- VerbTable: (RealTek ALC262)
- Revision ID = 0xFF, support all steps
- Codec Verb Table For AZALIA
- Codec Address: CAd value (0/1/2)
- Codec Vendor: 0x10EC0262
- */
+static const struct pch_azalia_verb_table azalia_verb_table[] = {
{{0x10ec0262,0x0000,0xff,0x01,0x000b,0x0002,},verb_table_data13}+};
+const struct pch_azalia_config azalia_config = {
.pme_enable = 1,.docking_supported = 1,.docking_attached = 0,.hdmi_codec_enable = 1,.azalia_v_ci_enable = 1,.rsvdbits = 0,.azalia_verb_table_num = 1,.azalia_verb_table = azalia_verb_table,.reset_wait_timer_us = 300+};
+void update_fsp_upd(struct upd_region *fsp_upd) +{
struct memory_down_data *mem;/** Configure everything here to avoid the poor hard-pressed user* needing to run Intel's binary configuration tool. It may also allow* us to support the 1GB single core variant easily.** TODO(sjg@chromium.org): Move to device tree*/fsp_upd->mrc_init_tseg_size = 8;fsp_upd->mrc_init_mmio_size = 0x800;fsp_upd->emmc_boot_mode = 0xff;fsp_upd->enable_sdio = 1;fsp_upd->enable_sdcard = 1;fsp_upd->enable_hsuart0 = 1;fsp_upd->azalia_config_ptr = (uint32_t)&azalia_config;fsp_upd->enable_i2_c0 = 0;fsp_upd->enable_i2_c2 = 0;fsp_upd->enable_i2_c3 = 0;fsp_upd->enable_i2_c4 = 0;fsp_upd->enable_xhci = 0;fsp_upd->igd_render_standby = 1;mem = &fsp_upd->memory_params;mem->enable_memory_down = 1;mem->dram_speed = 1;mem->dimm_width = 1;mem->dimm_density = 2;mem->dimm_tcl = 0xb;mem->dimm_trpt_rcd = 0xb;mem->dimm_twr = 0xc;mem->dimm_twtr = 6;mem->dimm_trrd = 6;mem->dimm_trtp = 6;mem->dimm_tfaw = 0x14;+}
I am trying to move this fsp upd to use device tree as I am trying to create a patch set to add the Intel Valley Island E38xx board (which uses a SODIMM rather than memory down). In doing so, I've found that global data doesn't seem to be available when update_fsp_upd() is called and generally it seems that gd->fdt_blob is used to get a reference to the flattened device tree.
I'm not super familiar with device tree, but I was attempting to use fdtdec_next_compatible(gd->fdt_blob, 0, COMPAT_INTEL_BAYTRAIL_FSP) in a similar way that Quark does in my patchset (I've properly created the COMPAT_INTEL_BAYTRAIL_FSP define and some device tree nodes in my dts file). When I call fdtdec_next_compatible() the board does something which I'm unable to debug (Valley Island does not have the early UART pins connected so I have no early UART capability) but things just seem to stop.
In manually tracing the calls which lead to update_fsp_upd(), it seems that we haven't yet set up global data, so it makes sense that I can't reference it. But the device tree should be available in NOR flash or in some other way which we can access in order to get the FSP UPD settings.
Is there a simple way to access the device tree while it's still in NOR flash so I can avoid using gd? Or can global data be setup prior to calling update_fsp_upd() (I believe we're still in CAR at this point)? Or am I misunderstanding something basic here?
Did you have a rough outline of how this could be moved to device tree?
This is a bit tricky. I would like to move fsp_init() later in the init sequence (e.g. to board_init_f()). See this TODO in the code:
/* * TODO: * * According to FSP architecture spec, the fsp_init() will not return * to its caller, instead it requires the bootloader to provide a * so-called continuation function to pass into the FSP as a parameter * of fsp_init, and fsp_init() will call that continuation function * directly. * * The call to fsp_init() may need to be moved out of the car_init() * to cpu_init_f() with the help of some inline assembly codes. * Note there is another issue that fsp_init() will setup another stack * using the fsp_init parameter stack_top after DRAM is initialized, * which means any data on the previous stack (on the CAR) gets lost * (ie: U-Boot global_data). FSP is supposed to support such scenario, * however it does not work. This should be revisited in the future. */
The primary issues are: 1. The need to recover the global_data 2. The need to change to a new stack
Re 1, my reading of the HOB stuff is that it is supposed to provide you with a pointer to the CAR RAM (all ~128KB of it) so that you can go back and find your old stack (and in our case, global_data).
Bin mentioned that this doesn't work - his is the comment above after I asked him about it.
But if it could be made to work, then we could delay the init.
Re 2, U-Boot expects to change to a new stack when it wants to, which is at the boundary of board_init_f() and board_init_r(). The Intel FSP should not mandate a stack change over a C function call. IMO that is just bad design. Dealing with it is not very easy, but one option is to run with the new stack for the rest of the board_init_f() sequence and then change stack again at the end of the sequence. Ick.
To specifically address your problem, global_data is not available until board_init_f() is called, and the device tree comes into existence soon after. We could hack around it - e.g. with microcode we find it in the device tree and stick a pointer to it in a special place. But the real solution is to figure out how to move this fsp_init() stuff to later in the sequence. For non-FSP boards we don't have this problem - e.g. ivybridge does RAM init long after we have global_data and device tree. Note it is still running from flash at this point, but CAR is set up and that is where global_data resides.
I'm interested to hear what you figure out.
Thanks for your help! -Andrew
Regards, Simon
Hi Simon,
On Wed, May 27, 2015 at 5:37 AM, Simon Glass sjg@chromium.org wrote:
Hi Andrew,
On 26 May 2015 at 13:52, Andrew Bradford andrew@bradfordembedded.com wrote:
Hi Simon and Bin (sorry for bringing this back from the dead),
But I have a question about fsp_configs.c down below:
On 01/27 22:13, Simon Glass wrote: ------------->8---------------
diff --git a/arch/x86/cpu/baytrail/fsp_configs.c b/arch/x86/cpu/baytrail/fsp_configs.c new file mode 100644 index 0000000..86b6926 --- /dev/null +++ b/arch/x86/cpu/baytrail/fsp_configs.c @@ -0,0 +1,156 @@ +/*
- Copyright (C) 2013, Intel Corporation
- Copyright (C) 2014, Bin Meng bmeng.cn@gmail.com
- SPDX-License-Identifier: Intel
- */
+#include <common.h> +#include <asm/arch/fsp/azalia.h> +#include <asm/fsp/fsp_support.h>
+/* ALC262 Verb Table - 10EC0262 */ +static const uint32_t verb_table_data13[] = {
/* Pin Complex (NID 0x11) */0x01171cf0,0x01171d11,0x01171e11,0x01171f41,/* Pin Complex (NID 0x12) */0x01271cf0,0x01271d11,0x01271e11,0x01271f41,/* Pin Complex (NID 0x14) */0x01471c10,0x01471d40,0x01471e01,0x01471f01,/* Pin Complex (NID 0x15) */0x01571cf0,0x01571d11,0x01571e11,0x01571f41,/* Pin Complex (NID 0x16) */0x01671cf0,0x01671d11,0x01671e11,0x01671f41,/* Pin Complex (NID 0x18) */0x01871c20,0x01871d98,0x01871ea1,0x01871f01,/* Pin Complex (NID 0x19) */0x01971c21,0x01971d98,0x01971ea1,0x01971f02,/* Pin Complex (NID 0x1A) */0x01a71c2f,0x01a71d30,0x01a71e81,0x01a71f01,/* Pin Complex */0x01b71c1f,0x01b71d40,0x01b71e21,0x01b71f02,/* Pin Complex */0x01c71cf0,0x01c71d11,0x01c71e11,0x01c71f41,/* Pin Complex */0x01d71c01,0x01d71dc6,0x01d71e14,0x01d71f40,/* Pin Complex */0x01e71cf0,0x01e71d11,0x01e71e11,0x01e71f41,/* Pin Complex */0x01f71cf0,0x01f71d11,0x01f71e11,0x01f71f41,+};
+/*
- This needs to be in ROM since if we put it in CAR, FSP init loses it when
- it drops CAR.
- TODO(sjg@chromium.org): Move to device tree when FSP allows it
- VerbTable: (RealTek ALC262)
- Revision ID = 0xFF, support all steps
- Codec Verb Table For AZALIA
- Codec Address: CAd value (0/1/2)
- Codec Vendor: 0x10EC0262
- */
+static const struct pch_azalia_verb_table azalia_verb_table[] = {
{{0x10ec0262,0x0000,0xff,0x01,0x000b,0x0002,},verb_table_data13}+};
+const struct pch_azalia_config azalia_config = {
.pme_enable = 1,.docking_supported = 1,.docking_attached = 0,.hdmi_codec_enable = 1,.azalia_v_ci_enable = 1,.rsvdbits = 0,.azalia_verb_table_num = 1,.azalia_verb_table = azalia_verb_table,.reset_wait_timer_us = 300+};
+void update_fsp_upd(struct upd_region *fsp_upd) +{
struct memory_down_data *mem;/** Configure everything here to avoid the poor hard-pressed user* needing to run Intel's binary configuration tool. It may also allow* us to support the 1GB single core variant easily.** TODO(sjg@chromium.org): Move to device tree*/fsp_upd->mrc_init_tseg_size = 8;fsp_upd->mrc_init_mmio_size = 0x800;fsp_upd->emmc_boot_mode = 0xff;fsp_upd->enable_sdio = 1;fsp_upd->enable_sdcard = 1;fsp_upd->enable_hsuart0 = 1;fsp_upd->azalia_config_ptr = (uint32_t)&azalia_config;fsp_upd->enable_i2_c0 = 0;fsp_upd->enable_i2_c2 = 0;fsp_upd->enable_i2_c3 = 0;fsp_upd->enable_i2_c4 = 0;fsp_upd->enable_xhci = 0;fsp_upd->igd_render_standby = 1;mem = &fsp_upd->memory_params;mem->enable_memory_down = 1;mem->dram_speed = 1;mem->dimm_width = 1;mem->dimm_density = 2;mem->dimm_tcl = 0xb;mem->dimm_trpt_rcd = 0xb;mem->dimm_twr = 0xc;mem->dimm_twtr = 6;mem->dimm_trrd = 6;mem->dimm_trtp = 6;mem->dimm_tfaw = 0x14;+}
I am trying to move this fsp upd to use device tree as I am trying to create a patch set to add the Intel Valley Island E38xx board (which uses a SODIMM rather than memory down). In doing so, I've found that global data doesn't seem to be available when update_fsp_upd() is called and generally it seems that gd->fdt_blob is used to get a reference to the flattened device tree.
I'm not super familiar with device tree, but I was attempting to use fdtdec_next_compatible(gd->fdt_blob, 0, COMPAT_INTEL_BAYTRAIL_FSP) in a similar way that Quark does in my patchset (I've properly created the COMPAT_INTEL_BAYTRAIL_FSP define and some device tree nodes in my dts file). When I call fdtdec_next_compatible() the board does something which I'm unable to debug (Valley Island does not have the early UART pins connected so I have no early UART capability) but things just seem to stop.
In manually tracing the calls which lead to update_fsp_upd(), it seems that we haven't yet set up global data, so it makes sense that I can't reference it. But the device tree should be available in NOR flash or in some other way which we can access in order to get the FSP UPD settings.
Is there a simple way to access the device tree while it's still in NOR flash so I can avoid using gd? Or can global data be setup prior to calling update_fsp_upd() (I believe we're still in CAR at this point)? Or am I misunderstanding something basic here?
Did you have a rough outline of how this could be moved to device tree?
This is a bit tricky. I would like to move fsp_init() later in the init sequence (e.g. to board_init_f()). See this TODO in the code:
/*
- TODO:
- According to FSP architecture spec, the fsp_init() will not return
- to its caller, instead it requires the bootloader to provide a
- so-called continuation function to pass into the FSP as a parameter
- of fsp_init, and fsp_init() will call that continuation function
- directly.
- The call to fsp_init() may need to be moved out of the car_init()
- to cpu_init_f() with the help of some inline assembly codes.
- Note there is another issue that fsp_init() will setup another stack
- using the fsp_init parameter stack_top after DRAM is initialized,
- which means any data on the previous stack (on the CAR) gets lost
- (ie: U-Boot global_data). FSP is supposed to support such scenario,
- however it does not work. This should be revisited in the future.
*/
The primary issues are:
- The need to recover the global_data
- The need to change to a new stack
Re 1, my reading of the HOB stuff is that it is supposed to provide you with a pointer to the CAR RAM (all ~128KB of it) so that you can go back and find your old stack (and in our case, global_data).
Bin mentioned that this doesn't work - his is the comment above after I asked him about it.
But if it could be made to work, then we could delay the init.
Re 2, U-Boot expects to change to a new stack when it wants to, which is at the boundary of board_init_f() and board_init_r(). The Intel FSP should not mandate a stack change over a C function call. IMO that is just bad design. Dealing with it is not very easy, but one option is to run with the new stack for the rest of the board_init_f() sequence and then change stack again at the end of the sequence. Ick.
To specifically address your problem, global_data is not available until board_init_f() is called, and the device tree comes into existence soon after. We could hack around it - e.g. with microcode we find it in the device tree and stick a pointer to it in a special place. But the real solution is to figure out how to move this fsp_init() stuff to later in the sequence. For non-FSP boards we don't have this problem - e.g. ivybridge does RAM init long after we have global_data and device tree. Note it is still running from flash at this point, but CAR is set up and that is where global_data resides.
I'm interested to hear what you figure out.
I just noticed that Intel has released FSP specification v1.1 [1] in April. After a rough read of the 1.1 spec, it looks to me that Intel changed the fsp_init() design by breaking it down into 3 sub-routines: FspMemoryInit(), TempRamExit() and FspSiliconInit(). I feel this might be more logical to adapt U-Boot, but again I am not sure if the stack migration stuff is still there. So far I don't see any new FSP releases using the 1.1 spec.
[1] https://www-ssl.intel.com/content/www/us/en/embedded/software/fsp/fsp-archit...
Regards, Bin
On 05/27 13:19, Bin Meng wrote:
Hi Simon,
On Wed, May 27, 2015 at 5:37 AM, Simon Glass sjg@chromium.org wrote:
Hi Andrew,
On 26 May 2015 at 13:52, Andrew Bradford andrew@bradfordembedded.com wrote:
Hi Simon and Bin (sorry for bringing this back from the dead),
But I have a question about fsp_configs.c down below:
On 01/27 22:13, Simon Glass wrote: ------------->8---------------
diff --git a/arch/x86/cpu/baytrail/fsp_configs.c b/arch/x86/cpu/baytrail/fsp_configs.c new file mode 100644 index 0000000..86b6926 --- /dev/null +++ b/arch/x86/cpu/baytrail/fsp_configs.c @@ -0,0 +1,156 @@ +/*
- Copyright (C) 2013, Intel Corporation
- Copyright (C) 2014, Bin Meng bmeng.cn@gmail.com
- SPDX-License-Identifier: Intel
- */
+#include <common.h> +#include <asm/arch/fsp/azalia.h> +#include <asm/fsp/fsp_support.h>
+/* ALC262 Verb Table - 10EC0262 */ +static const uint32_t verb_table_data13[] = {
/* Pin Complex (NID 0x11) */0x01171cf0,0x01171d11,0x01171e11,0x01171f41,/* Pin Complex (NID 0x12) */0x01271cf0,0x01271d11,0x01271e11,0x01271f41,/* Pin Complex (NID 0x14) */0x01471c10,0x01471d40,0x01471e01,0x01471f01,/* Pin Complex (NID 0x15) */0x01571cf0,0x01571d11,0x01571e11,0x01571f41,/* Pin Complex (NID 0x16) */0x01671cf0,0x01671d11,0x01671e11,0x01671f41,/* Pin Complex (NID 0x18) */0x01871c20,0x01871d98,0x01871ea1,0x01871f01,/* Pin Complex (NID 0x19) */0x01971c21,0x01971d98,0x01971ea1,0x01971f02,/* Pin Complex (NID 0x1A) */0x01a71c2f,0x01a71d30,0x01a71e81,0x01a71f01,/* Pin Complex */0x01b71c1f,0x01b71d40,0x01b71e21,0x01b71f02,/* Pin Complex */0x01c71cf0,0x01c71d11,0x01c71e11,0x01c71f41,/* Pin Complex */0x01d71c01,0x01d71dc6,0x01d71e14,0x01d71f40,/* Pin Complex */0x01e71cf0,0x01e71d11,0x01e71e11,0x01e71f41,/* Pin Complex */0x01f71cf0,0x01f71d11,0x01f71e11,0x01f71f41,+};
+/*
- This needs to be in ROM since if we put it in CAR, FSP init loses it when
- it drops CAR.
- TODO(sjg@chromium.org): Move to device tree when FSP allows it
- VerbTable: (RealTek ALC262)
- Revision ID = 0xFF, support all steps
- Codec Verb Table For AZALIA
- Codec Address: CAd value (0/1/2)
- Codec Vendor: 0x10EC0262
- */
+static const struct pch_azalia_verb_table azalia_verb_table[] = {
{{0x10ec0262,0x0000,0xff,0x01,0x000b,0x0002,},verb_table_data13}+};
+const struct pch_azalia_config azalia_config = {
.pme_enable = 1,.docking_supported = 1,.docking_attached = 0,.hdmi_codec_enable = 1,.azalia_v_ci_enable = 1,.rsvdbits = 0,.azalia_verb_table_num = 1,.azalia_verb_table = azalia_verb_table,.reset_wait_timer_us = 300+};
+void update_fsp_upd(struct upd_region *fsp_upd) +{
struct memory_down_data *mem;/** Configure everything here to avoid the poor hard-pressed user* needing to run Intel's binary configuration tool. It may also allow* us to support the 1GB single core variant easily.** TODO(sjg@chromium.org): Move to device tree*/fsp_upd->mrc_init_tseg_size = 8;fsp_upd->mrc_init_mmio_size = 0x800;fsp_upd->emmc_boot_mode = 0xff;fsp_upd->enable_sdio = 1;fsp_upd->enable_sdcard = 1;fsp_upd->enable_hsuart0 = 1;fsp_upd->azalia_config_ptr = (uint32_t)&azalia_config;fsp_upd->enable_i2_c0 = 0;fsp_upd->enable_i2_c2 = 0;fsp_upd->enable_i2_c3 = 0;fsp_upd->enable_i2_c4 = 0;fsp_upd->enable_xhci = 0;fsp_upd->igd_render_standby = 1;mem = &fsp_upd->memory_params;mem->enable_memory_down = 1;mem->dram_speed = 1;mem->dimm_width = 1;mem->dimm_density = 2;mem->dimm_tcl = 0xb;mem->dimm_trpt_rcd = 0xb;mem->dimm_twr = 0xc;mem->dimm_twtr = 6;mem->dimm_trrd = 6;mem->dimm_trtp = 6;mem->dimm_tfaw = 0x14;+}
I am trying to move this fsp upd to use device tree as I am trying to create a patch set to add the Intel Valley Island E38xx board (which uses a SODIMM rather than memory down). In doing so, I've found that global data doesn't seem to be available when update_fsp_upd() is called and generally it seems that gd->fdt_blob is used to get a reference to the flattened device tree.
I'm not super familiar with device tree, but I was attempting to use fdtdec_next_compatible(gd->fdt_blob, 0, COMPAT_INTEL_BAYTRAIL_FSP) in a similar way that Quark does in my patchset (I've properly created the COMPAT_INTEL_BAYTRAIL_FSP define and some device tree nodes in my dts file). When I call fdtdec_next_compatible() the board does something which I'm unable to debug (Valley Island does not have the early UART pins connected so I have no early UART capability) but things just seem to stop.
In manually tracing the calls which lead to update_fsp_upd(), it seems that we haven't yet set up global data, so it makes sense that I can't reference it. But the device tree should be available in NOR flash or in some other way which we can access in order to get the FSP UPD settings.
Is there a simple way to access the device tree while it's still in NOR flash so I can avoid using gd? Or can global data be setup prior to calling update_fsp_upd() (I believe we're still in CAR at this point)? Or am I misunderstanding something basic here?
Did you have a rough outline of how this could be moved to device tree?
This is a bit tricky. I would like to move fsp_init() later in the init sequence (e.g. to board_init_f()). See this TODO in the code:
/*
- TODO:
- According to FSP architecture spec, the fsp_init() will not return
- to its caller, instead it requires the bootloader to provide a
- so-called continuation function to pass into the FSP as a parameter
- of fsp_init, and fsp_init() will call that continuation function
- directly.
- The call to fsp_init() may need to be moved out of the car_init()
- to cpu_init_f() with the help of some inline assembly codes.
- Note there is another issue that fsp_init() will setup another stack
- using the fsp_init parameter stack_top after DRAM is initialized,
- which means any data on the previous stack (on the CAR) gets lost
- (ie: U-Boot global_data). FSP is supposed to support such scenario,
- however it does not work. This should be revisited in the future.
*/
The primary issues are:
- The need to recover the global_data
- The need to change to a new stack
Re 1, my reading of the HOB stuff is that it is supposed to provide you with a pointer to the CAR RAM (all ~128KB of it) so that you can go back and find your old stack (and in our case, global_data).
Bin mentioned that this doesn't work - his is the comment above after I asked him about it.
But if it could be made to work, then we could delay the init.
Re 2, U-Boot expects to change to a new stack when it wants to, which is at the boundary of board_init_f() and board_init_r(). The Intel FSP should not mandate a stack change over a C function call. IMO that is just bad design. Dealing with it is not very easy, but one option is to run with the new stack for the rest of the board_init_f() sequence and then change stack again at the end of the sequence. Ick.
To specifically address your problem, global_data is not available until board_init_f() is called, and the device tree comes into existence soon after. We could hack around it - e.g. with microcode we find it in the device tree and stick a pointer to it in a special place. But the real solution is to figure out how to move this fsp_init() stuff to later in the sequence. For non-FSP boards we don't have this problem - e.g. ivybridge does RAM init long after we have global_data and device tree. Note it is still running from flash at this point, but CAR is set up and that is where global_data resides.
I'm interested to hear what you figure out.
I just noticed that Intel has released FSP specification v1.1 [1] in April. After a rough read of the 1.1 spec, it looks to me that Intel changed the fsp_init() design by breaking it down into 3 sub-routines: FspMemoryInit(), TempRamExit() and FspSiliconInit(). I feel this might be more logical to adapt U-Boot, but again I am not sure if the stack migration stuff is still there. So far I don't see any new FSP releases using the 1.1 spec.
[1] https://www-ssl.intel.com/content/www/us/en/embedded/software/fsp/fsp-archit...
There's also a very good overview of how to use an FSP v1.1 firmware at [1]. It states that the problem in v1.0 for bootloaders was that when you call FspInit() that temporary ram was torn down unconditionally. Now, in v1.1, it says after calling FspMemoryInit() that control will be given back to the bootloader running in the temporary ram (CAR?). Then the bootloader is responsible for migrating to main memory and to call TempRamExit() so that temporary memory can be cleaned up.
This sounds like what u-boot would want and what Simon described above, for u-boot to be in charge of relocating from CAR to main memory, right? If so, likely things will be much easier once there's a v1.1 FSP for baytrail...
[1]:http://firmware.intel.com/sites/default/files/resources/A_Tour_Beyond_BIOS_C...
Thanks! -Andrew
Hi Andrew,
On 27 May 2015 at 08:39, Andrew Bradford andrew@bradfordembedded.com wrote:
On 05/27 13:19, Bin Meng wrote:
Hi Simon,
On Wed, May 27, 2015 at 5:37 AM, Simon Glass sjg@chromium.org wrote:
Hi Andrew,
On 26 May 2015 at 13:52, Andrew Bradford andrew@bradfordembedded.com wrote:
Hi Simon and Bin (sorry for bringing this back from the dead),
But I have a question about fsp_configs.c down below:
On 01/27 22:13, Simon Glass wrote: ------------->8---------------
diff --git a/arch/x86/cpu/baytrail/fsp_configs.c b/arch/x86/cpu/baytrail/fsp_configs.c new file mode 100644 index 0000000..86b6926 --- /dev/null +++ b/arch/x86/cpu/baytrail/fsp_configs.c @@ -0,0 +1,156 @@ +/*
- Copyright (C) 2013, Intel Corporation
- Copyright (C) 2014, Bin Meng bmeng.cn@gmail.com
- SPDX-License-Identifier: Intel
- */
+#include <common.h> +#include <asm/arch/fsp/azalia.h> +#include <asm/fsp/fsp_support.h>
+/* ALC262 Verb Table - 10EC0262 */ +static const uint32_t verb_table_data13[] = {
/* Pin Complex (NID 0x11) */0x01171cf0,0x01171d11,0x01171e11,0x01171f41,/* Pin Complex (NID 0x12) */0x01271cf0,0x01271d11,0x01271e11,0x01271f41,/* Pin Complex (NID 0x14) */0x01471c10,0x01471d40,0x01471e01,0x01471f01,/* Pin Complex (NID 0x15) */0x01571cf0,0x01571d11,0x01571e11,0x01571f41,/* Pin Complex (NID 0x16) */0x01671cf0,0x01671d11,0x01671e11,0x01671f41,/* Pin Complex (NID 0x18) */0x01871c20,0x01871d98,0x01871ea1,0x01871f01,/* Pin Complex (NID 0x19) */0x01971c21,0x01971d98,0x01971ea1,0x01971f02,/* Pin Complex (NID 0x1A) */0x01a71c2f,0x01a71d30,0x01a71e81,0x01a71f01,/* Pin Complex */0x01b71c1f,0x01b71d40,0x01b71e21,0x01b71f02,/* Pin Complex */0x01c71cf0,0x01c71d11,0x01c71e11,0x01c71f41,/* Pin Complex */0x01d71c01,0x01d71dc6,0x01d71e14,0x01d71f40,/* Pin Complex */0x01e71cf0,0x01e71d11,0x01e71e11,0x01e71f41,/* Pin Complex */0x01f71cf0,0x01f71d11,0x01f71e11,0x01f71f41,+};
+/*
- This needs to be in ROM since if we put it in CAR, FSP init loses it when
- it drops CAR.
- TODO(sjg@chromium.org): Move to device tree when FSP allows it
- VerbTable: (RealTek ALC262)
- Revision ID = 0xFF, support all steps
- Codec Verb Table For AZALIA
- Codec Address: CAd value (0/1/2)
- Codec Vendor: 0x10EC0262
- */
+static const struct pch_azalia_verb_table azalia_verb_table[] = {
{{0x10ec0262,0x0000,0xff,0x01,0x000b,0x0002,},verb_table_data13}+};
+const struct pch_azalia_config azalia_config = {
.pme_enable = 1,.docking_supported = 1,.docking_attached = 0,.hdmi_codec_enable = 1,.azalia_v_ci_enable = 1,.rsvdbits = 0,.azalia_verb_table_num = 1,.azalia_verb_table = azalia_verb_table,.reset_wait_timer_us = 300+};
+void update_fsp_upd(struct upd_region *fsp_upd) +{
struct memory_down_data *mem;/** Configure everything here to avoid the poor hard-pressed user* needing to run Intel's binary configuration tool. It may also allow* us to support the 1GB single core variant easily.** TODO(sjg@chromium.org): Move to device tree*/fsp_upd->mrc_init_tseg_size = 8;fsp_upd->mrc_init_mmio_size = 0x800;fsp_upd->emmc_boot_mode = 0xff;fsp_upd->enable_sdio = 1;fsp_upd->enable_sdcard = 1;fsp_upd->enable_hsuart0 = 1;fsp_upd->azalia_config_ptr = (uint32_t)&azalia_config;fsp_upd->enable_i2_c0 = 0;fsp_upd->enable_i2_c2 = 0;fsp_upd->enable_i2_c3 = 0;fsp_upd->enable_i2_c4 = 0;fsp_upd->enable_xhci = 0;fsp_upd->igd_render_standby = 1;mem = &fsp_upd->memory_params;mem->enable_memory_down = 1;mem->dram_speed = 1;mem->dimm_width = 1;mem->dimm_density = 2;mem->dimm_tcl = 0xb;mem->dimm_trpt_rcd = 0xb;mem->dimm_twr = 0xc;mem->dimm_twtr = 6;mem->dimm_trrd = 6;mem->dimm_trtp = 6;mem->dimm_tfaw = 0x14;+}
I am trying to move this fsp upd to use device tree as I am trying to create a patch set to add the Intel Valley Island E38xx board (which uses a SODIMM rather than memory down). In doing so, I've found that global data doesn't seem to be available when update_fsp_upd() is called and generally it seems that gd->fdt_blob is used to get a reference to the flattened device tree.
I'm not super familiar with device tree, but I was attempting to use fdtdec_next_compatible(gd->fdt_blob, 0, COMPAT_INTEL_BAYTRAIL_FSP) in a similar way that Quark does in my patchset (I've properly created the COMPAT_INTEL_BAYTRAIL_FSP define and some device tree nodes in my dts file). When I call fdtdec_next_compatible() the board does something which I'm unable to debug (Valley Island does not have the early UART pins connected so I have no early UART capability) but things just seem to stop.
In manually tracing the calls which lead to update_fsp_upd(), it seems that we haven't yet set up global data, so it makes sense that I can't reference it. But the device tree should be available in NOR flash or in some other way which we can access in order to get the FSP UPD settings.
Is there a simple way to access the device tree while it's still in NOR flash so I can avoid using gd? Or can global data be setup prior to calling update_fsp_upd() (I believe we're still in CAR at this point)? Or am I misunderstanding something basic here?
Did you have a rough outline of how this could be moved to device tree?
This is a bit tricky. I would like to move fsp_init() later in the init sequence (e.g. to board_init_f()). See this TODO in the code:
/*
- TODO:
- According to FSP architecture spec, the fsp_init() will not return
- to its caller, instead it requires the bootloader to provide a
- so-called continuation function to pass into the FSP as a parameter
- of fsp_init, and fsp_init() will call that continuation function
- directly.
- The call to fsp_init() may need to be moved out of the car_init()
- to cpu_init_f() with the help of some inline assembly codes.
- Note there is another issue that fsp_init() will setup another stack
- using the fsp_init parameter stack_top after DRAM is initialized,
- which means any data on the previous stack (on the CAR) gets lost
- (ie: U-Boot global_data). FSP is supposed to support such scenario,
- however it does not work. This should be revisited in the future.
*/
The primary issues are:
- The need to recover the global_data
- The need to change to a new stack
Re 1, my reading of the HOB stuff is that it is supposed to provide you with a pointer to the CAR RAM (all ~128KB of it) so that you can go back and find your old stack (and in our case, global_data).
Bin mentioned that this doesn't work - his is the comment above after I asked him about it.
But if it could be made to work, then we could delay the init.
Re 2, U-Boot expects to change to a new stack when it wants to, which is at the boundary of board_init_f() and board_init_r(). The Intel FSP should not mandate a stack change over a C function call. IMO that is just bad design. Dealing with it is not very easy, but one option is to run with the new stack for the rest of the board_init_f() sequence and then change stack again at the end of the sequence. Ick.
To specifically address your problem, global_data is not available until board_init_f() is called, and the device tree comes into existence soon after. We could hack around it - e.g. with microcode we find it in the device tree and stick a pointer to it in a special place. But the real solution is to figure out how to move this fsp_init() stuff to later in the sequence. For non-FSP boards we don't have this problem - e.g. ivybridge does RAM init long after we have global_data and device tree. Note it is still running from flash at this point, but CAR is set up and that is where global_data resides.
I'm interested to hear what you figure out.
I just noticed that Intel has released FSP specification v1.1 [1] in April. After a rough read of the 1.1 spec, it looks to me that Intel changed the fsp_init() design by breaking it down into 3 sub-routines: FspMemoryInit(), TempRamExit() and FspSiliconInit(). I feel this might be more logical to adapt U-Boot, but again I am not sure if the stack migration stuff is still there. So far I don't see any new FSP releases using the 1.1 spec.
[1] https://www-ssl.intel.com/content/www/us/en/embedded/software/fsp/fsp-archit...
There's also a very good overview of how to use an FSP v1.1 firmware at [1]. It states that the problem in v1.0 for bootloaders was that when you call FspInit() that temporary ram was torn down unconditionally. Now, in v1.1, it says after calling FspMemoryInit() that control will be given back to the bootloader running in the temporary ram (CAR?). Then the bootloader is responsible for migrating to main memory and to call TempRamExit() so that temporary memory can be cleaned up.
This sounds like what u-boot would want and what Simon described above, for u-boot to be in charge of relocating from CAR to main memory, right? If so, likely things will be much easier once there's a v1.1 FSP for baytrail...
Indeed, care to ping them to find out when this might happen?
Thanks! -Andrew
Regards, Simon
On 05/28 10:30, Simon Glass wrote:
Hi Andrew,
On 27 May 2015 at 08:39, Andrew Bradford andrew@bradfordembedded.com wrote:
On 05/27 13:19, Bin Meng wrote:
Hi Simon,
On Wed, May 27, 2015 at 5:37 AM, Simon Glass sjg@chromium.org wrote:
Hi Andrew,
On 26 May 2015 at 13:52, Andrew Bradford andrew@bradfordembedded.com wrote:
Hi Simon and Bin (sorry for bringing this back from the dead),
But I have a question about fsp_configs.c down below:
On 01/27 22:13, Simon Glass wrote: ------------->8---------------
diff --git a/arch/x86/cpu/baytrail/fsp_configs.c b/arch/x86/cpu/baytrail/fsp_configs.c new file mode 100644 index 0000000..86b6926 --- /dev/null +++ b/arch/x86/cpu/baytrail/fsp_configs.c @@ -0,0 +1,156 @@ +/*
- Copyright (C) 2013, Intel Corporation
- Copyright (C) 2014, Bin Meng bmeng.cn@gmail.com
- SPDX-License-Identifier: Intel
- */
+#include <common.h> +#include <asm/arch/fsp/azalia.h> +#include <asm/fsp/fsp_support.h>
+/* ALC262 Verb Table - 10EC0262 */ +static const uint32_t verb_table_data13[] = {
/* Pin Complex (NID 0x11) */0x01171cf0,0x01171d11,0x01171e11,0x01171f41,/* Pin Complex (NID 0x12) */0x01271cf0,0x01271d11,0x01271e11,0x01271f41,/* Pin Complex (NID 0x14) */0x01471c10,0x01471d40,0x01471e01,0x01471f01,/* Pin Complex (NID 0x15) */0x01571cf0,0x01571d11,0x01571e11,0x01571f41,/* Pin Complex (NID 0x16) */0x01671cf0,0x01671d11,0x01671e11,0x01671f41,/* Pin Complex (NID 0x18) */0x01871c20,0x01871d98,0x01871ea1,0x01871f01,/* Pin Complex (NID 0x19) */0x01971c21,0x01971d98,0x01971ea1,0x01971f02,/* Pin Complex (NID 0x1A) */0x01a71c2f,0x01a71d30,0x01a71e81,0x01a71f01,/* Pin Complex */0x01b71c1f,0x01b71d40,0x01b71e21,0x01b71f02,/* Pin Complex */0x01c71cf0,0x01c71d11,0x01c71e11,0x01c71f41,/* Pin Complex */0x01d71c01,0x01d71dc6,0x01d71e14,0x01d71f40,/* Pin Complex */0x01e71cf0,0x01e71d11,0x01e71e11,0x01e71f41,/* Pin Complex */0x01f71cf0,0x01f71d11,0x01f71e11,0x01f71f41,+};
+/*
- This needs to be in ROM since if we put it in CAR, FSP init loses it when
- it drops CAR.
- TODO(sjg@chromium.org): Move to device tree when FSP allows it
- VerbTable: (RealTek ALC262)
- Revision ID = 0xFF, support all steps
- Codec Verb Table For AZALIA
- Codec Address: CAd value (0/1/2)
- Codec Vendor: 0x10EC0262
- */
+static const struct pch_azalia_verb_table azalia_verb_table[] = {
{{0x10ec0262,0x0000,0xff,0x01,0x000b,0x0002,},verb_table_data13}+};
+const struct pch_azalia_config azalia_config = {
.pme_enable = 1,.docking_supported = 1,.docking_attached = 0,.hdmi_codec_enable = 1,.azalia_v_ci_enable = 1,.rsvdbits = 0,.azalia_verb_table_num = 1,.azalia_verb_table = azalia_verb_table,.reset_wait_timer_us = 300+};
+void update_fsp_upd(struct upd_region *fsp_upd) +{
struct memory_down_data *mem;/** Configure everything here to avoid the poor hard-pressed user* needing to run Intel's binary configuration tool. It may also allow* us to support the 1GB single core variant easily.** TODO(sjg@chromium.org): Move to device tree*/fsp_upd->mrc_init_tseg_size = 8;fsp_upd->mrc_init_mmio_size = 0x800;fsp_upd->emmc_boot_mode = 0xff;fsp_upd->enable_sdio = 1;fsp_upd->enable_sdcard = 1;fsp_upd->enable_hsuart0 = 1;fsp_upd->azalia_config_ptr = (uint32_t)&azalia_config;fsp_upd->enable_i2_c0 = 0;fsp_upd->enable_i2_c2 = 0;fsp_upd->enable_i2_c3 = 0;fsp_upd->enable_i2_c4 = 0;fsp_upd->enable_xhci = 0;fsp_upd->igd_render_standby = 1;mem = &fsp_upd->memory_params;mem->enable_memory_down = 1;mem->dram_speed = 1;mem->dimm_width = 1;mem->dimm_density = 2;mem->dimm_tcl = 0xb;mem->dimm_trpt_rcd = 0xb;mem->dimm_twr = 0xc;mem->dimm_twtr = 6;mem->dimm_trrd = 6;mem->dimm_trtp = 6;mem->dimm_tfaw = 0x14;+}
I am trying to move this fsp upd to use device tree as I am trying to create a patch set to add the Intel Valley Island E38xx board (which uses a SODIMM rather than memory down). In doing so, I've found that global data doesn't seem to be available when update_fsp_upd() is called and generally it seems that gd->fdt_blob is used to get a reference to the flattened device tree.
I'm not super familiar with device tree, but I was attempting to use fdtdec_next_compatible(gd->fdt_blob, 0, COMPAT_INTEL_BAYTRAIL_FSP) in a similar way that Quark does in my patchset (I've properly created the COMPAT_INTEL_BAYTRAIL_FSP define and some device tree nodes in my dts file). When I call fdtdec_next_compatible() the board does something which I'm unable to debug (Valley Island does not have the early UART pins connected so I have no early UART capability) but things just seem to stop.
In manually tracing the calls which lead to update_fsp_upd(), it seems that we haven't yet set up global data, so it makes sense that I can't reference it. But the device tree should be available in NOR flash or in some other way which we can access in order to get the FSP UPD settings.
Is there a simple way to access the device tree while it's still in NOR flash so I can avoid using gd? Or can global data be setup prior to calling update_fsp_upd() (I believe we're still in CAR at this point)? Or am I misunderstanding something basic here?
Did you have a rough outline of how this could be moved to device tree?
This is a bit tricky. I would like to move fsp_init() later in the init sequence (e.g. to board_init_f()). See this TODO in the code:
/*
- TODO:
- According to FSP architecture spec, the fsp_init() will not return
- to its caller, instead it requires the bootloader to provide a
- so-called continuation function to pass into the FSP as a parameter
- of fsp_init, and fsp_init() will call that continuation function
- directly.
- The call to fsp_init() may need to be moved out of the car_init()
- to cpu_init_f() with the help of some inline assembly codes.
- Note there is another issue that fsp_init() will setup another stack
- using the fsp_init parameter stack_top after DRAM is initialized,
- which means any data on the previous stack (on the CAR) gets lost
- (ie: U-Boot global_data). FSP is supposed to support such scenario,
- however it does not work. This should be revisited in the future.
*/
The primary issues are:
- The need to recover the global_data
- The need to change to a new stack
Re 1, my reading of the HOB stuff is that it is supposed to provide you with a pointer to the CAR RAM (all ~128KB of it) so that you can go back and find your old stack (and in our case, global_data).
Bin mentioned that this doesn't work - his is the comment above after I asked him about it.
But if it could be made to work, then we could delay the init.
Re 2, U-Boot expects to change to a new stack when it wants to, which is at the boundary of board_init_f() and board_init_r(). The Intel FSP should not mandate a stack change over a C function call. IMO that is just bad design. Dealing with it is not very easy, but one option is to run with the new stack for the rest of the board_init_f() sequence and then change stack again at the end of the sequence. Ick.
To specifically address your problem, global_data is not available until board_init_f() is called, and the device tree comes into existence soon after. We could hack around it - e.g. with microcode we find it in the device tree and stick a pointer to it in a special place. But the real solution is to figure out how to move this fsp_init() stuff to later in the sequence. For non-FSP boards we don't have this problem - e.g. ivybridge does RAM init long after we have global_data and device tree. Note it is still running from flash at this point, but CAR is set up and that is where global_data resides.
I'm interested to hear what you figure out.
I just noticed that Intel has released FSP specification v1.1 [1] in April. After a rough read of the 1.1 spec, it looks to me that Intel changed the fsp_init() design by breaking it down into 3 sub-routines: FspMemoryInit(), TempRamExit() and FspSiliconInit(). I feel this might be more logical to adapt U-Boot, but again I am not sure if the stack migration stuff is still there. So far I don't see any new FSP releases using the 1.1 spec.
[1] https://www-ssl.intel.com/content/www/us/en/embedded/software/fsp/fsp-archit...
There's also a very good overview of how to use an FSP v1.1 firmware at [1]. It states that the problem in v1.0 for bootloaders was that when you call FspInit() that temporary ram was torn down unconditionally. Now, in v1.1, it says after calling FspMemoryInit() that control will be given back to the bootloader running in the temporary ram (CAR?). Then the bootloader is responsible for migrating to main memory and to call TempRamExit() so that temporary memory can be cleaned up.
This sounds like what u-boot would want and what Simon described above, for u-boot to be in charge of relocating from CAR to main memory, right? If so, likely things will be much easier once there's a v1.1 FSP for baytrail...
Indeed, care to ping them to find out when this might happen?
I'm not sure, but I think Intel may have the source on Github [1]. I'm starting to look through the code to see if it's actually useful for E3800 parts or not, but a quick scan through the git log does show changes to support FSP v1.1 and it appears to be actively developed...
[1]:https://github.com/tianocore/edk2-IntelFspPkg
Having a few other, more experienced, eyes on this to see if it's useful would probably be good.
I will see what else I can find out about an FSP v1.1 release for E3800 parts, in the mean time.
Thanks! -Andrew
Hi Andrew, Simon,
On Fri, May 29, 2015 at 2:09 AM, Andrew Bradford andrew@bradfordembedded.com wrote:
On 05/28 10:30, Simon Glass wrote:
Hi Andrew,
On 27 May 2015 at 08:39, Andrew Bradford andrew@bradfordembedded.com wrote:
On 05/27 13:19, Bin Meng wrote:
Hi Simon,
On Wed, May 27, 2015 at 5:37 AM, Simon Glass sjg@chromium.org wrote:
Hi Andrew,
On 26 May 2015 at 13:52, Andrew Bradford andrew@bradfordembedded.com wrote:
Hi Simon and Bin (sorry for bringing this back from the dead),
But I have a question about fsp_configs.c down below:
On 01/27 22:13, Simon Glass wrote: ------------->8---------------
[snip]
I am trying to move this fsp upd to use device tree as I am trying to create a patch set to add the Intel Valley Island E38xx board (which uses a SODIMM rather than memory down). In doing so, I've found that global data doesn't seem to be available when update_fsp_upd() is called and generally it seems that gd->fdt_blob is used to get a reference to the flattened device tree.
I'm not super familiar with device tree, but I was attempting to use fdtdec_next_compatible(gd->fdt_blob, 0, COMPAT_INTEL_BAYTRAIL_FSP) in a similar way that Quark does in my patchset (I've properly created the COMPAT_INTEL_BAYTRAIL_FSP define and some device tree nodes in my dts file). When I call fdtdec_next_compatible() the board does something which I'm unable to debug (Valley Island does not have the early UART pins connected so I have no early UART capability) but things just seem to stop.
In manually tracing the calls which lead to update_fsp_upd(), it seems that we haven't yet set up global data, so it makes sense that I can't reference it. But the device tree should be available in NOR flash or in some other way which we can access in order to get the FSP UPD settings.
Is there a simple way to access the device tree while it's still in NOR flash so I can avoid using gd? Or can global data be setup prior to calling update_fsp_upd() (I believe we're still in CAR at this point)? Or am I misunderstanding something basic here?
Did you have a rough outline of how this could be moved to device tree?
This is a bit tricky. I would like to move fsp_init() later in the init sequence (e.g. to board_init_f()). See this TODO in the code:
/*
- TODO:
- According to FSP architecture spec, the fsp_init() will not return
- to its caller, instead it requires the bootloader to provide a
- so-called continuation function to pass into the FSP as a parameter
- of fsp_init, and fsp_init() will call that continuation function
- directly.
- The call to fsp_init() may need to be moved out of the car_init()
- to cpu_init_f() with the help of some inline assembly codes.
- Note there is another issue that fsp_init() will setup another stack
- using the fsp_init parameter stack_top after DRAM is initialized,
- which means any data on the previous stack (on the CAR) gets lost
- (ie: U-Boot global_data). FSP is supposed to support such scenario,
- however it does not work. This should be revisited in the future.
*/
The primary issues are:
- The need to recover the global_data
- The need to change to a new stack
Re 1, my reading of the HOB stuff is that it is supposed to provide you with a pointer to the CAR RAM (all ~128KB of it) so that you can go back and find your old stack (and in our case, global_data).
Bin mentioned that this doesn't work - his is the comment above after I asked him about it.
But if it could be made to work, then we could delay the init.
Re 2, U-Boot expects to change to a new stack when it wants to, which is at the boundary of board_init_f() and board_init_r(). The Intel FSP should not mandate a stack change over a C function call. IMO that is just bad design. Dealing with it is not very easy, but one option is to run with the new stack for the rest of the board_init_f() sequence and then change stack again at the end of the sequence. Ick.
To specifically address your problem, global_data is not available until board_init_f() is called, and the device tree comes into existence soon after. We could hack around it - e.g. with microcode we find it in the device tree and stick a pointer to it in a special place. But the real solution is to figure out how to move this fsp_init() stuff to later in the sequence. For non-FSP boards we don't have this problem - e.g. ivybridge does RAM init long after we have global_data and device tree. Note it is still running from flash at this point, but CAR is set up and that is where global_data resides.
I'm interested to hear what you figure out.
I just noticed that Intel has released FSP specification v1.1 [1] in April. After a rough read of the 1.1 spec, it looks to me that Intel changed the fsp_init() design by breaking it down into 3 sub-routines: FspMemoryInit(), TempRamExit() and FspSiliconInit(). I feel this might be more logical to adapt U-Boot, but again I am not sure if the stack migration stuff is still there. So far I don't see any new FSP releases using the 1.1 spec.
[1] https://www-ssl.intel.com/content/www/us/en/embedded/software/fsp/fsp-archit...
There's also a very good overview of how to use an FSP v1.1 firmware at [1]. It states that the problem in v1.0 for bootloaders was that when you call FspInit() that temporary ram was torn down unconditionally. Now, in v1.1, it says after calling FspMemoryInit() that control will be given back to the bootloader running in the temporary ram (CAR?). Then the bootloader is responsible for migrating to main memory and to call TempRamExit() so that temporary memory can be cleaned up.
This sounds like what u-boot would want and what Simon described above, for u-boot to be in charge of relocating from CAR to main memory, right? If so, likely things will be much easier once there's a v1.1 FSP for baytrail...
Indeed, care to ping them to find out when this might happen?
I'm not sure, but I think Intel may have the source on Github [1]. I'm starting to look through the code to see if it's actually useful for E3800 parts or not, but a quick scan through the git log does show changes to support FSP v1.1 and it appears to be actively developed...
Looks like this is not the FSP source codes, but just the support codes to get FSP integrated into the EDKII TianCore. I doubt Intel will release any source codes of FSP.
Having a few other, more experienced, eyes on this to see if it's useful would probably be good.
I will see if I can restart this FSP initialization sequence work next week.
I will see what else I can find out about an FSP v1.1 release for E3800 parts, in the mean time.
Regards, Bin
Hi Simon, Hi Andrew,
On Fri, May 29, 2015 at 9:54 PM, Bin Meng bmeng.cn@gmail.com wrote:
Hi Andrew, Simon,
On Fri, May 29, 2015 at 2:09 AM, Andrew Bradford andrew@bradfordembedded.com wrote:
On 05/28 10:30, Simon Glass wrote:
Hi Andrew,
On 27 May 2015 at 08:39, Andrew Bradford andrew@bradfordembedded.com wrote:
On 05/27 13:19, Bin Meng wrote:
Hi Simon,
On Wed, May 27, 2015 at 5:37 AM, Simon Glass sjg@chromium.org wrote:
Hi Andrew,
On 26 May 2015 at 13:52, Andrew Bradford andrew@bradfordembedded.com wrote: > Hi Simon and Bin (sorry for bringing this back from the dead), > > But I have a question about fsp_configs.c down below: > > On 01/27 22:13, Simon Glass wrote: > ------------->8---------------
[snip]
> > I am trying to move this fsp upd to use device tree as I am trying to > create a patch set to add the Intel Valley Island E38xx board (which > uses a SODIMM rather than memory down). In doing so, I've found that > global data doesn't seem to be available when update_fsp_upd() is called > and generally it seems that gd->fdt_blob is used to get a reference to > the flattened device tree. > > I'm not super familiar with device tree, but I was attempting to use > fdtdec_next_compatible(gd->fdt_blob, 0, COMPAT_INTEL_BAYTRAIL_FSP) in a > similar way that Quark does in my patchset (I've properly created the > COMPAT_INTEL_BAYTRAIL_FSP define and some device tree nodes in my dts > file). When I call fdtdec_next_compatible() the board does something > which I'm unable to debug (Valley Island does not have the early UART > pins connected so I have no early UART capability) but things just seem > to stop. > > In manually tracing the calls which lead to update_fsp_upd(), it seems > that we haven't yet set up global data, so it makes sense that I can't > reference it. But the device tree should be available in NOR flash or > in some other way which we can access in order to get the FSP UPD > settings. > > Is there a simple way to access the device tree while it's still in NOR > flash so I can avoid using gd? Or can global data be setup prior to > calling update_fsp_upd() (I believe we're still in CAR at this point)? > Or am I misunderstanding something basic here? > > Did you have a rough outline of how this could be moved to device tree?
This is a bit tricky. I would like to move fsp_init() later in the init sequence (e.g. to board_init_f()). See this TODO in the code:
/*
- TODO:
- According to FSP architecture spec, the fsp_init() will not return
- to its caller, instead it requires the bootloader to provide a
- so-called continuation function to pass into the FSP as a parameter
- of fsp_init, and fsp_init() will call that continuation function
- directly.
- The call to fsp_init() may need to be moved out of the car_init()
- to cpu_init_f() with the help of some inline assembly codes.
- Note there is another issue that fsp_init() will setup another stack
- using the fsp_init parameter stack_top after DRAM is initialized,
- which means any data on the previous stack (on the CAR) gets lost
- (ie: U-Boot global_data). FSP is supposed to support such scenario,
- however it does not work. This should be revisited in the future.
*/
The primary issues are:
- The need to recover the global_data
- The need to change to a new stack
Re 1, my reading of the HOB stuff is that it is supposed to provide you with a pointer to the CAR RAM (all ~128KB of it) so that you can go back and find your old stack (and in our case, global_data).
Bin mentioned that this doesn't work - his is the comment above after I asked him about it.
But if it could be made to work, then we could delay the init.
Re 2, U-Boot expects to change to a new stack when it wants to, which is at the boundary of board_init_f() and board_init_r(). The Intel FSP should not mandate a stack change over a C function call. IMO that is just bad design. Dealing with it is not very easy, but one option is to run with the new stack for the rest of the board_init_f() sequence and then change stack again at the end of the sequence. Ick.
To specifically address your problem, global_data is not available until board_init_f() is called, and the device tree comes into existence soon after. We could hack around it - e.g. with microcode we find it in the device tree and stick a pointer to it in a special place. But the real solution is to figure out how to move this fsp_init() stuff to later in the sequence. For non-FSP boards we don't have this problem - e.g. ivybridge does RAM init long after we have global_data and device tree. Note it is still running from flash at this point, but CAR is set up and that is where global_data resides.
I'm interested to hear what you figure out.
I just noticed that Intel has released FSP specification v1.1 [1] in April. After a rough read of the 1.1 spec, it looks to me that Intel changed the fsp_init() design by breaking it down into 3 sub-routines: FspMemoryInit(), TempRamExit() and FspSiliconInit(). I feel this might be more logical to adapt U-Boot, but again I am not sure if the stack migration stuff is still there. So far I don't see any new FSP releases using the 1.1 spec.
[1] https://www-ssl.intel.com/content/www/us/en/embedded/software/fsp/fsp-archit...
There's also a very good overview of how to use an FSP v1.1 firmware at [1]. It states that the problem in v1.0 for bootloaders was that when you call FspInit() that temporary ram was torn down unconditionally. Now, in v1.1, it says after calling FspMemoryInit() that control will be given back to the bootloader running in the temporary ram (CAR?). Then the bootloader is responsible for migrating to main memory and to call TempRamExit() so that temporary memory can be cleaned up.
This sounds like what u-boot would want and what Simon described above, for u-boot to be in charge of relocating from CAR to main memory, right? If so, likely things will be much easier once there's a v1.1 FSP for baytrail...
Indeed, care to ping them to find out when this might happen?
I'm not sure, but I think Intel may have the source on Github [1]. I'm starting to look through the code to see if it's actually useful for E3800 parts or not, but a quick scan through the git log does show changes to support FSP v1.1 and it appears to be actively developed...
Looks like this is not the FSP source codes, but just the support codes to get FSP integrated into the EDKII TianCore. I doubt Intel will release any source codes of FSP.
Having a few other, more experienced, eyes on this to see if it's useful would probably be good.
I will see if I can restart this FSP initialization sequence work next week.
I've reworked the FSP initialization sequence so that now it is called by board_init_f(). I tested it on Crown Bay. Would you please try the following two patches and see if it works on the MinnowMax board?
http://patchwork.ozlabs.org/patch/478943/ http://patchwork.ozlabs.org/patch/478944/
[snip]
Regards, Bin
Hi Simon,
On 05/28 10:30, Simon Glass wrote:
Hi Andrew,
On 27 May 2015 at 08:39, Andrew Bradford andrew@bradfordembedded.com wrote:
On 05/27 13:19, Bin Meng wrote:
Hi Simon,
------------->8--------------
I just noticed that Intel has released FSP specification v1.1 [1] in April. After a rough read of the 1.1 spec, it looks to me that Intel changed the fsp_init() design by breaking it down into 3 sub-routines: FspMemoryInit(), TempRamExit() and FspSiliconInit(). I feel this might be more logical to adapt U-Boot, but again I am not sure if the stack migration stuff is still there. So far I don't see any new FSP releases using the 1.1 spec.
[1] https://www-ssl.intel.com/content/www/us/en/embedded/software/fsp/fsp-archit...
There's also a very good overview of how to use an FSP v1.1 firmware at [1]. It states that the problem in v1.0 for bootloaders was that when you call FspInit() that temporary ram was torn down unconditionally. Now, in v1.1, it says after calling FspMemoryInit() that control will be given back to the bootloader running in the temporary ram (CAR?). Then the bootloader is responsible for migrating to main memory and to call TempRamExit() so that temporary memory can be cleaned up.
This sounds like what u-boot would want and what Simon described above, for u-boot to be in charge of relocating from CAR to main memory, right? If so, likely things will be much easier once there's a v1.1 FSP for baytrail...
Indeed, care to ping them to find out when this might happen?
It seems like there are no current plans to implement an FSP v1.1 compliant firmware release for Bay Trail [1], which is unfortunate.
[1]:https://embedded.communities.intel.com/thread/8218
I will continue to pester my contacts at Intel.
Thanks, Andrew
Hi Bin,
On 26 May 2015 at 23:19, Bin Meng bmeng.cn@gmail.com wrote:
Hi Simon,
On Wed, May 27, 2015 at 5:37 AM, Simon Glass sjg@chromium.org wrote:
Hi Andrew,
On 26 May 2015 at 13:52, Andrew Bradford andrew@bradfordembedded.com wrote:
Hi Simon and Bin (sorry for bringing this back from the dead),
But I have a question about fsp_configs.c down below:
On 01/27 22:13, Simon Glass wrote: ------------->8---------------
[snip]
+const struct pch_azalia_config azalia_config = {
.pme_enable = 1,.docking_supported = 1,.docking_attached = 0,.hdmi_codec_enable = 1,.azalia_v_ci_enable = 1,.rsvdbits = 0,.azalia_verb_table_num = 1,.azalia_verb_table = azalia_verb_table,.reset_wait_timer_us = 300+};
+void update_fsp_upd(struct upd_region *fsp_upd) +{
struct memory_down_data *mem;/** Configure everything here to avoid the poor hard-pressed user* needing to run Intel's binary configuration tool. It may also allow* us to support the 1GB single core variant easily.** TODO(sjg@chromium.org): Move to device tree*/fsp_upd->mrc_init_tseg_size = 8;fsp_upd->mrc_init_mmio_size = 0x800;fsp_upd->emmc_boot_mode = 0xff;fsp_upd->enable_sdio = 1;fsp_upd->enable_sdcard = 1;fsp_upd->enable_hsuart0 = 1;fsp_upd->azalia_config_ptr = (uint32_t)&azalia_config;fsp_upd->enable_i2_c0 = 0;fsp_upd->enable_i2_c2 = 0;fsp_upd->enable_i2_c3 = 0;fsp_upd->enable_i2_c4 = 0;fsp_upd->enable_xhci = 0;fsp_upd->igd_render_standby = 1;mem = &fsp_upd->memory_params;mem->enable_memory_down = 1;mem->dram_speed = 1;mem->dimm_width = 1;mem->dimm_density = 2;mem->dimm_tcl = 0xb;mem->dimm_trpt_rcd = 0xb;mem->dimm_twr = 0xc;mem->dimm_twtr = 6;mem->dimm_trrd = 6;mem->dimm_trtp = 6;mem->dimm_tfaw = 0x14;+}
I am trying to move this fsp upd to use device tree as I am trying to create a patch set to add the Intel Valley Island E38xx board (which uses a SODIMM rather than memory down). In doing so, I've found that global data doesn't seem to be available when update_fsp_upd() is called and generally it seems that gd->fdt_blob is used to get a reference to the flattened device tree.
I'm not super familiar with device tree, but I was attempting to use fdtdec_next_compatible(gd->fdt_blob, 0, COMPAT_INTEL_BAYTRAIL_FSP) in a similar way that Quark does in my patchset (I've properly created the COMPAT_INTEL_BAYTRAIL_FSP define and some device tree nodes in my dts file). When I call fdtdec_next_compatible() the board does something which I'm unable to debug (Valley Island does not have the early UART pins connected so I have no early UART capability) but things just seem to stop.
In manually tracing the calls which lead to update_fsp_upd(), it seems that we haven't yet set up global data, so it makes sense that I can't reference it. But the device tree should be available in NOR flash or in some other way which we can access in order to get the FSP UPD settings.
Is there a simple way to access the device tree while it's still in NOR flash so I can avoid using gd? Or can global data be setup prior to calling update_fsp_upd() (I believe we're still in CAR at this point)? Or am I misunderstanding something basic here?
Did you have a rough outline of how this could be moved to device tree?
This is a bit tricky. I would like to move fsp_init() later in the init sequence (e.g. to board_init_f()). See this TODO in the code:
/*
- TODO:
- According to FSP architecture spec, the fsp_init() will not return
- to its caller, instead it requires the bootloader to provide a
- so-called continuation function to pass into the FSP as a parameter
- of fsp_init, and fsp_init() will call that continuation function
- directly.
- The call to fsp_init() may need to be moved out of the car_init()
- to cpu_init_f() with the help of some inline assembly codes.
- Note there is another issue that fsp_init() will setup another stack
- using the fsp_init parameter stack_top after DRAM is initialized,
- which means any data on the previous stack (on the CAR) gets lost
- (ie: U-Boot global_data). FSP is supposed to support such scenario,
- however it does not work. This should be revisited in the future.
*/
The primary issues are:
- The need to recover the global_data
- The need to change to a new stack
Re 1, my reading of the HOB stuff is that it is supposed to provide you with a pointer to the CAR RAM (all ~128KB of it) so that you can go back and find your old stack (and in our case, global_data).
Bin mentioned that this doesn't work - his is the comment above after I asked him about it.
But if it could be made to work, then we could delay the init.
Re 2, U-Boot expects to change to a new stack when it wants to, which is at the boundary of board_init_f() and board_init_r(). The Intel FSP should not mandate a stack change over a C function call. IMO that is just bad design. Dealing with it is not very easy, but one option is to run with the new stack for the rest of the board_init_f() sequence and then change stack again at the end of the sequence. Ick.
To specifically address your problem, global_data is not available until board_init_f() is called, and the device tree comes into existence soon after. We could hack around it - e.g. with microcode we find it in the device tree and stick a pointer to it in a special place. But the real solution is to figure out how to move this fsp_init() stuff to later in the sequence. For non-FSP boards we don't have this problem - e.g. ivybridge does RAM init long after we have global_data and device tree. Note it is still running from flash at this point, but CAR is set up and that is where global_data resides.
I'm interested to hear what you figure out.
I just noticed that Intel has released FSP specification v1.1 [1] in April. After a rough read of the 1.1 spec, it looks to me that Intel changed the fsp_init() design by breaking it down into 3 sub-routines: FspMemoryInit(), TempRamExit() and FspSiliconInit(). I feel this might be more logical to adapt U-Boot, but again I am not sure if the stack migration stuff is still there. So far I don't see any new FSP releases using the 1.1 spec.
Great! I sent an email with this feedback to Intel so perhaps they took note. Although I suspect they would have got the same feedback from any other firmware project. Once we see an FSP with this we should be able to straighten this out. Hopefully they will update Minnowmax. Even better if they decide to just release the source code.
[1] https://www-ssl.intel.com/content/www/us/en/embedded/software/fsp/fsp-archit...
Regards, Bin
Regards, Simon
Hi Simon & Bin,
On 05/26 15:37, Simon Glass wrote:
Hi Andrew,
On 26 May 2015 at 13:52, Andrew Bradford andrew@bradfordembedded.com wrote:
Hi Simon and Bin (sorry for bringing this back from the dead),
But I have a question about fsp_configs.c down below:
On 01/27 22:13, Simon Glass wrote: ------------->8---------------
+void update_fsp_upd(struct upd_region *fsp_upd) +{
struct memory_down_data *mem;/** Configure everything here to avoid the poor hard-pressed user* needing to run Intel's binary configuration tool. It may also allow* us to support the 1GB single core variant easily.** TODO(sjg@chromium.org): Move to device tree*/fsp_upd->mrc_init_tseg_size = 8;fsp_upd->mrc_init_mmio_size = 0x800;fsp_upd->emmc_boot_mode = 0xff;fsp_upd->enable_sdio = 1;fsp_upd->enable_sdcard = 1;fsp_upd->enable_hsuart0 = 1;fsp_upd->azalia_config_ptr = (uint32_t)&azalia_config;fsp_upd->enable_i2_c0 = 0;fsp_upd->enable_i2_c2 = 0;fsp_upd->enable_i2_c3 = 0;fsp_upd->enable_i2_c4 = 0;fsp_upd->enable_xhci = 0;fsp_upd->igd_render_standby = 1;mem = &fsp_upd->memory_params;mem->enable_memory_down = 1;mem->dram_speed = 1;mem->dimm_width = 1;mem->dimm_density = 2;mem->dimm_tcl = 0xb;mem->dimm_trpt_rcd = 0xb;mem->dimm_twr = 0xc;mem->dimm_twtr = 6;mem->dimm_trrd = 6;mem->dimm_trtp = 6;mem->dimm_tfaw = 0x14;+}
I am trying to move this fsp upd to use device tree as I am trying to create a patch set to add the Intel Valley Island E38xx board (which uses a SODIMM rather than memory down). In doing so, I've found that global data doesn't seem to be available when update_fsp_upd() is called and generally it seems that gd->fdt_blob is used to get a reference to the flattened device tree.
I'm not super familiar with device tree, but I was attempting to use fdtdec_next_compatible(gd->fdt_blob, 0, COMPAT_INTEL_BAYTRAIL_FSP) in a similar way that Quark does in my patchset (I've properly created the COMPAT_INTEL_BAYTRAIL_FSP define and some device tree nodes in my dts file). When I call fdtdec_next_compatible() the board does something which I'm unable to debug (Valley Island does not have the early UART pins connected so I have no early UART capability) but things just seem to stop.
In manually tracing the calls which lead to update_fsp_upd(), it seems that we haven't yet set up global data, so it makes sense that I can't reference it. But the device tree should be available in NOR flash or in some other way which we can access in order to get the FSP UPD settings.
Is there a simple way to access the device tree while it's still in NOR flash so I can avoid using gd? Or can global data be setup prior to calling update_fsp_upd() (I believe we're still in CAR at this point)? Or am I misunderstanding something basic here?
Did you have a rough outline of how this could be moved to device tree?
This is a bit tricky. I would like to move fsp_init() later in the init sequence (e.g. to board_init_f()). See this TODO in the code:
/*
- TODO:
- According to FSP architecture spec, the fsp_init() will not return
- to its caller, instead it requires the bootloader to provide a
- so-called continuation function to pass into the FSP as a parameter
- of fsp_init, and fsp_init() will call that continuation function
- directly.
- The call to fsp_init() may need to be moved out of the car_init()
- to cpu_init_f() with the help of some inline assembly codes.
- Note there is another issue that fsp_init() will setup another stack
- using the fsp_init parameter stack_top after DRAM is initialized,
- which means any data on the previous stack (on the CAR) gets lost
- (ie: U-Boot global_data). FSP is supposed to support such scenario,
- however it does not work. This should be revisited in the future.
*/
The primary issues are:
- The need to recover the global_data
- The need to change to a new stack
Re 1, my reading of the HOB stuff is that it is supposed to provide you with a pointer to the CAR RAM (all ~128KB of it) so that you can go back and find your old stack (and in our case, global_data).
Bin mentioned that this doesn't work - his is the comment above after I asked him about it.
OK, if it doesn't work then that's frustrating.
I do see that HOB 15 on my Valley Island board has the right GUID to be the FSP_BOOTLOADER_TEMPORARY_MEMORY_HOB and its size is 16408. So that has me hopeful, but likely I'll run into similar things that you two have seen before.
Any pointers on why it was determined that the CAR RAM pointer doesn't work correctly so I can avoid spending too much time investigating things which have already been done?
But if it could be made to work, then we could delay the init.
Re 2, U-Boot expects to change to a new stack when it wants to, which is at the boundary of board_init_f() and board_init_r(). The Intel FSP should not mandate a stack change over a C function call. IMO that is just bad design. Dealing with it is not very easy, but one option is to run with the new stack for the rest of the board_init_f() sequence and then change stack again at the end of the sequence. Ick.
To specifically address your problem, global_data is not available until board_init_f() is called, and the device tree comes into existence soon after. We could hack around it - e.g. with microcode we find it in the device tree and stick a pointer to it in a special place. But the real solution is to figure out how to move this fsp_init() stuff to later in the sequence. For non-FSP boards we don't have this problem - e.g. ivybridge does RAM init long after we have global_data and device tree. Note it is still running from flash at this point, but CAR is set up and that is where global_data resides.
Assuming that we can recover the CAR RAM data, would it make sense to setup global data while in CAR so we can get access to the device tree and then call fsp_init(), and once we're running from main memory just set our global data pointer to the insides of the CAR RAM?
Likely I'm missing a few steps, here. But this feels a lot like how SPL works, except that u-boot is not in charge of how the relocation happens, we're just along for the ride.
Thanks! -Andrew
Hi Andrew,
On 27 May 2015 at 08:22, Andrew Bradford andrew@bradfordembedded.com wrote:
Hi Simon & Bin,
On 05/26 15:37, Simon Glass wrote:
Hi Andrew,
On 26 May 2015 at 13:52, Andrew Bradford andrew@bradfordembedded.com wrote:
Hi Simon and Bin (sorry for bringing this back from the dead),
But I have a question about fsp_configs.c down below:
On 01/27 22:13, Simon Glass wrote: ------------->8---------------
+void update_fsp_upd(struct upd_region *fsp_upd) +{
struct memory_down_data *mem;/** Configure everything here to avoid the poor hard-pressed user* needing to run Intel's binary configuration tool. It may also allow* us to support the 1GB single core variant easily.** TODO(sjg@chromium.org): Move to device tree*/fsp_upd->mrc_init_tseg_size = 8;fsp_upd->mrc_init_mmio_size = 0x800;fsp_upd->emmc_boot_mode = 0xff;fsp_upd->enable_sdio = 1;fsp_upd->enable_sdcard = 1;fsp_upd->enable_hsuart0 = 1;fsp_upd->azalia_config_ptr = (uint32_t)&azalia_config;fsp_upd->enable_i2_c0 = 0;fsp_upd->enable_i2_c2 = 0;fsp_upd->enable_i2_c3 = 0;fsp_upd->enable_i2_c4 = 0;fsp_upd->enable_xhci = 0;fsp_upd->igd_render_standby = 1;mem = &fsp_upd->memory_params;mem->enable_memory_down = 1;mem->dram_speed = 1;mem->dimm_width = 1;mem->dimm_density = 2;mem->dimm_tcl = 0xb;mem->dimm_trpt_rcd = 0xb;mem->dimm_twr = 0xc;mem->dimm_twtr = 6;mem->dimm_trrd = 6;mem->dimm_trtp = 6;mem->dimm_tfaw = 0x14;+}
I am trying to move this fsp upd to use device tree as I am trying to create a patch set to add the Intel Valley Island E38xx board (which uses a SODIMM rather than memory down). In doing so, I've found that global data doesn't seem to be available when update_fsp_upd() is called and generally it seems that gd->fdt_blob is used to get a reference to the flattened device tree.
I'm not super familiar with device tree, but I was attempting to use fdtdec_next_compatible(gd->fdt_blob, 0, COMPAT_INTEL_BAYTRAIL_FSP) in a similar way that Quark does in my patchset (I've properly created the COMPAT_INTEL_BAYTRAIL_FSP define and some device tree nodes in my dts file). When I call fdtdec_next_compatible() the board does something which I'm unable to debug (Valley Island does not have the early UART pins connected so I have no early UART capability) but things just seem to stop.
In manually tracing the calls which lead to update_fsp_upd(), it seems that we haven't yet set up global data, so it makes sense that I can't reference it. But the device tree should be available in NOR flash or in some other way which we can access in order to get the FSP UPD settings.
Is there a simple way to access the device tree while it's still in NOR flash so I can avoid using gd? Or can global data be setup prior to calling update_fsp_upd() (I believe we're still in CAR at this point)? Or am I misunderstanding something basic here?
Did you have a rough outline of how this could be moved to device tree?
This is a bit tricky. I would like to move fsp_init() later in the init sequence (e.g. to board_init_f()). See this TODO in the code:
/*
- TODO:
- According to FSP architecture spec, the fsp_init() will not return
- to its caller, instead it requires the bootloader to provide a
- so-called continuation function to pass into the FSP as a parameter
- of fsp_init, and fsp_init() will call that continuation function
- directly.
- The call to fsp_init() may need to be moved out of the car_init()
- to cpu_init_f() with the help of some inline assembly codes.
- Note there is another issue that fsp_init() will setup another stack
- using the fsp_init parameter stack_top after DRAM is initialized,
- which means any data on the previous stack (on the CAR) gets lost
- (ie: U-Boot global_data). FSP is supposed to support such scenario,
- however it does not work. This should be revisited in the future.
*/
The primary issues are:
- The need to recover the global_data
- The need to change to a new stack
Re 1, my reading of the HOB stuff is that it is supposed to provide you with a pointer to the CAR RAM (all ~128KB of it) so that you can go back and find your old stack (and in our case, global_data).
Bin mentioned that this doesn't work - his is the comment above after I asked him about it.
OK, if it doesn't work then that's frustrating.
I do see that HOB 15 on my Valley Island board has the right GUID to be the FSP_BOOTLOADER_TEMPORARY_MEMORY_HOB and its size is 16408. So that has me hopeful, but likely I'll run into similar things that you two have seen before.
Well if you can get access to the old global_data here then you can memcpy it to a new place in DRAM. That helps. But I forgot about issue 3:
3. Driver model will have created a few devices in temporary RAM and now they are gone.
The easiest solution is to run the board_init_f() sequence again from the start, this time skipping the dram init. It's horrible but pretty easy to implement. So you end up running dram_init() twice. The first time it runs the FSP call and then calls board_init_f() (or returns a special value such that the sequence restarts). The second time it does nothing.
Better might be to redo just the early malloc and driver model init: initf_malloc() and initf_dm(). That might work.
Any pointers on why it was determined that the CAR RAM pointer doesn't work correctly so I can avoid spending too much time investigating things which have already been done?
But if it could be made to work, then we could delay the init.
Re 2, U-Boot expects to change to a new stack when it wants to, which is at the boundary of board_init_f() and board_init_r(). The Intel FSP should not mandate a stack change over a C function call. IMO that is just bad design. Dealing with it is not very easy, but one option is to run with the new stack for the rest of the board_init_f() sequence and then change stack again at the end of the sequence. Ick.
To specifically address your problem, global_data is not available until board_init_f() is called, and the device tree comes into existence soon after. We could hack around it - e.g. with microcode we find it in the device tree and stick a pointer to it in a special place. But the real solution is to figure out how to move this fsp_init() stuff to later in the sequence. For non-FSP boards we don't have this problem - e.g. ivybridge does RAM init long after we have global_data and device tree. Note it is still running from flash at this point, but CAR is set up and that is where global_data resides.
Assuming that we can recover the CAR RAM data, would it make sense to setup global data while in CAR so we can get access to the device tree and then call fsp_init(), and once we're running from main memory just set our global data pointer to the insides of the CAR RAM?
CAR becomes unavailable when U-Boot relocates, since we want to use the cache for actual caching rather than for RAM. Currently this happens in init_cache_f_r() for non-FSP platforms, and it would be great if Intel could fix it so that this happens for FSP platforms too (as the link to the new FSP spec suggests).
Likely I'm missing a few steps, here. But this feels a lot like how SPL works, except that u-boot is not in charge of how the relocation happens, we're just along for the ride.
Exactly.
Note that the device tree is actually available very early - see the fdtdec_setup() call which is one of the first things in the init sequence. The problem is just how to move the FSP init into that sequence, so that global_data is available.
Regards, Simon
participants (3)
-
Andrew Bradford -
Bin Meng -
Simon Glass