[U-Boot] [PATCH] Add bank configuration to FSL spd_sdram.c
The routine assumed 4 bank SDRAMs, enhance to configure for 4 or 8 bank SDRAMs.
Signed-off-by: Gerald Van Baren vanbaren@cideas.com ---
I haven't made much headway on adapting the cpu/mpc8xxxx/ddr routines to the 83xx (8360). It has some 85xx (86xx) assumptions in that needs to be pulled out.
Meanwhile, the cpu/mpc83xx/spd_sdram.c routine /almost/ worked for me. It turns out my DIMM stick has 8 banks which was being ignored (hard-coded for 4 banks). The enhancement below fixed that for me.
It would be Really Good to get this verified and in the pending release.
Best regards, gvb
cpu/mpc83xx/spd_sdram.c | 8 +++++--- 1 files changed, 5 insertions(+), 3 deletions(-)
diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c index df116aa..df1ccae 100644 --- a/cpu/mpc83xx/spd_sdram.c +++ b/cpu/mpc83xx/spd_sdram.c @@ -220,7 +220,8 @@ long int spd_sdram() ddr->cs_config[0] = ( 1 << 31 | (odt_rd_cfg << 20) | (odt_wr_cfg << 16) - | (spd.nrow_addr - 12) << 8 + | ((spd.nbanks == 8 ? 1 : 0) << 14) + | ((spd.nrow_addr - 12) << 8) | (spd.ncol_addr - 8) ); debug("\n"); debug("cs0_bnds = 0x%08x\n",ddr->csbnds[0].csbnds); @@ -232,8 +233,9 @@ long int spd_sdram() ddr->cs_config[1] = ( 1<<31 | (odt_rd_cfg << 20) | (odt_wr_cfg << 16) - | (spd.nrow_addr-12) << 8 - | (spd.ncol_addr-8) ); + | ((spd.nbanks == 8 ? 1 : 0) << 14) + | ((spd.nrow_addr - 12) << 8) + | (spd.ncol_addr - 8) ); debug("cs1_bnds = 0x%08x\n",ddr->csbnds[1].csbnds); debug("cs1_config = 0x%08x\n",ddr->cs_config[1]); }
The routine assumed 4 bank SDRAMs, enhance to configure for 4 or 8 bank SDRAMs.
Signed-off-by: Gerald Van Baren vanbaren@cideas.com
I haven't made much headway on adapting the cpu/mpc8xxxx/ddr routines to the 83xx (8360). It has some 85xx (86xx) assumptions in that needs to be pulled out.
Meanwhile, the cpu/mpc83xx/spd_sdram.c routine /almost/ worked for me. It turns out my DIMM stick has 8 banks which was being ignored (hard-coded for 4 banks). The enhancement below fixed that for me.
It would be Really Good to get this verified and in the pending release.
Could you also make the same change to #CS2# and #CS3?
Thanks, Dave
Liu Dave-R63238 wrote:
The routine assumed 4 bank SDRAMs, enhance to configure for 4 or 8 bank SDRAMs.
Signed-off-by: Gerald Van Baren vanbaren@cideas.com
I haven't made much headway on adapting the cpu/mpc8xxxx/ddr routines to the 83xx (8360). It has some 85xx (86xx) assumptions in that needs to be pulled out.
Meanwhile, the cpu/mpc83xx/spd_sdram.c routine /almost/ worked for me. It turns out my DIMM stick has 8 banks which was being ignored (hard-coded for 4 banks). The enhancement below fixed that for me.
It would be Really Good to get this verified and in the pending release.
Could you also make the same change to #CS2# and #CS3?
Thanks, Dave
AAARGH, will do.
Sorry, gvb
The routine assumed 4 bank SDRAMs, enhance to configure for 4 or 8 bank SDRAMs.
Signed-off-by: Gerald Van Baren vanbaren@cideas.com ---
V2: Do both sets of chip selects. D'oh!
The cpu/mpc83xx/spd_sdram.c routine /almost/ worked for me. It turns out my DIMM stick has 8 banks which was being ignored (hard-coded for 4 banks). The enhancement below fixed that for me.
It would be Really Good to get this verified and in the pending release.
Best regards, gvb
cpu/mpc83xx/spd_sdram.c | 16 ++++++++++------ 1 files changed, 10 insertions(+), 6 deletions(-)
diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c index ecbc70c..0187ffb 100644 --- a/cpu/mpc83xx/spd_sdram.c +++ b/cpu/mpc83xx/spd_sdram.c @@ -219,7 +219,8 @@ long int spd_sdram() ddr->cs_config[0] = ( 1 << 31 | (odt_rd_cfg << 20) | (odt_wr_cfg << 16) - | (spd.nrow_addr - 12) << 8 + | ((spd.nbanks == 8 ? 1 : 0) << 14) + | ((spd.nrow_addr - 12) << 8) | (spd.ncol_addr - 8) ); debug("\n"); debug("cs0_bnds = 0x%08x\n",ddr->csbnds[0].csbnds); @@ -231,8 +232,9 @@ long int spd_sdram() ddr->cs_config[1] = ( 1<<31 | (odt_rd_cfg << 20) | (odt_wr_cfg << 16) - | (spd.nrow_addr-12) << 8 - | (spd.ncol_addr-8) ); + | ((spd.nbanks == 8 ? 1 : 0) << 14) + | ((spd.nrow_addr - 12) << 8) + | (spd.ncol_addr - 8) ); debug("cs1_bnds = 0x%08x\n",ddr->csbnds[1].csbnds); debug("cs1_config = 0x%08x\n",ddr->cs_config[1]); } @@ -242,7 +244,8 @@ long int spd_sdram() ddr->cs_config[2] = ( 1 << 31 | (odt_rd_cfg << 20) | (odt_wr_cfg << 16) - | (spd.nrow_addr - 12) << 8 + | ((spd.nbanks == 8 ? 1 : 0) << 14) + | ((spd.nrow_addr - 12) << 8) | (spd.ncol_addr - 8) ); debug("\n"); debug("cs2_bnds = 0x%08x\n",ddr->csbnds[2].csbnds); @@ -254,8 +257,9 @@ long int spd_sdram() ddr->cs_config[3] = ( 1<<31 | (odt_rd_cfg << 20) | (odt_wr_cfg << 16) - | (spd.nrow_addr-12) << 8 - | (spd.ncol_addr-8) ); + | ((spd.nbanks == 8 ? 1 : 0) << 14) + | ((spd.nrow_addr - 12) << 8) + | (spd.ncol_addr - 8) ); debug("cs3_bnds = 0x%08x\n",ddr->csbnds[3].csbnds); debug("cs3_config = 0x%08x\n",ddr->cs_config[3]); }
From: Jerry Van Baren [mailto:gvb.uboot@gmail.com] Sent: Friday, March 13, 2009 11:40 PM To: u-boot@lists.denx.de; Phillips Kim-R1AAHA; Liu Dave-R63238 Subject: [PATCH v2] Add bank configuration to FSL spd_sdram.c
The routine assumed 4 bank SDRAMs, enhance to configure for 4 or 8 bank SDRAMs.
Signed-off-by: Gerald Van Baren vanbaren@cideas.com
Acked-by: Dave Liu daveliu@freescale.com
On Fri, 13 Mar 2009 18:59:20 -0600 "Liu Dave-R63238" DaveLiu@freescale.com wrote:
From: Jerry Van Baren [mailto:gvb.uboot@gmail.com] Sent: Friday, March 13, 2009 11:40 PM To: u-boot@lists.denx.de; Phillips Kim-R1AAHA; Liu Dave-R63238 Subject: [PATCH v2] Add bank configuration to FSL spd_sdram.c
The routine assumed 4 bank SDRAMs, enhance to configure for 4 or 8 bank SDRAMs.
Signed-off-by: Gerald Van Baren vanbaren@cideas.com
Acked-by: Dave Liu daveliu@freescale.com
applied.
Thanks both,
Kim
participants (4)
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Jerry Van Baren -
Jerry Van Baren -
Kim Phillips -
Liu Dave-R63238