For all the devices used and set ACTIVE in U-Boot, U-Boot needs to power off all of them without the check of resource owner.

When we create software partition before booting Linux, the resource own checkw will return false, and cause the power domain not powered off. If without the check of resource owner, the power domain in the other software partition could be powered off with parent partition could access child partition resources.

Signed-off-by: Peng Fan peng.fan@nxp.com --- drivers/power/domain/imx8-power-domain-legacy.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/power/domain/imx8-power-domain-legacy.c b/drivers/power/domain/imx8-power-domain-legacy.c index e6e619358c..b68be40766 100644 --- a/drivers/power/domain/imx8-power-domain-legacy.c +++ b/drivers/power/domain/imx8-power-domain-legacy.c @@ -137,13 +137,13 @@ static int imx8_power_domain_off_node(struct power_domain *power_domain) }

if (pdata->resource_id != SC_R_LAST) { - if (!sc_rm_is_resource_owned(-1, pdata->resource_id)) { - printf("%s not owned by curr partition\n", dev->name); - return 0; - } ret = sc_pm_set_resource_power_mode(-1, pdata->resource_id, SC_PM_PW_MODE_OFF); if (ret) { + if (!sc_rm_is_resource_owned(-1, pdata->resource_id)) { + printf("%s not owned by curr partition %d\n", dev->name, pdata->resource_id); + return 0; + } printf("Error: %s Power off failed! (error = %d)\n", dev->name, ret); return -EIO;

From: Leonard Crestez leonard.crestez@nxp.com

We are currently using SC_R_LAST as a marker for imx8 power domain tree nodes without a resource attached. This value is compiled into dtb as part of the linux build and used by uboot.

The SC_R_LAST constant changes frequently as SCFW resources are added (by design) and every time we need to update linux and uboot headers together or boot can fail.

Fix this by replacing SC_R_LAST usage with a new constant SC_R_NONE defined to be 0xFFF0.

Reviewed-by: Peng Fan peng.fan@nxp.com Signed-off-by: Leonard Crestez leonard.crestez@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/dts/fsl-imx8dx.dtsi | 619 ------------------------ drivers/power/domain/imx8-power-domain-legacy.c | 6 +- 2 files changed, 3 insertions(+), 622 deletions(-) delete mode 100644 arch/arm/dts/fsl-imx8dx.dtsi

diff --git a/arch/arm/dts/fsl-imx8dx.dtsi b/arch/arm/dts/fsl-imx8dx.dtsi deleted file mode 100644 index ae1d1f460b..0000000000 --- a/arch/arm/dts/fsl-imx8dx.dtsi +++ /dev/null @@ -1,619 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2018 NXP - */ - -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include "fsl-imx8-ca35.dtsi" -#include <dt-bindings/soc/imx_rsrc.h> -#include <dt-bindings/soc/imx8_pd.h> -#include <dt-bindings/clock/imx8qxp-clock.h> -#include <dt-bindings/input/input.h> -#include <dt-bindings/pinctrl/pads-imx8qxp.h> -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/thermal/thermal.h> - -/ { - model = "Freescale i.MX8DX"; - compatible = "fsl,imx8dx", "fsl,imx8qxp"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - ethernet0 = &fec1; - ethernet1 = &fec2; - serial0 = &lpuart0; - mmc0 = &usdhc1; - mmc1 = &usdhc2; - mmc2 = &usdhc3; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - gpio0 = &gpio0; - gpio1 = &gpio1; - gpio2 = &gpio2; - gpio3 = &gpio3; - gpio4 = &gpio4; - gpio5 = &gpio5; - gpio6 = &gpio6; - gpio7 = &gpio7; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x00000000 0x80000000 0 0x40000000>; - /* DRAM space - 1, size : 1 GB DRAM */ - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - /* - * reserved-memory layout - * 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M4 - * Shouldn't be used at A core and Linux side. - * - */ - decoder_boot: decoder_boot@0x84000000 { - no-map; - reg = <0 0x84000000 0 0x2000000>; - }; - encoder_boot: encoder_boot@0x86000000 { - no-map; - reg = <0 0x86000000 0 0x2000000>; - }; - rpmsg_reserved: rpmsg@0x90000000 { - no-map; - reg = <0 0x90000000 0 0x400000>; - }; - decoder_rpc: decoder_rpc@0x90400000 { - no-map; - reg = <0 0x90400000 0 0x1000000>; - }; - encoder_rpc: encoder_rpc@0x91400000 { - no-map; - reg = <0 0x91400000 0 0x1000000>; - }; - dsp_reserved: dsp@0x92400000 { - no-map; - reg = <0 0x92400000 0 0x2000000>; - }; - decoder_str: str@0x94400000 { - no-map; - reg = <0 0x94400000 0 0x1800000>; - }; - /* global autoconfigured region for contiguous allocations */ - linux,cma { - compatible = "shared-dma-pool"; - reusable; - size = <0 0x28000000>; - alloc-ranges = <0 0x96000000 0 0x28000000>; - linux,cma-default; - }; - }; - - gic: interrupt-controller@51a00000 { - compatible = "arm,gic-v3"; - reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ - <0x0 0x51b00000 0 0xC0000>; /* GICR (RD_base + SGI_base) */ - #interrupt-cells = <3>; - interrupt-controller; - interrupts = <GIC_PPI 9 - (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>; - interrupt-parent = <&gic>; - }; - - mu: mu@5d1c0000 { - compatible = "fsl,imx8-mu"; - reg = <0x0 0x5d1c0000 0x0 0x10000>; - interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; - interrupt-parent = <&gic>; - status = "okay"; - - clk: clk { - compatible = "fsl,imx8qxp-clk"; - #clock-cells = <1>; - }; - - iomuxc: iomuxc { - compatible = "fsl,imx8qxp-iomuxc"; - }; - }; - - imx8qx-pm { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - pd_lsio: PD_LSIO { - compatible = "nxp,imx8-pd"; - reg = <SC_R_LAST>; - #power-domain-cells = <0>; - #address-cells = <1>; - #size-cells = <0>; - - pd_lsio_gpio0: PD_LSIO_GPIO_0 { - reg = <SC_R_GPIO_0>; - #power-domain-cells = <0>; - power-domains = <&pd_lsio>; - }; - pd_lsio_gpio1: PD_LSIO_GPIO_1 { - reg = <SC_R_GPIO_1>; - #power-domain-cells = <0>; - power-domains = <&pd_lsio>; - }; - pd_lsio_gpio2: PD_LSIO_GPIO_2 { - reg = <SC_R_GPIO_2>; - #power-domain-cells = <0>; - power-domains = <&pd_lsio>; - }; - pd_lsio_gpio3: PD_LSIO_GPIO_3 { - reg = <SC_R_GPIO_3>; - #power-domain-cells = <0>; - power-domains = <&pd_lsio>; - }; - pd_lsio_gpio4: PD_LSIO_GPIO_4 { - reg = <SC_R_GPIO_4>; - #power-domain-cells = <0>; - power-domains = <&pd_lsio>; - }; - pd_lsio_gpio5: PD_LSIO_GPIO_5{ - reg = <SC_R_GPIO_5>; - #power-domain-cells = <0>; - power-domains = <&pd_lsio>; - }; - pd_lsio_gpio6: PD_LSIO_GPIO_6 { - reg = <SC_R_GPIO_6>; - #power-domain-cells = <0>; - power-domains = <&pd_lsio>; - }; - pd_lsio_gpio7: PD_LSIO_GPIO_7 { - reg = <SC_R_GPIO_7>; - #power-domain-cells = <0>; - power-domains = <&pd_lsio>; - }; - }; - - pd_conn: PD_CONN { - compatible = "nxp,imx8-pd"; - reg = <SC_R_LAST>; - #power-domain-cells = <0>; - #address-cells = <1>; - #size-cells = <0>; - - pd_conn_sdch0: PD_CONN_SDHC_0 { - reg = <SC_R_SDHC_0>; - #power-domain-cells = <0>; - power-domains = <&pd_conn>; - }; - pd_conn_sdch1: PD_CONN_SDHC_1 { - reg = <SC_R_SDHC_1>; - #power-domain-cells = <0>; - power-domains = <&pd_conn>; - }; - pd_conn_sdch2: PD_CONN_SDHC_2 { - reg = <SC_R_SDHC_2>; - #power-domain-cells = <0>; - power-domains = <&pd_conn>; - }; - pd_conn_enet0: PD_CONN_ENET_0 { - reg = <SC_R_ENET_0>; - #power-domain-cells = <0>; - power-domains = <&pd_conn>; - }; - pd_conn_enet1: PD_CONN_ENET_1 { - reg = <SC_R_ENET_1>; - #power-domain-cells = <0>; - power-domains = <&pd_conn>; - }; - }; - - pd_dma: PD_DMA { - compatible = "nxp,imx8-pd"; - reg = <SC_R_LAST>; - #power-domain-cells = <0>; - #address-cells = <1>; - #size-cells = <0>; - - pd_dma_lpi2c0: PD_DMA_I2C_0 { - reg = <SC_R_I2C_0>; - #power-domain-cells = <0>; - power-domains = <&pd_dma>; - }; - pd_dma_lpi2c1: PD_DMA_I2C_1 { - reg = <SC_R_I2C_1>; - #power-domain-cells = <0>; - power-domains = <&pd_dma>; - }; - pd_dma_lpi2c2:PD_DMA_I2C_2 { - reg = <SC_R_I2C_2>; - #power-domain-cells = <0>; - power-domains = <&pd_dma>; - }; - pd_dma_lpi2c3: PD_DMA_I2C_3 { - reg = <SC_R_I2C_3>; - #power-domain-cells = <0>; - power-domains = <&pd_dma>; - }; - pd_dma_lpuart0: PD_DMA_UART0 { - reg = <SC_R_UART_0>; - #power-domain-cells = <0>; - power-domains = <&pd_dma>; - wakeup-irq = <225>; - }; - pd_dma_lpuart1: PD_DMA_UART1 { - reg = <SC_R_UART_1>; - #power-domain-cells = <0>; - power-domains = <&pd_dma>; - }; - pd_dma_lpuart2: PD_DMA_UART2 { - reg = <SC_R_UART_2>; - #power-domain-cells = <0>; - power-domains = <&pd_dma>; - }; - pd_dma_lpuart3: PD_DMA_UART3 { - reg = <SC_R_UART_3>; - #power-domain-cells = <0>; - power-domains = <&pd_dma>; - }; - }; - }; - - i2c0: i2c@5a800000 { - compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; - reg = <0x0 0x5a800000 0x0 0x4000>; - interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; - interrupt-parent = <&gic>; - clocks = <&clk IMX8QXP_I2C0_CLK>, - <&clk IMX8QXP_I2C0_IPG_CLK>; - clock-names = "per", "ipg"; - assigned-clocks = <&clk IMX8QXP_I2C0_CLK>; - assigned-clock-rates = <24000000>; - power-domains = <&pd_dma_lpi2c0>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c1: i2c@5a810000 { - compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; - reg = <0x0 0x5a810000 0x0 0x4000>; - interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; - interrupt-parent = <&gic>; - clocks = <&clk IMX8QXP_I2C1_CLK>, - <&clk IMX8QXP_I2C1_IPG_CLK>; - clock-names = "per", "ipg"; - assigned-clocks = <&clk IMX8QXP_I2C1_CLK>; - assigned-clock-rates = <24000000>; - power-domains = <&pd_dma_lpi2c1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@5a820000 { - compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; - reg = <0x0 0x5a820000 0x0 0x4000>; - interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; - interrupt-parent = <&gic>; - clocks = <&clk IMX8QXP_I2C2_CLK>, - <&clk IMX8QXP_I2C2_IPG_CLK>; - clock-names = "per", "ipg"; - assigned-clocks = <&clk IMX8QXP_I2C2_CLK>; - assigned-clock-rates = <24000000>; - power-domains = <&pd_dma_lpi2c2>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c3: i2c@5a830000 { - compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; - reg = <0x0 0x5a830000 0x0 0x4000>; - interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; - interrupt-parent = <&gic>; - clocks = <&clk IMX8QXP_I2C3_CLK>, - <&clk IMX8QXP_I2C3_IPG_CLK>; - clock-names = "per", "ipg"; - assigned-clocks = <&clk IMX8QXP_I2C3_CLK>; - assigned-clock-rates = <24000000>; - power-domains = <&pd_dma_lpi2c3>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - gpio0: gpio@5d080000 { - compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; - reg = <0x0 0x5d080000 0x0 0x10000>; - interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - power-domains = <&pd_lsio_gpio0>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio@5d090000 { - compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; - reg = <0x0 0x5d090000 0x0 0x10000>; - interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - power-domains = <&pd_lsio_gpio1>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@5d0a0000 { - compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; - reg = <0x0 0x5d0a0000 0x0 0x10000>; - interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - power-domains = <&pd_lsio_gpio2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio@5d0b0000 { - compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; - reg = <0x0 0x5d0b0000 0x0 0x10000>; - interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - power-domains = <&pd_lsio_gpio3>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio4: gpio@5d0c0000 { - compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; - reg = <0x0 0x5d0c0000 0x0 0x10000>; - interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - power-domains = <&pd_lsio_gpio4>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio5: gpio@5d0d0000 { - compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; - reg = <0x0 0x5d0d0000 0x0 0x10000>; - interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - power-domains = <&pd_lsio_gpio5>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio6: gpio@5d0e0000 { - compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; - reg = <0x0 0x5d0e0000 0x0 0x10000>; - interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - power-domains = <&pd_lsio_gpio6>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio7: gpio@5d0f0000 { - compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; - reg = <0x0 0x5d0f0000 0x0 0x10000>; - interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - power-domains = <&pd_lsio_gpio7>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - lpuart0: serial@5a060000 { - compatible = "fsl,imx8qm-lpuart"; - reg = <0x0 0x5a060000 0x0 0x1000>; - interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8QXP_UART0_CLK>, - <&clk IMX8QXP_UART0_IPG_CLK>; - clock-names = "per", "ipg"; - assigned-clocks = <&clk IMX8QXP_UART0_CLK>; - assigned-clock-rates = <80000000>; - power-domains = <&pd_dma_lpuart0>; - status = "disabled"; - }; - - lpuart1: serial@5a070000 { - compatible = "fsl,imx8qm-lpuart"; - reg = <0x0 0x5a070000 0x0 0x1000>; - interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8QXP_UART1_CLK>, - <&clk IMX8QXP_UART1_IPG_CLK>; - clock-names = "per", "ipg"; - assigned-clocks = <&clk IMX8QXP_UART1_CLK>; - assigned-clock-rates = <80000000>; - power-domains = <&pd_dma_lpuart1>; - status = "disabled"; - }; - - lpuart2: serial@5a080000 { - compatible = "fsl,imx8qm-lpuart"; - reg = <0x0 0x5a080000 0x0 0x1000>; - interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8QXP_UART2_CLK>, - <&clk IMX8QXP_UART2_IPG_CLK>; - clock-names = "per", "ipg"; - assigned-clocks = <&clk IMX8QXP_UART2_CLK>; - assigned-clock-rates = <80000000>; - power-domains = <&pd_dma_lpuart2>; - status = "disabled"; - }; - - lpuart3: serial@5a090000 { - compatible = "fsl,imx8qm-lpuart"; - reg = <0x0 0x5a090000 0x0 0x1000>; - interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8QXP_UART3_CLK>, - <&clk IMX8QXP_UART3_IPG_CLK>; - clock-names = "per", "ipg"; - assigned-clocks = <&clk IMX8QXP_UART3_CLK>; - assigned-clock-rates = <80000000>; - power-domains = <&pd_dma_lpuart3>; - status = "disabled"; - }; - - usdhc1: usdhc@5b010000 { - compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc"; - interrupt-parent = <&gic>; - interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0x5b010000 0x0 0x10000>; - clocks = <&clk IMX8QXP_SDHC0_IPG_CLK>, - <&clk IMX8QXP_SDHC0_CLK>, - <&clk IMX8QXP_CLK_DUMMY>; - clock-names = "ipg", "per", "ahb"; - assigned-clocks = <&clk IMX8QXP_SDHC0_SEL>, <&clk IMX8QXP_SDHC0_DIV>; - assigned-clock-parents = <&clk IMX8QXP_CONN_PLL0_CLK>; - assigned-clock-rates = <0>, <400000000>; - power-domains = <&pd_conn_sdch0>; - fsl,tuning-start-tap = <20>; - fsl,tuning-step= <2>; - status = "disabled"; - }; - - usdhc2: usdhc@5b020000 { - compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc"; - interrupt-parent = <&gic>; - interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0x5b020000 0x0 0x10000>; - clocks = <&clk IMX8QXP_SDHC1_IPG_CLK>, - <&clk IMX8QXP_SDHC1_CLK>, - <&clk IMX8QXP_CLK_DUMMY>; - clock-names = "ipg", "per", "ahb"; - assigned-clocks = <&clk IMX8QXP_SDHC1_SEL>, <&clk IMX8QXP_SDHC1_DIV>; - assigned-clock-parents = <&clk IMX8QXP_CONN_PLL0_CLK>; - assigned-clock-rates = <0>, <200000000>; - power-domains = <&pd_conn_sdch1>; - fsl,tuning-start-tap = <20>; - fsl,tuning-step= <2>; - status = "disabled"; - }; - - usdhc3: usdhc@5b030000 { - compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc"; - interrupt-parent = <&gic>; - interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0x5b030000 0x0 0x10000>; - clocks = <&clk IMX8QXP_SDHC2_IPG_CLK>, - <&clk IMX8QXP_SDHC2_CLK>, - <&clk IMX8QXP_CLK_DUMMY>; - clock-names = "ipg", "per", "ahb"; - assigned-clocks = <&clk IMX8QXP_SDHC2_SEL>, <&clk IMX8QXP_SDHC2_DIV>; - assigned-clock-parents = <&clk IMX8QXP_CONN_PLL0_CLK>; - assigned-clock-rates = <0>, <200000000>; - power-domains = <&pd_conn_sdch2>; - status = "disabled"; - }; - - fec1: ethernet@5b040000 { - compatible = "fsl,imx7d-fec", "fsl,imx8qm-fec"; - reg = <0x0 0x5b040000 0x0 0x10000>; - interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8QXP_ENET0_IPG_CLK>, <&clk IMX8QXP_ENET0_AHB_CLK>, - <&clk IMX8QXP_ENET0_RGMII_TX_CLK>, <&clk IMX8QXP_ENET0_PTP_CLK>; - clock-names = "ipg", "ahb", "enet_clk_ref", "ptp"; - assigned-clocks = <&clk IMX8QXP_ENET0_REF_DIV>, <&clk IMX8QXP_ENET0_PTP_CLK>; - assigned-clock-rates = <125000000>, <125000000>; - fsl,num-tx-queues=<3>; - fsl,num-rx-queues=<3>; - power-domains = <&pd_conn_enet0>; - status = "disabled"; - }; - - fec2: ethernet@5b050000 { - compatible = "fsl,imx7d-fec", "fsl,imx8qm-fec"; - reg = <0x0 0x5b050000 0x0 0x10000>; - interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8QXP_ENET1_IPG_CLK>, <&clk IMX8QXP_ENET1_AHB_CLK>, - <&clk IMX8QXP_ENET1_RGMII_TX_CLK>, <&clk IMX8QXP_ENET1_PTP_CLK>; - clock-names = "ipg", "ahb", "enet_clk_ref", "ptp"; - assigned-clocks = <&clk IMX8QXP_ENET1_REF_DIV>, <&clk IMX8QXP_ENET1_PTP_CLK>; - assigned-clock-rates = <125000000>, <125000000>; - fsl,num-tx-queues=<3>; - fsl,num-rx-queues=<3>; - power-domains = <&pd_conn_enet1>; - status = "disabled"; - }; - - tsens: thermal-sensor { - compatible = "nxp,imx8qxp-sc-tsens"; - /* number of the temp sensor on the chip */ - tsens-num = <2>; - #thermal-sensor-cells = <1>; - }; - - thermal_zones: thermal-zones { - /* cpu thermal */ - cpu-thermal0 { - polling-delay-passive = <250>; - polling-delay = <2000>; - /*the slope and offset of the temp sensor */ - thermal-sensors = <&tsens 0>; - trips { - cpu_alert0: trip0 { - temperature = <107000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu_crit0: trip1 { - temperature = <127000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - cooling-maps { - map0 { - trip = <&cpu_alert0>; - cooling-device = - <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - drc-thermal0 { - polling-delay-passive = <250>; - polling-delay = <2000>; - thermal-sensors = <&tsens 1>; - status = "disabled"; - trips { - drc_alert0: trip0 { - temperature = <107000>; - hysteresis = <2000>; - type = "passive"; - }; - drc_crit0: trip1 { - temperature = <127000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - }; -}; - -&A35_0 { - clocks = <&clk IMX8QXP_A35_DIV>; -}; - -/delete-node/ &A35_2; -/delete-node/ &A35_3; diff --git a/drivers/power/domain/imx8-power-domain-legacy.c b/drivers/power/domain/imx8-power-domain-legacy.c index a5f2f8a445..f679df9e5d 100644 --- a/drivers/power/domain/imx8-power-domain-legacy.c +++ b/drivers/power/domain/imx8-power-domain-legacy.c @@ -90,7 +90,7 @@ static int imx8_power_domain_on(struct power_domain *power_domain) if (ppriv->state_on) return 0;

- if (pdata->resource_id != SC_R_LAST) { + if (pdata->resource_id != SC_R_NONE) { if (!sc_rm_is_resource_owned(-1, pdata->resource_id)) printf("%s [%d] not owned by curr partition\n", dev->name, pdata->resource_id);

@@ -139,7 +139,7 @@ static int imx8_power_domain_off_node(struct power_domain *power_domain) } }

- if (pdata->resource_id != SC_R_LAST) { + if (pdata->resource_id != SC_R_NONE) { ret = sc_pm_set_resource_power_mode(-1, pdata->resource_id, SC_PM_PW_MODE_OFF); if (ret) { @@ -202,7 +202,7 @@ static int imx8_power_domain_off_parentnodes(struct power_domain *power_domain) }

/* power off parent */ - if (pdata->resource_id != SC_R_LAST) { + if (pdata->resource_id != SC_R_NONE) { ret = sc_pm_set_resource_power_mode(-1, pdata->resource_id, SC_PM_PW_MODE_OFF);