[U-Boot] [PATCH 1/2] i.MX6: Correct ANATOP_PFD (Phase Fractional Divider) register declarations
Some _CLKGATE_MASK and _FRAC_MASK macros were wrong for PFD_480 and the PFD_528 macros were missing.
Fortunately, the incorrect macros weren't being used.
Since both the PFD_480 and PFD_528 registers have the same structure, and the fields are identical for [0..3] in bytes [0..3], so a single set of macros will suffice.
Signed-off-by: Eric Nelson eric.nelson@boundarydevices.com --- arch/arm/include/asm/arch-mx6/imx-regs.h | 29 ++++++----------------------- 1 file changed, 6 insertions(+), 23 deletions(-)
diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index 5d6bccb..5fea7f2 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -629,29 +629,12 @@ struct anatop_regs { u32 digprog_sololite; /* 0x280 */ };
-#define ANATOP_PFD_480_PFD0_FRAC_SHIFT 0 -#define ANATOP_PFD_480_PFD0_FRAC_MASK (0x3f<<ANATOP_PFD_480_PFD0_FRAC_SHIFT) -#define ANATOP_PFD_480_PFD0_STABLE_SHIFT 6 -#define ANATOP_PFD_480_PFD0_STABLE_MASK (1<<ANATOP_PFD_480_PFD0_STABLE_SHIFT) -#define ANATOP_PFD_480_PFD0_CLKGATE_SHIFT 7 -#define ANATOP_PFD_480_PFD0_CLKGATE_MASK (1<<ANATOP_PFD_480_PFD0_CLKGATE_SHIFT) -#define ANATOP_PFD_480_PFD1_FRAC_SHIFT 8 -#define ANATOP_PFD_480_PFD1_FRAC_MASK (0x3f<<ANATOP_PFD_480_PFD1_FRAC_SHIFT) -#define ANATOP_PFD_480_PFD1_STABLE_SHIFT 14 -#define ANATOP_PFD_480_PFD1_STABLE_MASK (1<<ANATOP_PFD_480_PFD1_STABLE_SHIFT) -#define ANATOP_PFD_480_PFD1_CLKGATE_SHIFT 15 -#define ANATOP_PFD_480_PFD1_CLKGATE_MASK (0x3f<<ANATOP_PFD_480_PFD1_CLKGATE_SHIFT) -#define ANATOP_PFD_480_PFD2_FRAC_SHIFT 16 -#define ANATOP_PFD_480_PFD2_FRAC_MASK (1<<ANATOP_PFD_480_PFD2_FRAC_SHIFT) -#define ANATOP_PFD_480_PFD2_STABLE_SHIFT 22 -#define ANATOP_PFD_480_PFD2_STABLE_MASK (1<<ANATOP_PFD_480_PFD2_STABLE_SHIFT) -#define ANATOP_PFD_480_PFD2_CLKGATE_SHIFT 23 -#define ANATOP_PFD_480_PFD2_CLKGATE_MASK (0x3f<<ANATOP_PFD_480_PFD2_CLKGATE_SHIFT) -#define ANATOP_PFD_480_PFD3_FRAC_SHIFT 24 -#define ANATOP_PFD_480_PFD3_FRAC_MASK (1<<ANATOP_PFD_480_PFD3_FRAC_SHIFT) -#define ANATOP_PFD_480_PFD3_STABLE_SHIFT 30 -#define ANATOP_PFD_480_PFD3_STABLE_MASK (1<<ANATOP_PFD_480_PFD3_STABLE_SHIFT) -#define ANATOP_PFD_480_PFD3_CLKGATE_SHIFT 31 +#define ANATOP_PFD_FRAC_SHIFT(n) ((n)*8) +#define ANATOP_PFD_FRAC_MASK(n) (0x3f<<ANATOP_PFD_FRAC_SHIFT(n)) +#define ANATOP_PFD_STABLE_SHIFT(n) (6+((n)*8)) +#define ANATOP_PFD_STABLE_MASK(n) (1<<ANATOP_PFD_STABLE_SHIFT(n)) +#define ANATOP_PFD_CLKGATE_SHIFT(n) (7+((n)*8)) +#define ANATOP_PFD_CLKGATE_MASK(n) (1<<ANATOP_PFD_CLKGATE_SHIFT(n))
struct iomuxc_base_regs { u32 gpr[14]; /* 0x000 */
Signed-off-by: Eric Nelson eric.nelson@boundarydevices.com --- board/boundary/nitrogen6x/nitrogen6x.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c index 79ab449..58fe8ae 100644 --- a/board/boundary/nitrogen6x/nitrogen6x.c +++ b/board/boundary/nitrogen6x/nitrogen6x.c @@ -634,8 +634,8 @@ static void setup_display(void) writel(reg, &mxc_ccm->CCGR3);
/* set PFD1_FRAC to 0x13 == 455 MHz (480*18)/0x13 */ - writel(ANATOP_PFD_480_PFD1_FRAC_MASK, &anatop->pfd_480_clr); - writel(0x13<<ANATOP_PFD_480_PFD1_FRAC_SHIFT, &anatop->pfd_480_set); + writel(ANATOP_PFD_FRAC_MASK(1), &anatop->pfd_480_clr); + writel(0x13<<ANATOP_PFD_FRAC_SHIFT(1), &anatop->pfd_480_set);
/* set LDB0, LDB1 clk select to 011/011 */ reg = readl(&mxc_ccm->cs2cdr);
On 08/29/2013 10:45 AM, Eric Nelson wrote:
Signed-off-by: Eric Nelson eric.nelson@boundarydevices.com
board/boundary/nitrogen6x/nitrogen6x.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c index 79ab449..58fe8ae 100644 --- a/board/boundary/nitrogen6x/nitrogen6x.c +++ b/board/boundary/nitrogen6x/nitrogen6x.c @@ -634,8 +634,8 @@ static void setup_display(void) writel(reg, &mxc_ccm->CCGR3);
/* set PFD1_FRAC to 0x13 == 455 MHz (480*18)/0x13 */
- writel(ANATOP_PFD_480_PFD1_FRAC_MASK, &anatop->pfd_480_clr);
- writel(0x13<<ANATOP_PFD_480_PFD1_FRAC_SHIFT, &anatop->pfd_480_set);
- writel(ANATOP_PFD_FRAC_MASK(1), &anatop->pfd_480_clr);
- writel(0x13<<ANATOP_PFD_FRAC_SHIFT(1), &anatop->pfd_480_set);
Nak.
It turns out that PLL3/PFD1 isn't feeding anything in U-Boot on SABRE Lite or Nitrogen6X so there's no reason to change the value.
participants (1)
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Eric Nelson