[U-Boot] [PATCH 0/6] mips: mscc: Add multi-dtb support to luton+ocelot

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Lars Povlsen

19 Dec 2018 19 Dec '18

1:42 p.m.

This patch series add support for using multi-dtb on the MSCC luton and ocelot SOC reference boards. The appropriate board will be determined during startup, and the right DT will be selected.

The patch is based off u-boot-mips repo.

Lars Povlsen (6): mips: luton+ocelot: Remove board-specific config options mips: mscc: Add generic PHY MIIM utility functions mips: mscc: Add generic GPIO control utility function mips: luton: DT: Add pcb090 mips: luton: Add multi-dtb support mips: ocelot: Add multi-dtb support

arch/mips/dts/Makefile | 2 + arch/mips/dts/luton_pcb090.dts | 36 +++++++++ arch/mips/mach-mscc/Kconfig | 38 +++------- arch/mips/mach-mscc/Makefile | 2 +- arch/mips/mach-mscc/gpio.c | 33 +++++++++ arch/mips/mach-mscc/include/mach/common.h | 22 ++++++ .../include/mach/luton/luton_devcpu_gcb.h | 4 + .../mach/luton/luton_devcpu_gcb_miim_regs.h | 26 +++++++ .../include/mach/ocelot/ocelot_devcpu_gcb.h | 2 + .../mach/ocelot/ocelot_devcpu_gcb_miim_regs.h | 25 +++++++ arch/mips/mach-mscc/phy.c | 73 +++++++++++++++++++ board/mscc/luton/luton.c | 46 +++++++++++- board/mscc/ocelot/ocelot.c | 52 +++++++++++-- configs/mscc_luton_defconfig | 7 +- configs/mscc_ocelot_defconfig | 7 +- configs/mscc_ocelot_pcb120_defconfig | 60 --------------- include/configs/vcoreiii.h | 2 + 17 files changed, 333 insertions(+), 104 deletions(-) create mode 100644 arch/mips/dts/luton_pcb090.dts create mode 100644 arch/mips/mach-mscc/gpio.c create mode 100644 arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb_miim_regs.h create mode 100644 arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb_miim_regs.h create mode 100644 arch/mips/mach-mscc/phy.c delete mode 100644 configs/mscc_ocelot_pcb120_defconfig

-- 2.19.2

Show replies by date

Lars Povlsen

19 Dec 19 Dec

1:42 p.m.

New subject: [U-Boot] [PATCH 1/6] mips: luton+ocelot: Remove board-specific config options

As we are moving to multi-dtb and board detection, remove static board config options.

Signed-off-by: Lars Povlsen lars.povlsen@microchip.com --- arch/mips/mach-mscc/Kconfig | 38 ++++++++++--------------------------- 1 file changed, 10 insertions(+), 28 deletions(-)

diff --git a/arch/mips/mach-mscc/Kconfig b/arch/mips/mach-mscc/Kconfig index 0e35b77c9d..37ef432e48 100644 --- a/arch/mips/mach-mscc/Kconfig +++ b/arch/mips/mach-mscc/Kconfig @@ -15,47 +15,29 @@ config SOC_VCOREIII config SYS_SOC default "mscc"

+choice + + prompt "SOC Family Variant" + config SOC_OCELOT - bool + bool "Ocelot SOC Family" select SOC_VCOREIII + select DESIGNWARE_SPI help This supports MSCC Ocelot family of SOCs.

config SOC_LUTON - bool + bool "Luton SOC Family" select SOC_VCOREIII + select MSCC_BITBANG_SPI_GPIO help This supports MSCC Luton family of SOCs.

+endchoice + config SYS_CONFIG_NAME default "vcoreiii"

-choice - prompt "Board select" - -config TARGET_OCELOT_PCB120 - bool "MSCC PCB120 Reference Board (aka VSC5635EV)" - select SOC_OCELOT - help - When selected, CONFIG_DEFAULT_DEVICE_TREE should be set to - ocelot_pcb120 - -config TARGET_OCELOT_PCB123 - bool "MSCC PCB123 Reference Board (aka VSC7514EV))" - select SOC_OCELOT - help - When selected, CONFIG_DEFAULT_DEVICE_TREE should be set to - ocelot_pcb123 - -config TARGET_LUTON_PCB091 - bool "MSCC PCB091 Reference Board" - select SOC_LUTON - select MSCC_BITBANG_SPI_GPIO - help - When selected, CONFIG_DEFAULT_DEVICE_TREE should be set to - luton_pcb091 -endchoice - choice prompt "DDR type"

-- 2.19.2

Daniel Schwierzeck

6:25 p.m.

New subject: [U-Boot] [PATCH 1/6] mips: luton+ocelot: Remove board-specific config options

Am 19.12.18 um 13:42 schrieb Lars Povlsen:

...

As we are moving to multi-dtb and board detection, remove static board config options.

Signed-off-by: Lars Povlsen lars.povlsen@microchip.com

arch/mips/mach-mscc/Kconfig | 38 ++++++++++--------------------------- 1 file changed, 10 insertions(+), 28 deletions(-)

This patch should be squashed into the last commit to not break bisectability. After only applying this patch you can't build any Ocelot/Luton baords anymore until the last patch is applied. Otherwise the series looks good.

...

diff --git a/arch/mips/mach-mscc/Kconfig b/arch/mips/mach-mscc/Kconfig index 0e35b77c9d..37ef432e48 100644 --- a/arch/mips/mach-mscc/Kconfig +++ b/arch/mips/mach-mscc/Kconfig @@ -15,47 +15,29 @@ config SOC_VCOREIII config SYS_SOC default "mscc"

+choice

prompt "SOC Family Variant"

config SOC_OCELOT

bool

bool "Ocelot SOC Family" select SOC_VCOREIII

select DESIGNWARE_SPI help This supports MSCC Ocelot family of SOCs.

config SOC_LUTON

bool

bool "Luton SOC Family" select SOC_VCOREIII

select MSCC_BITBANG_SPI_GPIO help This supports MSCC Luton family of SOCs.

+endchoice

config SYS_CONFIG_NAME default "vcoreiii"

-choice

prompt "Board select"

-config TARGET_OCELOT_PCB120
bool "MSCC PCB120 Reference Board (aka VSC5635EV)"

select SOC_OCELOT

help
 When selected, CONFIG_DEFAULT_DEVICE_TREE should be set to
 ocelot_pcb120
-config TARGET_OCELOT_PCB123
bool "MSCC PCB123 Reference Board (aka VSC7514EV))"

select SOC_OCELOT

help
 When selected, CONFIG_DEFAULT_DEVICE_TREE should be set to
 ocelot_pcb123
-config TARGET_LUTON_PCB091
bool "MSCC PCB091 Reference Board"

select SOC_LUTON

select MSCC_BITBANG_SPI_GPIO

help
 When selected, CONFIG_DEFAULT_DEVICE_TREE should be set to
 luton_pcb091
-endchoice

choice prompt "DDR type"

-- - Daniel

Lars.Povlsen＠microchip.com

20 Dec 20 Dec

9:17 a.m.

New subject: [U-Boot] [PATCH 1/6] mips: luton+ocelot: Remove board-specific config options

...

From: Daniel Schwierzeck daniel.schwierzeck@gmail.com Sent: Wednesday, December 19, 2018 18:26 To: Lars Povlsen - M31675 Lars.Povlsen@microchip.com; u- boot@lists.denx.de Cc: gregory.clement@bootlin.com; Horatiu Vultur - M31836 Horatiu.Vultur@microchip.com Subject: Re: [PATCH 1/6] mips: luton+ocelot: Remove board-specific config options

Am 19.12.18 um 13:42 schrieb Lars Povlsen:

...
As we are moving to multi-dtb and board detection, remove static board config options.

Signed-off-by: Lars Povlsen lars.povlsen@microchip.com

arch/mips/mach-mscc/Kconfig | 38 ++++++++++--------------------------

...
1 file changed, 10 insertions(+), 28 deletions(-)

This patch should be squashed into the last commit to not break bisectability. After only applying this patch you can't build any Ocelot/Luton baords anymore until the last patch is applied. Otherwise the series looks good.

Thank you for the comments - makes totally sense.

Actually then the first and the last two patches should be squashed, as the Kconfig and *_defconfigs need to go hand in hand.

I will send a new (v2) patch asap.

Cheers,

---Lars

Lars Povlsen

19 Dec 19 Dec

1:42 p.m.

New subject: [U-Boot] [PATCH 2/6] mips: mscc: Add generic PHY MIIM utility functions

The PHY MIIM utility functions can/will be used for board detection purposes.

Signed-off-by: Lars Povlsen lars.povlsen@microchip.com --- arch/mips/mach-mscc/Makefile | 2 +- arch/mips/mach-mscc/include/mach/common.h | 20 +++++ .../mach/luton/luton_devcpu_gcb_miim_regs.h | 26 +++++++ .../mach/ocelot/ocelot_devcpu_gcb_miim_regs.h | 25 +++++++ arch/mips/mach-mscc/phy.c | 73 +++++++++++++++++++ 5 files changed, 145 insertions(+), 1 deletion(-) create mode 100644 arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb_miim_regs.h create mode 100644 arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb_miim_regs.h create mode 100644 arch/mips/mach-mscc/phy.c

diff --git a/arch/mips/mach-mscc/Makefile b/arch/mips/mach-mscc/Makefile index 6c60f26ca4..300c88b5cd 100644 --- a/arch/mips/mach-mscc/Makefile +++ b/arch/mips/mach-mscc/Makefile @@ -2,5 +2,5 @@

CFLAGS_cpu.o += -finline-limit=64000

-obj-y += cpu.o dram.o reset.o lowlevel_init.o +obj-y += cpu.o dram.o reset.o phy.o lowlevel_init.o obj-$(CONFIG_SOC_LUTON) += lowlevel_init_luton.o diff --git a/arch/mips/mach-mscc/include/mach/common.h b/arch/mips/mach-mscc/include/mach/common.h index 931ecd7985..92a055561e 100644 --- a/arch/mips/mach-mscc/include/mach/common.h +++ b/arch/mips/mach-mscc/include/mach/common.h @@ -9,10 +9,12 @@ #if defined(CONFIG_SOC_OCELOT) #include <mach/ocelot/ocelot.h> #include <mach/ocelot/ocelot_devcpu_gcb.h> +#include <mach/ocelot/ocelot_devcpu_gcb_miim_regs.h> #include <mach/ocelot/ocelot_icpu_cfg.h> #elif defined(CONFIG_SOC_LUTON) #include <mach/luton/luton.h> #include <mach/luton/luton_devcpu_gcb.h> +#include <mach/luton/luton_devcpu_gcb_miim_regs.h> #include <mach/luton/luton_icpu_cfg.h> #else #error Unsupported platform @@ -25,4 +27,22 @@

#define VCOREIII_TIMER_DIVIDER 25 /* Clock tick ~ 0.1 us */

+/* Common utility functions */ + +int mscc_phy_rd_wr(u8 read, + u32 miim_controller, + u8 miim_addr, + u8 addr, + u16 *value); + +int mscc_phy_rd(u32 miim_controller, + u8 miim_addr, + u8 addr, + u16 *value); + +int mscc_phy_wr(u32 miim_controller, + u8 miim_addr, + u8 addr, + u16 value); + #endif /* __ASM_MACH_COMMON_H */ diff --git a/arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb_miim_regs.h b/arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb_miim_regs.h new file mode 100644 index 0000000000..2303734894 --- /dev/null +++ b/arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb_miim_regs.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Microsemi Ocelot Switch driver + * + * Copyright (c) 2018 Microsemi Corporation + */ + +#ifndef _MSCC_LUTON_MIIM_REGS_H_ +#define _MSCC_LUTON_MIIM_REGS_H_ + +#define MIIM_MII_STATUS(gi) (0xa0 + (gi * 36)) +#define MIIM_MII_CMD(gi) (0xa8 + (gi * 36)) +#define MIIM_MII_DATA(gi) (0xac + (gi * 36)) + +#define MSCC_F_MII_STATUS_MIIM_STAT_BUSY(x) (x ? BIT(3) : 0) + +#define MSCC_F_MII_CMD_MIIM_CMD_VLD(x) (x ? BIT(31) : 0) +#define MSCC_F_MII_CMD_MIIM_CMD_PHYAD(x) (GENMASK(29, 25) & (x << 25)) +#define MSCC_F_MII_CMD_MIIM_CMD_REGAD(x) (GENMASK(24, 20) & (x << 20)) +#define MSCC_F_MII_CMD_MIIM_CMD_WRDATA(x) (GENMASK(19, 4) & (x << 4)) +#define MSCC_F_MII_CMD_MIIM_CMD_OPR_FIELD(x) (GENMASK(2, 1) & (x << 1)) + +#define MSCC_M_MII_DATA_MIIM_DATA_SUCCESS GENMASK(17, 16) +#define MSCC_X_MII_DATA_MIIM_DATA_RDDATA(x) ((x >> 0) & GENMASK(15, 0)) + +#endif diff --git a/arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb_miim_regs.h b/arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb_miim_regs.h new file mode 100644 index 0000000000..4ad92214a3 --- /dev/null +++ b/arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb_miim_regs.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2018 Microsemi Corporation + */ + +#ifndef _MSCC_OCELOT_DEVCPU_GCB_MIIM_REGS_H_ +#define _MSCC_OCELOT_DEVCPU_GCB_MIIM_REGS_H_ + +#define MIIM_MII_STATUS(gi) (0x9c + (gi * 36)) +#define MIIM_MII_CMD(gi) (0xa4 + (gi * 36)) +#define MIIM_MII_DATA(gi) (0xa8 + (gi * 36)) + +#define MSCC_F_MII_STATUS_MIIM_STAT_BUSY(x) ((x) ? BIT(3) : 0) + +#define MSCC_F_MII_CMD_MIIM_CMD_VLD(x) ((x) ? BIT(31) : 0) +#define MSCC_F_MII_CMD_MIIM_CMD_PHYAD(x) (GENMASK(29, 25) & ((x) << 25)) +#define MSCC_F_MII_CMD_MIIM_CMD_REGAD(x) (GENMASK(24, 20) & ((x) << 20)) +#define MSCC_F_MII_CMD_MIIM_CMD_WRDATA(x) (GENMASK(19, 4) & ((x) << 4)) +#define MSCC_F_MII_CMD_MIIM_CMD_OPR_FIELD(x) (GENMASK(2, 1) & ((x) << 1)) +#define MSCC_F_MII_CMD_MIIM_CMD_SCAN(x) ((x) ? BIT(0) : 0) + +#define MSCC_M_MII_DATA_MIIM_DATA_SUCCESS GENMASK(17, 16) +#define MSCC_X_MII_DATA_MIIM_DATA_RDDATA(x) (((x) >> 0) & GENMASK(15, 0)) + +#endif diff --git a/arch/mips/mach-mscc/phy.c b/arch/mips/mach-mscc/phy.c new file mode 100644 index 0000000000..add6280e38 --- /dev/null +++ b/arch/mips/mach-mscc/phy.c @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Microsemi Corporation + */ + +#include <common.h> +#include <asm/io.h> + +int mscc_phy_rd_wr(u8 read, + u32 miimdev, + u8 miim_addr, + u8 addr, + u16 *value) +{ + u32 data; + int i; + + /* Command part */ + data = (read ? MSCC_F_MII_CMD_MIIM_CMD_OPR_FIELD(2) : /* Read */ + MSCC_F_MII_CMD_MIIM_CMD_OPR_FIELD(1) | /* Write */ + MSCC_F_MII_CMD_MIIM_CMD_WRDATA(*value)); /* value */ + + /* Addressing part */ + data |= + MSCC_F_MII_CMD_MIIM_CMD_VLD(1) | /* Valid command */ + MSCC_F_MII_CMD_MIIM_CMD_REGAD(addr) | /* Reg addr */ + MSCC_F_MII_CMD_MIIM_CMD_PHYAD(miim_addr); /* Miim addr */ + + /* Enqueue MIIM operation to be executed */ + writel(data, BASE_DEVCPU_GCB + MIIM_MII_CMD(miimdev)); + + /* Wait for MIIM operation to finish */ + i = 0; + do { + if (i++ > 100) { + debug("Miim timeout"); + return -1; + } + data = readl(BASE_DEVCPU_GCB + MIIM_MII_STATUS(miimdev)); + debug("Read status miim(%d): 0x%08x\n", miimdev, data); + } while (data & MSCC_F_MII_STATUS_MIIM_STAT_BUSY(1)); + + if (read) { + data = readl(BASE_DEVCPU_GCB + MIIM_MII_DATA(miimdev)); + if (data & MSCC_M_MII_DATA_MIIM_DATA_SUCCESS) { + debug("Read(%d, %d) returned 0x%08x\n", + miim_addr, addr, data); + return -1; + } + *value = MSCC_X_MII_DATA_MIIM_DATA_RDDATA(data); + } + + return 0; +} + +int mscc_phy_rd(u32 miimdev, + u8 miim_addr, + u8 addr, + u16 *value) +{ + if (mscc_phy_rd_wr(1, miimdev, miim_addr, addr, value) == 0) + return 0; + debug("Read(%d, %d) returned error\n", miim_addr, addr); + return -1; +} + +int mscc_phy_wr(u32 miimdev, + u8 miim_addr, + u8 addr, + u16 value) +{ + return mscc_phy_rd_wr(0, miimdev, miim_addr, addr, &value); +}

-- 2.19.2

Lars Povlsen

1:42 p.m.

New subject: [U-Boot] [PATCH 3/6] mips: mscc: Add generic GPIO control utility function

The GPIO control function can be used for controlling alternate functions associated with a GPIO.

Signed-off-by: Lars Povlsen lars.povlsen@microchip.com --- arch/mips/mach-mscc/Makefile | 2 +- arch/mips/mach-mscc/gpio.c | 33 +++++++++++++++++++ arch/mips/mach-mscc/include/mach/common.h | 2 ++ .../include/mach/luton/luton_devcpu_gcb.h | 2 ++ .../include/mach/ocelot/ocelot_devcpu_gcb.h | 2 ++ 5 files changed, 40 insertions(+), 1 deletion(-) create mode 100644 arch/mips/mach-mscc/gpio.c

diff --git a/arch/mips/mach-mscc/Makefile b/arch/mips/mach-mscc/Makefile index 300c88b5cd..44538b7118 100644 --- a/arch/mips/mach-mscc/Makefile +++ b/arch/mips/mach-mscc/Makefile @@ -2,5 +2,5 @@

CFLAGS_cpu.o += -finline-limit=64000

-obj-y += cpu.o dram.o reset.o phy.o lowlevel_init.o +obj-y += cpu.o dram.o reset.o phy.o gpio.o lowlevel_init.o obj-$(CONFIG_SOC_LUTON) += lowlevel_init_luton.o diff --git a/arch/mips/mach-mscc/gpio.c b/arch/mips/mach-mscc/gpio.c new file mode 100644 index 0000000000..5e3a53372d --- /dev/null +++ b/arch/mips/mach-mscc/gpio.c @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Microsemi Corporation + */ + +#include <common.h> +#include <asm/io.h> + +void mscc_gpio_set_alternate(int gpio, int mode) +{ + u32 mask = BIT(gpio); + u32 val0, val1; + + val0 = readl(BASE_DEVCPU_GCB + GPIO_ALT(0)); + val1 = readl(BASE_DEVCPU_GCB + GPIO_ALT(1)); + + if (mode == 1) { + val0 |= mask; + val1 &= ~mask; + } else if (mode == 2) { + val0 &= ~mask; + val1 |= mask; + } else if (mode == 3) { + val0 |= mask; + val1 |= mask; + } else { + val0 &= ~mask; + val1 &= ~mask; + } + + writel(val0, BASE_DEVCPU_GCB + GPIO_ALT(0)); + writel(val1, BASE_DEVCPU_GCB + GPIO_ALT(1)); +} diff --git a/arch/mips/mach-mscc/include/mach/common.h b/arch/mips/mach-mscc/include/mach/common.h index 92a055561e..d18ae78bfd 100644 --- a/arch/mips/mach-mscc/include/mach/common.h +++ b/arch/mips/mach-mscc/include/mach/common.h @@ -45,4 +45,6 @@ int mscc_phy_wr(u32 miim_controller, u8 addr, u16 value);

+void mscc_gpio_set_alternate(int gpio, int mode); + #endif /* __ASM_MACH_COMMON_H */ diff --git a/arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb.h b/arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb.h index 8c0b612325..a06cf819b0 100644 --- a/arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb.h +++ b/arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb.h @@ -11,4 +11,6 @@ #define PERF_SOFT_RST_SOFT_SWC_RST BIT(1) #define PERF_SOFT_RST_SOFT_CHIP_RST BIT(0)

+#define GPIO_ALT(x) (0x88 + 4 * (x)) + #endif diff --git a/arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb.h b/arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb.h index f8aa97ba26..d3a76412e2 100644 --- a/arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb.h +++ b/arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb.h @@ -18,4 +18,6 @@

#define PERF_GPIO_OE 0x44

+#define GPIO_ALT(x) (0x54 + 4 * (x)) + #endif

-- 2.19.2

Lars Povlsen

1:42 p.m.

New subject: [U-Boot] [PATCH 4/6] mips: luton: DT: Add pcb090

This prepares individual device trees for MSCC luton-based reference boards - pcb090 and pcb091.

Note: Even though the devices trees are quite common, they will differ significantly in coming patches.

Signed-off-by: Lars Povlsen lars.povlsen@microchip.com --- arch/mips/dts/luton_pcb090.dts | 36 ++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) create mode 100644 arch/mips/dts/luton_pcb090.dts

diff --git a/arch/mips/dts/luton_pcb090.dts b/arch/mips/dts/luton_pcb090.dts new file mode 100644 index 0000000000..a3f8926ad9 --- /dev/null +++ b/arch/mips/dts/luton_pcb090.dts @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Microsemi Corporation + */ + +/dts-v1/; +#include "mscc,luton.dtsi" + +/ { + model = "Luton26 PCB090 Reference Board"; + compatible = "mscc,luton-pcb090", "mscc,luton"; + + aliases { + serial0 = &uart0; + spi0 = &spi0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + spi-flash@0 { + compatible = "spi-flash"; + spi-max-frequency = <18000000>; /* input clock */ + reg = <0>; /* CS0 */ + spi-cs-high; + }; +}; +

-- 2.19.2

Lars Povlsen

1:42 p.m.

New subject: [U-Boot] [PATCH 5/6] mips: luton: Add multi-dtb support

This add single-binary support for the two MSCC luton-based reference boards - pcb090 and pcb091.

Signed-off-by: Lars Povlsen lars.povlsen@microchip.com --- arch/mips/dts/Makefile | 1 + .../include/mach/luton/luton_devcpu_gcb.h | 2 + board/mscc/luton/luton.c | 46 +++++++++++++++++-- configs/mscc_luton_defconfig | 7 ++- include/configs/vcoreiii.h | 2 + 5 files changed, 52 insertions(+), 6 deletions(-)

diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile index 647d2bf0d5..3d436b2248 100644 --- a/arch/mips/dts/Makefile +++ b/arch/mips/dts/Makefile @@ -17,6 +17,7 @@ dtb-$(CONFIG_BOARD_NETGEAR_DGND3700V2) += netgear,dgnd3700v2.dtb dtb-$(CONFIG_BOARD_SAGEM_FAST1704) += sagem,f@st1704.dtb dtb-$(CONFIG_BOARD_TPLINK_WDR4300) += tplink_wdr4300.dtb dtb-$(CONFIG_TARGET_JZ4780_CI20) += ci20.dtb +dtb-$(CONFIG_SOC_LUTON) += luton_pcb090.dtb luton_pcb091.dtb

targets += $(dtb-y)

diff --git a/arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb.h b/arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb.h index a06cf819b0..a74a68593d 100644 --- a/arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb.h +++ b/arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb.h @@ -13,4 +13,6 @@

#define GPIO_ALT(x) (0x88 + 4 * (x))

+#define CHIP_ID (0x08) + #endif diff --git a/board/mscc/luton/luton.c b/board/mscc/luton/luton.c index 41fc6d56a7..b509b6beb3 100644 --- a/board/mscc/luton/luton.c +++ b/board/mscc/luton/luton.c @@ -6,15 +6,18 @@ #include <common.h> #include <asm/io.h>

-#define MSCC_GPIO_ALT0 0x88 -#define MSCC_GPIO_ALT1 0x8C - DECLARE_GLOBAL_DATA_PTR;

+enum { + BOARD_TYPE_PCB090 = 0xAABBCD00, + BOARD_TYPE_PCB091, +}; + void board_debug_uart_init(void) { /* too early for the pinctrl driver, so configure the UART pins here */ - setbits_le32(BASE_DEVCPU_GCB + MSCC_GPIO_ALT0, BIT(30) | BIT(31)); + mscc_gpio_set_alternate(30, 1); + mscc_gpio_set_alternate(31, 1); }

int board_early_init_r(void) @@ -26,3 +29,38 @@ int board_early_init_r(void) gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE; return 0; } + +static void do_board_detect(void) +{ + u32 chipid = (readl(BASE_DEVCPU_GCB + CHIP_ID) >> 12) & 0xFFFF; + + if (chipid == 0x7428 || chipid == 0x7424) + gd->board_type = BOARD_TYPE_PCB091; // Lu10 + else + gd->board_type = BOARD_TYPE_PCB090; // Lu26 +} + +#if defined(CONFIG_MULTI_DTB_FIT) +int board_fit_config_name_match(const char *name) +{ + if (gd->board_type == BOARD_TYPE_PCB090 && + strcmp(name, "luton_pcb090") == 0) + return 0; + + if (gd->board_type == BOARD_TYPE_PCB091 && + strcmp(name, "luton_pcb091") == 0) + return 0; + + return -1; +} +#endif + +#if defined(CONFIG_DTB_RESELECT) +int embedded_dtb_select(void) +{ + do_board_detect(); + fdtdec_setup(); + + return 0; +} +#endif diff --git a/configs/mscc_luton_defconfig b/configs/mscc_luton_defconfig index d7476c4863..03922f5379 100644 --- a/configs/mscc_luton_defconfig +++ b/configs/mscc_luton_defconfig @@ -5,7 +5,7 @@ CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0x70100000 CONFIG_DEBUG_UART_CLOCK=208333333 CONFIG_ARCH_MSCC=y -CONFIG_TARGET_LUTON_PCB091=y +CONFIG_SOC_LUTON=y CONFIG_DDRTYPE_MT47H128M8HQ=y CONFIG_SYS_LITTLE_ENDIAN=y CONFIG_MIPS_BOOT_FDT=y @@ -16,7 +16,7 @@ CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200" CONFIG_LOGLEVEL=7 CONFIG_DISPLAY_CPUINFO=y -CONFIG_SYS_PROMPT="pcb091 # " +CONFIG_SYS_PROMPT="luton # " # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_ELF is not set @@ -39,6 +39,9 @@ CONFIG_MTDIDS_DEFAULT="nor0=spi_flash" CONFIG_MTDPARTS_DEFAULT="mtdparts=spi_flash:512k(UBoot),256k(Env),256k(conf),6m@1m(linux)" # CONFIG_ISO_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="luton_pcb091" +CONFIG_OF_LIST="luton_pcb090 luton_pcb091" +CONFIG_DTB_RESELECT=y +CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_CLK=y diff --git a/include/configs/vcoreiii.h b/include/configs/vcoreiii.h index df89cdaebf..4ea5f40ec5 100644 --- a/include/configs/vcoreiii.h +++ b/include/configs/vcoreiii.h @@ -22,6 +22,8 @@ #endif #define CONFIG_SYS_NS16550_CLK CONFIG_SYS_MIPS_TIMER_FREQ

+#define CONFIG_BOARD_TYPES + #if defined(CONFIG_ENV_IS_IN_SPI_FLASH) && !defined(CONFIG_ENV_OFFSET) #define CONFIG_ENV_OFFSET (1024 * 1024) #define CONFIG_ENV_SIZE (256 * 1024)

-- 2.19.2

Lars Povlsen

1:42 p.m.

New subject: [U-Boot] [PATCH 6/6] mips: ocelot: Add multi-dtb support

This add single-binary support for the two MSCC ocelot-based reference boards - pcb120 and pcb123.

The PHY ids on specific ports are used to determine the board type.

Signed-off-by: Lars Povlsen lars.povlsen@microchip.com --- arch/mips/dts/Makefile | 1 + board/mscc/ocelot/ocelot.c | 52 +++++++++++++++++++++--- configs/mscc_ocelot_defconfig | 7 ++-- configs/mscc_ocelot_pcb120_defconfig | 60 ---------------------------- 4 files changed, 51 insertions(+), 69 deletions(-) delete mode 100644 configs/mscc_ocelot_pcb120_defconfig

diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile index 3d436b2248..b61afe6504 100644 --- a/arch/mips/dts/Makefile +++ b/arch/mips/dts/Makefile @@ -18,6 +18,7 @@ dtb-$(CONFIG_BOARD_SAGEM_FAST1704) += sagem,f@st1704.dtb dtb-$(CONFIG_BOARD_TPLINK_WDR4300) += tplink_wdr4300.dtb dtb-$(CONFIG_TARGET_JZ4780_CI20) += ci20.dtb dtb-$(CONFIG_SOC_LUTON) += luton_pcb090.dtb luton_pcb091.dtb +dtb-$(CONFIG_SOC_OCELOT) += ocelot_pcb120.dtb ocelot_pcb123.dtb

targets += $(dtb-y)

diff --git a/board/mscc/ocelot/ocelot.c b/board/mscc/ocelot/ocelot.c index d521a61957..a557cacd1b 100644 --- a/board/mscc/ocelot/ocelot.c +++ b/board/mscc/ocelot/ocelot.c @@ -12,16 +12,18 @@

DECLARE_GLOBAL_DATA_PTR;

-#define MSCC_GPIO_ALT0 0x54 -#define MSCC_GPIO_ALT1 0x58 +enum { + BOARD_TYPE_PCB120 = 0xAABBCC00, + BOARD_TYPE_PCB123, +};

void external_cs_manage(struct udevice *dev, bool enable) { u32 cs = spi_chip_select(dev); /* IF_SI0_OWNER, select the owner of the SI interface * Encoding: 0: SI Slave - * 1: SI Boot Master - * 2: SI Master Controller + * 1: SI Boot Master + * 2: SI Master Controller */ if (!enable) { writel(ICPU_SW_MODE_SW_PIN_CTRL_MODE | @@ -40,8 +42,8 @@ void external_cs_manage(struct udevice *dev, bool enable) void board_debug_uart_init(void) { /* too early for the pinctrl driver, so configure the UART pins here */ - setbits_le32(BASE_DEVCPU_GCB + MSCC_GPIO_ALT0, BIT(6) | BIT(7)); - clrbits_le32(BASE_DEVCPU_GCB + MSCC_GPIO_ALT1, BIT(6) | BIT(7)); + mscc_gpio_set_alternate(6, 1); + mscc_gpio_set_alternate(7, 1); }

int board_early_init_r(void) @@ -56,3 +58,41 @@ int board_early_init_r(void) gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE; return 0; } + +static void do_board_detect(void) +{ + u16 dummy = 0; + + /* Enable MIIM */ + mscc_gpio_set_alternate(14, 1); + mscc_gpio_set_alternate(15, 1); + if (mscc_phy_rd(1, 0, 0, &dummy) == 0) + gd->board_type = BOARD_TYPE_PCB120; + else + gd->board_type = BOARD_TYPE_PCB123; +} + +#if defined(CONFIG_MULTI_DTB_FIT) +int board_fit_config_name_match(const char *name) +{ + if (gd->board_type == BOARD_TYPE_PCB120 && + strcmp(name, "ocelot_pcb120") == 0) + return 0; + + if (gd->board_type == BOARD_TYPE_PCB123 && + strcmp(name, "ocelot_pcb123") == 0) + return 0; + + return -1; +} +#endif + +#if defined(CONFIG_DTB_RESELECT) +int embedded_dtb_select(void) +{ + do_board_detect(); + fdtdec_setup(); + + return 0; +} +#endif diff --git a/configs/mscc_ocelot_defconfig b/configs/mscc_ocelot_defconfig index 5fa74db2ff..66451000d9 100644 --- a/configs/mscc_ocelot_defconfig +++ b/configs/mscc_ocelot_defconfig @@ -5,7 +5,6 @@ CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0x70100000 CONFIG_DEBUG_UART_CLOCK=250000000 CONFIG_ARCH_MSCC=y -CONFIG_TARGET_OCELOT_PCB123=y CONFIG_SYS_LITTLE_ENDIAN=y CONFIG_DEBUG_UART=y CONFIG_FIT=y @@ -14,7 +13,7 @@ CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200" CONFIG_LOGLEVEL=7 CONFIG_DISPLAY_CPUINFO=y -CONFIG_SYS_PROMPT="pcb123 # " +CONFIG_SYS_PROMPT="ocelot # " # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_ELF is not set @@ -40,6 +39,9 @@ CONFIG_CMD_UBI=y # CONFIG_CMD_UBIFS is not set # CONFIG_ISO_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="ocelot_pcb123" +CONFIG_OF_LIST="ocelot_pcb120 ocelot_pcb123" +CONFIG_DTB_RESELECT=y +CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_CLK=y @@ -63,5 +65,4 @@ CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y -CONFIG_DESIGNWARE_SPI=y CONFIG_LZMA=y diff --git a/configs/mscc_ocelot_pcb120_defconfig b/configs/mscc_ocelot_pcb120_defconfig deleted file mode 100644 index c5a9f96977..0000000000 --- a/configs/mscc_ocelot_pcb120_defconfig +++ /dev/null @@ -1,60 +0,0 @@ -CONFIG_MIPS=y -CONFIG_SYS_TEXT_BASE=0x40000000 -CONFIG_SYS_MALLOC_F_LEN=0x2000 -CONFIG_ARCH_MSCC=y -CONFIG_SYS_LITTLE_ENDIAN=y -CONFIG_FIT=y -CONFIG_BOOTDELAY=3 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttyS0,115200" -CONFIG_LOGLEVEL=7 -CONFIG_DISPLAY_CPUINFO=y -CONFIG_SYS_PROMPT="pcb120 # " -# CONFIG_CMD_BDI is not set -# CONFIG_CMD_CONSOLE is not set -# CONFIG_CMD_ELF is not set -# CONFIG_CMD_EXPORTENV is not set -# CONFIG_CMD_IMPORTENV is not set -# CONFIG_CMD_CRC32 is not set -CONFIG_CMD_MD5SUM=y -CONFIG_CMD_MEMINFO=y -CONFIG_CMD_MEMTEST=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_GPIO=y -CONFIG_CMD_MTD=y -CONFIG_CMD_SF=y -CONFIG_CMD_SPI=y -CONFIG_CMD_DHCP=y -# CONFIG_NET_TFTP_VARS is not set -# CONFIG_CMD_NFS is not set -CONFIG_CMD_PING=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nor0=spi_flash" -CONFIG_MTDPARTS_DEFAULT="mtdparts=spi_flash:512k(UBoot),256k(Env),256k(conf),15m(linux),15m(linux.bk)" -CONFIG_CMD_UBI=y -# CONFIG_CMD_UBIFS is not set -# CONFIG_ISO_PARTITION is not set -CONFIG_DEFAULT_DEVICE_TREE="ocelot_pcb120" -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_CLK=y -CONFIG_DM_GPIO=y -CONFIG_MTD=y -CONFIG_MTD_SPI_NAND=y -CONFIG_DM_SPI_FLASH=y -CONFIG_SPI_FLASH=y -CONFIG_SPI_FLASH_BAR=y -CONFIG_SPI_FLASH_GIGADEVICE=y -CONFIG_SPI_FLASH_MACRONIX=y -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_SPI_FLASH_WINBOND=y -CONFIG_SPI_FLASH_MTD=y -CONFIG_DM_ETH=y -CONFIG_PINCTRL=y -CONFIG_PINCONF=y -CONFIG_DM_SERIAL=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_DESIGNWARE_SPI=y -CONFIG_LZMA=y

-- 2.19.2

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Daniel Schwierzeck
Lars Povlsen
Lars.Povlsen＠microchip.com