[U-Boot] [PATCH v6 00/15] Add Support for eMMC in Am65x-evm
Add Support for eMMC in TI's AM65x-evm. The series starts by syncing the sdhci0 node from the kernel. Then it adds APIs and changes to the driver required for handling the driver's integrated phy. The current maximum supported speed is DDR52. Higher speeds and tuning support will be added in a subsequent series.
Changes in v6: 1. Squashed one more dependency for clk_200mhz from Andreas's patches[1] into patch 1. Patches now build without any help from the other series.
2. Improved line wrapping in patch 8.
Changes in v5: Patches were tested with Andreas's system firmware patches[1] but can now be independently merged cleanly on latest U-boot.
Changes in v4: 1. Dropped the patch including regmap_read_poll_timeout() because that support was already added by someone else 2. Fixed a NULL pointer exception in patch 8. 3. Rebased on top of latest master 4. Added extra patches to support GPT partitions in user partition 5. Added Support for environment in eMMC by default
Changes in v3: Patch 9: Got rid of variable ret
Changes in v2: Patch 9: Fixed return value Patch 12: Fixed spacing
[1] https://www.mail-archive.com/u-boot@lists.denx.de/msg325811.html
Faiz Abbas (15): arm64: dts: k3: Sync sdhci0 node from kernel and change driver name mmc: am654_sdhci: Remove quirks regmap: Add API regmap_init_mem_index() mmc: sdhci: Add support for sdhci-caps-mask mmc: sdhci: Make sdhci_set_clock() non static arm: dts: k3: Add phy specific properties to SD card node mmc: sdhci: Make set_ios_post() return int mmc: am654_sdhci: Add Support for PHY configs: am65x_evm: Enable CONFIG_REGMAP mmc: am654_sdhci: Use f_max in mmc_config mmc: sdhci: Add support for HOST_CONTROL2 and setting UHS timings mmc: am654_sdhci: Add a platform specific set_control_reg() callback configs: am65x: Add configs to support environment in eMMC am65x_evm: Add Support for creating a filesystem GPT partition in eMMC configs: am65x_evm_a53: Add Support for creating GPT partitions
arch/arm/dts/k3-am65-main.dtsi | 22 ++ arch/arm/dts/k3-am654-base-board-u-boot.dtsi | 30 +- arch/arm/dts/k3-am654-base-board.dts | 28 ++ arch/arm/dts/k3-am654-r5-base-board.dts | 38 +++ configs/am65x_evm_a53_defconfig | 11 +- configs/am65x_evm_r5_defconfig | 4 +- drivers/core/regmap.c | 42 +++ drivers/mmc/Kconfig | 9 +- drivers/mmc/Makefile | 2 +- drivers/mmc/am654_sdhci.c | 333 +++++++++++++++++++ drivers/mmc/k3_arsan_sdhci.c | 109 ------ drivers/mmc/sdhci.c | 47 ++- drivers/mmc/xenon_sdhci.c | 4 +- drivers/mmc/zynq_sdhci.c | 31 +- include/configs/am65x_evm.h | 19 +- include/regmap.h | 2 + include/sdhci.h | 22 +- 17 files changed, 568 insertions(+), 185 deletions(-) create mode 100644 drivers/mmc/am654_sdhci.c delete mode 100644 drivers/mmc/k3_arsan_sdhci.c
Sync the sdhci0 node from kernel. This changes the compatible that is required to be there in the driver. Change the same for the SD card node which is not yet supported in kernel. This also syncs the main_pmx0 node as a side effect.
Also change the name of the driver to match the compatible in kernel.
Signed-off-by: Faiz Abbas faiz_abbas@ti.com Reviewed-by: Tom Rini trini@konsulko.com --- arch/arm/dts/k3-am65-main.dtsi | 22 +++++++++++ arch/arm/dts/k3-am654-base-board-u-boot.dtsi | 27 ++------------ arch/arm/dts/k3-am654-base-board.dts | 28 ++++++++++++++ arch/arm/dts/k3-am654-r5-base-board.dts | 37 +++++++++++++++++++ configs/am65x_evm_a53_defconfig | 2 +- configs/am65x_evm_r5_defconfig | 2 +- drivers/mmc/Kconfig | 8 ++-- drivers/mmc/Makefile | 2 +- .../mmc/{k3_arsan_sdhci.c => am654_sdhci.c} | 36 +++++++++--------- 9 files changed, 115 insertions(+), 49 deletions(-) rename drivers/mmc/{k3_arsan_sdhci.c => am654_sdhci.c} (67%)
diff --git a/arch/arm/dts/k3-am65-main.dtsi b/arch/arm/dts/k3-am65-main.dtsi index adcd6341e4..84fed12fbd 100644 --- a/arch/arm/dts/k3-am65-main.dtsi +++ b/arch/arm/dts/k3-am65-main.dtsi @@ -69,4 +69,26 @@ clock-frequency = <48000000>; current-speed = <115200>; }; + + main_pmx0: pinmux@11c000 { + compatible = "pinctrl-single"; + reg = <0x0 0x11c000 0x0 0x2e4>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + }; + + sdhci0: sdhci@4f80000 { + compatible = "ti,am654-sdhci-5.1"; + reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>; + power-domains = <&k3_pds 47>; + clocks = <&k3_clks 47 0>, <&k3_clks 47 1>; + clock-names = "clk_ahb", "clk_xin"; + interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + ti,otap-del-sel = <0x2>; + ti,trm-icp = <0x8>; + dma-coherent; + }; }; diff --git a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi index f5c8253831..589a90f9f9 100644 --- a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi +++ b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi @@ -19,14 +19,6 @@ &cbass_main{ u-boot,dm-spl;
- main_pmx0: pinmux@11c000 { - compatible = "pinctrl-single"; - reg = <0x0 0x11c000 0x0 0x2e4>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0xffffffff>; - }; - main_pmx1: pinmux@11c2e8 { compatible = "pinctrl-single"; reg = <0x0 0x11c2e8 0x0 0x24>; @@ -35,17 +27,8 @@ pinctrl-single,function-mask = <0xffffffff>; };
- sdhci0: sdhci@04F80000 { - compatible = "arasan,sdhci-5.1"; - reg = <0x0 0x4F80000 0x0 0x1000>, - <0x0 0x4F90000 0x0 0x400>; - clocks = <&k3_clks 47 1>; - power-domains = <&k3_pds 47>; - max-frequency = <25000000>; - }; - sdhci1: sdhci@04FA0000 { - compatible = "arasan,sdhci-5.1"; + compatible = "ti,am654-sdhci-5.1"; reg = <0x0 0x4FA0000 0x0 0x1000>, <0x0 0x4FB0000 0x0 0x400>; clocks = <&k3_clks 48 1>; @@ -164,7 +147,8 @@ AM65X_IOPAD(0x0190, PIN_INPUT_PULLUP, 0) /* (A24) MMC0_DAT5 */ AM65X_IOPAD(0x018c, PIN_INPUT_PULLUP, 0) /* (B26) MMC0_DAT6 */ AM65X_IOPAD(0x0188, PIN_INPUT_PULLUP, 0) /* (D25) MMC0_DAT7 */ - AM65X_IOPAD(0x01b0, PIN_INPUT, 0) /* (C25) MMC0_DS */ + AM65X_IOPAD(0x01b4, PIN_INPUT_PULLUP, 0) /* (A23) MMC0_SDCD */ + AM65X_IOPAD(0x01b0, PIN_INPUT, 0) /* (C25) MMC0_DS */ >; u-boot,dm-spl; }; @@ -198,11 +182,6 @@
&sdhci0 { u-boot,dm-spl; - status = "okay"; - non-removable; - bus-width = <8>; - pinctrl-names = "default"; - pinctrl-0 = <&main_mmc0_pins_default>; };
&sdhci1 { diff --git a/arch/arm/dts/k3-am654-base-board.dts b/arch/arm/dts/k3-am654-base-board.dts index af6956fdc1..ab233916c6 100644 --- a/arch/arm/dts/k3-am654-base-board.dts +++ b/arch/arm/dts/k3-am654-base-board.dts @@ -6,6 +6,7 @@ /dts-v1/;
#include "k3-am654.dtsi" +#include <dt-bindings/pinctrl/k3.h>
/ { compatible = "ti,am654-evm", "ti,am654"; @@ -34,3 +35,30 @@ }; }; }; + +&main_pmx0 { + main_mmc0_pins_default: main_mmc0_pins_default { + pinctrl-single,pins = < + AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /* (B25) MMC0_CLK */ + AM65X_IOPAD(0x01aC, PIN_INPUT_PULLUP, 0) /* (B27) MMC0_CMD */ + AM65X_IOPAD(0x01a4, PIN_INPUT_PULLUP, 0) /* (A26) MMC0_DAT0 */ + AM65X_IOPAD(0x01a0, PIN_INPUT_PULLUP, 0) /* (E25) MMC0_DAT1 */ + AM65X_IOPAD(0x019c, PIN_INPUT_PULLUP, 0) /* (C26) MMC0_DAT2 */ + AM65X_IOPAD(0x0198, PIN_INPUT_PULLUP, 0) /* (A25) MMC0_DAT3 */ + AM65X_IOPAD(0x0194, PIN_INPUT_PULLUP, 0) /* (E24) MMC0_DAT4 */ + AM65X_IOPAD(0x0190, PIN_INPUT_PULLUP, 0) /* (A24) MMC0_DAT5 */ + AM65X_IOPAD(0x018c, PIN_INPUT_PULLUP, 0) /* (B26) MMC0_DAT6 */ + AM65X_IOPAD(0x0188, PIN_INPUT_PULLUP, 0) /* (D25) MMC0_DAT7 */ + AM65X_IOPAD(0x01b4, PIN_INPUT_PULLUP, 0) /* (A23) MMC0_SDCD */ + AM65X_IOPAD(0x01b0, PIN_INPUT, 0) /* (C25) MMC0_DS */ + >; + }; +}; + +&sdhci0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_mmc0_pins_default>; + bus-width = <8>; + non-removable; + ti,driver-strength-ohm = <50>; +}; diff --git a/arch/arm/dts/k3-am654-r5-base-board.dts b/arch/arm/dts/k3-am654-r5-base-board.dts index a07038be70..768141cf6f 100644 --- a/arch/arm/dts/k3-am654-r5-base-board.dts +++ b/arch/arm/dts/k3-am654-r5-base-board.dts @@ -96,6 +96,12 @@ u-boot,dm-spl; };
+ clk_200mhz: dummy_clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + u-boot,dm-spl; + }; };
&dmsc { @@ -132,8 +138,39 @@ }; };
+&main_pmx0 { + u-boot,dm-spl; + main_mmc0_pins_default: main_mmc0_pins_default { + pinctrl-single,pins = < + AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /* (B25) MMC0_CLK */ + AM65X_IOPAD(0x01aC, PIN_INPUT_PULLUP, 0) /* (B27) MMC0_CMD */ + AM65X_IOPAD(0x01a4, PIN_INPUT_PULLUP, 0) /* (A26) MMC0_DAT0 */ + AM65X_IOPAD(0x01a0, PIN_INPUT_PULLUP, 0) /* (E25) MMC0_DAT1 */ + AM65X_IOPAD(0x019c, PIN_INPUT_PULLUP, 0) /* (C26) MMC0_DAT2 */ + AM65X_IOPAD(0x0198, PIN_INPUT_PULLUP, 0) /* (A25) MMC0_DAT3 */ + AM65X_IOPAD(0x0194, PIN_INPUT_PULLUP, 0) /* (E24) MMC0_DAT4 */ + AM65X_IOPAD(0x0190, PIN_INPUT_PULLUP, 0) /* (A24) MMC0_DAT5 */ + AM65X_IOPAD(0x018c, PIN_INPUT_PULLUP, 0) /* (B26) MMC0_DAT6 */ + AM65X_IOPAD(0x0188, PIN_INPUT_PULLUP, 0) /* (D25) MMC0_DAT7 */ + AM65X_IOPAD(0x01b0, PIN_INPUT, 0) /* (C25) MMC0_DS */ + >; + }; +}; + &memorycontroller { vtt-supply = <&vtt_supply>; pinctrl-names = "default"; pinctrl-0 = <&wkup_vtt_pins_default>; }; + +&sdhci0 { + clock-names = "clk_xin"; + clocks = <&clk_200mhz>; + /delete-property/ power-domains; +}; + +&sdhci1 { + clock-names = "clk_xin"; + clocks = <&clk_200mhz>; + /delete-property/ power-domains; +}; diff --git a/configs/am65x_evm_a53_defconfig b/configs/am65x_evm_a53_defconfig index 41cf0100fa..ff41d66e4d 100644 --- a/configs/am65x_evm_a53_defconfig +++ b/configs/am65x_evm_a53_defconfig @@ -57,7 +57,7 @@ CONFIG_DM_MAILBOX=y CONFIG_K3_SEC_PROXY=y CONFIG_DM_MMC=y CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_K3_ARASAN=y +CONFIG_MMC_SDHCI_AM654=y CONFIG_PINCTRL=y # CONFIG_PINCTRL_GENERIC is not set CONFIG_SPL_PINCTRL=y diff --git a/configs/am65x_evm_r5_defconfig b/configs/am65x_evm_r5_defconfig index 3814872ec7..6d7ba4d77c 100644 --- a/configs/am65x_evm_r5_defconfig +++ b/configs/am65x_evm_r5_defconfig @@ -63,7 +63,7 @@ CONFIG_K3_SEC_PROXY=y CONFIG_MISC=y CONFIG_DM_MMC=y CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_K3_ARASAN=y +CONFIG_MMC_SDHCI_AM654=y CONFIG_PINCTRL=y # CONFIG_PINCTRL_GENERIC is not set CONFIG_SPL_PINCTRL=y diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index c23299ea96..0062ad1bb9 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -453,14 +453,14 @@ config MMC_SDHCI_CADENCE
If unsure, say N.
-config MMC_SDHCI_K3_ARASAN - bool "Arasan SDHCI controller for TI's K3 based SoCs" +config MMC_SDHCI_AM654 + bool "SDHCI Controller on TI's Am654 devices" depends on ARCH_K3 depends on MMC_SDHCI depends on DM_MMC && OF_CONTROL && BLK help - Support for Arasan SDHCI host controller on Texas Instruments' - K3 family based SoC platforms + Support for Secure Digital Host Controller Interface (SDHCI) + controllers present on TI's AM654 SOCs.
config MMC_SDHCI_KONA bool "SDHCI support on Broadcom KONA platform" diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index 0076fc393b..d02138b566 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -49,7 +49,7 @@ obj-$(CONFIG_MMC_SDHCI_ATMEL) += atmel_sdhci.o obj-$(CONFIG_MMC_SDHCI_BCM2835) += bcm2835_sdhci.o obj-$(CONFIG_MMC_SDHCI_BCMSTB) += bcmstb_sdhci.o obj-$(CONFIG_MMC_SDHCI_CADENCE) += sdhci-cadence.o -obj-$(CONFIG_MMC_SDHCI_K3_ARASAN) += k3_arsan_sdhci.o +obj-$(CONFIG_MMC_SDHCI_AM654) += am654_sdhci.o obj-$(CONFIG_MMC_SDHCI_KONA) += kona_sdhci.o obj-$(CONFIG_MMC_SDHCI_MSM) += msm_sdhci.o obj-$(CONFIG_MMC_SDHCI_MV) += mv_sdhci.o diff --git a/drivers/mmc/k3_arsan_sdhci.c b/drivers/mmc/am654_sdhci.c similarity index 67% rename from drivers/mmc/k3_arsan_sdhci.c rename to drivers/mmc/am654_sdhci.c index d5f2857382..2d08fe3347 100644 --- a/drivers/mmc/k3_arsan_sdhci.c +++ b/drivers/mmc/am654_sdhci.c @@ -12,17 +12,17 @@ #include <power-domain.h> #include <sdhci.h>
-#define K3_ARASAN_SDHCI_MIN_FREQ 0 +#define AM654_SDHCI_MIN_FREQ 400000
-struct k3_arasan_sdhci_plat { +struct am654_sdhci_plat { struct mmc_config cfg; struct mmc mmc; unsigned int f_max; };
-static int k3_arasan_sdhci_probe(struct udevice *dev) +static int am654_sdhci_probe(struct udevice *dev) { - struct k3_arasan_sdhci_plat *plat = dev_get_platdata(dev); + struct am654_sdhci_plat *plat = dev_get_platdata(dev); struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); struct sdhci_host *host = dev_get_priv(dev); struct power_domain sdhci_pwrdmn; @@ -60,7 +60,7 @@ static int k3_arasan_sdhci_probe(struct udevice *dev) host->max_clk = clock;
ret = sdhci_setup_cfg(&plat->cfg, host, plat->f_max, - K3_ARASAN_SDHCI_MIN_FREQ); + AM654_SDHCI_MIN_FREQ); host->mmc = &plat->mmc; if (ret) return ret; @@ -71,9 +71,9 @@ static int k3_arasan_sdhci_probe(struct udevice *dev) return sdhci_probe(dev); }
-static int k3_arasan_sdhci_ofdata_to_platdata(struct udevice *dev) +static int am654_sdhci_ofdata_to_platdata(struct udevice *dev) { - struct k3_arasan_sdhci_plat *plat = dev_get_platdata(dev); + struct am654_sdhci_plat *plat = dev_get_platdata(dev); struct sdhci_host *host = dev_get_priv(dev);
host->name = dev->name; @@ -84,26 +84,26 @@ static int k3_arasan_sdhci_ofdata_to_platdata(struct udevice *dev) return 0; }
-static int k3_arasan_sdhci_bind(struct udevice *dev) +static int am654_sdhci_bind(struct udevice *dev) { - struct k3_arasan_sdhci_plat *plat = dev_get_platdata(dev); + struct am654_sdhci_plat *plat = dev_get_platdata(dev);
return sdhci_bind(dev, &plat->mmc, &plat->cfg); }
-static const struct udevice_id k3_arasan_sdhci_ids[] = { - { .compatible = "arasan,sdhci-5.1" }, +static const struct udevice_id am654_sdhci_ids[] = { + { .compatible = "ti,am654-sdhci-5.1" }, { } };
-U_BOOT_DRIVER(k3_arasan_sdhci_drv) = { - .name = "k3_arasan_sdhci", +U_BOOT_DRIVER(am654_sdhci_drv) = { + .name = "am654_sdhci", .id = UCLASS_MMC, - .of_match = k3_arasan_sdhci_ids, - .ofdata_to_platdata = k3_arasan_sdhci_ofdata_to_platdata, + .of_match = am654_sdhci_ids, + .ofdata_to_platdata = am654_sdhci_ofdata_to_platdata, .ops = &sdhci_ops, - .bind = k3_arasan_sdhci_bind, - .probe = k3_arasan_sdhci_probe, + .bind = am654_sdhci_bind, + .probe = am654_sdhci_probe, .priv_auto_alloc_size = sizeof(struct sdhci_host), - .platdata_auto_alloc_size = sizeof(struct k3_arasan_sdhci_plat), + .platdata_auto_alloc_size = sizeof(struct am654_sdhci_plat), };
The host controller works perfectly well without having to add any quirks. Remove them.
Signed-off-by: Faiz Abbas faiz_abbas@ti.com Reviewed-by: Tom Rini trini@konsulko.com --- drivers/mmc/am654_sdhci.c | 3 --- 1 file changed, 3 deletions(-)
diff --git a/drivers/mmc/am654_sdhci.c b/drivers/mmc/am654_sdhci.c index 2d08fe3347..a8c92277f7 100644 --- a/drivers/mmc/am654_sdhci.c +++ b/drivers/mmc/am654_sdhci.c @@ -54,9 +54,6 @@ static int am654_sdhci_probe(struct udevice *dev) return clock; }
- host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD | - SDHCI_QUIRK_BROKEN_R1B; - host->max_clk = clock;
ret = sdhci_setup_cfg(&plat->cfg, host, plat->f_max,
In device nodes with more than one entry in the reg property, it is sometimes useful to regmap only of the entries. Add an API regmap_init_mem_index() to facilitate this.
Signed-off-by: Faiz Abbas faiz_abbas@ti.com Reviewed-by: Tom Rini trini@konsulko.com --- drivers/core/regmap.c | 42 ++++++++++++++++++++++++++++++++++++++++++ include/regmap.h | 2 ++ 2 files changed, 44 insertions(+)
diff --git a/drivers/core/regmap.c b/drivers/core/regmap.c index 5ef0f71c8b..d1d12eef38 100644 --- a/drivers/core/regmap.c +++ b/drivers/core/regmap.c @@ -108,6 +108,48 @@ static int init_range(ofnode node, struct regmap_range *range, int addr_len, return 0; }
+int regmap_init_mem_index(ofnode node, struct regmap **mapp, int index) +{ + struct regmap *map; + int addr_len, size_len; + int ret; + + addr_len = ofnode_read_simple_addr_cells(ofnode_get_parent(node)); + if (addr_len < 0) { + debug("%s: Error while reading the addr length (ret = %d)\n", + ofnode_get_name(node), addr_len); + return addr_len; + } + + size_len = ofnode_read_simple_size_cells(ofnode_get_parent(node)); + if (size_len < 0) { + debug("%s: Error while reading the size length: (ret = %d)\n", + ofnode_get_name(node), size_len); + return size_len; + } + + map = regmap_alloc(1); + if (!map) + return -ENOMEM; + + ret = init_range(node, map->ranges, addr_len, size_len, index); + if (ret) + return ret; + + if (ofnode_read_bool(node, "little-endian")) + map->endianness = REGMAP_LITTLE_ENDIAN; + else if (ofnode_read_bool(node, "big-endian")) + map->endianness = REGMAP_BIG_ENDIAN; + else if (ofnode_read_bool(node, "native-endian")) + map->endianness = REGMAP_NATIVE_ENDIAN; + else /* Default: native endianness */ + map->endianness = REGMAP_NATIVE_ENDIAN; + + *mapp = map; + + return ret; +} + int regmap_init_mem(ofnode node, struct regmap **mapp) { struct regmap_range *range; diff --git a/include/regmap.h b/include/regmap.h index 3cd7a66cea..0854200a9c 100644 --- a/include/regmap.h +++ b/include/regmap.h @@ -330,6 +330,8 @@ int regmap_init_mem(ofnode node, struct regmap **mapp); int regmap_init_mem_platdata(struct udevice *dev, fdt_val_t *reg, int count, struct regmap **mapp);
+int regmap_init_mem_index(ofnode node, struct regmap **mapp, int index); + /** * regmap_get_range() - Obtain the base memory address of a regmap range *
Add Support for masking some bits in the capabilities register of a host controller.
Also remove the redundant readl() into caps1.
Signed-off-by: Faiz Abbas faiz_abbas@ti.com Reviewed-by: Tom Rini trini@konsulko.com --- drivers/mmc/sdhci.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-)
diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c index e2bb90abbd..fa6bb0a944 100644 --- a/drivers/mmc/sdhci.c +++ b/drivers/mmc/sdhci.c @@ -8,6 +8,7 @@ */
#include <common.h> +#include <dm.h> #include <errno.h> #include <malloc.h> #include <mmc.h> @@ -643,8 +644,15 @@ int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host, u32 f_max, u32 f_min) { u32 caps, caps_1 = 0; + u32 mask[2] = {0}; + int ret; + + ret = dev_read_u32_array(host->mmc->dev, "sdhci-caps-mask", + mask, 2); + if (ret && ret != -1) + return ret;
- caps = sdhci_readl(host, SDHCI_CAPABILITIES); + caps = ~mask[1] & sdhci_readl(host, SDHCI_CAPABILITIES);
#ifdef CONFIG_MMC_SDHCI_SDMA if (!(caps & SDHCI_CAN_DO_SDMA)) { @@ -684,7 +692,7 @@ int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host,
/* Check whether the clock multiplier is supported or not */ if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) { - caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1); + caps_1 = ~mask[0] & sdhci_readl(host, SDHCI_CAPABILITIES_1); host->clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >> SDHCI_CLOCK_MUL_SHIFT; } @@ -741,9 +749,6 @@ int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host, cfg->host_caps &= ~MMC_MODE_HS_52MHz; }
- if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) - caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1); - if (!(cfg->voltages & MMC_VDD_165_195) || (host->quirks & SDHCI_QUIRK_NO_1_8_V)) caps_1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
The am654_sdhci driver needs to switch the clock off before disabling its phy dll and needs to re-enable the clock before enabling the phy again.
Therefore, make the sdhci_set_clock() function accessible in the am654_sdhci driver.
Signed-off-by: Faiz Abbas faiz_abbas@ti.com Reviewed-by: Tom Rini trini@konsulko.com --- drivers/mmc/sdhci.c | 2 +- include/sdhci.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c index fa6bb0a944..4646dbec9f 100644 --- a/drivers/mmc/sdhci.c +++ b/drivers/mmc/sdhci.c @@ -409,7 +409,7 @@ static int sdhci_execute_tuning(struct udevice *dev, uint opcode) return 0; } #endif -static int sdhci_set_clock(struct mmc *mmc, unsigned int clock) +int sdhci_set_clock(struct mmc *mmc, unsigned int clock) { struct sdhci_host *host = mmc->priv; unsigned int div, clk = 0, timeout; diff --git a/include/sdhci.h b/include/sdhci.h index eee493ab5f..820cd16e92 100644 --- a/include/sdhci.h +++ b/include/sdhci.h @@ -470,6 +470,7 @@ int add_sdhci(struct sdhci_host *host, u32 f_max, u32 f_min); #ifdef CONFIG_DM_MMC /* Export the operations to drivers */ int sdhci_probe(struct udevice *dev); +int sdhci_set_clock(struct mmc *mmc, unsigned int clock); extern const struct dm_mmc_ops sdhci_ops; #else #endif
With changes in the driver requiring phy related properties, add the same for the SD card node to prevent breaking boot with the driver update.
Signed-off-by: Faiz Abbas faiz_abbas@ti.com Reviewed-by: Tom Rini trini@konsulko.com --- arch/arm/dts/k3-am654-base-board-u-boot.dtsi | 3 +++ arch/arm/dts/k3-am654-r5-base-board.dts | 1 + 2 files changed, 4 insertions(+)
diff --git a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi index 589a90f9f9..c43888f36d 100644 --- a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi +++ b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi @@ -34,6 +34,8 @@ clocks = <&k3_clks 48 1>; power-domains = <&k3_pds 48>; max-frequency = <25000000>; + ti,otap-del-sel = <0x2>; + ti,trm-icp = <0x8>; };
}; @@ -190,4 +192,5 @@ pinctrl-names = "default"; pinctrl-0 = <&main_mmc1_pins_default>; sdhci-caps-mask = <0x7 0x0>; + ti,driver-strength-ohm = <50>; }; diff --git a/arch/arm/dts/k3-am654-r5-base-board.dts b/arch/arm/dts/k3-am654-r5-base-board.dts index 768141cf6f..3fb877fe7c 100644 --- a/arch/arm/dts/k3-am654-r5-base-board.dts +++ b/arch/arm/dts/k3-am654-r5-base-board.dts @@ -173,4 +173,5 @@ clock-names = "clk_xin"; clocks = <&clk_200mhz>; /delete-property/ power-domains; + ti,driver-strength-ohm = <50>; };
Make set_ios_post() return int to faciliate error handling in platform drivers.
Signed-off-by: Faiz Abbas faiz_abbas@ti.com --- drivers/mmc/sdhci.c | 2 +- drivers/mmc/xenon_sdhci.c | 4 +++- include/sdhci.h | 2 +- 3 files changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c index 4646dbec9f..75e6567631 100644 --- a/drivers/mmc/sdhci.c +++ b/drivers/mmc/sdhci.c @@ -583,7 +583,7 @@ static int sdhci_set_ios(struct mmc *mmc)
/* If available, call the driver specific "post" set_ios() function */ if (host->ops && host->ops->set_ios_post) - host->ops->set_ios_post(host); + return host->ops->set_ios_post(host);
return 0; } diff --git a/drivers/mmc/xenon_sdhci.c b/drivers/mmc/xenon_sdhci.c index b576511338..829b75683b 100644 --- a/drivers/mmc/xenon_sdhci.c +++ b/drivers/mmc/xenon_sdhci.c @@ -326,7 +326,7 @@ static void xenon_mask_cmd_conflict_err(struct sdhci_host *host) }
/* Platform specific function for post set_ios configuration */ -static void xenon_sdhci_set_ios_post(struct sdhci_host *host) +static int xenon_sdhci_set_ios_post(struct sdhci_host *host) { struct xenon_sdhci_priv *priv = host->mmc->priv; uint speed = host->mmc->tran_speed; @@ -364,6 +364,8 @@ static void xenon_sdhci_set_ios_post(struct sdhci_host *host)
/* Re-init the PHY */ xenon_mmc_phy_set(host); + + return 0; }
/* Install a driver specific handler for post set_ios configuration */ diff --git a/include/sdhci.h b/include/sdhci.h index 820cd16e92..3dcbc14965 100644 --- a/include/sdhci.h +++ b/include/sdhci.h @@ -247,7 +247,7 @@ struct sdhci_ops { #endif int (*get_cd)(struct sdhci_host *host); void (*set_control_reg)(struct sdhci_host *host); - void (*set_ios_post)(struct sdhci_host *host); + int (*set_ios_post)(struct sdhci_host *host); void (*set_clock)(struct sdhci_host *host, u32 div); int (*platform_execute_tuning)(struct mmc *host, u8 opcode); void (*set_delay)(struct sdhci_host *host);
Add support in the driver for handling phy specific registers.
Signed-off-by: Faiz Abbas faiz_abbas@ti.com Reviewed-by: Tom Rini trini@konsulko.com --- drivers/mmc/Kconfig | 1 + drivers/mmc/am654_sdhci.c | 223 +++++++++++++++++++++++++++++++++++++- 2 files changed, 218 insertions(+), 6 deletions(-)
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index 0062ad1bb9..41e8a270d8 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -458,6 +458,7 @@ config MMC_SDHCI_AM654 depends on ARCH_K3 depends on MMC_SDHCI depends on DM_MMC && OF_CONTROL && BLK + depends on REGMAP help Support for Secure Digital Host Controller Interface (SDHCI) controllers present on TI's AM654 SOCs. diff --git a/drivers/mmc/am654_sdhci.c b/drivers/mmc/am654_sdhci.c index a8c92277f7..cd7ad03479 100644 --- a/drivers/mmc/am654_sdhci.c +++ b/drivers/mmc/am654_sdhci.c @@ -10,16 +10,184 @@ #include <dm.h> #include <malloc.h> #include <power-domain.h> +#include <regmap.h> #include <sdhci.h>
+/* CTL_CFG Registers */ +#define CTL_CFG_2 0x14 + +#define SLOTTYPE_MASK GENMASK(31, 30) +#define SLOTTYPE_EMBEDDED BIT(30) + +/* PHY Registers */ +#define PHY_CTRL1 0x100 +#define PHY_CTRL2 0x104 +#define PHY_CTRL3 0x108 +#define PHY_CTRL4 0x10C +#define PHY_CTRL5 0x110 +#define PHY_CTRL6 0x114 +#define PHY_STAT1 0x130 +#define PHY_STAT2 0x134 + +#define IOMUX_ENABLE_SHIFT 31 +#define IOMUX_ENABLE_MASK BIT(IOMUX_ENABLE_SHIFT) +#define OTAPDLYENA_SHIFT 20 +#define OTAPDLYENA_MASK BIT(OTAPDLYENA_SHIFT) +#define OTAPDLYSEL_SHIFT 12 +#define OTAPDLYSEL_MASK GENMASK(15, 12) +#define STRBSEL_SHIFT 24 +#define STRBSEL_MASK GENMASK(27, 24) +#define SEL50_SHIFT 8 +#define SEL50_MASK BIT(SEL50_SHIFT) +#define SEL100_SHIFT 9 +#define SEL100_MASK BIT(SEL100_SHIFT) +#define DLL_TRIM_ICP_SHIFT 4 +#define DLL_TRIM_ICP_MASK GENMASK(7, 4) +#define DR_TY_SHIFT 20 +#define DR_TY_MASK GENMASK(22, 20) +#define ENDLL_SHIFT 1 +#define ENDLL_MASK BIT(ENDLL_SHIFT) +#define DLLRDY_SHIFT 0 +#define DLLRDY_MASK BIT(DLLRDY_SHIFT) +#define PDB_SHIFT 0 +#define PDB_MASK BIT(PDB_SHIFT) +#define CALDONE_SHIFT 1 +#define CALDONE_MASK BIT(CALDONE_SHIFT) +#define RETRIM_SHIFT 17 +#define RETRIM_MASK BIT(RETRIM_SHIFT) + +#define DRIVER_STRENGTH_50_OHM 0x0 +#define DRIVER_STRENGTH_33_OHM 0x1 +#define DRIVER_STRENGTH_66_OHM 0x2 +#define DRIVER_STRENGTH_100_OHM 0x3 +#define DRIVER_STRENGTH_40_OHM 0x4 + #define AM654_SDHCI_MIN_FREQ 400000
struct am654_sdhci_plat { struct mmc_config cfg; struct mmc mmc; unsigned int f_max; + struct regmap *base; + bool non_removable; + u32 otap_del_sel; + u32 trm_icp; + u32 drv_strength; + bool dll_on; +}; + +static int am654_sdhci_set_ios_post(struct sdhci_host *host) +{ + struct udevice *dev = host->mmc->dev; + struct am654_sdhci_plat *plat = dev_get_platdata(dev); + unsigned int speed = host->mmc->clock; + int sel50, sel100; + u32 mask, val; + int ret; + + /* Reset SD Clock Enable */ + val = sdhci_readw(host, SDHCI_CLOCK_CONTROL); + val &= ~SDHCI_CLOCK_CARD_EN; + sdhci_writew(host, val, SDHCI_CLOCK_CONTROL); + + /* power off phy */ + if (plat->dll_on) { + regmap_update_bits(plat->base, PHY_CTRL1, ENDLL_MASK, 0); + + plat->dll_on = false; + } + + /* restart clock */ + sdhci_set_clock(host->mmc, speed); + + /* switch phy back on */ + if (speed > AM654_SDHCI_MIN_FREQ) { + mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; + val = (1 << OTAPDLYENA_SHIFT) | + (plat->otap_del_sel << OTAPDLYSEL_SHIFT); + regmap_update_bits(plat->base, PHY_CTRL4, mask, val); + switch (speed) { + case 200000000: + sel50 = 0; + sel100 = 0; + break; + case 100000000: + sel50 = 0; + sel100 = 1; + break; + default: + sel50 = 1; + sel100 = 0; + } + + /* Configure PHY DLL frequency */ + mask = SEL50_MASK | SEL100_MASK; + val = (sel50 << SEL50_SHIFT) | (sel100 << SEL100_SHIFT); + regmap_update_bits(plat->base, PHY_CTRL5, mask, val); + + /* Enable DLL */ + regmap_update_bits(plat->base, PHY_CTRL1, ENDLL_MASK, + 0x1 << ENDLL_SHIFT); + /* + * Poll for DLL ready. Use a one second timeout. + * Works in all experiments done so far + */ + ret = regmap_read_poll_timeout(plat->base, PHY_STAT1, val, + val & DLLRDY_MASK, 1000, 1000000); + if (ret) + return ret; + + plat->dll_on = true; + } + + return 0; +} + +const struct sdhci_ops am654_sdhci_ops = { + .set_ios_post = &am654_sdhci_set_ios_post, };
+int am654_sdhci_init(struct am654_sdhci_plat *plat) +{ + u32 ctl_cfg_2 = 0; + u32 mask, val; + int ret; + + /* Reset OTAP to default value */ + mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; + regmap_update_bits(plat->base, PHY_CTRL4, mask, 0x0); + + regmap_read(plat->base, PHY_STAT1, &val); + if (~val & CALDONE_MASK) { + /* Calibrate IO lines */ + regmap_update_bits(plat->base, PHY_CTRL1, PDB_MASK, PDB_MASK); + ret = regmap_read_poll_timeout(plat->base, PHY_STAT1, val, + val & CALDONE_MASK, 1, 20); + if (ret) + return ret; + } + + /* Configure DLL TRIM */ + mask = DLL_TRIM_ICP_MASK; + val = plat->trm_icp << DLL_TRIM_ICP_SHIFT; + + /* Configure DLL driver strength */ + mask |= DR_TY_MASK; + val |= plat->drv_strength << DR_TY_SHIFT; + regmap_update_bits(plat->base, PHY_CTRL1, mask, val); + + /* Enable pins by setting IO mux to 0 */ + regmap_update_bits(plat->base, PHY_CTRL1, IOMUX_ENABLE_MASK, 0); + + /* Set slot type based on SD or eMMC */ + if (plat->non_removable) + ctl_cfg_2 = SLOTTYPE_EMBEDDED; + + regmap_update_bits(plat->base, CTL_CFG_2, SLOTTYPE_MASK, ctl_cfg_2); + + return 0; +} + static int am654_sdhci_probe(struct udevice *dev) { struct am654_sdhci_plat *plat = dev_get_platdata(dev); @@ -55,16 +223,20 @@ static int am654_sdhci_probe(struct udevice *dev) }
host->max_clk = clock; - - ret = sdhci_setup_cfg(&plat->cfg, host, plat->f_max, - AM654_SDHCI_MIN_FREQ); host->mmc = &plat->mmc; + host->mmc->dev = dev; + ret = sdhci_setup_cfg(cfg, host, cfg->f_max, + AM654_SDHCI_MIN_FREQ); if (ret) return ret; + host->ops = &am654_sdhci_ops; host->mmc->priv = host; - host->mmc->dev = dev; upriv->mmc = host->mmc;
+ regmap_init_mem_index(dev_ofnode(dev), &plat->base, 1); + + am654_sdhci_init(plat); + return sdhci_probe(dev); }
@@ -72,11 +244,50 @@ static int am654_sdhci_ofdata_to_platdata(struct udevice *dev) { struct am654_sdhci_plat *plat = dev_get_platdata(dev); struct sdhci_host *host = dev_get_priv(dev); + struct mmc_config *cfg = &plat->cfg; + u32 drv_strength; + int ret;
host->name = dev->name; host->ioaddr = (void *)dev_read_addr(dev); - host->bus_width = dev_read_u32_default(dev, "bus-width", 4); - plat->f_max = dev_read_u32_default(dev, "max-frequency", 0); + plat->non_removable = dev_read_bool(dev, "non-removable"); + + ret = dev_read_u32(dev, "ti,trm-icp", &plat->trm_icp); + if (ret) + return ret; + + ret = dev_read_u32(dev, "ti,otap-del-sel", &plat->otap_del_sel); + if (ret) + return ret; + + ret = dev_read_u32(dev, "ti,driver-strength-ohm", &drv_strength); + if (ret) + return ret; + + switch (drv_strength) { + case 50: + plat->drv_strength = DRIVER_STRENGTH_50_OHM; + break; + case 33: + plat->drv_strength = DRIVER_STRENGTH_33_OHM; + break; + case 66: + plat->drv_strength = DRIVER_STRENGTH_66_OHM; + break; + case 100: + plat->drv_strength = DRIVER_STRENGTH_100_OHM; + break; + case 40: + plat->drv_strength = DRIVER_STRENGTH_40_OHM; + break; + default: + dev_err(dev, "Invalid driver strength\n"); + return -EINVAL; + } + + ret = mmc_of_parse(dev, cfg); + if (ret) + return ret;
return 0; }
Add Support for CONFIG_REGMAP.
Signed-off-by: Faiz Abbas faiz_abbas@ti.com Reviewed-by: Tom Rini trini@konsulko.com --- configs/am65x_evm_a53_defconfig | 2 ++ configs/am65x_evm_r5_defconfig | 2 ++ 2 files changed, 4 insertions(+)
diff --git a/configs/am65x_evm_a53_defconfig b/configs/am65x_evm_a53_defconfig index ff41d66e4d..3f6cf7e6b3 100644 --- a/configs/am65x_evm_a53_defconfig +++ b/configs/am65x_evm_a53_defconfig @@ -47,6 +47,8 @@ CONFIG_ENV_FAT_DEVICE_AND_PART="1:1" CONFIG_DM=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y CONFIG_CLK=y CONFIG_SPL_CLK=y CONFIG_CLK_TI_SCI=y diff --git a/configs/am65x_evm_r5_defconfig b/configs/am65x_evm_r5_defconfig index 6d7ba4d77c..6a261c20ac 100644 --- a/configs/am65x_evm_r5_defconfig +++ b/configs/am65x_evm_r5_defconfig @@ -51,6 +51,8 @@ CONFIG_ENV_FAT_DEVICE_AND_PART="1:1" CONFIG_DM=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y CONFIG_SPL_OF_TRANSLATE=y CONFIG_CLK=y CONFIG_SPL_CLK=y
Use f_max provided in mmc_config and remove it from the platform specific data.
Signed-off-by: Faiz Abbas faiz_abbas@ti.com --- drivers/mmc/am654_sdhci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mmc/am654_sdhci.c b/drivers/mmc/am654_sdhci.c index cd7ad03479..b9a7924d4e 100644 --- a/drivers/mmc/am654_sdhci.c +++ b/drivers/mmc/am654_sdhci.c @@ -67,7 +67,6 @@ struct am654_sdhci_plat { struct mmc_config cfg; struct mmc mmc; - unsigned int f_max; struct regmap *base; bool non_removable; u32 otap_del_sel; @@ -193,6 +192,7 @@ static int am654_sdhci_probe(struct udevice *dev) struct am654_sdhci_plat *plat = dev_get_platdata(dev); struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); struct sdhci_host *host = dev_get_priv(dev); + struct mmc_config *cfg = &plat->cfg; struct power_domain sdhci_pwrdmn; struct clk clk; unsigned long clock;
The HOST_CONTROL2 register is a part of SDHC v3.00 and not just specific to arasan/zynq controllers. Add the same to sdhci.h.
Also create a common API to set UHS timings in HOST_CONTROL2.
Signed-off-by: Faiz Abbas faiz_abbas@ti.com Reviewed-by: Tom Rini trini@konsulko.com --- drivers/mmc/sdhci.c | 28 ++++++++++++++++++++++++++++ drivers/mmc/zynq_sdhci.c | 31 ++----------------------------- include/sdhci.h | 19 ++++++++++++++++++- 3 files changed, 48 insertions(+), 30 deletions(-)
diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c index 75e6567631..79edb18fe5 100644 --- a/drivers/mmc/sdhci.c +++ b/drivers/mmc/sdhci.c @@ -533,6 +533,34 @@ static void sdhci_set_power(struct sdhci_host *host, unsigned short power) sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); }
+void sdhci_set_uhs_timing(struct sdhci_host *host) +{ + struct mmc *mmc = (struct mmc *)host->mmc; + u32 reg; + + reg = sdhci_readw(host, SDHCI_HOST_CONTROL2); + reg &= ~SDHCI_CTRL_UHS_MASK; + + switch (mmc->selected_mode) { + case UHS_SDR50: + case MMC_HS_52: + reg |= SDHCI_CTRL_UHS_SDR50; + break; + case UHS_DDR50: + case MMC_DDR_52: + reg |= SDHCI_CTRL_UHS_DDR50; + break; + case UHS_SDR104: + case MMC_HS_200: + reg |= SDHCI_CTRL_UHS_SDR104; + break; + default: + reg |= SDHCI_CTRL_UHS_SDR12; + } + + sdhci_writew(host, reg, SDHCI_HOST_CONTROL2); +} + #ifdef CONFIG_DM_MMC static int sdhci_set_ios(struct udevice *dev) { diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c index 08023783de..b39e1d7a19 100644 --- a/drivers/mmc/zynq_sdhci.c +++ b/drivers/mmc/zynq_sdhci.c @@ -48,11 +48,6 @@ static const u8 mode2timing[] = { [MMC_HS_200] = MMC_HS200_BUS_SPEED, };
-#define SDHCI_HOST_CTRL2 0x3E -#define SDHCI_CTRL2_MODE_MASK 0x7 -#define SDHCI_18V_SIGNAL 0x8 -#define SDHCI_CTRL_EXEC_TUNING 0x0040 -#define SDHCI_CTRL_TUNED_CLK 0x80 #define SDHCI_TUNING_LOOP_COUNT 40
static void arasan_zynqmp_dll_reset(struct sdhci_host *host, u8 deviceid) @@ -190,30 +185,8 @@ static void arasan_sdhci_set_control_reg(struct sdhci_host *host) }
if (mmc->selected_mode > SD_HS && - mmc->selected_mode <= UHS_DDR50) { - reg = sdhci_readw(host, SDHCI_HOST_CTRL2); - reg &= ~SDHCI_CTRL2_MODE_MASK; - switch (mmc->selected_mode) { - case UHS_SDR12: - reg |= UHS_SDR12_BUS_SPEED; - break; - case UHS_SDR25: - reg |= UHS_SDR25_BUS_SPEED; - break; - case UHS_SDR50: - reg |= UHS_SDR50_BUS_SPEED; - break; - case UHS_SDR104: - reg |= UHS_SDR104_BUS_SPEED; - break; - case UHS_DDR50: - reg |= UHS_DDR50_BUS_SPEED; - break; - default: - break; - } - sdhci_writew(host, reg, SDHCI_HOST_CTRL2); - } + mmc->selected_mode <= UHS_DDR50) + sdhci_set_uhs_timing(host); } #endif
diff --git a/include/sdhci.h b/include/sdhci.h index 3dcbc14965..01addb7a60 100644 --- a/include/sdhci.h +++ b/include/sdhci.h @@ -144,7 +144,23 @@
#define SDHCI_ACMD12_ERR 0x3C
-/* 3E-3F reserved */ +#define SDHCI_HOST_CONTROL2 0x3E +#define SDHCI_CTRL_UHS_MASK 0x0007 +#define SDHCI_CTRL_UHS_SDR12 0x0000 +#define SDHCI_CTRL_UHS_SDR25 0x0001 +#define SDHCI_CTRL_UHS_SDR50 0x0002 +#define SDHCI_CTRL_UHS_SDR104 0x0003 +#define SDHCI_CTRL_UHS_DDR50 0x0004 +#define SDHCI_CTRL_HS400 0x0005 /* Non-standard */ +#define SDHCI_CTRL_VDD_180 0x0008 +#define SDHCI_CTRL_DRV_TYPE_MASK 0x0030 +#define SDHCI_CTRL_DRV_TYPE_B 0x0000 +#define SDHCI_CTRL_DRV_TYPE_A 0x0010 +#define SDHCI_CTRL_DRV_TYPE_C 0x0020 +#define SDHCI_CTRL_DRV_TYPE_D 0x0030 +#define SDHCI_CTRL_EXEC_TUNING 0x0040 +#define SDHCI_CTRL_TUNED_CLK 0x0080 +#define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000
#define SDHCI_CAPABILITIES 0x40 #define SDHCI_TIMEOUT_CLK_MASK 0x0000003F @@ -467,6 +483,7 @@ int sdhci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg); int add_sdhci(struct sdhci_host *host, u32 f_max, u32 f_min); #endif /* !CONFIG_BLK */
+void sdhci_set_uhs_timing(struct sdhci_host *host); #ifdef CONFIG_DM_MMC /* Export the operations to drivers */ int sdhci_probe(struct udevice *dev);
Add a platform specific set_control_reg() callback to help switch to UHS speed modes.
Signed-off-by: Faiz Abbas faiz_abbas@ti.com Reviewed-by: Tom Rini trini@konsulko.com --- drivers/mmc/am654_sdhci.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/am654_sdhci.c b/drivers/mmc/am654_sdhci.c index b9a7924d4e..fe633aa39a 100644 --- a/drivers/mmc/am654_sdhci.c +++ b/drivers/mmc/am654_sdhci.c @@ -75,6 +75,21 @@ struct am654_sdhci_plat { bool dll_on; };
+static void am654_sdhci_set_control_reg(struct sdhci_host *host) +{ + struct mmc *mmc = (struct mmc *)host->mmc; + u32 reg; + + if (IS_SD(host->mmc) && + mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) { + reg = sdhci_readw(host, SDHCI_HOST_CONTROL2); + reg |= SDHCI_CTRL_VDD_180; + sdhci_writew(host, reg, SDHCI_HOST_CONTROL2); + } + + sdhci_set_uhs_timing(host); +} + static int am654_sdhci_set_ios_post(struct sdhci_host *host) { struct udevice *dev = host->mmc->dev; @@ -143,7 +158,8 @@ static int am654_sdhci_set_ios_post(struct sdhci_host *host) }
const struct sdhci_ops am654_sdhci_ops = { - .set_ios_post = &am654_sdhci_set_ios_post, + .set_ios_post = &am654_sdhci_set_ios_post, + .set_control_reg = &am654_sdhci_set_control_reg, };
int am654_sdhci_init(struct am654_sdhci_plat *plat)
Add configs such that U-boot environment is in eMMC by default.
Signed-off-by: Faiz Abbas faiz_abbas@ti.com --- configs/am65x_evm_a53_defconfig | 5 ++--- include/configs/am65x_evm.h | 10 ++++++++++ 2 files changed, 12 insertions(+), 3 deletions(-)
diff --git a/configs/am65x_evm_a53_defconfig b/configs/am65x_evm_a53_defconfig index 3f6cf7e6b3..5fd9aacd68 100644 --- a/configs/am65x_evm_a53_defconfig +++ b/configs/am65x_evm_a53_defconfig @@ -41,9 +41,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="k3-am654-base-board" CONFIG_SPL_MULTI_DTB_FIT=y CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y -CONFIG_ENV_IS_IN_FAT=y -CONFIG_ENV_FAT_INTERFACE="mmc" -CONFIG_ENV_FAT_DEVICE_AND_PART="1:1" +CONFIG_ENV_IS_IN_MMC=y CONFIG_DM=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y @@ -76,3 +74,4 @@ CONFIG_SOC_TI=y CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_TI_SCI=y +CONFIG_FAT_WRITE=y diff --git a/include/configs/am65x_evm.h b/include/configs/am65x_evm.h index b043bf886b..e9e9d4a9dc 100644 --- a/include/configs/am65x_evm.h +++ b/include/configs/am65x_evm.h @@ -68,6 +68,16 @@ EXTRA_ENV_AM65X_BOARD_SETTINGS \ EXTRA_ENV_AM65X_BOARD_SETTINGS_MMC
+/* MMC ENV related defines */ +#ifdef CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_SYS_MMC_ENV_PART 1 +#define CONFIG_ENV_SIZE (128 << 10) +#define CONFIG_ENV_OFFSET 0x680000 +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT +#endif + /* Now for the remaining common defines */ #include <configs/ti_armv7_common.h>
Add Support for creating a GPT partition for the filesystem in eMMC. The filesystem is created in the user partition (partition 0).
Signed-off-by: Faiz Abbas faiz_abbas@ti.com --- include/configs/am65x_evm.h | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/include/configs/am65x_evm.h b/include/configs/am65x_evm.h index e9e9d4a9dc..51abab3943 100644 --- a/include/configs/am65x_evm.h +++ b/include/configs/am65x_evm.h @@ -34,6 +34,10 @@
#define CONFIG_SYS_BOOTM_LEN SZ_64M
+#define PARTS_DEFAULT \ + /* Linux partitions */ \ + "name=rootfs,start=0,size=-,uuid=${uuid_gpt_rootfs}\0" + /* U-Boot general configuration */ #define EXTRA_ENV_AM65X_BOARD_SETTINGS \ "findfdt=" \ @@ -48,7 +52,7 @@ "name_kern=Image\0" \ "console=ttyS2,115200n8\0" \ "args_all=setenv optargs earlycon=ns16550a,mmio32,0x02800000\0" \ - "run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr}\0" + "run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr}\0" \
/* U-Boot MMC-specific configuration */ #define EXTRA_ENV_AM65X_BOARD_SETTINGS_MMC \ @@ -60,7 +64,8 @@ "init_mmc=run args_all args_mmc\0" \ "get_fdt_mmc=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${name_fdt}\0" \ "get_kern_mmc=load mmc ${bootpart} ${loadaddr} " \ - "${bootdir}/${name_kern}\0" + "${bootdir}/${name_kern}\0" \ + "partitions=" PARTS_DEFAULT
/* Incorporate settings into the U-Boot environment */ #define CONFIG_EXTRA_ENV_SETTINGS \
Add Support for creating GPT partitions in U-boot.
Signed-off-by: Faiz Abbas faiz_abbas@ti.com --- configs/am65x_evm_a53_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/configs/am65x_evm_a53_defconfig b/configs/am65x_evm_a53_defconfig index 5fd9aacd68..43d2ccc5ed 100644 --- a/configs/am65x_evm_a53_defconfig +++ b/configs/am65x_evm_a53_defconfig @@ -30,12 +30,12 @@ CONFIG_SPL_REMOTEPROC=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_CMD_ASKENV=y # CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y CONFIG_CMD_REMOTEPROC=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y # CONFIG_ISO_PARTITION is not set -# CONFIG_EFI_PARTITION is not set CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="k3-am654-base-board"
On 04/06/19 6:46 PM, Faiz Abbas wrote:
Add Support for eMMC in TI's AM65x-evm. The series starts by syncing the sdhci0 node from the kernel. Then it adds APIs and changes to the driver required for handling the driver's integrated phy. The current maximum supported speed is DDR52. Higher speeds and tuning support will be added in a subsequent series.
Changes in v6:
Squashed one more dependency for clk_200mhz from Andreas's patches[1] into patch 1. Patches now build without any help from the other series.
Improved line wrapping in patch 8.
Thanks for the quick update. For the entire series:
Tested-by: Lokesh Vutla lokeshvutla@ti.com
Thanks and regards, Lokesh
On Tue, Jun 04, 2019 at 09:32:21PM +0530, Lokesh Vutla wrote:
On 04/06/19 6:46 PM, Faiz Abbas wrote:
Add Support for eMMC in TI's AM65x-evm. The series starts by syncing the sdhci0 node from the kernel. Then it adds APIs and changes to the driver required for handling the driver's integrated phy. The current maximum supported speed is DDR52. Higher speeds and tuning support will be added in a subsequent series.
Changes in v6:
Squashed one more dependency for clk_200mhz from Andreas's patches[1] into patch 1. Patches now build without any help from the other series.
Improved line wrapping in patch 8.
Thanks for the quick update. For the entire series:
Tested-by: Lokesh Vutla lokeshvutla@ti.com
Seems like the test coverage was limited.
While eMMC (sdhci0) works when booting from SD card (sdhci1) the eMMC probe fails when booting from eMMC itself defeating the main purpose of a series adding eMMC support.
"sdhci@4f80000 - probe failed: -22"
I did some debugging and tracked this down to a missing drive strength setting on the R5 DTS file:
$ git diff diff --git a/arch/arm/dts/k3-am654-r5-base-board.dts b/arch/arm/dts/k3-am654-r5-base-board.dts index 2f178c8b07..b10df50ef9 100644 --- a/arch/arm/dts/k3-am654-r5-base-board.dts +++ b/arch/arm/dts/k3-am654-r5-base-board.dts @@ -186,6 +186,7 @@ clock-names = "clk_xin"; clocks = <&clk_200mhz>; /delete-property/ power-domains; + ti,driver-strength-ohm = <50>; };
&sdhci1 {
Can we please have this added.
With this change added and SYSFW loader series applied I can boot all the way to U-Boot prompt on AM654x EVM from eMMC.
Also SYSFW loader series no longer applies on top of this; will re-post a rebased/refactored version to be used on top of this series.
-- Andreas Dannenberg Texas Instruments Inc
On 04/06/19 11:57 PM, Andreas Dannenberg wrote:
On Tue, Jun 04, 2019 at 09:32:21PM +0530, Lokesh Vutla wrote:
On 04/06/19 6:46 PM, Faiz Abbas wrote:
Add Support for eMMC in TI's AM65x-evm. The series starts by syncing the sdhci0 node from the kernel. Then it adds APIs and changes to the driver required for handling the driver's integrated phy. The current maximum supported speed is DDR52. Higher speeds and tuning support will be added in a subsequent series.
Changes in v6:
Squashed one more dependency for clk_200mhz from Andreas's patches[1] into patch 1. Patches now build without any help from the other series.
Improved line wrapping in patch 8.
Thanks for the quick update. For the entire series:
Tested-by: Lokesh Vutla lokeshvutla@ti.com
Seems like the test coverage was limited.
While eMMC (sdhci0) works when booting from SD card (sdhci1) the eMMC probe fails when booting from eMMC itself defeating the main purpose of a series adding eMMC support.
Series talks about the eMMC support and not the eMMC boot support. So I did verify what is claimed. Anyways it is a valid bug you pointed out.
Faiz, Can you please re post with the fix incorporated.
Thanks and regards, Lokesh
"sdhci@4f80000 - probe failed: -22"
I did some debugging and tracked this down to a missing drive strength setting on the R5 DTS file:
$ git diff diff --git a/arch/arm/dts/k3-am654-r5-base-board.dts b/arch/arm/dts/k3-am654-r5-base-board.dts index 2f178c8b07..b10df50ef9 100644 --- a/arch/arm/dts/k3-am654-r5-base-board.dts +++ b/arch/arm/dts/k3-am654-r5-base-board.dts @@ -186,6 +186,7 @@ clock-names = "clk_xin"; clocks = <&clk_200mhz>; /delete-property/ power-domains;
ti,driver-strength-ohm = <50>;};
&sdhci1 {
Can we please have this added.
With this change added and SYSFW loader series applied I can boot all the way to U-Boot prompt on AM654x EVM from eMMC.
Also SYSFW loader series no longer applies on top of this; will re-post a rebased/refactored version to be used on top of this series.
-- Andreas Dannenberg Texas Instruments Inc
Hi,
On 05/06/19 9:16 AM, Lokesh Vutla wrote:
On 04/06/19 11:57 PM, Andreas Dannenberg wrote:
On Tue, Jun 04, 2019 at 09:32:21PM +0530, Lokesh Vutla wrote:
On 04/06/19 6:46 PM, Faiz Abbas wrote:
Add Support for eMMC in TI's AM65x-evm. The series starts by syncing the sdhci0 node from the kernel. Then it adds APIs and changes to the driver required for handling the driver's integrated phy. The current maximum supported speed is DDR52. Higher speeds and tuning support will be added in a subsequent series.
Changes in v6:
Squashed one more dependency for clk_200mhz from Andreas's patches[1] into patch 1. Patches now build without any help from the other series.
Improved line wrapping in patch 8.
Thanks for the quick update. For the entire series:
Tested-by: Lokesh Vutla lokeshvutla@ti.com
Seems like the test coverage was limited.
While eMMC (sdhci0) works when booting from SD card (sdhci1) the eMMC probe fails when booting from eMMC itself defeating the main purpose of a series adding eMMC support.
Series talks about the eMMC support and not the eMMC boot support. So I did verify what is claimed. Anyways it is a valid bug you pointed out.
Faiz, Can you please re post with the fix incorporated.
Sending one more version.
Thanks, Faiz
participants (3)
-
Andreas Dannenberg -
Faiz Abbas -
Lokesh Vutla