[PATCH v3 0/7] Add Rockchip RK3399 USB3.0 Host support
This series add quirks for DWC3 and add Rockchip RK3399 USB3.0 host support.
Tested on top of Jagan 'rockchip: PHY drivers (USB)' series [1].
For V3 update: - Fix compile error for [PATCH v2 1/9]. - Use Jagan's Type-C driver instead of [PATCH v2 5/9]. - Cleanup dts changes for [PATCH v2 7/9]. - Cleanup config changes for [PATCH v2 8/9] and [PATCH v2 9/9].
For V2 update: - Amend type-c driver followed Jagan's comments for [PATCH 5/8]. - Fix dts commit for [PATCH 7/8]. - Split RK3399 default config for [PATCH 8/8]. - Add 'Reviewed-by' tag for [PATCH 1/8], [PATCH 2/8] and [PATCH 3/8].
[1] https://patchwork.ozlabs.org/project/uboot/cover/20200506075025.1677-1-jagan...
BR, Frank
Frank Wang (7): usb: dwc3: add dis_enblslpm_quirk usb: dwc3: add dis_u2_freeclk_exists_quirk usb: dwc3: amend UTMI/UTMIW phy interface setup usb: dwc3: add make compatible for rockchip platform driver: usb: drop legacy rockchip xhci driver ARM: dts: rk3399-evb: usb3.0 host support configs: evb-rk3399: update support usb3.0 host
arch/arm/dts/rk3399-evb.dts | 13 ++ configs/evb-rk3399_defconfig | 6 + drivers/usb/common/common.c | 25 ++++ drivers/usb/dwc3/core.c | 77 +++++++----- drivers/usb/dwc3/core.h | 9 ++ drivers/usb/dwc3/dwc3-generic.c | 33 +++++- drivers/usb/host/Kconfig | 9 -- drivers/usb/host/Makefile | 1 - drivers/usb/host/xhci-rockchip.c | 196 ------------------------------- include/dwc3-uboot.h | 2 + include/linux/usb/phy.h | 18 +++ 11 files changed, 146 insertions(+), 243 deletions(-) delete mode 100644 drivers/usb/host/xhci-rockchip.c
Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller.
Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel.
Signed-off-by: Frank Wang frank.wang@rock-chips.com Reviewed-by: Kever Yang kever.yang@rock-chips.com --- Changes for v3: - Fix compile error for 'DWC3_GUSB2PHYCFG_ENBLSLPM' macro.
drivers/usb/dwc3/core.c | 6 ++++++ drivers/usb/dwc3/core.h | 2 ++ include/dwc3-uboot.h | 1 + 3 files changed, 9 insertions(+)
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index 6e438e5604..e2b30ab734 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -398,6 +398,9 @@ static void dwc3_phy_setup(struct dwc3 *dwc) if (dwc->dis_u2_susphy_quirk) reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
+ if (dwc->dis_enblslpm_quirk) + reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; + dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
mdelay(100); @@ -719,6 +722,7 @@ int dwc3_uboot_init(struct dwc3_device *dwc3_dev) dwc->dis_u3_susphy_quirk = dwc3_dev->dis_u3_susphy_quirk; dwc->dis_u2_susphy_quirk = dwc3_dev->dis_u2_susphy_quirk; dwc->dis_del_phy_power_chg_quirk = dwc3_dev->dis_del_phy_power_chg_quirk; + dwc->dis_enblslpm_quirk = dwc3_dev->dis_enblslpm_quirk;
dwc->tx_de_emphasis_quirk = dwc3_dev->tx_de_emphasis_quirk; if (dwc3_dev->tx_de_emphasis) @@ -981,6 +985,8 @@ void dwc3_of_parse(struct dwc3 *dwc) "snps,dis_u2_susphy_quirk"); dwc->dis_del_phy_power_chg_quirk = dev_read_bool(dev, "snps,dis-del-phy-power-chg-quirk"); + dwc->dis_enblslpm_quirk = dev_read_bool(dev, + "snps,dis_enblslpm_quirk"); dwc->tx_de_emphasis_quirk = dev_read_bool(dev, "snps,tx_de_emphasis_quirk"); tmp = dev_read_u8_array_ptr(dev, "snps,tx_de_emphasis", 1); diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index 7f45a9c459..e76e357f1e 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -162,6 +162,7 @@ /* Global USB2 PHY Configuration Register */ #define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31) #define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6) +#define DWC3_GUSB2PHYCFG_ENBLSLPM (1 << 8) #define DWC3_GUSB2PHYCFG_PHYIF(n) ((n) << 3) #define DWC3_GUSB2PHYCFG_PHYIF_MASK DWC3_GUSB2PHYCFG_PHYIF(1) #define DWC3_GUSB2PHYCFG_USBTRDTIM(n) ((n) << 10) @@ -822,6 +823,7 @@ struct dwc3 { unsigned dis_u3_susphy_quirk:1; unsigned dis_u2_susphy_quirk:1; unsigned dis_del_phy_power_chg_quirk:1; + unsigned dis_enblslpm_quirk:1;
unsigned tx_de_emphasis_quirk:1; unsigned tx_de_emphasis:2; diff --git a/include/dwc3-uboot.h b/include/dwc3-uboot.h index f5086fb946..05b19e1226 100644 --- a/include/dwc3-uboot.h +++ b/include/dwc3-uboot.h @@ -33,6 +33,7 @@ struct dwc3_device { unsigned dis_u3_susphy_quirk; unsigned dis_u2_susphy_quirk; unsigned dis_del_phy_power_chg_quirk; + unsigned dis_enblslpm_quirk; unsigned tx_de_emphasis_quirk; unsigned tx_de_emphasis; int index;
On Thu, May 7, 2020 at 1:42 PM Frank Wang frank.wang@rock-chips.com wrote:
Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller.
Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel.
Signed-off-by: Frank Wang frank.wang@rock-chips.com Reviewed-by: Kever Yang kever.yang@rock-chips.com
Reviewed-by: Jagan Teki jagan@amarulasolutions.com
Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active.
Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel.
Signed-off-by: Frank Wang frank.wang@rock-chips.com Reviewed-by: Kever Yang kever.yang@rock-chips.com --- Changes for v3: - none
drivers/usb/dwc3/core.c | 6 ++++++ drivers/usb/dwc3/core.h | 2 ++ include/dwc3-uboot.h | 1 + 3 files changed, 9 insertions(+)
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index e2b30ab734..4fb56aaf03 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -401,6 +401,9 @@ static void dwc3_phy_setup(struct dwc3 *dwc) if (dwc->dis_enblslpm_quirk) reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
+ if (dwc->dis_u2_freeclk_exists_quirk) + reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS; + dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
mdelay(100); @@ -723,6 +726,7 @@ int dwc3_uboot_init(struct dwc3_device *dwc3_dev) dwc->dis_u2_susphy_quirk = dwc3_dev->dis_u2_susphy_quirk; dwc->dis_del_phy_power_chg_quirk = dwc3_dev->dis_del_phy_power_chg_quirk; dwc->dis_enblslpm_quirk = dwc3_dev->dis_enblslpm_quirk; + dwc->dis_u2_freeclk_exists_quirk = dwc3_dev->dis_u2_freeclk_exists_quirk;
dwc->tx_de_emphasis_quirk = dwc3_dev->tx_de_emphasis_quirk; if (dwc3_dev->tx_de_emphasis) @@ -987,6 +991,8 @@ void dwc3_of_parse(struct dwc3 *dwc) "snps,dis-del-phy-power-chg-quirk"); dwc->dis_enblslpm_quirk = dev_read_bool(dev, "snps,dis_enblslpm_quirk"); + dwc->dis_u2_freeclk_exists_quirk = dev_read_bool(dev, + "snps,dis-u2-freeclk-exists-quirk"); dwc->tx_de_emphasis_quirk = dev_read_bool(dev, "snps,tx_de_emphasis_quirk"); tmp = dev_read_u8_array_ptr(dev, "snps,tx_de_emphasis", 1); diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index e76e357f1e..c5e656885a 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -161,6 +161,7 @@
/* Global USB2 PHY Configuration Register */ #define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31) +#define DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS (1 << 30) #define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6) #define DWC3_GUSB2PHYCFG_ENBLSLPM (1 << 8) #define DWC3_GUSB2PHYCFG_PHYIF(n) ((n) << 3) @@ -824,6 +825,7 @@ struct dwc3 { unsigned dis_u2_susphy_quirk:1; unsigned dis_del_phy_power_chg_quirk:1; unsigned dis_enblslpm_quirk:1; + unsigned dis_u2_freeclk_exists_quirk:1;
unsigned tx_de_emphasis_quirk:1; unsigned tx_de_emphasis:2; diff --git a/include/dwc3-uboot.h b/include/dwc3-uboot.h index 05b19e1226..f69d4a1926 100644 --- a/include/dwc3-uboot.h +++ b/include/dwc3-uboot.h @@ -34,6 +34,7 @@ struct dwc3_device { unsigned dis_u2_susphy_quirk; unsigned dis_del_phy_power_chg_quirk; unsigned dis_enblslpm_quirk; + unsigned dis_u2_freeclk_exists_quirk; unsigned tx_de_emphasis_quirk; unsigned tx_de_emphasis; int index;
On Thu, May 7, 2020 at 1:43 PM Frank Wang frank.wang@rock-chips.com wrote:
Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active.
Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel.
Signed-off-by: Frank Wang frank.wang@rock-chips.com Reviewed-by: Kever Yang kever.yang@rock-chips.com
Reviewed-by: Jagan Teki jagan@amarulasolutions.com
Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process.
Signed-off-by: Frank Wang frank.wang@rock-chips.com Reviewed-by: Kever Yang kever.yang@rock-chips.com --- Changes for v3: - none
drivers/usb/common/common.c | 25 ++++++++++++++ drivers/usb/dwc3/core.c | 65 +++++++++++++++++++------------------ drivers/usb/dwc3/core.h | 5 +++ include/linux/usb/phy.h | 18 ++++++++++ 4 files changed, 82 insertions(+), 31 deletions(-)
diff --git a/drivers/usb/common/common.c b/drivers/usb/common/common.c index 0db281b970..48b0a9a5f1 100644 --- a/drivers/usb/common/common.c +++ b/drivers/usb/common/common.c @@ -10,6 +10,7 @@ #include <dm.h> #include <linux/usb/otg.h> #include <linux/usb/ch9.h> +#include <linux/usb/phy.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -64,3 +65,27 @@ enum usb_device_speed usb_get_maximum_speed(ofnode node)
return USB_SPEED_UNKNOWN; } + +#if CONFIG_IS_ENABLED(OF_LIVE) && CONFIG_IS_ENABLED(DM_USB) +static const char *const usbphy_modes[] = { + [USBPHY_INTERFACE_MODE_UNKNOWN] = "", + [USBPHY_INTERFACE_MODE_UTMI] = "utmi", + [USBPHY_INTERFACE_MODE_UTMIW] = "utmi_wide", +}; + +enum usb_phy_interface usb_get_phy_mode(ofnode node) +{ + const char *phy_type; + int i; + + phy_type = ofnode_get_property(node, "phy_type", NULL); + if (!phy_type) + return USBPHY_INTERFACE_MODE_UNKNOWN; + + for (i = 0; i < ARRAY_SIZE(usbphy_modes); i++) + if (!strcmp(phy_type, usbphy_modes[i])) + return i; + + return USBPHY_INTERFACE_MODE_UNKNOWN; +} +#endif diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index 4fb56aaf03..b44282582a 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -334,6 +334,34 @@ static void dwc3_cache_hwparams(struct dwc3 *dwc) parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8); }
+static void dwc3_hsphy_mode_setup(struct dwc3 *dwc) +{ + enum usb_phy_interface hsphy_mode = dwc->hsphy_mode; + u32 reg; + + /* Set dwc3 usb2 phy config */ + reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); + + switch (hsphy_mode) { + case USBPHY_INTERFACE_MODE_UTMI: + reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | + DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); + reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) | + DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT); + break; + case USBPHY_INTERFACE_MODE_UTMIW: + reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | + DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); + reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) | + DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT); + break; + default: + break; + } + + dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); +} + /** * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core * @dwc: Pointer to our controller context structure @@ -382,6 +410,8 @@ static void dwc3_phy_setup(struct dwc3 *dwc)
dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
+ dwc3_hsphy_mode_setup(dwc); + mdelay(100);
reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); @@ -626,35 +656,6 @@ static void dwc3_core_exit_mode(struct dwc3 *dwc) dwc3_gadget_run(dwc); }
-static void dwc3_uboot_hsphy_mode(struct dwc3_device *dwc3_dev, - struct dwc3 *dwc) -{ - enum usb_phy_interface hsphy_mode = dwc3_dev->hsphy_mode; - u32 reg; - - /* Set dwc3 usb2 phy config */ - reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); - - switch (hsphy_mode) { - case USBPHY_INTERFACE_MODE_UTMI: - reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | - DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); - reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) | - DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT); - break; - case USBPHY_INTERFACE_MODE_UTMIW: - reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | - DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); - reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) | - DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT); - break; - default: - break; - } - - dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); -} - #define DWC3_ALIGN_MASK (16 - 1)
/** @@ -742,6 +743,8 @@ int dwc3_uboot_init(struct dwc3_device *dwc3_dev) dwc->hird_threshold = hird_threshold | (dwc->is_utmi_l1_suspend << 4);
+ dwc->hsphy_mode = dwc3_dev->hsphy_mode; + dwc->index = dwc3_dev->index;
dwc3_cache_hwparams(dwc); @@ -766,8 +769,6 @@ int dwc3_uboot_init(struct dwc3_device *dwc3_dev) goto err0; }
- dwc3_uboot_hsphy_mode(dwc3_dev, dwc); - ret = dwc3_event_buffers_setup(dwc); if (ret) { dev_err(dwc->dev, "failed to setup event buffers\n"); @@ -955,6 +956,8 @@ void dwc3_of_parse(struct dwc3 *dwc) */ hird_threshold = 12;
+ dwc->hsphy_mode = usb_get_phy_mode(dev->node); + dwc->has_lpm_erratum = dev_read_bool(dev, "snps,has-lpm-erratum"); tmp = dev_read_u8_array_ptr(dev, "snps,lpm-nyet-threshold", 1); diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index c5e656885a..8fa56004e7 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -21,6 +21,7 @@
#include <linux/usb/ch9.h> #include <linux/usb/otg.h> +#include <linux/usb/phy.h>
#define DWC3_MSG_MAX 500
@@ -650,6 +651,9 @@ struct dwc3_scratchpad_array { * @maximum_speed: maximum speed requested (mainly for testing purposes) * @revision: revision register contents * @dr_mode: requested mode of operation + * @hsphy_mode: UTMI phy mode, one of following: + * - USBPHY_INTERFACE_MODE_UTMI + * - USBPHY_INTERFACE_MODE_UTMIW * @dcfg: saved contents of DCFG register * @gctl: saved contents of GCTL register * @isoch_delay: wValue from Set Isochronous Delay request; @@ -741,6 +745,7 @@ struct dwc3 { size_t regs_size;
enum usb_dr_mode dr_mode; + enum usb_phy_interface hsphy_mode;
/* used for suspend/resume */ u32 dcfg; diff --git a/include/linux/usb/phy.h b/include/linux/usb/phy.h index 158ca9cd85..e4924ffe68 100644 --- a/include/linux/usb/phy.h +++ b/include/linux/usb/phy.h @@ -10,10 +10,28 @@ #ifndef __LINUX_USB_PHY_H #define __LINUX_USB_PHY_H
+#include <dm/ofnode.h> + enum usb_phy_interface { USBPHY_INTERFACE_MODE_UNKNOWN, USBPHY_INTERFACE_MODE_UTMI, USBPHY_INTERFACE_MODE_UTMIW, };
+#if CONFIG_IS_ENABLED(OF_LIVE) && CONFIG_IS_ENABLED(DM_USB) +/** + * usb_get_phy_mode - Get phy mode for given device_node + * @np: Pointer to the given device_node + * + * The function gets phy interface string from property 'phy_type', + * and returns the corresponding enum usb_phy_interface + */ +enum usb_phy_interface usb_get_phy_mode(ofnode node); +#else +static inline enum usb_phy_interface usb_get_phy_mode(ofnode node) +{ + return USBPHY_INTERFACE_MODE_UNKNOWN; +} +#endif + #endif /* __LINUX_USB_PHY_H */
RK3399 Type-C PHY is required that must hold whole USB3.0 OTG controller in resetting to hold pipe power state in P2 before initializing the PHY. This commit fixed it and added device compatible for rockchip platform.
Signed-off-by: Frank Wang frank.wang@rock-chips.com --- Changes for v3: - none
drivers/usb/dwc3/dwc3-generic.c | 33 +++++++++++++++++++++++++++------ 1 file changed, 27 insertions(+), 6 deletions(-)
diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c index febcfc0f54..0031e8bf44 100644 --- a/drivers/usb/dwc3/dwc3-generic.c +++ b/drivers/usb/dwc3/dwc3-generic.c @@ -24,6 +24,12 @@ #include <clk.h> #include <usb/xhci.h>
+struct dwc3_glue_data { + struct clk_bulk clks; + struct reset_ctl_bulk resets; + fdt_addr_t regs; +}; + struct dwc3_generic_plat { fdt_addr_t base; u32 maximum_speed; @@ -48,6 +54,7 @@ static int dwc3_generic_probe(struct udevice *dev, int rc; struct dwc3_generic_plat *plat = dev_get_platdata(dev); struct dwc3 *dwc3 = &priv->dwc3; + struct dwc3_glue_data *glue = dev_get_platdata(dev->parent);
dwc3->dev = dev; dwc3->maximum_speed = plat->maximum_speed; @@ -56,10 +63,22 @@ static int dwc3_generic_probe(struct udevice *dev, dwc3_of_parse(dwc3); #endif
+ /* + * It must hold whole USB3.0 OTG controller in resetting to hold pipe + * power state in P2 before initializing TypeC PHY on RK3399 platform. + */ + if (device_is_compatible(dev->parent, "rockchip,rk3399-dwc3")) { + reset_assert_bulk(&glue->resets); + udelay(1); + } + rc = dwc3_setup_phy(dev, &priv->phys, &priv->num_phys); if (rc) return rc;
+ if (device_is_compatible(dev->parent, "rockchip,rk3399-dwc3")) + reset_deassert_bulk(&glue->resets); + priv->base = map_physmem(plat->base, DWC3_OTG_REGS_END, MAP_NOCACHE); dwc3->regs = priv->base + DWC3_GLOBALS_REGS_START;
@@ -187,12 +206,6 @@ U_BOOT_DRIVER(dwc3_generic_host) = { }; #endif
-struct dwc3_glue_data { - struct clk_bulk clks; - struct reset_ctl_bulk resets; - fdt_addr_t regs; -}; - struct dwc3_glue_ops { void (*select_dr_mode)(struct udevice *dev, int index, enum usb_dr_mode mode); @@ -395,6 +408,12 @@ static int dwc3_glue_probe(struct udevice *dev) if (ret) return ret;
+ if (glue->resets.count < 1) { + ret = dwc3_glue_reset_init(child, glue); + if (ret) + return ret; + } + while (child) { enum usb_dr_mode dr_mode;
@@ -425,6 +444,8 @@ static const struct udevice_id dwc3_glue_ids[] = { { .compatible = "ti,dwc3", .data = (ulong)&ti_ops }, { .compatible = "ti,am437x-dwc3", .data = (ulong)&ti_ops }, { .compatible = "ti,am654-dwc3" }, + { .compatible = "rockchip,rk3328-dwc3" }, + { .compatible = "rockchip,rk3399-dwc3" }, { } };
We have changed to use dwc3 generic driver for usb3.0 host, so the legacy Rockchip's xHCI driver is not needed, and drop it.
Signed-off-by: Frank Wang frank.wang@rock-chips.com --- Changes for v3: - none
drivers/usb/host/Kconfig | 9 -- drivers/usb/host/Makefile | 1 - drivers/usb/host/xhci-rockchip.c | 196 ------------------------------- 3 files changed, 206 deletions(-) delete mode 100644 drivers/usb/host/xhci-rockchip.c
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 94ac969058..94232358a0 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -47,15 +47,6 @@ config USB_XHCI_PCI help Enables support for the PCI-based xHCI controller.
-config USB_XHCI_ROCKCHIP - bool "Support for Rockchip on-chip xHCI USB controller" - depends on ARCH_ROCKCHIP - depends on DM_REGULATOR - depends on DM_USB - default y - help - Enables support for the on-chip xHCI controller on Rockchip SoCs. - config USB_XHCI_RCAR bool "Renesas RCar USB 3.0 support" default y diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile index b62f346094..1754714673 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile @@ -48,7 +48,6 @@ obj-$(CONFIG_USB_XHCI_BRCM) += xhci-brcm.o obj-$(CONFIG_USB_XHCI_HCD) += xhci.o xhci-mem.o xhci-ring.o obj-$(CONFIG_USB_XHCI_DWC3) += xhci-dwc3.o obj-$(CONFIG_USB_XHCI_DWC3_OF_SIMPLE) += dwc3-of-simple.o -obj-$(CONFIG_USB_XHCI_ROCKCHIP) += xhci-rockchip.o obj-$(CONFIG_USB_XHCI_EXYNOS) += xhci-exynos5.o obj-$(CONFIG_USB_XHCI_FSL) += xhci-fsl.o obj-$(CONFIG_USB_XHCI_MVEBU) += xhci-mvebu.o diff --git a/drivers/usb/host/xhci-rockchip.c b/drivers/usb/host/xhci-rockchip.c deleted file mode 100644 index b67722fe45..0000000000 --- a/drivers/usb/host/xhci-rockchip.c +++ /dev/null @@ -1,196 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (c) 2016 Rockchip, Inc. - * Authors: Daniel Meng daniel.meng@rock-chips.com - */ -#include <common.h> -#include <dm.h> -#include <malloc.h> -#include <usb.h> -#include <watchdog.h> -#include <linux/errno.h> -#include <linux/compat.h> -#include <linux/usb/dwc3.h> -#include <power/regulator.h> - -#include <usb/xhci.h> - -struct rockchip_xhci_platdata { - fdt_addr_t hcd_base; - struct udevice *vbus_supply; -}; - -/* - * Contains pointers to register base addresses - * for the usb controller. - */ -struct rockchip_xhci { - struct usb_platdata usb_plat; - struct xhci_ctrl ctrl; - struct xhci_hccr *hcd; - struct dwc3 *dwc3_reg; -}; - -static int xhci_usb_ofdata_to_platdata(struct udevice *dev) -{ - struct rockchip_xhci_platdata *plat = dev_get_platdata(dev); - int ret = 0; - - /* - * Get the base address for XHCI controller from the device node - */ - plat->hcd_base = dev_read_addr(dev); - if (plat->hcd_base == FDT_ADDR_T_NONE) { - pr_err("Can't get the XHCI register base address\n"); - return -ENXIO; - } - - /* Vbus regulator */ - ret = device_get_supply_regulator(dev, "vbus-supply", - &plat->vbus_supply); - if (ret) - debug("Can't get VBus regulator!\n"); - - return 0; -} - -/* - * rockchip_dwc3_phy_setup() - Configure USB PHY Interface of DWC3 Core - * @dwc: Pointer to our controller context structure - * @dev: Pointer to ulcass device - */ -static void rockchip_dwc3_phy_setup(struct dwc3 *dwc3_reg, - struct udevice *dev) -{ - u32 reg; - u32 utmi_bits; - - /* Set dwc3 usb2 phy config */ - reg = readl(&dwc3_reg->g_usb2phycfg[0]); - - if (dev_read_bool(dev, "snps,dis-enblslpm-quirk")) - reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; - - utmi_bits = dev_read_u32_default(dev, "snps,phyif-utmi-bits", -1); - if (utmi_bits == 16) { - reg |= DWC3_GUSB2PHYCFG_PHYIF; - reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK; - reg |= DWC3_GUSB2PHYCFG_USBTRDTIM_16BIT; - } else if (utmi_bits == 8) { - reg &= ~DWC3_GUSB2PHYCFG_PHYIF; - reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK; - reg |= DWC3_GUSB2PHYCFG_USBTRDTIM_8BIT; - } - - if (dev_read_bool(dev, "snps,dis-u2-freeclk-exists-quirk")) - reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS; - - if (dev_read_bool(dev, "snps,dis-u2-susphy-quirk")) - reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; - - writel(reg, &dwc3_reg->g_usb2phycfg[0]); -} - -static int rockchip_xhci_core_init(struct rockchip_xhci *rkxhci, - struct udevice *dev) -{ - int ret; - - ret = dwc3_core_init(rkxhci->dwc3_reg); - if (ret) { - pr_err("failed to initialize core\n"); - return ret; - } - - rockchip_dwc3_phy_setup(rkxhci->dwc3_reg, dev); - - /* We are hard-coding DWC3 core to Host Mode */ - dwc3_set_mode(rkxhci->dwc3_reg, DWC3_GCTL_PRTCAP_HOST); - - return 0; -} - -static int rockchip_xhci_core_exit(struct rockchip_xhci *rkxhci) -{ - return 0; -} - -static int xhci_usb_probe(struct udevice *dev) -{ - struct rockchip_xhci_platdata *plat = dev_get_platdata(dev); - struct rockchip_xhci *ctx = dev_get_priv(dev); - struct xhci_hcor *hcor; - int ret; - - ctx->hcd = (struct xhci_hccr *)plat->hcd_base; - ctx->dwc3_reg = (struct dwc3 *)((char *)(ctx->hcd) + DWC3_REG_OFFSET); - hcor = (struct xhci_hcor *)((uint64_t)ctx->hcd + - HC_LENGTH(xhci_readl(&ctx->hcd->cr_capbase))); - - if (plat->vbus_supply) { - ret = regulator_set_enable(plat->vbus_supply, true); - if (ret) { - pr_err("XHCI: failed to set VBus supply\n"); - return ret; - } - } - - ret = rockchip_xhci_core_init(ctx, dev); - if (ret) { - pr_err("XHCI: failed to initialize controller\n"); - return ret; - } - - return xhci_register(dev, ctx->hcd, hcor); -} - -static int xhci_usb_remove(struct udevice *dev) -{ - struct rockchip_xhci_platdata *plat = dev_get_platdata(dev); - struct rockchip_xhci *ctx = dev_get_priv(dev); - int ret; - - ret = xhci_deregister(dev); - if (ret) - return ret; - ret = rockchip_xhci_core_exit(ctx); - if (ret) - return ret; - - if (plat->vbus_supply) { - ret = regulator_set_enable(plat->vbus_supply, false); - if (ret) - pr_err("XHCI: failed to set VBus supply\n"); - } - - return ret; -} - -static const struct udevice_id xhci_usb_ids[] = { - { .compatible = "rockchip,rk3328-xhci" }, - { } -}; - -U_BOOT_DRIVER(usb_xhci) = { - .name = "xhci_rockchip", - .id = UCLASS_USB, - .of_match = xhci_usb_ids, - .ofdata_to_platdata = xhci_usb_ofdata_to_platdata, - .probe = xhci_usb_probe, - .remove = xhci_usb_remove, - .ops = &xhci_usb_ops, - .bind = dm_scan_fdt_dev, - .platdata_auto_alloc_size = sizeof(struct rockchip_xhci_platdata), - .priv_auto_alloc_size = sizeof(struct rockchip_xhci), - .flags = DM_FLAG_ALLOC_PRIV_DMA, -}; - -static const struct udevice_id usb_phy_ids[] = { - { .compatible = "rockchip,rk3328-usb3-phy" }, - { } -}; - -U_BOOT_DRIVER(usb_phy) = { - .name = "usb_phy_rockchip", - .of_match = usb_phy_ids, -};
Configure 'tcphy1' and 'usbdrd_dwc3_1' nodes to support USB3.0 host for Rockchip RK3399 Evaluation Board.
Signed-off-by: Frank Wang frank.wang@rock-chips.com --- Changes for v3: - drop dtsi changes to keep the same with Linux Kernel. - amend rk3399-evb.dts to support usb3.0 host.
arch/arm/dts/rk3399-evb.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+)
diff --git a/arch/arm/dts/rk3399-evb.dts b/arch/arm/dts/rk3399-evb.dts index 694b0d08d6..5aa46f4e37 100644 --- a/arch/arm/dts/rk3399-evb.dts +++ b/arch/arm/dts/rk3399-evb.dts @@ -417,6 +417,10 @@ status = "disabled"; };
+&tcphy1 { + status = "okay"; +}; + &u2phy0 { status = "okay"; }; @@ -439,6 +443,15 @@ status = "okay"; };
+&usbdrd3_1 { + status = "okay"; +}; + +&usbdrd_dwc3_1 { + dr_mode = "host"; + status = "okay"; +}; + &usb_host0_ehci { status = "okay"; };
On Thu, May 7, 2020 at 9:13 AM Frank Wang frank.wang@rock-chips.com wrote:
Configure 'tcphy1' and 'usbdrd_dwc3_1' nodes to support USB3.0 host for Rockchip RK3399 Evaluation Board.
Signed-off-by: Frank Wang frank.wang@rock-chips.com
Changes for v3:
- drop dtsi changes to keep the same with Linux Kernel.
- amend rk3399-evb.dts to support usb3.0 host.
If this is specific to U-Boot it should go in arch/arm/dts/rk3399-evb-u-boot.dtsi as the rk3399-evb.dts is intended to be the same as what's in Linux.
arch/arm/dts/rk3399-evb.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+)
diff --git a/arch/arm/dts/rk3399-evb.dts b/arch/arm/dts/rk3399-evb.dts index 694b0d08d6..5aa46f4e37 100644 --- a/arch/arm/dts/rk3399-evb.dts +++ b/arch/arm/dts/rk3399-evb.dts @@ -417,6 +417,10 @@ status = "disabled"; };
+&tcphy1 {
status = "okay";+};
&u2phy0 { status = "okay"; }; @@ -439,6 +443,15 @@ status = "okay"; };
+&usbdrd3_1 {
status = "okay";+};
+&usbdrd_dwc3_1 {
dr_mode = "host";status = "okay";+};
&usb_host0_ehci { status = "okay"; }; -- 2.17.1
Hi Peter,
On 2020/5/7 16:17, Peter Robinson wrote:
On Thu, May 7, 2020 at 9:13 AM Frank Wang frank.wang@rock-chips.com wrote:
Configure 'tcphy1' and 'usbdrd_dwc3_1' nodes to support USB3.0 host for Rockchip RK3399 Evaluation Board.
Signed-off-by: Frank Wang frank.wang@rock-chips.com
Changes for v3:
- drop dtsi changes to keep the same with Linux Kernel.
- amend rk3399-evb.dts to support usb3.0 host.
If this is specific to U-Boot it should go in arch/arm/dts/rk3399-evb-u-boot.dtsi as the rk3399-evb.dts is intended to be the same as what's in Linux.
Will fix.
arch/arm/dts/rk3399-evb.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+)
diff --git a/arch/arm/dts/rk3399-evb.dts b/arch/arm/dts/rk3399-evb.dts index 694b0d08d6..5aa46f4e37 100644 --- a/arch/arm/dts/rk3399-evb.dts +++ b/arch/arm/dts/rk3399-evb.dts @@ -417,6 +417,10 @@ status = "disabled"; };
+&tcphy1 {
status = "okay";+};
- &u2phy0 { status = "okay"; };
@@ -439,6 +443,15 @@ status = "okay"; };
+&usbdrd3_1 {
status = "okay";+};
+&usbdrd_dwc3_1 {
dr_mode = "host";status = "okay";+};
- &usb_host0_ehci { status = "okay"; };
-- 2.17.1
Update evb-rk3399 default config to support USB3.0 Host.
Signed-off-by: Frank Wang frank.wang@rock-chips.com --- Changes for v3: - select more config to support USB3.0 host.
configs/evb-rk3399_defconfig | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig index 7f14e18b1b..6cfb4e5dac 100644 --- a/configs/evb-rk3399_defconfig +++ b/configs/evb-rk3399_defconfig @@ -28,6 +28,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y CONFIG_MMC_DW=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ROCKCHIP=y @@ -35,10 +36,13 @@ CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y +CONFIG_DM_RESET=y CONFIG_DM_RNG=y CONFIG_RNG_ROCKCHIP=y CONFIG_BAUDRATE=1500000 @@ -49,6 +53,8 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_ASIX88179=y
On Thu, May 7, 2020 at 1:43 PM Frank Wang frank.wang@rock-chips.com wrote:
Update evb-rk3399 default config to support USB3.0 Host.
Signed-off-by: Frank Wang frank.wang@rock-chips.com
Changes for v3:
- select more config to support USB3.0 host.
configs/evb-rk3399_defconfig | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig index 7f14e18b1b..6cfb4e5dac 100644 --- a/configs/evb-rk3399_defconfig +++ b/configs/evb-rk3399_defconfig @@ -28,6 +28,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y CONFIG_MMC_DW=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ROCKCHIP=y @@ -35,10 +36,13 @@ CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y +CONFIG_DM_RESET=y CONFIG_DM_RNG=y CONFIG_RNG_ROCKCHIP=y CONFIG_BAUDRATE=1500000 @@ -49,6 +53,8 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y
We need to enable OF_LIVE otherwise phy_type would be 0 but the actual one is 0x2 (utmi_wide). For phy_type 0 device cannot respond to the set address.
scanning bus dwc3 for devices... Device not responding to set address. USB device not accepting new address (error=80000000) 1 USB Device(s) found scanning usb for storage devices... 0 Storage Device(s) found
Jagan.
On 5/8/20 7:24 PM, Jagan Teki wrote:
On Thu, May 7, 2020 at 1:43 PM Frank Wang frank.wang@rock-chips.com wrote:
Update evb-rk3399 default config to support USB3.0 Host.
Signed-off-by: Frank Wang frank.wang@rock-chips.com
Changes for v3:
- select more config to support USB3.0 host.
configs/evb-rk3399_defconfig | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig index 7f14e18b1b..6cfb4e5dac 100644 --- a/configs/evb-rk3399_defconfig +++ b/configs/evb-rk3399_defconfig @@ -28,6 +28,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y CONFIG_MMC_DW=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ROCKCHIP=y @@ -35,10 +36,13 @@ CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y +CONFIG_DM_RESET=y CONFIG_DM_RNG=y CONFIG_RNG_ROCKCHIP=y CONFIG_BAUDRATE=1500000 @@ -49,6 +53,8 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y
We need to enable OF_LIVE otherwise phy_type would be 0 but the actual one is 0x2 (utmi_wide). For phy_type 0 device cannot respond to the set address.
scanning bus dwc3 for devices... Device not responding to set address. USB device not accepting new address (error=80000000) 1 USB Device(s) found scanning usb for storage devices... 0 Storage Device(s) found
How is OF_LIVE related to setting the phy width ?
On Fri, May 8, 2020 at 11:13 PM Marek Vasut marex@denx.de wrote:
On 5/8/20 7:24 PM, Jagan Teki wrote:
On Thu, May 7, 2020 at 1:43 PM Frank Wang frank.wang@rock-chips.com wrote:
Update evb-rk3399 default config to support USB3.0 Host.
Signed-off-by: Frank Wang frank.wang@rock-chips.com
Changes for v3:
- select more config to support USB3.0 host.
configs/evb-rk3399_defconfig | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig index 7f14e18b1b..6cfb4e5dac 100644 --- a/configs/evb-rk3399_defconfig +++ b/configs/evb-rk3399_defconfig @@ -28,6 +28,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y CONFIG_MMC_DW=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ROCKCHIP=y @@ -35,10 +36,13 @@ CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y +CONFIG_DM_RESET=y CONFIG_DM_RNG=y CONFIG_RNG_ROCKCHIP=y CONFIG_BAUDRATE=1500000 @@ -49,6 +53,8 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y
We need to enable OF_LIVE otherwise phy_type would be 0 but the actual one is 0x2 (utmi_wide). For phy_type 0 device cannot respond to the set address.
scanning bus dwc3 for devices... Device not responding to set address. USB device not accepting new address (error=80000000) 1 USB Device(s) found scanning usb for storage devices... 0 Storage Device(s) found
How is OF_LIVE related to setting the phy width ?
One of Frank patch [1] get the phy_type with OF_LIVE build depending.
[1] https://patchwork.ozlabs.org/project/uboot/patch/20200507081213.16107-4-fran...
On 5/8/20 7:46 PM, Jagan Teki wrote:
On Fri, May 8, 2020 at 11:13 PM Marek Vasut marex@denx.de wrote:
On 5/8/20 7:24 PM, Jagan Teki wrote:
On Thu, May 7, 2020 at 1:43 PM Frank Wang frank.wang@rock-chips.com wrote:
Update evb-rk3399 default config to support USB3.0 Host.
Signed-off-by: Frank Wang frank.wang@rock-chips.com
Changes for v3:
- select more config to support USB3.0 host.
configs/evb-rk3399_defconfig | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig index 7f14e18b1b..6cfb4e5dac 100644 --- a/configs/evb-rk3399_defconfig +++ b/configs/evb-rk3399_defconfig @@ -28,6 +28,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y CONFIG_MMC_DW=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ROCKCHIP=y @@ -35,10 +36,13 @@ CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y +CONFIG_DM_RESET=y CONFIG_DM_RNG=y CONFIG_RNG_ROCKCHIP=y CONFIG_BAUDRATE=1500000 @@ -49,6 +53,8 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y
We need to enable OF_LIVE otherwise phy_type would be 0 but the actual one is 0x2 (utmi_wide). For phy_type 0 device cannot respond to the set address.
scanning bus dwc3 for devices... Device not responding to set address. USB device not accepting new address (error=80000000) 1 USB Device(s) found scanning usb for storage devices... 0 Storage Device(s) found
How is OF_LIVE related to setting the phy width ?
One of Frank patch [1] get the phy_type with OF_LIVE build depending.
[1] https://patchwork.ozlabs.org/project/uboot/patch/20200507081213.16107-4-fran...
Maybe that needs to be fixed, to work even without OF_LIVE ?
On Sat, May 9, 2020 at 12:03 AM Marek Vasut marex@denx.de wrote:
On 5/8/20 7:46 PM, Jagan Teki wrote:
On Fri, May 8, 2020 at 11:13 PM Marek Vasut marex@denx.de wrote:
On 5/8/20 7:24 PM, Jagan Teki wrote:
On Thu, May 7, 2020 at 1:43 PM Frank Wang frank.wang@rock-chips.com wrote:
Update evb-rk3399 default config to support USB3.0 Host.
Signed-off-by: Frank Wang frank.wang@rock-chips.com
Changes for v3:
- select more config to support USB3.0 host.
configs/evb-rk3399_defconfig | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig index 7f14e18b1b..6cfb4e5dac 100644 --- a/configs/evb-rk3399_defconfig +++ b/configs/evb-rk3399_defconfig @@ -28,6 +28,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y CONFIG_MMC_DW=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ROCKCHIP=y @@ -35,10 +36,13 @@ CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y +CONFIG_DM_RESET=y CONFIG_DM_RNG=y CONFIG_RNG_ROCKCHIP=y CONFIG_BAUDRATE=1500000 @@ -49,6 +53,8 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y
We need to enable OF_LIVE otherwise phy_type would be 0 but the actual one is 0x2 (utmi_wide). For phy_type 0 device cannot respond to the set address.
scanning bus dwc3 for devices... Device not responding to set address. USB device not accepting new address (error=80000000) 1 USB Device(s) found scanning usb for storage devices... 0 Storage Device(s) found
How is OF_LIVE related to setting the phy width ?
One of Frank patch [1] get the phy_type with OF_LIVE build depending.
[1] https://patchwork.ozlabs.org/project/uboot/patch/20200507081213.16107-4-fran...
Maybe that needs to be fixed, to work even without OF_LIVE ?
Yes, you are correct. It can get the phy_type value even without OF_LIVE.
Hi Marek & Jagan,
On 2020/5/9 2:52, Jagan Teki wrote:
On Sat, May 9, 2020 at 12:03 AM Marek Vasut marex@denx.de wrote:
On 5/8/20 7:46 PM, Jagan Teki wrote:
On Fri, May 8, 2020 at 11:13 PM Marek Vasut marex@denx.de wrote:
On 5/8/20 7:24 PM, Jagan Teki wrote:
On Thu, May 7, 2020 at 1:43 PM Frank Wang frank.wang@rock-chips.com wrote:
Update evb-rk3399 default config to support USB3.0 Host.
Signed-off-by: Frank Wang frank.wang@rock-chips.com
Changes for v3:
select more config to support USB3.0 host.
configs/evb-rk3399_defconfig | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig index 7f14e18b1b..6cfb4e5dac 100644 --- a/configs/evb-rk3399_defconfig +++ b/configs/evb-rk3399_defconfig @@ -28,6 +28,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y CONFIG_MMC_DW=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ROCKCHIP=y @@ -35,10 +36,13 @@ CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y +CONFIG_DM_RESET=y CONFIG_DM_RNG=y CONFIG_RNG_ROCKCHIP=y CONFIG_BAUDRATE=1500000 @@ -49,6 +53,8 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y
We need to enable OF_LIVE otherwise phy_type would be 0 but the actual one is 0x2 (utmi_wide). For phy_type 0 device cannot respond to the set address.
scanning bus dwc3 for devices... Device not responding to set address. USB device not accepting new address (error=80000000) 1 USB Device(s) found scanning usb for storage devices... 0 Storage Device(s) found
How is OF_LIVE related to setting the phy width ?
One of Frank patch [1] get the phy_type with OF_LIVE build depending.
[1] https://patchwork.ozlabs.org/project/uboot/patch/20200507081213.16107-4-fran...
Maybe that needs to be fixed, to work even without OF_LIVE ?
Yes, you are correct. It can get the phy_type value even without OF_LIVE.
Okay, keep 'CONFIG_DM_USB' only and fix it in next patch.
BR, Frank
participants (4)
-
Frank Wang -
Jagan Teki -
Marek Vasut -
Peter Robinson