[U-Boot] [PATCH 1/3] mvebu: pinctrl: sync compatible string with Linux 4.17-rc4
From: Evan Wang xswang@marvell.com
Signed-off-by: Evan Wang xswang@marvell.com ---
arch/arm/dts/armada-ap806.dtsi | 2 +- arch/arm/dts/armada-cp110-master.dtsi | 4 ++-- arch/arm/dts/armada-cp110-slave.dtsi | 2 +- .../pinctrl/marvell,mvebu-pinctrl.txt | 16 ++++++++-------- drivers/pinctrl/mvebu/pinctrl-mvebu.c | 8 ++++---- 5 files changed, 16 insertions(+), 16 deletions(-)
diff --git a/arch/arm/dts/armada-ap806.dtsi b/arch/arm/dts/armada-ap806.dtsi index e0d3016..ebdee51 100644 --- a/arch/arm/dts/armada-ap806.dtsi +++ b/arch/arm/dts/armada-ap806.dtsi @@ -141,7 +141,7 @@ };
ap_pinctl: ap-pinctl@6F4000 { - compatible = "marvell,armada-ap806-pinctrl"; + compatible = "marvell,ap806-pinctrl"; bank-name ="apn-806"; reg = <0x6F4000 0x10>; pin-count = <20>; diff --git a/arch/arm/dts/armada-cp110-master.dtsi b/arch/arm/dts/armada-cp110-master.dtsi index 8c336f2..551d00d 100644 --- a/arch/arm/dts/armada-cp110-master.dtsi +++ b/arch/arm/dts/armada-cp110-master.dtsi @@ -120,8 +120,8 @@
cpm_pinctl: cpm-pinctl@440000 { compatible = "marvell,mvebu-pinctrl", - "marvell,a70x0-pinctrl", - "marvell,a80x0-cp0-pinctrl"; + "marvell,armada-7k-pinctrl", + "marvell,armada-8k-cpm-pinctrl"; bank-name ="cp0-110"; reg = <0x440000 0x20>; pin-count = <63>; diff --git a/arch/arm/dts/armada-cp110-slave.dtsi b/arch/arm/dts/armada-cp110-slave.dtsi index 0cdb3d3..2ea9004 100644 --- a/arch/arm/dts/armada-cp110-slave.dtsi +++ b/arch/arm/dts/armada-cp110-slave.dtsi @@ -120,7 +120,7 @@
cps_pinctl: cps-pinctl@440000 { compatible = "marvell,mvebu-pinctrl", - "marvell,a80x0-cp1-pinctrl"; + "marvell,armada-8k-cps-pinctrl"; bank-name ="cp1-110"; reg = <0x440000 0x20>; pin-count = <63>; diff --git a/doc/device-tree-bindings/pinctrl/marvell,mvebu-pinctrl.txt b/doc/device-tree-bindings/pinctrl/marvell,mvebu-pinctrl.txt index 5f86c0a..1fc1bc6 100644 --- a/doc/device-tree-bindings/pinctrl/marvell,mvebu-pinctrl.txt +++ b/doc/device-tree-bindings/pinctrl/marvell,mvebu-pinctrl.txt @@ -6,10 +6,10 @@ mpp pins or group of pins and a mpp function common to all pins.
Required properties for the pinctrl driver: - compatible: "marvell,mvebu-pinctrl", - "marvell,armada-ap806-pinctrl", - "marvell,a70x0-pinctrl", - "marvell,a80x0-cp0-pinctrl", - "marvell,a80x0-cp1-pinctrl" + "marvell,ap806-pinctrl", + "marvell,armada-7k-pinctrl", + "marvell,armada-8k-cpm-pinctrl", + "marvell,armada-8k-cps-pinctrl" - bank-name: A string defining the pinc controller bank name - reg: A pair of values defining the pin controller base address and the address space @@ -31,7 +31,7 @@ Example: config-space { pinctl: pinctl@6F4000 { compatible = "marvell,mvebu-pinctrl", - "marvell,armada-ap806-pinctrl"; + "marvell,ap806-pinctrl"; bank-name ="apn-806"; reg = <0x6F4000 0x10>; pin-count = <20>; @@ -52,8 +52,8 @@ Example: config-space { cpm_pinctl: pinctl@44000 { compatible = "marvell,mvebu-pinctrl", - "marvell,a70x0-pinctrl", - "marvell,a80x0-cp0-pinctrl"; + "marvell,armada-7k-pinctrl", + "marvell,armada-8k-cpm-pinctrl"; bank-name ="cp0-110"; reg = <0x440000 0x20>; pin-count = <63>; @@ -89,7 +89,7 @@ Example: config-space { cps_pinctl: pinctl@44000 { compatible = "marvell,mvebu-pinctrl", - "marvell,a80x0-cp1-pinctrl"; + "marvell,armada-8k-cps-pinctrl"; bank-name ="cp1-110"; reg = <0x440000 0x20>; pin-count = <63>; diff --git a/drivers/pinctrl/mvebu/pinctrl-mvebu.c b/drivers/pinctrl/mvebu/pinctrl-mvebu.c index ec19583..556bf78 100644 --- a/drivers/pinctrl/mvebu/pinctrl-mvebu.c +++ b/drivers/pinctrl/mvebu/pinctrl-mvebu.c @@ -162,10 +162,10 @@ static struct pinctrl_ops mvebu_pinctrl_ops = {
static const struct udevice_id mvebu_pinctrl_ids[] = { { .compatible = "marvell,mvebu-pinctrl" }, - { .compatible = "marvell,armada-ap806-pinctrl" }, - { .compatible = "marvell,a70x0-pinctrl" }, - { .compatible = "marvell,a80x0-cp0-pinctrl" }, - { .compatible = "marvell,a80x0-cp1-pinctrl" }, + { .compatible = "marvell,ap806-pinctrl" }, + { .compatible = "marvell,armada-7k-pinctrl" }, + { .compatible = "marvell,armada-8k-cpm-pinctrl" }, + { .compatible = "marvell,armada-8k-cps-pinctrl" }, { } };
From: Konstantin Porotchkin kostap@marvell.com
When the pin control driver selects SD/eMMC function for a pin group, there is additional configuration to be done for this case - switch the PHY to work with SDHCI interface. This patch adds the missing functionality into the pin control driver.
Signed-off-by: Konstantin Porotchkin kostap@marvell.com Signed-off-by: Evan Wang xswang@marvell.com ---
drivers/pinctrl/mvebu/pinctrl-mvebu.c | 59 +++++++++++++++++++++++++++++++++-- 1 file changed, 57 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/mvebu/pinctrl-mvebu.c b/drivers/pinctrl/mvebu/pinctrl-mvebu.c index 556bf78..7d8a0b0 100644 --- a/drivers/pinctrl/mvebu/pinctrl-mvebu.c +++ b/drivers/pinctrl/mvebu/pinctrl-mvebu.c @@ -17,8 +17,48 @@ #include <asm/arch-armada8k/soc-info.h> #include "pinctrl-mvebu.h"
+#define AP_EMMC_PHY_CTRL_REG 0x100 +#define CP_EMMC_PHY_CTRL_REG 0x424 +#define EMMC_PHY_CTRL_SDPHY_EN BIT(0) + +#define AP806_EMMC_CLK_PIN_ID 0 +#define AP806_EMMC_CLK_FUNC 0x1 +#define CP110_EMMC_CLK_PIN_ID 56 +#define CP110_EMMC_CLK_FUNC 0xe + DECLARE_GLOBAL_DATA_PTR;
+/* mvebu_pinctl_emmc_set_mux: configure sd/mmc PHY mux + * To enable SDIO/eMMC in Armada-APN806/CP110, need to configure PHY mux. + * eMMC/SD PHY register responsible for muxing between MPPs and SD/eMMC + * controller: + * - Bit0 enabled SDIO/eMMC PHY is used as a MPP muxltiplexer, + * - Bit0 disabled SDIO/eMMC PHY is connected to SDIO/eMMC controller + * If pin function is set to eMMC/SD, then configure the eMMC/SD PHY + * muxltiplexer register to be on SDIO/eMMC controller + */ +void mvebu_pinctl_emmc_set_mux(struct udevice *dev, u32 pin, u32 func) +{ + const void *blob = gd->fdt_blob; + int node = dev_of_offset(dev); + struct mvebu_pinctrl_priv *priv = dev_get_priv(dev); + + if (!fdt_node_check_compatible(blob, node, "marvell,ap806-pinctrl")) { + if ((pin == AP806_EMMC_CLK_PIN_ID) && + (func == AP806_EMMC_CLK_FUNC)) { + clrbits_le32(priv->base_reg + AP_EMMC_PHY_CTRL_REG, + EMMC_PHY_CTRL_SDPHY_EN); + } + } else if (!fdt_node_check_compatible(blob, node, + "marvell,armada-8k-cpm-pinctrl")) { + if ((pin == CP110_EMMC_CLK_PIN_ID) && + (func == CP110_EMMC_CLK_FUNC)) { + clrbits_le32(priv->base_reg + CP_EMMC_PHY_CTRL_REG, + EMMC_PHY_CTRL_SDPHY_EN); + } + } +} + /* * mvebu_pinctrl_set_state: configure pin functions. * @dev: the pinctrl device to be configured. @@ -48,9 +88,16 @@ int mvebu_pinctrl_set_state(struct udevice *dev, struct udevice *config)
function = fdtdec_get_int(blob, node, "marvell,function", 0xff);
+ /* + * Check if setup of PHY mux is needed for this pins group. + * Only the first pin id in array is tested, all the rest use the same + * pin function. + */ + mvebu_pinctl_emmc_set_mux(dev, pin_arr[0], function); + for (i = 0; i < pin_count; i++) { - int reg_offset; - int field_offset; + int reg_offset; + int field_offset; int pin = pin_arr[i];
if (function > priv->max_func) { @@ -97,6 +144,14 @@ static int mvebu_pinctrl_set_state_all(struct udevice *dev, return -EINVAL; }
+ /* Check if setup of PHY mux is needed for this pins group. */ + if (priv->pin_cnt < CP110_EMMC_CLK_PIN_ID) + mvebu_pinctl_emmc_set_mux(dev, AP806_EMMC_CLK_PIN_ID, + func_arr[AP806_EMMC_CLK_PIN_ID]); + else + mvebu_pinctl_emmc_set_mux(dev, CP110_EMMC_CLK_PIN_ID, + func_arr[CP110_EMMC_CLK_PIN_ID]); + for (pin = 0; pin < priv->pin_cnt; pin++) { int reg_offset; int field_offset;
On 24.05.2018 10:20, xswang@marvell.com wrote:
From: Konstantin Porotchkin kostap@marvell.com
When the pin control driver selects SD/eMMC function for a pin group, there is additional configuration to be done for this case - switch the PHY to work with SDHCI interface. This patch adds the missing functionality into the pin control driver.
Signed-off-by: Konstantin Porotchkin kostap@marvell.com Signed-off-by: Evan Wang xswang@marvell.com
drivers/pinctrl/mvebu/pinctrl-mvebu.c | 59 +++++++++++++++++++++++++++++++++-- 1 file changed, 57 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/mvebu/pinctrl-mvebu.c b/drivers/pinctrl/mvebu/pinctrl-mvebu.c index 556bf78..7d8a0b0 100644 --- a/drivers/pinctrl/mvebu/pinctrl-mvebu.c +++ b/drivers/pinctrl/mvebu/pinctrl-mvebu.c @@ -17,8 +17,48 @@ #include <asm/arch-armada8k/soc-info.h> #include "pinctrl-mvebu.h"
+#define AP_EMMC_PHY_CTRL_REG 0x100 +#define CP_EMMC_PHY_CTRL_REG 0x424 +#define EMMC_PHY_CTRL_SDPHY_EN BIT(0)
+#define AP806_EMMC_CLK_PIN_ID 0 +#define AP806_EMMC_CLK_FUNC 0x1 +#define CP110_EMMC_CLK_PIN_ID 56 +#define CP110_EMMC_CLK_FUNC 0xe
- DECLARE_GLOBAL_DATA_PTR;
+/* mvebu_pinctl_emmc_set_mux: configure sd/mmc PHY mux
- To enable SDIO/eMMC in Armada-APN806/CP110, need to configure PHY mux.
- eMMC/SD PHY register responsible for muxing between MPPs and SD/eMMC
- controller:
- Bit0 enabled SDIO/eMMC PHY is used as a MPP muxltiplexer,
- Bit0 disabled SDIO/eMMC PHY is connected to SDIO/eMMC controller
- If pin function is set to eMMC/SD, then configure the eMMC/SD PHY
- muxltiplexer register to be on SDIO/eMMC controller
- */
+void mvebu_pinctl_emmc_set_mux(struct udevice *dev, u32 pin, u32 func) +{
- const void *blob = gd->fdt_blob;
- int node = dev_of_offset(dev);
- struct mvebu_pinctrl_priv *priv = dev_get_priv(dev);
- if (!fdt_node_check_compatible(blob, node, "marvell,ap806-pinctrl")) {
if ((pin == AP806_EMMC_CLK_PIN_ID) &&(func == AP806_EMMC_CLK_FUNC)) {clrbits_le32(priv->base_reg + AP_EMMC_PHY_CTRL_REG,EMMC_PHY_CTRL_SDPHY_EN);}- } else if (!fdt_node_check_compatible(blob, node,
"marvell,armada-8k-cpm-pinctrl")) {if ((pin == CP110_EMMC_CLK_PIN_ID) &&(func == CP110_EMMC_CLK_FUNC)) {clrbits_le32(priv->base_reg + CP_EMMC_PHY_CTRL_REG,EMMC_PHY_CTRL_SDPHY_EN);}- }
+}
- /*
- mvebu_pinctrl_set_state: configure pin functions.
- @dev: the pinctrl device to be configured.
@@ -48,9 +88,16 @@ int mvebu_pinctrl_set_state(struct udevice *dev, struct udevice *config)
function = fdtdec_get_int(blob, node, "marvell,function", 0xff);
- /*
* Check if setup of PHY mux is needed for this pins group.* Only the first pin id in array is tested, all the rest use the same* pin function.*/- mvebu_pinctl_emmc_set_mux(dev, pin_arr[0], function);
- for (i = 0; i < pin_count; i++) {
- int reg_offset;
- int field_offset;
int reg_offset;int field_offset;int pin = pin_arr[i];
if (function > priv->max_func) {
@@ -97,6 +144,14 @@ static int mvebu_pinctrl_set_state_all(struct udevice *dev, return -EINVAL; }
- /* Check if setup of PHY mux is needed for this pins group. */
- if (priv->pin_cnt < CP110_EMMC_CLK_PIN_ID)
mvebu_pinctl_emmc_set_mux(dev, AP806_EMMC_CLK_PIN_ID,func_arr[AP806_EMMC_CLK_PIN_ID]);- else
mvebu_pinctl_emmc_set_mux(dev, CP110_EMMC_CLK_PIN_ID,func_arr[CP110_EMMC_CLK_PIN_ID]);- for (pin = 0; pin < priv->pin_cnt; pin++) { int reg_offset; int field_offset;
Reviewed-by: Stefan Roese sr@denx.de
Thanks, Stefan
From: Konstantin Porotchkin kostap@marvell.com
Enable SDHCI interface on AP and CP0 in A80x0 DTS files
Signed-off-by: Konstantin Porotchkin kostap@marvell.com Signed-off-by: Evan Wang xswang@marvell.com ---
arch/arm/dts/armada-8040-db.dts | 14 ++++++++++++++ arch/arm/dts/armada-8040-mcbin.dts | 8 ++++++++ 2 files changed, 22 insertions(+)
diff --git a/arch/arm/dts/armada-8040-db.dts b/arch/arm/dts/armada-8040-db.dts index fa58995..65b30bb 100644 --- a/arch/arm/dts/armada-8040-db.dts +++ b/arch/arm/dts/armada-8040-db.dts @@ -81,6 +81,13 @@ 1 3 0 0 0 0 0 0 0 3 >; };
+&ap_sdhci0 { + pinctrl-names = "default"; + pinctrl-0 = <&ap_emmc_pins>; + bus-width = <8>; + status = "okay"; +}; + &cpm_pinctl { /* MPP Bus: * [0-31] = 0xff: Keep default CP0_shared_pins @@ -182,6 +189,13 @@ status = "okay"; };
+&cpm_sdhci0 { + pinctrl-names = "default"; + pinctrl-0 = <&cpm_sdhci_pins>; + bus-width = <4>; + status = "okay"; +}; + &cps_pinctl { /* MPP Bus: * [0-11] RGMII0 diff --git a/arch/arm/dts/armada-8040-mcbin.dts b/arch/arm/dts/armada-8040-mcbin.dts index 991ddc0..46b32f2 100644 --- a/arch/arm/dts/armada-8040-mcbin.dts +++ b/arch/arm/dts/armada-8040-mcbin.dts @@ -156,6 +156,14 @@ status = "okay"; };
+/* uSD slot */ +&cpm_sdhci0 { + pinctrl-names = "default"; + pinctrl-0 = <&cpm_sdhci_pins>; + bus-width = <4>; + status = "okay"; +}; + &cpm_comphy { /* * CP0 Serdes Configuration:
On 24.05.2018 10:20, xswang@marvell.com wrote:
From: Konstantin Porotchkin kostap@marvell.com
Enable SDHCI interface on AP and CP0 in A80x0 DTS files
Signed-off-by: Konstantin Porotchkin kostap@marvell.com Signed-off-by: Evan Wang xswang@marvell.com
arch/arm/dts/armada-8040-db.dts | 14 ++++++++++++++ arch/arm/dts/armada-8040-mcbin.dts | 8 ++++++++ 2 files changed, 22 insertions(+)
diff --git a/arch/arm/dts/armada-8040-db.dts b/arch/arm/dts/armada-8040-db.dts index fa58995..65b30bb 100644 --- a/arch/arm/dts/armada-8040-db.dts +++ b/arch/arm/dts/armada-8040-db.dts @@ -81,6 +81,13 @@ 1 3 0 0 0 0 0 0 0 3 >; };
+&ap_sdhci0 {
- pinctrl-names = "default";
- pinctrl-0 = <&ap_emmc_pins>;
- bus-width = <8>;
- status = "okay";
+};
- &cpm_pinctl { /* MPP Bus:
- [0-31] = 0xff: Keep default CP0_shared_pins
@@ -182,6 +189,13 @@ status = "okay"; };
+&cpm_sdhci0 {
- pinctrl-names = "default";
- pinctrl-0 = <&cpm_sdhci_pins>;
- bus-width = <4>;
- status = "okay";
+};
- &cps_pinctl { /* MPP Bus:
- [0-11] RGMII0
diff --git a/arch/arm/dts/armada-8040-mcbin.dts b/arch/arm/dts/armada-8040-mcbin.dts index 991ddc0..46b32f2 100644 --- a/arch/arm/dts/armada-8040-mcbin.dts +++ b/arch/arm/dts/armada-8040-mcbin.dts @@ -156,6 +156,14 @@ status = "okay"; };
+/* uSD slot */ +&cpm_sdhci0 {
- pinctrl-names = "default";
- pinctrl-0 = <&cpm_sdhci_pins>;
- bus-width = <4>;
- status = "okay";
+};
- &cpm_comphy { /*
- CP0 Serdes Configuration:
Reviewed-by: Stefan Roese sr@denx.de
Thanks, Stefan
On 24.05.2018 10:20, xswang@marvell.com wrote:
From: Evan Wang xswang@marvell.com
Signed-off-by: Evan Wang xswang@marvell.com
Even for minimal changes (which this patch is not btw), a small commit text is mandatory. Please insert a short patch description here in your v2.
Other than this, please add my:
Reviewed-by: Stefan Roese sr@denx.de
Thanks, Stefan
arch/arm/dts/armada-ap806.dtsi | 2 +- arch/arm/dts/armada-cp110-master.dtsi | 4 ++-- arch/arm/dts/armada-cp110-slave.dtsi | 2 +- .../pinctrl/marvell,mvebu-pinctrl.txt | 16 ++++++++-------- drivers/pinctrl/mvebu/pinctrl-mvebu.c | 8 ++++---- 5 files changed, 16 insertions(+), 16 deletions(-)
diff --git a/arch/arm/dts/armada-ap806.dtsi b/arch/arm/dts/armada-ap806.dtsi index e0d3016..ebdee51 100644 --- a/arch/arm/dts/armada-ap806.dtsi +++ b/arch/arm/dts/armada-ap806.dtsi @@ -141,7 +141,7 @@ };
ap_pinctl: ap-pinctl@6F4000 {
compatible = "marvell,armada-ap806-pinctrl";
compatible = "marvell,ap806-pinctrl"; bank-name ="apn-806"; reg = <0x6F4000 0x10>; pin-count = <20>;diff --git a/arch/arm/dts/armada-cp110-master.dtsi b/arch/arm/dts/armada-cp110-master.dtsi index 8c336f2..551d00d 100644 --- a/arch/arm/dts/armada-cp110-master.dtsi +++ b/arch/arm/dts/armada-cp110-master.dtsi @@ -120,8 +120,8 @@
cpm_pinctl: cpm-pinctl@440000 { compatible = "marvell,mvebu-pinctrl",
"marvell,a70x0-pinctrl","marvell,a80x0-cp0-pinctrl";
"marvell,armada-7k-pinctrl","marvell,armada-8k-cpm-pinctrl"; bank-name ="cp0-110"; reg = <0x440000 0x20>; pin-count = <63>;diff --git a/arch/arm/dts/armada-cp110-slave.dtsi b/arch/arm/dts/armada-cp110-slave.dtsi index 0cdb3d3..2ea9004 100644 --- a/arch/arm/dts/armada-cp110-slave.dtsi +++ b/arch/arm/dts/armada-cp110-slave.dtsi @@ -120,7 +120,7 @@
cps_pinctl: cps-pinctl@440000 { compatible = "marvell,mvebu-pinctrl",
"marvell,a80x0-cp1-pinctrl";
"marvell,armada-8k-cps-pinctrl"; bank-name ="cp1-110"; reg = <0x440000 0x20>; pin-count = <63>;diff --git a/doc/device-tree-bindings/pinctrl/marvell,mvebu-pinctrl.txt b/doc/device-tree-bindings/pinctrl/marvell,mvebu-pinctrl.txt index 5f86c0a..1fc1bc6 100644 --- a/doc/device-tree-bindings/pinctrl/marvell,mvebu-pinctrl.txt +++ b/doc/device-tree-bindings/pinctrl/marvell,mvebu-pinctrl.txt @@ -6,10 +6,10 @@ mpp pins or group of pins and a mpp function common to all pins.
Required properties for the pinctrl driver:
- compatible: "marvell,mvebu-pinctrl",
"marvell,armada-ap806-pinctrl","marvell,a70x0-pinctrl","marvell,a80x0-cp0-pinctrl","marvell,a80x0-cp1-pinctrl"
"marvell,ap806-pinctrl","marvell,armada-7k-pinctrl","marvell,armada-8k-cpm-pinctrl","marvell,armada-8k-cps-pinctrl"and the address space
- bank-name: A string defining the pinc controller bank name
- reg: A pair of values defining the pin controller base address
@@ -31,7 +31,7 @@ Example: config-space { pinctl: pinctl@6F4000 { compatible = "marvell,mvebu-pinctrl",
"marvell,armada-ap806-pinctrl";
"marvell,ap806-pinctrl"; bank-name ="apn-806"; reg = <0x6F4000 0x10>; pin-count = <20>;@@ -52,8 +52,8 @@ Example: config-space { cpm_pinctl: pinctl@44000 { compatible = "marvell,mvebu-pinctrl",
"marvell,a70x0-pinctrl","marvell,a80x0-cp0-pinctrl";
"marvell,armada-7k-pinctrl","marvell,armada-8k-cpm-pinctrl"; bank-name ="cp0-110"; reg = <0x440000 0x20>; pin-count = <63>;@@ -89,7 +89,7 @@ Example: config-space { cps_pinctl: pinctl@44000 { compatible = "marvell,mvebu-pinctrl",
"marvell,a80x0-cp1-pinctrl";
"marvell,armada-8k-cps-pinctrl"; bank-name ="cp1-110"; reg = <0x440000 0x20>; pin-count = <63>;diff --git a/drivers/pinctrl/mvebu/pinctrl-mvebu.c b/drivers/pinctrl/mvebu/pinctrl-mvebu.c index ec19583..556bf78 100644 --- a/drivers/pinctrl/mvebu/pinctrl-mvebu.c +++ b/drivers/pinctrl/mvebu/pinctrl-mvebu.c @@ -162,10 +162,10 @@ static struct pinctrl_ops mvebu_pinctrl_ops = {
static const struct udevice_id mvebu_pinctrl_ids[] = { { .compatible = "marvell,mvebu-pinctrl" },
- { .compatible = "marvell,armada-ap806-pinctrl" },
- { .compatible = "marvell,a70x0-pinctrl" },
- { .compatible = "marvell,a80x0-cp0-pinctrl" },
- { .compatible = "marvell,a80x0-cp1-pinctrl" },
- { .compatible = "marvell,ap806-pinctrl" },
- { .compatible = "marvell,armada-7k-pinctrl" },
- { .compatible = "marvell,armada-8k-cpm-pinctrl" },
- { .compatible = "marvell,armada-8k-cps-pinctrl" }, { } };
Viele Grüße, Stefan
participants (2)
-
Stefan Roese -
xswang＠marvell.com