[PATCH 0/5] board: rockchip: Add Pine64 Quartz64 and SOQuartz boards
This series was created in collaboration with Nicolas Frattaroli and add support for Pine64 Quartz64 and SOQuartz boards with a RK3566 SoC.
- Pine64 Quartz64-A Board - Pine64 Quartz64-B Board - Pine64 SOQuartz on Model A - Pine64 SOQuartz on Blade - Pine64 SOQuartz on CM4-IO
Device trees have been imported from linux v6.4.
This series have loose dependencies on the following series: - rockchip: Fix PCIe and NVMe support on RK3568 [1] - rockchip: rk3568: Use dwc3-generic driver [2] - rockchip: rk3568: Fix alloc space exhausted in SPL [3] - rockchip: rk3568: Device Tree updates [4] - rockchip: rk35xx: Fix SPI Flash alias [5] - board: rockchip: Add Hardkernel ODROID-M1 [6]
A copy of this series with above dependencies can be found at [7].
[1] https://patchwork.ozlabs.org/project/uboot/list/?series=365195 [2] https://patchwork.ozlabs.org/project/uboot/list/?series=364127 [3] https://patchwork.ozlabs.org/project/uboot/list/?series=361999 [4] https://patchwork.ozlabs.org/project/uboot/list/?series=362030 [5] https://patchwork.ozlabs.org/project/uboot/list/?series=363527 [6] https://patchwork.ozlabs.org/project/uboot/list/?series=365198 [7] https://github.com/Kwiboo/u-boot-rockchip/commits/rk3568-quartz64-v1
Jonas Karlman (5): board: rockchip: Add Pine64 Quartz64-A Board board: rockchip: Add Pine64 Quartz64-B Board board: rockchip: Add Pine64 SOQuartz on Model A board: rockchip: Add Pine64 SOQuartz on Blade board: rockchip: Add Pine64 SOQuartz on CM4-IO
arch/arm/dts/Makefile | 5 + arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi | 55 ++ arch/arm/dts/rk3566-quartz64-a.dts | 839 ++++++++++++++++++ arch/arm/dts/rk3566-quartz64-b-u-boot.dtsi | 47 + arch/arm/dts/rk3566-quartz64-b.dts | 739 +++++++++++++++ .../arm/dts/rk3566-soquartz-blade-u-boot.dtsi | 3 + arch/arm/dts/rk3566-soquartz-blade.dts | 194 ++++ arch/arm/dts/rk3566-soquartz-cm4-u-boot.dtsi | 3 + arch/arm/dts/rk3566-soquartz-cm4.dts | 192 ++++ .../dts/rk3566-soquartz-model-a-u-boot.dtsi | 3 + arch/arm/dts/rk3566-soquartz-model-a.dts | 232 +++++ arch/arm/dts/rk3566-soquartz-u-boot.dtsi | 30 + arch/arm/dts/rk3566-soquartz.dtsi | 688 ++++++++++++++ arch/arm/mach-rockchip/rk3568/Kconfig | 6 + board/pine64/quartz64_rk3566/Kconfig | 15 + board/pine64/quartz64_rk3566/MAINTAINERS | 23 + board/pine64/quartz64_rk3566/Makefile | 3 + .../pine64/quartz64_rk3566/quartz64-rk3566.c | 1 + configs/quartz64-a-rk3566_defconfig | 110 +++ configs/quartz64-b-rk3566_defconfig | 106 +++ configs/soquartz-blade-rk3566_defconfig | 90 ++ configs/soquartz-cm4-rk3566_defconfig | 90 ++ configs/soquartz-model-a-rk3566_defconfig | 90 ++ doc/board/rockchip/rockchip.rst | 5 + include/configs/quartz64_rk3566.h | 10 + 25 files changed, 3579 insertions(+) create mode 100644 arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi create mode 100644 arch/arm/dts/rk3566-quartz64-a.dts create mode 100644 arch/arm/dts/rk3566-quartz64-b-u-boot.dtsi create mode 100644 arch/arm/dts/rk3566-quartz64-b.dts create mode 100644 arch/arm/dts/rk3566-soquartz-blade-u-boot.dtsi create mode 100644 arch/arm/dts/rk3566-soquartz-blade.dts create mode 100644 arch/arm/dts/rk3566-soquartz-cm4-u-boot.dtsi create mode 100644 arch/arm/dts/rk3566-soquartz-cm4.dts create mode 100644 arch/arm/dts/rk3566-soquartz-model-a-u-boot.dtsi create mode 100644 arch/arm/dts/rk3566-soquartz-model-a.dts create mode 100644 arch/arm/dts/rk3566-soquartz-u-boot.dtsi create mode 100644 arch/arm/dts/rk3566-soquartz.dtsi create mode 100644 board/pine64/quartz64_rk3566/Kconfig create mode 100644 board/pine64/quartz64_rk3566/MAINTAINERS create mode 100644 board/pine64/quartz64_rk3566/Makefile create mode 100644 board/pine64/quartz64_rk3566/quartz64-rk3566.c create mode 100644 configs/quartz64-a-rk3566_defconfig create mode 100644 configs/quartz64-b-rk3566_defconfig create mode 100644 configs/soquartz-blade-rk3566_defconfig create mode 100644 configs/soquartz-cm4-rk3566_defconfig create mode 100644 configs/soquartz-model-a-rk3566_defconfig create mode 100644 include/configs/quartz64_rk3566.h
The Pine64 Quartz64 Model A is a single-board computer based on the Rockchip RK3566 SoC. The board features USB3, SATA, PCIe, HDMI, USB2.0, CSI, DSI, eDP, eMMC, SD, and an e-paper parallel port, as well as a 20 pin GPIO header.
Features tested on a Quartz64-A 8GB v2.0 2021-04-27: - SD-card boot - eMMC boot - PCIe/NVMe/AHCI - USB host
Device tree is imported from linux v6.4.
Co-developed-by: Nicolas Frattaroli frattaroli.nicolas@gmail.com Signed-off-by: Nicolas Frattaroli frattaroli.nicolas@gmail.com Signed-off-by: Jonas Karlman jonas@kwiboo.se --- arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi | 55 ++ arch/arm/dts/rk3566-quartz64-a.dts | 839 ++++++++++++++++++ arch/arm/mach-rockchip/rk3568/Kconfig | 6 + board/pine64/quartz64_rk3566/Kconfig | 15 + board/pine64/quartz64_rk3566/MAINTAINERS | 9 + board/pine64/quartz64_rk3566/Makefile | 3 + .../pine64/quartz64_rk3566/quartz64-rk3566.c | 1 + configs/quartz64-a-rk3566_defconfig | 110 +++ doc/board/rockchip/rockchip.rst | 1 + include/configs/quartz64_rk3566.h | 10 + 11 files changed, 1050 insertions(+) create mode 100644 arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi create mode 100644 arch/arm/dts/rk3566-quartz64-a.dts create mode 100644 board/pine64/quartz64_rk3566/Kconfig create mode 100644 board/pine64/quartz64_rk3566/MAINTAINERS create mode 100644 board/pine64/quartz64_rk3566/Makefile create mode 100644 board/pine64/quartz64_rk3566/quartz64-rk3566.c create mode 100644 configs/quartz64-a-rk3566_defconfig create mode 100644 include/configs/quartz64_rk3566.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 6764ded580ab..45ef73fdf0ca 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -167,6 +167,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
dtb-$(CONFIG_ROCKCHIP_RK3568) += \ rk3566-anbernic-rgxx3.dtb \ + rk3566-quartz64-a.dtb \ rk3566-radxa-cm3-io.dtb \ rk3568-evb.dtb \ rk3568-odroid-m1.dtb \ diff --git a/arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi b/arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi new file mode 100644 index 000000000000..700c2d3edfe6 --- /dev/null +++ b/arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include "rk356x-u-boot.dtsi" + +/ { + chosen { + stdout-path = &uart2; + }; +}; + +&gpio0 { + bootph-all; +}; + +&pcie2x1 { + pinctrl-0 = <&pcie20m2_pins &pcie_reset_h>; +}; + +&sdhci { + cap-mmc-highspeed; + mmc-ddr-1_8v; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; +}; + +&sfc { + bootph-pre-ram; + u-boot,spl-sfc-no-dma; + + flash@0 { + bootph-pre-ram; + }; +}; + +&uart2 { + bootph-all; + clock-frequency = <24000000>; + status = "okay"; +}; + +/* + * U-Boot does not support multiple regulators using the same gpio, + * use vcc5v0_usb20_host to fix use of USB 2.0 port + */ +&usb2phy0_otg { + phy-supply = <&vcc5v0_usb20_host>; +}; + +&vcc3v3_sd { + bootph-pre-ram; +}; + +&vcc_sd_h { + bootph-all; +}; diff --git a/arch/arm/dts/rk3566-quartz64-a.dts b/arch/arm/dts/rk3566-quartz64-a.dts new file mode 100644 index 000000000000..25a8c781f4e7 --- /dev/null +++ b/arch/arm/dts/rk3566-quartz64-a.dts @@ -0,0 +1,839 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/soc/rockchip,vop2.h> +#include "rk3566.dtsi" + +/ { + model = "Pine64 RK3566 Quartz64-A Board"; + compatible = "pine64,quartz64-a", "rockchip,rk3566"; + + aliases { + ethernet0 = &gmac1; + mmc0 = &sdmmc0; + mmc1 = &sdhci; + }; + + chosen: chosen { + stdout-path = "serial2:1500000n8"; + }; + + gmac1_clkin: external-gmac1-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "gmac1_clkin"; + #clock-cells = <0>; + }; + + fan: gpio_fan { + compatible = "gpio-fan"; + gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; + gpio-fan,speed-map = <0 0 + 4500 1>; + pinctrl-names = "default"; + pinctrl-0 = <&fan_en_h>; + #cooling-cells = <2>; + }; + + hdmi-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-work { + label = "work-led"; + default-state = "off"; + gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&work_led_enable_h>; + retain-state-suspended; + }; + + led-diy { + label = "diy-led"; + default-state = "on"; + gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + pinctrl-names = "default"; + pinctrl-0 = <&diy_led_enable_h>; + retain-state-suspended; + }; + }; + + rk817-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "Analog RK817"; + simple-audio-card,mclk-fs = <256>; + + simple-audio-card,cpu { + sound-dai = <&i2s1_8ch>; + }; + + simple-audio-card,codec { + sound-dai = <&rk817>; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk817 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + post-power-on-delay-ms = <100>; + power-off-delay-us = <5000000>; + reset-gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_LOW>; + }; + + spdif_dit: spdif-dit { + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + }; + + spdif_sound: spdif-sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "SPDIF"; + + simple-audio-card,cpu { + sound-dai = <&spdif>; + }; + + simple-audio-card,codec { + sound-dai = <&spdif_dit>; + }; + }; + + vcc12v_dcin: vcc12v_dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + /* vbus feeds the rk817 usb input. + * With no battery attached, also feeds vcc_bat+ + * via ON/OFF_BAT jumper + */ + vbus: vbus { + compatible = "regulator-fixed"; + regulator-name = "vbus"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc3v3_pcie_p: vcc3v3-pcie-p-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_enable_h>; + regulator-name = "vcc3v3_pcie_p"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3>; + }; + + vcc5v0_usb: vcc5v0_usb { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + /* all four ports are controlled by one gpio + * the host ports are sourced from vcc5v0_usb + * the otg port is sourced from vcc5v0_midu + */ + vcc5v0_usb20_host: vcc5v0_usb20_host { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_usb20_host_en>; + regulator-name = "vcc5v0_usb20_host"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usb>; + }; + + vcc5v0_usb20_otg: vcc5v0_usb20_otg { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; + regulator-name = "vcc5v0_usb20_otg"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dcdc_boost>; + }; + + vcc3v3_sd: vcc3v3_sd { + compatible = "regulator-fixed"; + gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc_sd_h>; + regulator-boot-on; + regulator-name = "vcc3v3_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3>; + }; + + /* sourced from vbus and vcc_bat+ via rk817 sw5 */ + vcc_sys: vcc_sys { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <4400000>; + regulator-max-microvolt = <4400000>; + vin-supply = <&vbus>; + }; + + /* sourced from vcc_sys, sdio module operates internally at 3.3v */ + vcc_wl: vcc_wl { + compatible = "regulator-fixed"; + regulator-name = "vcc_wl"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_sys>; + }; +}; + +&combphy1 { + status = "okay"; +}; + +&combphy2 { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu_thermal { + trips { + cpu_hot: cpu_hot { + temperature = <55000>; + hysteresis = <2000>; + type = "active"; + }; + }; + + cooling-maps { + map1 { + trip = <&cpu_hot>; + cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; +}; + +&gmac1 { + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>, <&gmac1_clkin>; + clock_in_out = "input"; + phy-supply = <&vcc_3v3>; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m0_miim + &gmac1m0_tx_bus2 + &gmac1m0_rx_bus2 + &gmac1m0_rgmii_clk + &gmac1m0_clkinout + &gmac1m0_rgmii_bus>; + snps,reset-gpio = <&gpio0 RK_PC3 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + tx_delay = <0x30>; + rx_delay = <0x10>; + phy-handle = <&rgmii_phy1>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + avdd-0v9-supply = <&vdda_0v9>; + avdd-1v8-supply = <&vcc_1v8>; + status = "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&hdmi_sound { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + vdd_cpu: regulator@1c { + compatible = "tcs,tcs4525"; + reg = <0x1c>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-ramp-delay = <2300>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk817: pmic@20 { + compatible = "rockchip,rk817"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>; + assigned-clocks = <&cru I2S1_MCLKOUT_TX>; + assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>; + clock-names = "mclk"; + clocks = <&cru I2S1_MCLKOUT_TX>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + #clock-cells = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>, <&i2s1m0_mclk>; + rockchip,system-power-controller; + #sound-dai-cells = <0>; + wakeup-source; + + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc5-supply = <&vcc_sys>; + vcc6-supply = <&vcc_sys>; + vcc7-supply = <&vcc_sys>; + vcc8-supply = <&vcc_sys>; + vcc9-supply = <&dcdc_boost>; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_logic"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_gpu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_3v3: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_3v3"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda_0v9"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda0v9_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_acodec"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_1v8: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc1v8_dvp: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc2v8_dvp: LDO_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-name = "vcc2v8_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + dcdc_boost: BOOST { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "boost"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + otg_switch: OTG_SWITCH { + regulator-name = "otg_switch"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +/* i2c3 is exposed on con40 + * pin 3 - i2c3_sda_m0, pullup to vcc_3v3 + * pin 5 - i2c3_scl_m0, pullup to vcc_3v3 + */ +&i2c3 { + status = "okay"; +}; + +&i2s0_8ch { + status = "okay"; +}; + +&i2s1_8ch { + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_sclktx + &i2s1m0_lrcktx + &i2s1m0_sdi0 + &i2s1m0_sdo0>; + rockchip,trcm-sync-tx-only; + status = "okay"; +}; + +&mdio1 { + rgmii_phy1: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; +}; + +&pcie2x1 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_reset_h>; + reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie_p>; + status = "okay"; +}; + +&pinctrl { + bt { + bt_enable_h: bt-enable-h { + rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_host_wake_l: bt-host-wake-l { + rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + bt_wake_l: bt-wake-l { + rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + fan { + fan_en_h: fan-en-h { + rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + leds { + work_led_enable_h: work-led-enable-h { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + diy_led_enable_h: diy-led-enable-h { + rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie { + pcie_enable_h: pcie-enable-h { + rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie_reset_h: pcie-reset-h { + rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb2 { + vcc5v0_usb20_host_en: vcc5v0-usb20-host-en { + rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + vcc_sd { + vcc_sd_h: vcc-sd-h { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio2-supply = <&vcc_1v8>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc1v8_dvp>; + vccio7-supply = <&vcc_3v3>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + mmc-hs200-1_8v; + non-removable; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdmmc0 { + bus-width = <4>; + cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&sdmmc1 { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; + sd-uhs-sdr104; + vmmc-supply = <&vcc_wl>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sfc { + pinctrl-0 = <&fspi_pins>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <24000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + }; +}; + +/* spdif is exposed on con40 pin 18 */ +&spdif { + status = "okay"; +}; + +/* spi1 is exposed on con40 + * pin 11 - spi1_mosi_m1 + * pin 13 - spi1_miso_m1 + * pin 15 - spi1_clk_m1 + * pin 17 - spi1_cs0_m1 + */ +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&spi1m1_cs0 &spi1m1_pins>; +}; + +&tsadc { + /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-mode = <1>; + /* tshut polarity 0:LOW 1:HIGH */ + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + +/* uart0 is exposed on con40 + * pin 12 - uart0_tx + * pin 14 - uart0_rx + */ +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>; + status = "okay"; + uart-has-rtscts; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + clocks = <&rk817 1>; + clock-names = "lpo"; + host-wakeup-gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; + device-wakeup-gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>; + vbat-supply = <&vcc_sys>; + vddio-supply = <&vcca1v8_pmu>; + max-speed = <3000000>; + }; +}; + +/* uart2 is exposed on con40 + * pin 8 - uart2_tx_m0_debug + * pin 10 - uart2_rx_m0_debug + */ +&uart2 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usb_host0_xhci { + dr_mode = "host"; + status = "okay"; +}; + +/* usb3 controller is muxed with sata1 */ +&usb_host1_xhci { + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy0_host { + phy-supply = <&vcc5v0_usb20_host>; + status = "okay"; +}; + +&usb2phy0_otg { + phy-supply = <&vcc5v0_usb20_otg>; + status = "okay"; +}; + +&usb2phy1 { + status = "okay"; +}; + +&usb2phy1_host { + phy-supply = <&vcc5v0_usb20_host>; + status = "okay"; +}; + +&usb2phy1_otg { + phy-supply = <&vcc5v0_usb20_host>; + status = "okay"; +}; + +&vop { + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = <ROCKCHIP_VOP2_EP_HDMI0>; + remote-endpoint = <&hdmi_in_vp0>; + }; +}; diff --git a/arch/arm/mach-rockchip/rk3568/Kconfig b/arch/arm/mach-rockchip/rk3568/Kconfig index f46be3d081fe..baa51349f4be 100644 --- a/arch/arm/mach-rockchip/rk3568/Kconfig +++ b/arch/arm/mach-rockchip/rk3568/Kconfig @@ -22,6 +22,11 @@ config TARGET_ODROID_M1_RK3568 help Hardkernel ODROID-M1 single board computer with a RK3568B2 SoC.
+config TARGET_QUARTZ64_RK3566 + bool "Pine64 Quartz64" + help + Pine64 Quartz64 single board computer with a RK3566 SoC. + endchoice
config ROCKCHIP_BOOT_MODE_REG @@ -39,5 +44,6 @@ config SYS_MALLOC_F_LEN source "board/rockchip/evb_rk3568/Kconfig" source "board/anbernic/rgxx3_rk3566/Kconfig" source "board/hardkernel/odroid_m1/Kconfig" +source "board/pine64/quartz64_rk3566/Kconfig"
endif diff --git a/board/pine64/quartz64_rk3566/Kconfig b/board/pine64/quartz64_rk3566/Kconfig new file mode 100644 index 000000000000..3de1d8f7a993 --- /dev/null +++ b/board/pine64/quartz64_rk3566/Kconfig @@ -0,0 +1,15 @@ +if TARGET_QUARTZ64_RK3566 + +config SYS_BOARD + default "quartz64_rk3566" + +config SYS_VENDOR + default "pine64" + +config SYS_CONFIG_NAME + default "quartz64_rk3566" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + +endif diff --git a/board/pine64/quartz64_rk3566/MAINTAINERS b/board/pine64/quartz64_rk3566/MAINTAINERS new file mode 100644 index 000000000000..dbc0dfbd9787 --- /dev/null +++ b/board/pine64/quartz64_rk3566/MAINTAINERS @@ -0,0 +1,9 @@ +QUARTZ64-RK3566 +M: Nicolas Frattaroli frattaroli.nicolas@gmail.com +R: Jonas Karlman jonas@kwiboo.se +S: Maintained +F: board/pine64/quartz64_rk3566/ +F: include/configs/quartz64_rk3566.h +F: configs/quartz64-a-rk3566_defconfig +F: arch/arm/dts/rk3566-quartz64-a.dts +F: arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi diff --git a/board/pine64/quartz64_rk3566/Makefile b/board/pine64/quartz64_rk3566/Makefile new file mode 100644 index 000000000000..c24a40e724d7 --- /dev/null +++ b/board/pine64/quartz64_rk3566/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-y += quartz64-rk3566.o diff --git a/board/pine64/quartz64_rk3566/quartz64-rk3566.c b/board/pine64/quartz64_rk3566/quartz64-rk3566.c new file mode 100644 index 000000000000..4c027f2a7af9 --- /dev/null +++ b/board/pine64/quartz64_rk3566/quartz64-rk3566.c @@ -0,0 +1 @@ +// SPDX-License-Identifier: GPL-2.0+ diff --git a/configs/quartz64-a-rk3566_defconfig b/configs/quartz64-a-rk3566_defconfig new file mode 100644 index 000000000000..d55b224feacd --- /dev/null +++ b/configs/quartz64-a-rk3566_defconfig @@ -0,0 +1,110 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_TEXT_BASE=0x00a00000 +CONFIG_SPL_GPIO=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 +CONFIG_SF_DEFAULT_SPEED=24000000 +CONFIG_SF_DEFAULT_MODE=0x2000 +CONFIG_DEFAULT_DEVICE_TREE="rk3566-quartz64-a" +CONFIG_ROCKCHIP_RK3568=y +CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y +CONFIG_ROCKCHIP_SPI_IMAGE=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_STACK_R_ADDR=0x600000 +CONFIG_TARGET_QUARTZ64_RK3566=y +CONFIG_SPL_STACK=0x400000 +CONFIG_DEBUG_UART_BASE=0xFE660000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI=y +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_PCI=y +CONFIG_DEBUG_UART=y +CONFIG_AHCI=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-quartz64-a.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x4000000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_POWER=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000 +CONFIG_SPL_ATF=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_SCSI_AHCI=y +CONFIG_AHCI_PCI=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_SF_DEFAULT_BUS=4 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_NVME_PCI=y +CONFIG_PCIE_DW_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_SPL_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_SPL_RAM=y +CONFIG_SCSI=y +CONFIG_DM_SCSI=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_ROCKCHIP_SFC=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_ERRNO_STR=y diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index b89f35954d33..c7d4c835db80 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -96,6 +96,7 @@ List of mainline supported Rockchip boards: * rk3568 - Rockchip Evb-RK3568 (evb-rk3568) - Hardkernel ODROID-M1 (odroid-m1-rk3568) + - Pine64 Quartz64-A Board (quartz64-a-rk3566_defconfig)
* rk3588 - Rockchip EVB (evb-rk3588) diff --git a/include/configs/quartz64_rk3566.h b/include/configs/quartz64_rk3566.h new file mode 100644 index 000000000000..dfe0fee94cdb --- /dev/null +++ b/include/configs/quartz64_rk3566.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __QUARTZ64_RK3566_H +#define __QUARTZ64_RK3566_H + +#define ROCKCHIP_DEVICE_SETTINGS + +#include <configs/rk3568_common.h> + +#endif
On 2023-07-23 16:55, Jonas Karlman wrote:
The Pine64 Quartz64 Model A is a single-board computer based on the Rockchip RK3566 SoC. The board features USB3, SATA, PCIe, HDMI, USB2.0, CSI, DSI, eDP, eMMC, SD, and an e-paper parallel port, as well as a 20 pin GPIO header.
Features tested on a Quartz64-A 8GB v2.0 2021-04-27:
- SD-card boot
- eMMC boot
- PCIe/NVMe/AHCI
- USB host
Device tree is imported from linux v6.4.
Co-developed-by: Nicolas Frattaroli frattaroli.nicolas@gmail.com Signed-off-by: Nicolas Frattaroli frattaroli.nicolas@gmail.com Signed-off-by: Jonas Karlman jonas@kwiboo.se
[...]
Boot log with ROCKCHIP_TPL=rk3566_ddr_1056MHz_v1.17.bin and BL31=rk3568_bl31_v1.43.elf:
DDR V1.17 992b933606 typ 23/04/25-10:10:19 ln LP4/4x derate en, other dram:1x trefi ddrconfig:7 LPDDR4X, 324MHz BW=32 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 Size=8192MB tdqss: cs0 dqs0: 72ps, dqs1: -96ps, dqs2: -48ps, dqs3: -144ps, tdqss: cs1 dqs0: 48ps, dqs1: -96ps, dqs2: -48ps, dqs3: -120ps,
change to: 324MHz clk skew:0x61
change to: 528MHz clk skew:0x58
change to: 780MHz clk skew:0x58
change to: 1056MHz(final freq) PHY drv:clk:36,ca:36,DQ:29,odt:60 vrefinner:16%, vrefout:22% dram drv:40,odt:80 vref_ca:00000071 clk skew:0x2f cs 0: the read training result: DQS0:0x3e, DQS1:0x3d, DQS2:0x42, DQS3:0x3a, min : 0xd 0xe 0xe 0xd 0x1 0x2 0x5 0x1 , 0x6 0x7 0x2 0x1 0xa 0x9 0xe 0x9 , 0x10 0xf 0xe 0xa 0x6 0x1 0x1 0x4 , 0xb 0x8 0x4 0x1 0xd 0xa 0x9 0xc , mid :0x2b 0x2c 0x2d 0x2c 0x20 0x22 0x24 0x20 ,0x26 0x26 0x22 0x20 0x2a 0x29 0x2c 0x29 , 0x30 0x2f 0x2d 0x29 0x25 0x20 0x21 0x23 ,0x2a 0x26 0x24 0x20 0x2c 0x29 0x28 0x2b , max :0x49 0x4a 0x4d 0x4c 0x40 0x42 0x43 0x40 ,0x46 0x46 0x43 0x40 0x4b 0x49 0x4b 0x49 , 0x51 0x50 0x4c 0x49 0x45 0x3f 0x41 0x43 ,0x49 0x45 0x44 0x40 0x4c 0x49 0x47 0x4a , range:0x3c 0x3c 0x3f 0x3f 0x3f 0x40 0x3e 0x3f ,0x40 0x3f 0x41 0x3f 0x41 0x40 0x3d 0x40 , 0x41 0x41 0x3e 0x3f 0x3f 0x3e 0x40 0x3f ,0x3e 0x3d 0x40 0x3f 0x3f 0x3f 0x3e 0x3e , the write training result: DQS0:0x38, DQS1:0x23, DQS2:0x29, DQS3:0x1c, min :0x64 0x67 0x68 0x68 0x5b 0x5d 0x5f 0x64 0x62 ,0x4c 0x4d 0x48 0x48 0x50 0x50 0x52 0x50 0x4e , 0x54 0x53 0x51 0x50 0x4c 0x4a 0x4a 0x4e 0x4f ,0x47 0x46 0x44 0x41 0x4a 0x4a 0x48 0x4c 0x45 , mid :0x81 0x83 0x84 0x83 0x77 0x79 0x7c 0x7d 0x7c ,0x6a 0x6a 0x64 0x63 0x6c 0x6b 0x6c 0x6b 0x69 , 0x72 0x71 0x6d 0x6d 0x68 0x61 0x62 0x69 0x6a ,0x65 0x60 0x5f 0x5c 0x65 0x66 0x61 0x68 0x60 , max :0x9e 0xa0 0xa1 0x9e 0x93 0x95 0x99 0x96 0x96 ,0x88 0x87 0x81 0x7e 0x88 0x87 0x87 0x87 0x85 , 0x90 0x8f 0x89 0x8a 0x84 0x79 0x7b 0x85 0x86 ,0x83 0x7b 0x7a 0x77 0x81 0x82 0x7b 0x85 0x7c , range:0x3a 0x39 0x39 0x36 0x38 0x38 0x3a 0x32 0x34 ,0x3c 0x3a 0x39 0x36 0x38 0x37 0x35 0x37 0x37 , 0x3c 0x3c 0x38 0x3a 0x38 0x2f 0x31 0x37 0x37 ,0x3c 0x35 0x36 0x36 0x37 0x38 0x33 0x39 0x37 , cs 1: the read training result: DQS0:0x3c, DQS1:0x3d, DQS2:0x42, DQS3:0x3b, min : 0xc 0xc 0xd 0xc 0x1 0x2 0x6 0x3 , 0x7 0x7 0x2 0x1 0x9 0x9 0xd 0x9 , 0x10 0xf 0xe 0xb 0x7 0x1 0x2 0x5 , 0xa 0x9 0x6 0x1 0xd 0xc 0xb 0xe , mid :0x29 0x2a 0x2c 0x2a 0x20 0x21 0x24 0x20 ,0x26 0x26 0x22 0x21 0x2a 0x29 0x2c 0x28 , 0x2f 0x2e 0x2c 0x2a 0x26 0x20 0x21 0x24 ,0x29 0x27 0x26 0x21 0x2d 0x2c 0x2a 0x2d , max :0x47 0x48 0x4b 0x49 0x3f 0x41 0x43 0x3e ,0x46 0x46 0x42 0x41 0x4b 0x49 0x4b 0x48 , 0x4f 0x4e 0x4a 0x49 0x45 0x40 0x41 0x44 ,0x49 0x46 0x46 0x41 0x4d 0x4c 0x49 0x4d , range:0x3b 0x3c 0x3e 0x3d 0x3e 0x3f 0x3d 0x3b ,0x3f 0x3f 0x40 0x40 0x42 0x40 0x3e 0x3f , 0x3f 0x3f 0x3c 0x3e 0x3e 0x3f 0x3f 0x3f ,0x3f 0x3d 0x40 0x40 0x40 0x40 0x3e 0x3f , the write training result: DQS0:0x38, DQS1:0x23, DQS2:0x29, DQS3:0x1c, min :0x62 0x64 0x65 0x64 0x57 0x59 0x5d 0x5f 0x5c ,0x4b 0x4c 0x46 0x46 0x4e 0x4e 0x52 0x4f 0x4c , 0x54 0x53 0x4f 0x4f 0x4b 0x47 0x49 0x4e 0x4e ,0x4a 0x4a 0x48 0x44 0x4e 0x4c 0x4b 0x4f 0x49 , mid :0x7f 0x80 0x81 0x80 0x74 0x76 0x7a 0x7a 0x78 ,0x68 0x68 0x62 0x61 0x69 0x69 0x6c 0x6a 0x68 , 0x71 0x70 0x6b 0x6b 0x65 0x5f 0x62 0x67 0x69 ,0x68 0x65 0x61 0x5f 0x69 0x69 0x64 0x6c 0x63 , max :0x9c 0x9d 0x9e 0x9c 0x91 0x94 0x97 0x95 0x94 ,0x86 0x84 0x7e 0x7c 0x85 0x85 0x86 0x85 0x84 , 0x8f 0x8d 0x88 0x88 0x80 0x78 0x7b 0x80 0x85 ,0x87 0x81 0x7a 0x7a 0x84 0x87 0x7d 0x89 0x7e , range:0x3a 0x39 0x39 0x38 0x3a 0x3b 0x3a 0x36 0x38 ,0x3b 0x38 0x38 0x36 0x37 0x37 0x34 0x36 0x38 , 0x3b 0x3a 0x39 0x39 0x35 0x31 0x32 0x32 0x37 ,0x3d 0x37 0x32 0x36 0x36 0x3b 0x32 0x3a 0x35 , CA Training result: cs:0 min :0x51 0x50 0x4a 0x43 0x49 0x43 0x4c ,0x4e 0x49 0x48 0x42 0x47 0x3f 0x49 , cs:0 mid :0x8f 0x91 0x84 0x84 0x84 0x84 0x7b ,0x8a 0x89 0x83 0x82 0x82 0x80 0x78 , cs:0 max :0xcd 0xd2 0xbf 0xc6 0xc0 0xc5 0xab ,0xc6 0xc9 0xbf 0xc2 0xbd 0xc1 0xa7 , cs:0 range:0x7c 0x82 0x75 0x83 0x77 0x82 0x5f ,0x78 0x80 0x77 0x80 0x76 0x82 0x5e , cs:1 min :0x4e 0x53 0x45 0x45 0x45 0x45 0x4a ,0x4a 0x4c 0x44 0x46 0x42 0x43 0x48 , cs:1 mid :0x8e 0x90 0x84 0x83 0x84 0x81 0x7b ,0x8a 0x88 0x84 0x83 0x83 0x80 0x78 , cs:1 max :0xcf 0xcd 0xc4 0xc1 0xc3 0xbe 0xad ,0xcb 0xc5 0xc4 0xc0 0xc4 0xbe 0xa9 , cs:1 range:0x81 0x7a 0x7f 0x7c 0x7e 0x79 0x63 ,0x81 0x79 0x80 0x7a 0x82 0x7b 0x61 , out
U-Boot SPL 2023.07 (Jul 23 2023 - 12:42:18 +0000) rockchip_sdhci_probe clk set rate fail! Trying to boot from MMC1 ## Checking hash(es) for config config-1 ... OK ## Checking hash(es) for Image atf-1 ... sha256+ OK ## Checking hash(es) for Image u-boot ... sha256+ OK ## Checking hash(es) for Image fdt-1 ... sha256+ OK ## Checking hash(es) for Image atf-2 ... sha256+ OK ## Checking hash(es) for Image atf-3 ... sha256+ OK ## Checking hash(es) for Image atf-4 ... sha256+ OK ## Checking hash(es) for Image atf-5 ... sha256+ OK ## Checking hash(es) for Image atf-6 ... sha256+ OK INFO: Preloader serial: 2 NOTICE: BL31: v2.3():v2.3-607-gbf602aff1:cl NOTICE: BL31: Built : 10:16:03, Jun 5 2023 INFO: GICv3 without legacy support detected. INFO: ARM GICv3 driver initialized in EL3 INFO: pmu v1 is valid 220114 INFO: dfs DDR fsp_param[0].freq_mhz= 1056MHz INFO: dfs DDR fsp_param[1].freq_mhz= 324MHz INFO: dfs DDR fsp_param[2].freq_mhz= 528MHz INFO: dfs DDR fsp_param[3].freq_mhz= 780MHz INFO: Using opteed sec cpu_context! INFO: boot cpu mask: 0 INFO: BL31: Initializing runtime services WARNING: No OPTEE provided by BL2 boot loader, Booting device without OPTEE initialization. SMC`s destined for OPTEE will return SMC_UNK ERROR: Error initializing runtime service opteed_fast INFO: BL31: Preparing for EL3 exit to normal world INFO: Entry point address = 0xa00000 INFO: SPSR = 0x3c9
U-Boot 2023.07 (Jul 23 2023 - 12:42:18 +0000)
Model: Pine64 RK3566 Quartz64-A Board DRAM: 8 GiB (effective 7.7 GiB) PMIC: RK8170 (on=0x10, off=0x00) Core: 321 devices, 27 uclasses, devicetree: separate MMC: rockchip_sdhci_probe clk set rate fail! mmc@fe2b0000: 1, mmc@fe2c0000: 2, mmc@fe310000: 0 Loading Environment from nowhere... OK In: serial@fe660000 Out: serial@fe660000 Err: serial@fe660000 Model: Pine64 RK3566 Quartz64-A Board Net: No ethernet found.
Hit any key to stop autoboot: 0 =>
Regards, Jonas
Hi Jonas,
On Sun, 2023-07-23 at 15:04 +0000, Jonas Karlman wrote:
On 2023-07-23 16:55, Jonas Karlman wrote:
The Pine64 Quartz64 Model A is a single-board computer based on the Rockchip RK3566 SoC. The board features USB3, SATA, PCIe, HDMI, USB2.0, CSI, DSI, eDP, eMMC, SD, and an e-paper parallel port, as well as a 20 pin GPIO header.
Features tested on a Quartz64-A 8GB v2.0 2021-04-27:
- SD-card boot
- eMMC boot
- PCIe/NVMe/AHCI
- USB host
Device tree is imported from linux v6.4.
Co-developed-by: Nicolas Frattaroli frattaroli.nicolas@gmail.com Signed-off-by: Nicolas Frattaroli frattaroli.nicolas@gmail.com Signed-off-by: Jonas Karlman jonas@kwiboo.se
[...]
Boot log with ROCKCHIP_TPL=rk3566_ddr_1056MHz_v1.17.bin and BL31=rk3568_bl31_v1.43.elf:
[...]
U-Boot 2023.07 (Jul 23 2023 - 12:42:18 +0000)
Model: Pine64 RK3566 Quartz64-A Board DRAM:Â 8 GiB (effective 7.7 GiB) PMIC:Â RK8170 (on=0x10, off=0x00) Core:Â 321 devices, 27 uclasses, devicetree: separate MMC:Â Â rockchip_sdhci_probe clk set rate fail! mmc@fe2b0000: 1, mmc@fe2c0000: 2, mmc@fe310000: 0 Loading Environment from nowhere... OK In:Â Â Â serial@fe660000 Out:Â Â serial@fe660000 Err:Â Â serial@fe660000 Model: Pine64 RK3566 Quartz64-A Board Net:Â Â No ethernet found.
Hit any key to stop autoboot:Â 0 =>
I just tried booting U-Boot v2023.10-rc2 with ROCKCHIP_TPL=rk3566_ddr_1056MHz_v1.17.bin and BL31=rk3568_bl31_v1.43.elf, on my Quartz64-A but it fails during loading of some parts. I removed the output of the RK TPL from my logs as there were no errors.
This is when booting from eMMC.
I also tried building your branch from https://github.com/Kwiboo/u-boot-rockchip/tree/rk3568-2023.10 and
The full build commands:
export ROCKCHIP_TPL=rkbin/bin/rk35/rk3566_ddr_1056MHz_v1.17.bin export BL31=rkbin/bin/rk35/rk3568_bl31_v1.43.elf make quartz64-a-rk3566_defconfig make -j16
rkdeveloptool db rk356x_spl_loader_v1.13.112.bin rkdeveloptool wl 64 u-boot-rockchip.bin
Boot log (v2023.10-rc2):
U-Boot SPL 2023.10-rc2 (Aug 08 2023 - 14:02:34 +0100) rockchip_sdhci_probe clk set rate fail! Trying to boot from MMC1 spl: mmc init failed with error: -110 Trying to boot from MMC2 Card did not respond to voltage select! : -110 spl: mmc init failed with error: -95 Trying to boot from MMC1 ## Checking hash(es) for config config-1 ... OK ## Checking hash(es) for Image atf-1 ... sha256+ OK spl_load_simple_fit: can't load image loadables index 0 (ret = -5) mmc_load_image_raw_sector: mmc block read error SPL: failed to boot from all boot devices ### ERROR ### Please RESET the board ###
Boot log (your branch):
U-Boot SPL 2023.10-rc1-00368-g16cb31d427 (Aug 08 2023 - 15:17:35 +0100) Trying to boot from MMC1 spl: mmc init failed with error: -70 Trying to boot from MMC2 Card did not respond to voltage select! : -110 spl: mmc init failed with error: -95 Trying to boot from MMC1 ## Checking hash(es) for config config-1 ... OK mmc_load_image_raw_sector: mmc block read error SPL: failed to boot from all boot devices ### ERROR ### Please RESET the board ###
Thanks!
Chris
Hi Christopher,
On 2023-08-08 16:25, Christopher Obbard wrote:
Hi Jonas,
On Sun, 2023-07-23 at 15:04 +0000, Jonas Karlman wrote:
On 2023-07-23 16:55, Jonas Karlman wrote:
The Pine64 Quartz64 Model A is a single-board computer based on the Rockchip RK3566 SoC. The board features USB3, SATA, PCIe, HDMI, USB2.0, CSI, DSI, eDP, eMMC, SD, and an e-paper parallel port, as well as a 20 pin GPIO header.
Features tested on a Quartz64-A 8GB v2.0 2021-04-27:
- SD-card boot
- eMMC boot
- PCIe/NVMe/AHCI
- USB host
Device tree is imported from linux v6.4.
Co-developed-by: Nicolas Frattaroli frattaroli.nicolas@gmail.com Signed-off-by: Nicolas Frattaroli frattaroli.nicolas@gmail.com Signed-off-by: Jonas Karlman jonas@kwiboo.se
[...]
Boot log with ROCKCHIP_TPL=rk3566_ddr_1056MHz_v1.17.bin and BL31=rk3568_bl31_v1.43.elf:
[...]
U-Boot 2023.07 (Jul 23 2023 - 12:42:18 +0000)
Model: Pine64 RK3566 Quartz64-A Board DRAM:Â 8 GiB (effective 7.7 GiB) PMIC:Â RK8170 (on=0x10, off=0x00) Core:Â 321 devices, 27 uclasses, devicetree: separate MMC:Â Â rockchip_sdhci_probe clk set rate fail! mmc@fe2b0000: 1, mmc@fe2c0000: 2, mmc@fe310000: 0 Loading Environment from nowhere... OK In:Â Â Â serial@fe660000 Out:Â Â serial@fe660000 Err:Â Â serial@fe660000 Model: Pine64 RK3566 Quartz64-A Board Net:Â Â No ethernet found.
Hit any key to stop autoboot:Â 0 =>
I just tried booting U-Boot v2023.10-rc2 with ROCKCHIP_TPL=rk3566_ddr_1056MHz_v1.17.bin and BL31=rk3568_bl31_v1.43.elf, on my Quartz64-A but it fails during loading of some parts. I removed the output of the RK TPL from my logs as there were no errors.
Try with latest rk3566_ddr_1056MHz_v1.18.bin and see if that makes any difference.
This is when booting from eMMC.
Does it boot with SD-card or other eMMC modules?
I also tried building your branch from https://github.com/Kwiboo/u-boot-rockchip/tree/rk3568-2023.10 and
Please try with a GitHub actions built u-boot-rockchip.bin based on my rk3568-2023.07.02 branch at https://github.com/Kwiboo/u-boot-build/actions/runs/5777761235
The full build commands:
export ROCKCHIP_TPL=rkbin/bin/rk35/rk3566_ddr_1056MHz_v1.17.bin export BL31=rkbin/bin/rk35/rk3568_bl31_v1.43.elf make quartz64-a-rk3566_defconfig make -j16
rkdeveloptool db rk356x_spl_loader_v1.13.112.bin rkdeveloptool wl 64 u-boot-rockchip.bin
What happens if you write u-boot-rockchip.bin to eMMC module usinga USB adapter:
dd if=u-boot-rockchip.bin of=/dev/<device> bs=32k seek=1 conv=fsync
or using U-Boot cmd when booted from a SD-card?
# Read u-boot-rockchip.bin from first partition of a SD card load mmc 1:1 10000000 u-boot-rockchip.bin
# Change to eMMC mmc dev 0
# Write 10 MiB (0x5000 blocks) at sector 64 (0x40) mmc write $fileaddr 40 5000
Does that make any difference?
Boot log (v2023.10-rc2):
U-Boot SPL 2023.10-rc2 (Aug 08 2023 - 14:02:34 +0100) rockchip_sdhci_probe clk set rate fail! Trying to boot from MMC1 spl: mmc init failed with error: -110 Trying to boot from MMC2 Card did not respond to voltage select! : -110 spl: mmc init failed with error: -95 Trying to boot from MMC1
Strange that second try of eMMC (MMC1) gets little bit longer.
## Checking hash(es) for config config-1 ... OK ## Checking hash(es) for Image atf-1 ... sha256+ OK spl_load_simple_fit: can't load image loadables index 0 (ret = -5) mmc_load_image_raw_sector: mmc block read error SPL: failed to boot from all boot devices ### ERROR ### Please RESET the board ###
Boot log (your branch):
U-Boot SPL 2023.10-rc1-00368-g16cb31d427 (Aug 08 2023 - 15:17:35 +0100) Trying to boot from MMC1 spl: mmc init failed with error: -70 Trying to boot from MMC2 Card did not respond to voltage select! : -110 spl: mmc init failed with error: -95 Trying to boot from MMC1 ## Checking hash(es) for config config-1 ... OK mmc_load_image_raw_sector: mmc block read error SPL: failed to boot from all boot devices ### ERROR ### Please RESET the board ###
I have not been able to reproduce this kind of issue on any of my two Quartz64-A boards, tested with different eMMC modules.
Does your eMMC module have some compatibility issue? Do you have any more details on the eMMC module you have tested with?
There was also some clk and pinctrl changes recently merged into master branch, but they was probably included in the build from my branch based on the lack of "rockchip_sdhci_probe clk set rate fail!" message.
Regards, Jonas
Thanks!
Chris
Hi Jonas,
Sorry for the late response, I've been meaning to test this for a while but not got around to it.
On Thu, 2023-08-17 at 23:56 +0000, Jonas Karlman wrote:
Hi Christopher,
On 2023-08-08 16:25, Christopher Obbard wrote:
Hi Jonas,
On Sun, 2023-07-23 at 15:04 +0000, Jonas Karlman wrote:
On 2023-07-23 16:55, Jonas Karlman wrote:
The Pine64 Quartz64 Model A is a single-board computer based on the Rockchip RK3566 SoC. The board features USB3, SATA, PCIe, HDMI, USB2.0, CSI, DSI, eDP, eMMC, SD, and an e-paper parallel port, as well as a 20 pin GPIO header.
Features tested on a Quartz64-A 8GB v2.0 2021-04-27:
- SD-card boot
- eMMC boot
- PCIe/NVMe/AHCI
- USB host
Device tree is imported from linux v6.4.
Co-developed-by: Nicolas Frattaroli frattaroli.nicolas@gmail.com Signed-off-by: Nicolas Frattaroli frattaroli.nicolas@gmail.com Signed-off-by: Jonas Karlman jonas@kwiboo.se
[...]
Boot log with ROCKCHIP_TPL=rk3566_ddr_1056MHz_v1.17.bin and BL31=rk3568_bl31_v1.43.elf:
[...]
U-Boot 2023.07 (Jul 23 2023 - 12:42:18 +0000)
Model: Pine64 RK3566 Quartz64-A Board DRAM:Â 8 GiB (effective 7.7 GiB) PMIC:Â RK8170 (on=0x10, off=0x00) Core:Â 321 devices, 27 uclasses, devicetree: separate MMC:Â Â rockchip_sdhci_probe clk set rate fail! mmc@fe2b0000: 1, mmc@fe2c0000: 2, mmc@fe310000: 0 Loading Environment from nowhere... OK In:Â Â Â serial@fe660000 Out:Â Â serial@fe660000 Err:Â Â serial@fe660000 Model: Pine64 RK3566 Quartz64-A Board Net:Â Â No ethernet found.
Hit any key to stop autoboot:Â 0 =>
I just tried booting U-Boot v2023.10-rc2 with ROCKCHIP_TPL=rk3566_ddr_1056MHz_v1.17.bin and BL31=rk3568_bl31_v1.43.elf, on my Quartz64-A but it fails during loading of some parts. I removed the output of the RK TPL from my logs as there were no errors.
Try with latest rk3566_ddr_1056MHz_v1.18.bin and see if that makes any difference.
No difference.
I've also checked, there is no other maskrom bootable media such as SPI flash connected to the board.
This is when booting from eMMC.
Does it boot with SD-card or other eMMC modules?
Booting from SD card (without eMMC connected), everything works fine.
I also tried building your branch from https://github.com/Kwiboo/u-boot-rockchip/tree/rk3568-2023.10%C2%A0and
Please try with a GitHub actions built u-boot-rockchip.bin based on my rk3568-2023.07.02 branch at https://github.com/Kwiboo/u-boot-build/actions/runs/5777761235
With that exact artifact, flashed with:
rkdeveloptool db rk356x_spl_loader_v1.18.113.bin rkdeveloptool ef rkdeveloptool wl 64 u-boot-rockchip.bin rkdeveloptool rd
it fails to boot with with:
DDR V1.18 f366f69a7d typ 23/07/17-15:48:58 ln LP4/4x derate en, other dram:1x trefi SRX ddrconfig:7 LPDDR4X, 324MHz BW=32 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 Size=8192MB
change to: 324MHz clk skew:0x60
change to: 528MHz clk skew:0x58
change to: 780MHz clk skew:0x58
change to: 1056MHz(final freq) clk skew:0x32 out
U-Boot SPL 2023.07.02-g09919887 (Aug 06 2023 - 16:59:31 +0000) Trying to boot from MMC1 spl: mmc init failed with error: -70 Trying to boot from MMC2 Card did not respond to voltage select! : -110 spl: mmc init failed with error: -95 Trying to boot from MMC1 mmc fail to send stop cmd mmc_load_image_raw_sector: mmc block read error SPL: failed to boot from all boot devices ### ERROR ### Please RESET the board ###
I also tried a second eMMC, but it also failed to boot with the same "mmc block read error" message.
What happens if you write u-boot-rockchip.bin to eMMC module usinga USB adapter:
dd if=u-boot-rockchip.bin of=/dev/<device> bs=32k seek=1 conv=fsync
or using U-Boot cmd when booted from a SD-card?
# Read u-boot-rockchip.bin from first partition of a SD card  load mmc 1:1 10000000 u-boot-rockchip.bin
# Change to eMMC Â mmc dev 0
# Write 10 MiB (0x5000 blocks) at sector 64 (0x40) Â mmc write $fileaddr 40 5000
Does that make any difference?
I don't think I have an eMMC writer for Pine64 eMMCs, I will try to get hold of one this week. But it fails to write to the eMMC with:
=> load mmc 1:2 10000000 u-boot-rockchip.bin 9510400 bytes read in 791 ms (11.5 MiB/s)
=> mmc dev 0 switch to partitions #0, OK mmc0(part 0) is current device
=> mmc write $fileaddr 40 5000 MMC write: dev # 0, block # 64, count 20480 ... mmc write failed 0 blocks written: ERROR
=> mmc info Device: mmc@fe310000 Manufacturer ID: 45 OEM: 0 Name: DF4016 Bus Speed: 52000000 Mode: MMC DDR52 (52MHz) Rd Block Len: 512 MMC version 5.1 High Capacity: Yes Capacity: 14.7 GiB Bus Width: 8-bit DDR Erase Group Size: 512 KiB HC WP Group Size: 8 MiB User Capacity: 14.7 GiB WRREL Boot Capacity: 4 MiB ENH RPMB Capacity: 4 MiB ENH
I think this points to some issue with the mmc driver in U-Boot, or possibly some issue with my board. But I find that hard to believe because the Rockchip usbloader seems to write to the eMMC just fine ?
Boot log (v2023.10-rc2):
U-Boot SPL 2023.10-rc2 (Aug 08 2023 - 14:02:34 +0100) rockchip_sdhci_probe clk set rate fail! Trying to boot from MMC1 spl: mmc init failed with error: -110 Trying to boot from MMC2 Card did not respond to voltage select! : -110 spl: mmc init failed with error: -95 Trying to boot from MMC1
Strange that second try of eMMC (MMC1) gets little bit longer.
## Checking hash(es) for config config-1 ... OK ## Checking hash(es) for Image atf-1 ... sha256+ OK spl_load_simple_fit: can't load image loadables index 0 (ret = -5) mmc_load_image_raw_sector: mmc block read error SPL: failed to boot from all boot devices ### ERROR ### Please RESET the board ###
Boot log (your branch):
U-Boot SPL 2023.10-rc1-00368-g16cb31d427 (Aug 08 2023 - 15:17:35 +0100) Trying to boot from MMC1 spl: mmc init failed with error: -70 Trying to boot from MMC2 Card did not respond to voltage select! : -110 spl: mmc init failed with error: -95 Trying to boot from MMC1 ## Checking hash(es) for config config-1 ... OK mmc_load_image_raw_sector: mmc block read error SPL: failed to boot from all boot devices ### ERROR ### Please RESET the board ###
I have not been able to reproduce this kind of issue on any of my two Quartz64-A boards, tested with different eMMC modules.
Does your eMMC module have some compatibility issue? Do you have any more details on the eMMC module you have tested with?
I have two eMMCs, one from FORESEE which came with a Pine64 and one marked SanDisk (which I posted the mmc info for above).
My hardware is marked Quartz64-RK3399-V2.0 2021-04-27 Maybe there is some difference with your board?
I will also try an image with vendor u-boot as a next step.
There was also some clk and pinctrl changes recently merged into master branch, but they was probably included in the build from my branch based on the lack of "rockchip_sdhci_probe clk set rate fail!" message.
I tried with your build, but I will investigate more with master.
Thanks!
Chris
Hi Jonas,
On Thu, 2023-10-12 at 10:51 +0100, Christopher Obbard wrote:
Hi Jonas,
Sorry for the late response, I've been meaning to test this for a while but not got around to it.
On Thu, 2023-08-17 at 23:56 +0000, Jonas Karlman wrote:
Hi Christopher,
On 2023-08-08 16:25, Christopher Obbard wrote:
Hi Jonas,
On Sun, 2023-07-23 at 15:04 +0000, Jonas Karlman wrote:
On 2023-07-23 16:55, Jonas Karlman wrote:
The Pine64 Quartz64 Model A is a single-board computer based on the Rockchip RK3566 SoC. The board features USB3, SATA, PCIe, HDMI, USB2.0, CSI, DSI, eDP, eMMC, SD, and an e-paper parallel port, as well as a 20 pin GPIO header.
Features tested on a Quartz64-A 8GB v2.0 2021-04-27:
- SD-card boot
- eMMC boot
- PCIe/NVMe/AHCI
- USB host
Device tree is imported from linux v6.4.
Co-developed-by: Nicolas Frattaroli frattaroli.nicolas@gmail.com Signed-off-by: Nicolas Frattaroli frattaroli.nicolas@gmail.com Signed-off-by: Jonas Karlman jonas@kwiboo.se
[...]
Boot log with ROCKCHIP_TPL=rk3566_ddr_1056MHz_v1.17.bin and BL31=rk3568_bl31_v1.43.elf:
[...]
U-Boot 2023.07 (Jul 23 2023 - 12:42:18 +0000)
Model: Pine64 RK3566 Quartz64-A Board DRAM:Â 8 GiB (effective 7.7 GiB) PMIC:Â RK8170 (on=0x10, off=0x00) Core:Â 321 devices, 27 uclasses, devicetree: separate MMC:Â Â rockchip_sdhci_probe clk set rate fail! mmc@fe2b0000: 1, mmc@fe2c0000: 2, mmc@fe310000: 0 Loading Environment from nowhere... OK In:Â Â Â serial@fe660000 Out:Â Â serial@fe660000 Err:Â Â serial@fe660000 Model: Pine64 RK3566 Quartz64-A Board Net:Â Â No ethernet found.
Hit any key to stop autoboot:Â 0 =>
I just tried booting U-Boot v2023.10-rc2 with ROCKCHIP_TPL=rk3566_ddr_1056MHz_v1.17.bin and BL31=rk3568_bl31_v1.43.elf, on my Quartz64-A but it fails during loading of some parts. I removed the output of the RK TPL from my logs as there were no errors.
Try with latest rk3566_ddr_1056MHz_v1.18.bin and see if that makes any difference.
No difference.
I've also checked, there is no other maskrom bootable media such as SPI flash connected to the board.
This is when booting from eMMC.
Does it boot with SD-card or other eMMC modules?
Booting from SD card (without eMMC connected), everything works fine.
I also tried building your branch from https://github.com/Kwiboo/u-boot-rockchip/tree/rk3568-2023.10%C2%A0and
Please try with a GitHub actions built u-boot-rockchip.bin based on my rk3568-2023.07.02 branch at https://github.com/Kwiboo/u-boot-build/actions/runs/5777761235
With that exact artifact, flashed with:
rkdeveloptool db rk356x_spl_loader_v1.18.113.bin rkdeveloptool ef rkdeveloptool wl 64 u-boot-rockchip.bin rkdeveloptool rd
it fails to boot with with:
DDR V1.18 f366f69a7d typ 23/07/17-15:48:58 ln LP4/4x derate en, other dram:1x trefi SRX ddrconfig:7 LPDDR4X, 324MHz BW=32 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 Size=8192MB
change to: 324MHz clk skew:0x60
change to: 528MHz clk skew:0x58
change to: 780MHz clk skew:0x58
change to: 1056MHz(final freq) clk skew:0x32 out
U-Boot SPL 2023.07.02-g09919887 (Aug 06 2023 - 16:59:31 +0000) Trying to boot from MMC1 spl: mmc init failed with error: -70 Trying to boot from MMC2 Card did not respond to voltage select! : -110 spl: mmc init failed with error: -95 Trying to boot from MMC1 mmc fail to send stop cmd mmc_load_image_raw_sector: mmc block read error SPL: failed to boot from all boot devices ### ERROR ### Please RESET the board ###
I also tried a second eMMC, but it also failed to boot with the same "mmc block read error" message.
I tried with your latest branch https://github.com/Kwiboo/u-boot-rockchip/commits/rk3568-2023.10
and this time a different error message, loading from the eMMC appears to get a bit further:
U-Boot SPL 2023.10-00054-gef68159087 (Oct 12 2023 - 12:14:22 +0100) Trying to boot from MMC1 ## Checking hash(es) for config config-1 ... OK ## Checking hash(es) for Image atf-1 ... sha256+ OK spl_load_simple_fit: can't load image loadables index 0 (ret = -5) mmc_load_image_raw_sector: mmc block read error Trying to boot from MMC2 Card did not respond to voltage select! : -110 spl: mmc init failed with error: -95 Trying to boot from MMC1 mmc_load_image_raw_sector: mmc block read error SPL: failed to boot from all boot devices ### ERROR ### Please RESET the board ###
So this is pointing to an issue reading from the MMC...
I found https://lists.denx.de/pipermail/u-boot/2023-April/514315.html (which is applied to your branch) and added the following to defconfig:
CONFIG_MMC_SDHCI_SDMA=y +# CONFIG_SPL_MMC_SDHCI_SDMA is not set
but this seemed to make the loading less reliable:
U-Boot SPL 2023.10-00054-gef68159087-dirty (Oct 12 2023 - 12:23:10 +0100) Trying to boot from MMC1 ## Checking hash(es) for config config-1 ... OK mmc fail to send stop cmd mmc_load_image_raw_sector: mmc block read error Trying to boot from MMC2 Card did not respond to voltage select! : -110 spl: mmc init failed with error: -95 Trying to boot from MMC1 mmc_load_image_raw_sector: mmc block read error SPL: failed to boot from all boot devices ### ERROR ### Please RESET the board ###
...
What happens if you write u-boot-rockchip.bin to eMMC module usinga USB adapter:
dd if=u-boot-rockchip.bin of=/dev/<device> bs=32k seek=1 conv=fsync
or using U-Boot cmd when booted from a SD-card?
# Read u-boot-rockchip.bin from first partition of a SD card  load mmc 1:1 10000000 u-boot-rockchip.bin
# Change to eMMC Â mmc dev 0
# Write 10 MiB (0x5000 blocks) at sector 64 (0x40) Â mmc write $fileaddr 40 5000
Does that make any difference?
I don't think I have an eMMC writer for Pine64 eMMCs, I will try to get hold of one this week.
I have two USB writers. Anyway, the first boot, it fails with:
U-Boot SPL 2023.10-00054-gef68159087 (Oct 12 2023 - 12:30:14 +0100) Trying to boot from MMC1 ## Checking hash(es) for config config-1 ... OK ## Checking hash(es) for Image atf-1 ... sha256+ OK ## Checking hash(es) for Image u-boot ... sha256+ OK
<hang>
Then again after a reset:
U-Boot SPL 2023.10-00054-gef68159087 (Oct 12 2023 - 12:30:14 +0100) Trying to boot from MMC1 mmc fail to send stop cmd mmc_load_image_raw_sector: mmc block read error Trying to boot from MMC2 Card did not respond to voltage select! : -110 spl: mmc init failed with error: -95 Trying to boot from MMC1 mmc_load_image_raw_sector: mmc block read error SPL: failed to boot from all boot devices ### ERROR ### Please RESET the board ###
But it fails to write to the eMMC with:
=> load mmc 1:2 10000000 u-boot-rockchip.bin 9510400 bytes read in 791 ms (11.5 MiB/s)
=> mmc dev 0 switch to partitions #0, OK mmc0(part 0) is current device
=> mmc write $fileaddr 40 5000 MMC write: dev # 0, block # 64, count 20480 ... mmc write failed 0 blocks written: ERROR
=> mmc info Device: mmc@fe310000 Manufacturer ID: 45 OEM: 0 Name: DF4016 Bus Speed: 52000000 Mode: MMC DDR52 (52MHz) Rd Block Len: 512 MMC version 5.1 High Capacity: Yes Capacity: 14.7 GiB Bus Width: 8-bit DDR Erase Group Size: 512 KiB HC WP Group Size: 8 MiB User Capacity: 14.7 GiB WRREL Boot Capacity: 4 MiB ENH RPMB Capacity: 4 MiB ENH
I think this points to some issue with the mmc driver in U-Boot, or possibly some issue with my board. But I find that hard to believe because the Rockchip usbloader seems to write to the eMMC just fine ?
Boot log (v2023.10-rc2):
U-Boot SPL 2023.10-rc2 (Aug 08 2023 - 14:02:34 +0100) rockchip_sdhci_probe clk set rate fail! Trying to boot from MMC1 spl: mmc init failed with error: -110 Trying to boot from MMC2 Card did not respond to voltage select! : -110 spl: mmc init failed with error: -95 Trying to boot from MMC1
Strange that second try of eMMC (MMC1) gets little bit longer.
## Checking hash(es) for config config-1 ... OK ## Checking hash(es) for Image atf-1 ... sha256+ OK spl_load_simple_fit: can't load image loadables index 0 (ret = -5) mmc_load_image_raw_sector: mmc block read error SPL: failed to boot from all boot devices ### ERROR ### Please RESET the board ###
Boot log (your branch):
U-Boot SPL 2023.10-rc1-00368-g16cb31d427 (Aug 08 2023 - 15:17:35 +0100) Trying to boot from MMC1 spl: mmc init failed with error: -70 Trying to boot from MMC2 Card did not respond to voltage select! : -110 spl: mmc init failed with error: -95 Trying to boot from MMC1 ## Checking hash(es) for config config-1 ... OK mmc_load_image_raw_sector: mmc block read error SPL: failed to boot from all boot devices ### ERROR ### Please RESET the board ###
I have not been able to reproduce this kind of issue on any of my two Quartz64-A boards, tested with different eMMC modules.
Does your eMMC module have some compatibility issue? Do you have any more details on the eMMC module you have tested with?
I have two eMMCs, one from FORESEE which came with a Pine64 and one marked SanDisk (which I posted the mmc info for above).
My hardware is marked Quartz64-RK3399-V2.0 2021-04-27 Maybe there is some difference with your board?
I will also try an image with vendor u-boot as a next step.
I tried latest Armbian (which seems to use ) from https://github.com/armbian/build/releases/ and flashed the eMMC with the USB writer. It ended up booting to Linux, which proves that the hardware I have is most likey in a good working order ;-)!
U-Boot SPL 2022.10-rc4-armbian (Feb 11 2023 - 22:25:16 +0000) saradc@fe720000: Can't update Vdd. Error: -38saradc@fe720000: Can't update Vss. Error: -38can't get vref-supply: -38 rockchip_dnl_key_pressed: adc_channel_single_shot fail! Trying to boot from MMC2 INFO: Preloader serial: 2 NOTICE: BL31: v2.3():v2.3-152-g4e725b15f:cl NOTICE: BL31: Built : 10:51:13, Jul 15 2021 INFO: GICv3 without legacy support detected. INFO: ARM GICv3 driver initialized in EL3 INFO: pmu v1 is valid INFO: dfs DDR fsp_param[0].freq_mhz= 1560MHz INFO: dfs DDR fsp_param[1].freq_mhz= 324MHz INFO: dfs DDR fsp_param[2].freq_mhz= 528MHz INFO: dfs DDR fsp_param[3].freq_mhz= 780MHz INFO: Using opteed sec cpu_context! INFO: boot cpu mask: 0 INFO: BL31: Initializing runtime services WARNING: No OPTEE provided by BL2 boot loader, Booting device without OPTEE initialization. SMC`s destined for OPTEE will return SMC_UNK ERROR: Error initializing runtime service opteed_fast INFO: BL31: Preparing for EL3 exit to normal world INFO: Entry point address = 0xa00000 INFO: SPSR = 0x3c9
U-Boot 2022.10-rc4-armbian (Feb 11 2023 - 22:25:16 +0000)
Model: Pine64 RK3566 Quartz64-A Board DRAM: 2 GiB PMIC: RK8170 (on=0x10, off=0x00) Core: 266 devices, 21 uclasses, devicetree: separate MMC: mmc@fe2b0000: 1, mmc@fe310000: 0 Loading Environment from nowhere... OK In: serial@fe660000 Out: serial@fe660000 Err: serial@fe660000 Model: Pine64 RK3566 Quartz64-A Board can't get vref-supply: -2 rockchip_dnl_key_pressed: adc_channel_single_shot fail! Net: No ethernet found. Hit any key to stop autoboot: 0 starting USB... Bus usb@fcc00000: Port not available. Bus usb@fd000000: Port not available. Bus usb@fd800000: USB EHCI 1.00 Bus usb@fd840000: USB OHCI 1.0 Bus usb@fd880000: USB EHCI 1.00 Bus usb@fd8c0000: USB OHCI 1.0 scanning bus usb@fd800000 for devices... 1 USB Device(s) found scanning bus usb@fd840000 for devices... ERROR: USB-error: DEVICENOTRESPONDING: Device did not respond to token (IN) or did not provide a handshake (OUT) (5) ERROR: USB-error: DEVICENOTRESPONDING: Device did not respond to token (IN) or did not provide a handshake (OUT) (5) unable to get device descriptor (error=-1) 1 USB Device(s) found scanning bus usb@fd880000 for devices... 1 USB Device(s) found scanning bus usb@fd8c0000 for devices... 1 USB Device(s) found scanning usb for storage devices... 0 Storage Device(s) found
Device 0: unknown device Card did not respond to voltage select! : -110 switch to partitions #0, OK mmc0(part 0) is current device Scanning mmc 0:1... Found /boot/extlinux/extlinux.conf Retrieving file: /boot/extlinux/extlinux.conf 1: Armbian Retrieving file: /boot/uInitrd Retrieving file: /boot/Image append: root=UUID=7f9c9970-93ba-46ca-9f03-f3241712ead8 console=ttyS02,1500000 console=tty0 rw no_console_suspend consoleblank=0 fsck.fix=yes fsck.repair=yes net.ifnames=0 splash plymouth.ignore- serial-consoles Retrieving file: /boot/dtb/rockchip/rk3566-quartz64-a.dtb Moving Image from 0x2080000 to 0x2200000, end=3de0000 ## Loading init Ramdisk from Legacy Image at 0a200000 ... Image Name: uInitrd Image Type: AArch64 Linux RAMDisk Image (gzip compressed) Data Size: 34402446 Bytes = 32.8 MiB Load Address: 00000000 Entry Point: 00000000 Verifying Checksum ... OK ## Flattened Device Tree blob at 0a100000 Booting using the fdt blob at 0xa100000 Loading Ramdisk to 7be16000, end 7dee508e ... OK Loading Device Tree to 000000007bdf7000, end 000000007be158e2 ... OK
Starting kernel ...
efi_free_pool: illegal free 0x000000007cee7040 efi_free_pool: illegal free 0x000000007cee4040 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050] [ 0.000000] Linux version 6.2.0-rc6-media (root@d00a59921686) (aarch64-linux-gnu-gcc (GNU Toolchain for the A-profile Architecture 8.3-2019.03 (arm-rel-8.36)) 8.3.0, GNU ld (GNU Toolchain for the A-profile Architecture 8.3-2019.03 (arm-rel-8.36)) 2.32.0.20190321) #trunk.0252 SMP PREEMPT_DYNAMIC Sat Feb 11 22:41:21 UTC 2023 [ 0.000000] Machine model: Pine64 RK3566 Quartz64-A Board
Thanks!
Chris
Hi Christopher,
On 2023-10-12 13:46, Christopher Obbard wrote:
Hi Jonas,
On Thu, 2023-10-12 at 10:51 +0100, Christopher Obbard wrote:
Hi Jonas,
Sorry for the late response, I've been meaning to test this for a while but not got around to it.
On Thu, 2023-08-17 at 23:56 +0000, Jonas Karlman wrote:
Hi Christopher,
On 2023-08-08 16:25, Christopher Obbard wrote:
Hi Jonas,
On Sun, 2023-07-23 at 15:04 +0000, Jonas Karlman wrote:
On 2023-07-23 16:55, Jonas Karlman wrote:
The Pine64 Quartz64 Model A is a single-board computer based on the Rockchip RK3566 SoC. The board features USB3, SATA, PCIe, HDMI, USB2.0, CSI, DSI, eDP, eMMC, SD, and an e-paper parallel port, as well as a 20 pin GPIO header.
Features tested on a Quartz64-A 8GB v2.0 2021-04-27:
- SD-card boot
- eMMC boot
- PCIe/NVMe/AHCI
- USB host
Device tree is imported from linux v6.4.
Co-developed-by: Nicolas Frattaroli frattaroli.nicolas@gmail.com Signed-off-by: Nicolas Frattaroli frattaroli.nicolas@gmail.com Signed-off-by: Jonas Karlman jonas@kwiboo.se
[...]
Boot log with ROCKCHIP_TPL=rk3566_ddr_1056MHz_v1.17.bin and BL31=rk3568_bl31_v1.43.elf:
[...]
U-Boot 2023.07 (Jul 23 2023 - 12:42:18 +0000)
Model: Pine64 RK3566 Quartz64-A Board DRAM:Â 8 GiB (effective 7.7 GiB) PMIC:Â RK8170 (on=0x10, off=0x00) Core:Â 321 devices, 27 uclasses, devicetree: separate MMC:Â Â rockchip_sdhci_probe clk set rate fail! mmc@fe2b0000: 1, mmc@fe2c0000: 2, mmc@fe310000: 0 Loading Environment from nowhere... OK In:Â Â Â serial@fe660000 Out:Â Â serial@fe660000 Err:Â Â serial@fe660000 Model: Pine64 RK3566 Quartz64-A Board Net:Â Â No ethernet found.
Hit any key to stop autoboot:Â 0 =>
I just tried booting U-Boot v2023.10-rc2 with ROCKCHIP_TPL=rk3566_ddr_1056MHz_v1.17.bin and BL31=rk3568_bl31_v1.43.elf, on my Quartz64-A but it fails during loading of some parts. I removed the output of the RK TPL from my logs as there were no errors.
Try with latest rk3566_ddr_1056MHz_v1.18.bin and see if that makes any difference.
No difference.
I've also checked, there is no other maskrom bootable media such as SPI flash connected to the board.
This is when booting from eMMC.
Does it boot with SD-card or other eMMC modules?
Booting from SD card (without eMMC connected), everything works fine.
I also tried building your branch from https://github.com/Kwiboo/u-boot-rockchip/tree/rk3568-2023.10
Please try with a GitHub actions built u-boot-rockchip.bin based on my rk3568-2023.07.02 branch at https://github.com/Kwiboo/u-boot-build/actions/runs/5777761235
With that exact artifact, flashed with:
rkdeveloptool db rk356x_spl_loader_v1.18.113.bin rkdeveloptool ef rkdeveloptool wl 64 u-boot-rockchip.bin rkdeveloptool rd
it fails to boot with with:
DDR V1.18 f366f69a7d typ 23/07/17-15:48:58 ln LP4/4x derate en, other dram:1x trefi SRX ddrconfig:7 LPDDR4X, 324MHz BW=32 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 Size=8192MB
change to: 324MHz clk skew:0x60
change to: 528MHz clk skew:0x58
change to: 780MHz clk skew:0x58
change to: 1056MHz(final freq) clk skew:0x32 out
U-Boot SPL 2023.07.02-g09919887 (Aug 06 2023 - 16:59:31 +0000) Trying to boot from MMC1 spl: mmc init failed with error: -70 Trying to boot from MMC2 Card did not respond to voltage select! : -110 spl: mmc init failed with error: -95 Trying to boot from MMC1 mmc fail to send stop cmd mmc_load_image_raw_sector: mmc block read error SPL: failed to boot from all boot devices ### ERROR ### Please RESET the board ###
I also tried a second eMMC, but it also failed to boot with the same "mmc block read error" message.
I tried with your latest branch https://github.com/Kwiboo/u-boot-rockchip/commits/rk3568-2023.10
and this time a different error message, loading from the eMMC appears to get a bit further:
U-Boot SPL 2023.10-00054-gef68159087 (Oct 12 2023 - 12:14:22 +0100) Trying to boot from MMC1 ## Checking hash(es) for config config-1 ... OK ## Checking hash(es) for Image atf-1 ... sha256+ OK spl_load_simple_fit: can't load image loadables index 0 (ret = -5) mmc_load_image_raw_sector: mmc block read error Trying to boot from MMC2 Card did not respond to voltage select! : -110 spl: mmc init failed with error: -95 Trying to boot from MMC1 mmc_load_image_raw_sector: mmc block read error SPL: failed to boot from all boot devices ### ERROR ### Please RESET the board ###
So this is pointing to an issue reading from the MMC...
I found https://lists.denx.de/pipermail/u-boot/2023-April/514315.html (which is applied to your branch) and added the following to defconfig:
CONFIG_MMC_SDHCI_SDMA=y +# CONFIG_SPL_MMC_SDHCI_SDMA is not set
but this seemed to make the loading less reliable:
U-Boot SPL 2023.10-00054-gef68159087-dirty (Oct 12 2023 - 12:23:10 +0100) Trying to boot from MMC1 ## Checking hash(es) for config config-1 ... OK mmc fail to send stop cmd mmc_load_image_raw_sector: mmc block read error Trying to boot from MMC2 Card did not respond to voltage select! : -110 spl: mmc init failed with error: -95 Trying to boot from MMC1 mmc_load_image_raw_sector: mmc block read error SPL: failed to boot from all boot devices ### ERROR ### Please RESET the board ###
Thanks for testing different combinations.
I did find an issue with emmc write using ddr52 and hs400 modes on rk3568. On rk3588 emmc write only worked reliable after hs200 mode had been used.
Please try the changes from following commit, or my rk35xx-2024.01 work-in-progress branch:
WIP: rockchip: rk35xx: improve emmc write https://github.com/Kwiboo/u-boot-rockchip/commit/aa6156179bb2034e8ba26753e05...
Most rk356x boards currently default to ddr52 mode, and possible emmc read is also affected with similar issue as emmc write.
I have also discovered a strange issue on an Amlogic soc related to U-Boot mmc commands and gcc optimization, please see following patch: https://patchwork.ozlabs.org/patch/1839392/
Please try with CONFIG_MMC_TRACE=y to see what commands fails on your device.
If above patches does not work also try with following options applied:
CONFIG_MMC_HS200_SUPPORT=y CONFIG_SPL_MMC_HS200_SUPPORT=y
Use of HS200 seem to be the most reliable option on rk35xx based on my limited testing.
...
What happens if you write u-boot-rockchip.bin to eMMC module usinga USB adapter:
dd if=u-boot-rockchip.bin of=/dev/<device> bs=32k seek=1 conv=fsync
or using U-Boot cmd when booted from a SD-card?
# Read u-boot-rockchip.bin from first partition of a SD card  load mmc 1:1 10000000 u-boot-rockchip.bin
# Change to eMMC Â mmc dev 0
# Write 10 MiB (0x5000 blocks) at sector 64 (0x40) Â mmc write $fileaddr 40 5000
Does that make any difference?
I don't think I have an eMMC writer for Pine64 eMMCs, I will try to get hold of one this week.
I have two USB writers. Anyway, the first boot, it fails with:
U-Boot SPL 2023.10-00054-gef68159087 (Oct 12 2023 - 12:30:14 +0100) Trying to boot from MMC1 ## Checking hash(es) for config config-1 ... OK ## Checking hash(es) for Image atf-1 ... sha256+ OK ## Checking hash(es) for Image u-boot ... sha256+ OK
<hang>
Then again after a reset:
U-Boot SPL 2023.10-00054-gef68159087 (Oct 12 2023 - 12:30:14 +0100) Trying to boot from MMC1 mmc fail to send stop cmd mmc_load_image_raw_sector: mmc block read error Trying to boot from MMC2 Card did not respond to voltage select! : -110 spl: mmc init failed with error: -95 Trying to boot from MMC1 mmc_load_image_raw_sector: mmc block read error SPL: failed to boot from all boot devices ### ERROR ### Please RESET the board ###
But it fails to write to the eMMC with:
=> load mmc 1:2 10000000 u-boot-rockchip.bin 9510400 bytes read in 791 ms (11.5 MiB/s)
=> mmc dev 0 switch to partitions #0, OK mmc0(part 0) is current device
=> mmc write $fileaddr 40 5000 MMC write: dev # 0, block # 64, count 20480 ... mmc write failed 0 blocks written: ERROR
=> mmc info Device: mmc@fe310000 Manufacturer ID: 45 OEM: 0 Name: DF4016 Bus Speed: 52000000 Mode: MMC DDR52 (52MHz) Rd Block Len: 512 MMC version 5.1 High Capacity: Yes Capacity: 14.7 GiB Bus Width: 8-bit DDR Erase Group Size: 512 KiB HC WP Group Size: 8 MiB User Capacity: 14.7 GiB WRREL Boot Capacity: 4 MiB ENH RPMB Capacity: 4 MiB ENH
I think this points to some issue with the mmc driver in U-Boot, or possibly some issue with my board. But I find that hard to believe because the Rockchip usbloader seems to write to the eMMC just fine ?
Probably related to sdhci driver and rx/tx tap and/or delay num etc.
Boot log (v2023.10-rc2):
U-Boot SPL 2023.10-rc2 (Aug 08 2023 - 14:02:34 +0100) rockchip_sdhci_probe clk set rate fail! Trying to boot from MMC1 spl: mmc init failed with error: -110 Trying to boot from MMC2 Card did not respond to voltage select! : -110 spl: mmc init failed with error: -95 Trying to boot from MMC1
Strange that second try of eMMC (MMC1) gets little bit longer.
## Checking hash(es) for config config-1 ... OK ## Checking hash(es) for Image atf-1 ... sha256+ OK spl_load_simple_fit: can't load image loadables index 0 (ret = -5) mmc_load_image_raw_sector: mmc block read error SPL: failed to boot from all boot devices ### ERROR ### Please RESET the board ###
Boot log (your branch):
U-Boot SPL 2023.10-rc1-00368-g16cb31d427 (Aug 08 2023 - 15:17:35 +0100) Trying to boot from MMC1 spl: mmc init failed with error: -70 Trying to boot from MMC2 Card did not respond to voltage select! : -110 spl: mmc init failed with error: -95 Trying to boot from MMC1 ## Checking hash(es) for config config-1 ... OK mmc_load_image_raw_sector: mmc block read error SPL: failed to boot from all boot devices ### ERROR ### Please RESET the board ###
I have not been able to reproduce this kind of issue on any of my two Quartz64-A boards, tested with different eMMC modules.
Does your eMMC module have some compatibility issue? Do you have any more details on the eMMC module you have tested with?
I have two eMMCs, one from FORESEE which came with a Pine64 and one marked SanDisk (which I posted the mmc info for above).
My eMMC modules is also FORESEE or SanDisk, from Pine64, Radxa and Hardkernel.
My hardware is marked Quartz64-RK3399-V2.0 2021-04-27 Maybe there is some difference with your board?
Should match my board, I have the hw revision where SATA port is removed. (boards with/without SATA have same version silk on the board)
I will also try an image with vendor u-boot as a next step.
I tried latest Armbian (which seems to use ) from https://github.com/armbian/build/releases/ and flashed the eMMC with the USB writer. It ended up booting to Linux, which proves that the hardware I have is most likey in a good working order ;-)!
Hopefully the issue is related to the peephole2 optimization issue or the use of a not fully supported ddr52 mode.
Regards, Jonas
U-Boot SPL 2022.10-rc4-armbian (Feb 11 2023 - 22:25:16 +0000) saradc@fe720000: Can't update Vdd. Error: -38saradc@fe720000: Can't update Vss. Error: -38can't get vref-supply: -38 rockchip_dnl_key_pressed: adc_channel_single_shot fail! Trying to boot from MMC2 INFO: Preloader serial: 2 NOTICE: BL31: v2.3():v2.3-152-g4e725b15f:cl NOTICE: BL31: Built : 10:51:13, Jul 15 2021 INFO: GICv3 without legacy support detected. INFO: ARM GICv3 driver initialized in EL3 INFO: pmu v1 is valid INFO: dfs DDR fsp_param[0].freq_mhz= 1560MHz INFO: dfs DDR fsp_param[1].freq_mhz= 324MHz INFO: dfs DDR fsp_param[2].freq_mhz= 528MHz INFO: dfs DDR fsp_param[3].freq_mhz= 780MHz INFO: Using opteed sec cpu_context! INFO: boot cpu mask: 0 INFO: BL31: Initializing runtime services WARNING: No OPTEE provided by BL2 boot loader, Booting device without OPTEE initialization. SMC`s destined for OPTEE will return SMC_UNK ERROR: Error initializing runtime service opteed_fast INFO: BL31: Preparing for EL3 exit to normal world INFO: Entry point address = 0xa00000 INFO: SPSR = 0x3c9
U-Boot 2022.10-rc4-armbian (Feb 11 2023 - 22:25:16 +0000)
Model: Pine64 RK3566 Quartz64-A Board DRAM: 2 GiB PMIC: RK8170 (on=0x10, off=0x00) Core: 266 devices, 21 uclasses, devicetree: separate MMC: mmc@fe2b0000: 1, mmc@fe310000: 0 Loading Environment from nowhere... OK In: serial@fe660000 Out: serial@fe660000 Err: serial@fe660000 Model: Pine64 RK3566 Quartz64-A Board can't get vref-supply: -2 rockchip_dnl_key_pressed: adc_channel_single_shot fail! Net: No ethernet found. Hit any key to stop autoboot: 0 starting USB... Bus usb@fcc00000: Port not available. Bus usb@fd000000: Port not available. Bus usb@fd800000: USB EHCI 1.00 Bus usb@fd840000: USB OHCI 1.0 Bus usb@fd880000: USB EHCI 1.00 Bus usb@fd8c0000: USB OHCI 1.0 scanning bus usb@fd800000 for devices... 1 USB Device(s) found scanning bus usb@fd840000 for devices... ERROR: USB-error: DEVICENOTRESPONDING: Device did not respond to token (IN) or did not provide a handshake (OUT) (5) ERROR: USB-error: DEVICENOTRESPONDING: Device did not respond to token (IN) or did not provide a handshake (OUT) (5) unable to get device descriptor (error=-1) 1 USB Device(s) found scanning bus usb@fd880000 for devices... 1 USB Device(s) found scanning bus usb@fd8c0000 for devices... 1 USB Device(s) found scanning usb for storage devices... 0 Storage Device(s) found
Device 0: unknown device Card did not respond to voltage select! : -110 switch to partitions #0, OK mmc0(part 0) is current device Scanning mmc 0:1... Found /boot/extlinux/extlinux.conf Retrieving file: /boot/extlinux/extlinux.conf 1: Armbian Retrieving file: /boot/uInitrd Retrieving file: /boot/Image append: root=UUID=7f9c9970-93ba-46ca-9f03-f3241712ead8 console=ttyS02,1500000 console=tty0 rw no_console_suspend consoleblank=0 fsck.fix=yes fsck.repair=yes net.ifnames=0 splash plymouth.ignore- serial-consoles Retrieving file: /boot/dtb/rockchip/rk3566-quartz64-a.dtb Moving Image from 0x2080000 to 0x2200000, end=3de0000 ## Loading init Ramdisk from Legacy Image at 0a200000 ... Image Name: uInitrd Image Type: AArch64 Linux RAMDisk Image (gzip compressed) Data Size: 34402446 Bytes = 32.8 MiB Load Address: 00000000 Entry Point: 00000000 Verifying Checksum ... OK ## Flattened Device Tree blob at 0a100000 Booting using the fdt blob at 0xa100000 Loading Ramdisk to 7be16000, end 7dee508e ... OK Loading Device Tree to 000000007bdf7000, end 000000007be158e2 ... OK
Starting kernel ...
efi_free_pool: illegal free 0x000000007cee7040 efi_free_pool: illegal free 0x000000007cee4040 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050] [ 0.000000] Linux version 6.2.0-rc6-media (root@d00a59921686) (aarch64-linux-gnu-gcc (GNU Toolchain for the A-profile Architecture 8.3-2019.03 (arm-rel-8.36)) 8.3.0, GNU ld (GNU Toolchain for the A-profile Architecture 8.3-2019.03 (arm-rel-8.36)) 2.32.0.20190321) #trunk.0252 SMP PREEMPT_DYNAMIC Sat Feb 11 22:41:21 UTC 2023 [ 0.000000] Machine model: Pine64 RK3566 Quartz64-A Board
Thanks!
Chris
On 2023-10-14 20:58, Jonas Karlman wrote:
Hi Christopher,
On 2023-10-12 13:46, Christopher Obbard wrote:
Hi Jonas,
On Thu, 2023-10-12 at 10:51 +0100, Christopher Obbard wrote:
Hi Jonas,
Sorry for the late response, I've been meaning to test this for a while but not got around to it.
On Thu, 2023-08-17 at 23:56 +0000, Jonas Karlman wrote:
Hi Christopher,
On 2023-08-08 16:25, Christopher Obbard wrote:
Hi Jonas,
On Sun, 2023-07-23 at 15:04 +0000, Jonas Karlman wrote:
On 2023-07-23 16:55, Jonas Karlman wrote: > The Pine64 Quartz64 Model A is a single-board computer based on the > Rockchip RK3566 SoC. The board features USB3, SATA, PCIe, HDMI, USB2.0, > CSI, DSI, eDP, eMMC, SD, and an e-paper parallel port, as well as a > 20 pin GPIO header. > > Features tested on a Quartz64-A 8GB v2.0 2021-04-27: > - SD-card boot > - eMMC boot > - PCIe/NVMe/AHCI > - USB host > > Device tree is imported from linux v6.4. > > Co-developed-by: Nicolas Frattaroli frattaroli.nicolas@gmail.com > Signed-off-by: Nicolas Frattaroli frattaroli.nicolas@gmail.com > Signed-off-by: Jonas Karlman jonas@kwiboo.se > ---
[...]
Boot log with ROCKCHIP_TPL=rk3566_ddr_1056MHz_v1.17.bin and BL31=rk3568_bl31_v1.43.elf:
[...]
U-Boot 2023.07 (Jul 23 2023 - 12:42:18 +0000)
Model: Pine64 RK3566 Quartz64-A Board DRAM:Â 8 GiB (effective 7.7 GiB) PMIC:Â RK8170 (on=0x10, off=0x00) Core:Â 321 devices, 27 uclasses, devicetree: separate MMC:Â Â rockchip_sdhci_probe clk set rate fail! mmc@fe2b0000: 1, mmc@fe2c0000: 2, mmc@fe310000: 0 Loading Environment from nowhere... OK In:Â Â Â serial@fe660000 Out:Â Â serial@fe660000 Err:Â Â serial@fe660000 Model: Pine64 RK3566 Quartz64-A Board Net:Â Â No ethernet found.
Hit any key to stop autoboot:Â 0 =>
I just tried booting U-Boot v2023.10-rc2 with ROCKCHIP_TPL=rk3566_ddr_1056MHz_v1.17.bin and BL31=rk3568_bl31_v1.43.elf, on my Quartz64-A but it fails during loading of some parts. I removed the output of the RK TPL from my logs as there were no errors.
Try with latest rk3566_ddr_1056MHz_v1.18.bin and see if that makes any difference.
No difference.
I've also checked, there is no other maskrom bootable media such as SPI flash connected to the board.
This is when booting from eMMC.
Does it boot with SD-card or other eMMC modules?
Booting from SD card (without eMMC connected), everything works fine.
I also tried building your branch from https://github.com/Kwiboo/u-boot-rockchip/tree/rk3568-2023.10
Please try with a GitHub actions built u-boot-rockchip.bin based on my rk3568-2023.07.02 branch at https://github.com/Kwiboo/u-boot-build/actions/runs/5777761235
With that exact artifact, flashed with:
rkdeveloptool db rk356x_spl_loader_v1.18.113.bin rkdeveloptool ef rkdeveloptool wl 64 u-boot-rockchip.bin rkdeveloptool rd
it fails to boot with with:
DDR V1.18 f366f69a7d typ 23/07/17-15:48:58 ln LP4/4x derate en, other dram:1x trefi SRX ddrconfig:7 LPDDR4X, 324MHz BW=32 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 Size=8192MB
change to: 324MHz clk skew:0x60
change to: 528MHz clk skew:0x58
change to: 780MHz clk skew:0x58
change to: 1056MHz(final freq) clk skew:0x32 out
U-Boot SPL 2023.07.02-g09919887 (Aug 06 2023 - 16:59:31 +0000) Trying to boot from MMC1 spl: mmc init failed with error: -70 Trying to boot from MMC2 Card did not respond to voltage select! : -110 spl: mmc init failed with error: -95 Trying to boot from MMC1 mmc fail to send stop cmd mmc_load_image_raw_sector: mmc block read error SPL: failed to boot from all boot devices ### ERROR ### Please RESET the board ###
I also tried a second eMMC, but it also failed to boot with the same "mmc block read error" message.
I tried with your latest branch https://github.com/Kwiboo/u-boot-rockchip/commits/rk3568-2023.10
and this time a different error message, loading from the eMMC appears to get a bit further:
U-Boot SPL 2023.10-00054-gef68159087 (Oct 12 2023 - 12:14:22 +0100) Trying to boot from MMC1 ## Checking hash(es) for config config-1 ... OK ## Checking hash(es) for Image atf-1 ... sha256+ OK spl_load_simple_fit: can't load image loadables index 0 (ret = -5) mmc_load_image_raw_sector: mmc block read error Trying to boot from MMC2 Card did not respond to voltage select! : -110 spl: mmc init failed with error: -95 Trying to boot from MMC1 mmc_load_image_raw_sector: mmc block read error SPL: failed to boot from all boot devices ### ERROR ### Please RESET the board ###
So this is pointing to an issue reading from the MMC...
I found https://lists.denx.de/pipermail/u-boot/2023-April/514315.html (which is applied to your branch) and added the following to defconfig:
CONFIG_MMC_SDHCI_SDMA=y +# CONFIG_SPL_MMC_SDHCI_SDMA is not set
but this seemed to make the loading less reliable:
U-Boot SPL 2023.10-00054-gef68159087-dirty (Oct 12 2023 - 12:23:10 +0100) Trying to boot from MMC1 ## Checking hash(es) for config config-1 ... OK mmc fail to send stop cmd mmc_load_image_raw_sector: mmc block read error Trying to boot from MMC2 Card did not respond to voltage select! : -110 spl: mmc init failed with error: -95 Trying to boot from MMC1 mmc_load_image_raw_sector: mmc block read error SPL: failed to boot from all boot devices ### ERROR ### Please RESET the board ###
Thanks for testing different combinations.
I did find an issue with emmc write using ddr52 and hs400 modes on rk3568. On rk3588 emmc write only worked reliable after hs200 mode had been used.
Please try the changes from following commit, or my rk35xx-2024.01 work-in-progress branch:
WIP: rockchip: rk35xx: improve emmc write https://github.com/Kwiboo/u-boot-rockchip/commit/aa6156179bb2034e8ba26753e05...
Most rk356x boards currently default to ddr52 mode, and possible emmc read is also affected with similar issue as emmc write.
I have also discovered a strange issue on an Amlogic soc related to U-Boot mmc commands and gcc optimization, please see following patch: https://patchwork.ozlabs.org/patch/1839392/
Posted link to wrong patch, I meant the following patch:
[RFC] mmc: Remove alignment hole for cmdidx in struct mmc_cmd https://patchwork.ozlabs.org/patch/1841495/
Regards, Jonas
Please try with CONFIG_MMC_TRACE=y to see what commands fails on your device.
If above patches does not work also try with following options applied:
CONFIG_MMC_HS200_SUPPORT=y CONFIG_SPL_MMC_HS200_SUPPORT=y
Use of HS200 seem to be the most reliable option on rk35xx based on my limited testing.
...
What happens if you write u-boot-rockchip.bin to eMMC module usinga USB adapter:
dd if=u-boot-rockchip.bin of=/dev/<device> bs=32k seek=1 conv=fsync
or using U-Boot cmd when booted from a SD-card?
# Read u-boot-rockchip.bin from first partition of a SD card  load mmc 1:1 10000000 u-boot-rockchip.bin
# Change to eMMC Â mmc dev 0
# Write 10 MiB (0x5000 blocks) at sector 64 (0x40) Â mmc write $fileaddr 40 5000
Does that make any difference?
I don't think I have an eMMC writer for Pine64 eMMCs, I will try to get hold of one this week.
I have two USB writers. Anyway, the first boot, it fails with:
U-Boot SPL 2023.10-00054-gef68159087 (Oct 12 2023 - 12:30:14 +0100) Trying to boot from MMC1 ## Checking hash(es) for config config-1 ... OK ## Checking hash(es) for Image atf-1 ... sha256+ OK ## Checking hash(es) for Image u-boot ... sha256+ OK
<hang>
Then again after a reset:
U-Boot SPL 2023.10-00054-gef68159087 (Oct 12 2023 - 12:30:14 +0100) Trying to boot from MMC1 mmc fail to send stop cmd mmc_load_image_raw_sector: mmc block read error Trying to boot from MMC2 Card did not respond to voltage select! : -110 spl: mmc init failed with error: -95 Trying to boot from MMC1 mmc_load_image_raw_sector: mmc block read error SPL: failed to boot from all boot devices ### ERROR ### Please RESET the board ###
But it fails to write to the eMMC with:
=> load mmc 1:2 10000000 u-boot-rockchip.bin 9510400 bytes read in 791 ms (11.5 MiB/s)
=> mmc dev 0 switch to partitions #0, OK mmc0(part 0) is current device
=> mmc write $fileaddr 40 5000 MMC write: dev # 0, block # 64, count 20480 ... mmc write failed 0 blocks written: ERROR
=> mmc info Device: mmc@fe310000 Manufacturer ID: 45 OEM: 0 Name: DF4016 Bus Speed: 52000000 Mode: MMC DDR52 (52MHz) Rd Block Len: 512 MMC version 5.1 High Capacity: Yes Capacity: 14.7 GiB Bus Width: 8-bit DDR Erase Group Size: 512 KiB HC WP Group Size: 8 MiB User Capacity: 14.7 GiB WRREL Boot Capacity: 4 MiB ENH RPMB Capacity: 4 MiB ENH
I think this points to some issue with the mmc driver in U-Boot, or possibly some issue with my board. But I find that hard to believe because the Rockchip usbloader seems to write to the eMMC just fine ?
Probably related to sdhci driver and rx/tx tap and/or delay num etc.
Boot log (v2023.10-rc2):
U-Boot SPL 2023.10-rc2 (Aug 08 2023 - 14:02:34 +0100) rockchip_sdhci_probe clk set rate fail! Trying to boot from MMC1 spl: mmc init failed with error: -110 Trying to boot from MMC2 Card did not respond to voltage select! : -110 spl: mmc init failed with error: -95 Trying to boot from MMC1
Strange that second try of eMMC (MMC1) gets little bit longer.
## Checking hash(es) for config config-1 ... OK ## Checking hash(es) for Image atf-1 ... sha256+ OK spl_load_simple_fit: can't load image loadables index 0 (ret = -5) mmc_load_image_raw_sector: mmc block read error SPL: failed to boot from all boot devices ### ERROR ### Please RESET the board ###
Boot log (your branch):
U-Boot SPL 2023.10-rc1-00368-g16cb31d427 (Aug 08 2023 - 15:17:35 +0100) Trying to boot from MMC1 spl: mmc init failed with error: -70 Trying to boot from MMC2 Card did not respond to voltage select! : -110 spl: mmc init failed with error: -95 Trying to boot from MMC1 ## Checking hash(es) for config config-1 ... OK mmc_load_image_raw_sector: mmc block read error SPL: failed to boot from all boot devices ### ERROR ### Please RESET the board ###
I have not been able to reproduce this kind of issue on any of my two Quartz64-A boards, tested with different eMMC modules.
Does your eMMC module have some compatibility issue? Do you have any more details on the eMMC module you have tested with?
I have two eMMCs, one from FORESEE which came with a Pine64 and one marked SanDisk (which I posted the mmc info for above).
My eMMC modules is also FORESEE or SanDisk, from Pine64, Radxa and Hardkernel.
My hardware is marked Quartz64-RK3399-V2.0 2021-04-27 Maybe there is some difference with your board?
Should match my board, I have the hw revision where SATA port is removed. (boards with/without SATA have same version silk on the board)
I will also try an image with vendor u-boot as a next step.
I tried latest Armbian (which seems to use ) from https://github.com/armbian/build/releases/ and flashed the eMMC with the USB writer. It ended up booting to Linux, which proves that the hardware I have is most likey in a good working order ;-)!
Hopefully the issue is related to the peephole2 optimization issue or the use of a not fully supported ddr52 mode.
Regards, Jonas
U-Boot SPL 2022.10-rc4-armbian (Feb 11 2023 - 22:25:16 +0000) saradc@fe720000: Can't update Vdd. Error: -38saradc@fe720000: Can't update Vss. Error: -38can't get vref-supply: -38 rockchip_dnl_key_pressed: adc_channel_single_shot fail! Trying to boot from MMC2 INFO: Preloader serial: 2 NOTICE: BL31: v2.3():v2.3-152-g4e725b15f:cl NOTICE: BL31: Built : 10:51:13, Jul 15 2021 INFO: GICv3 without legacy support detected. INFO: ARM GICv3 driver initialized in EL3 INFO: pmu v1 is valid INFO: dfs DDR fsp_param[0].freq_mhz= 1560MHz INFO: dfs DDR fsp_param[1].freq_mhz= 324MHz INFO: dfs DDR fsp_param[2].freq_mhz= 528MHz INFO: dfs DDR fsp_param[3].freq_mhz= 780MHz INFO: Using opteed sec cpu_context! INFO: boot cpu mask: 0 INFO: BL31: Initializing runtime services WARNING: No OPTEE provided by BL2 boot loader, Booting device without OPTEE initialization. SMC`s destined for OPTEE will return SMC_UNK ERROR: Error initializing runtime service opteed_fast INFO: BL31: Preparing for EL3 exit to normal world INFO: Entry point address = 0xa00000 INFO: SPSR = 0x3c9
U-Boot 2022.10-rc4-armbian (Feb 11 2023 - 22:25:16 +0000)
Model: Pine64 RK3566 Quartz64-A Board DRAM: 2 GiB PMIC: RK8170 (on=0x10, off=0x00) Core: 266 devices, 21 uclasses, devicetree: separate MMC: mmc@fe2b0000: 1, mmc@fe310000: 0 Loading Environment from nowhere... OK In: serial@fe660000 Out: serial@fe660000 Err: serial@fe660000 Model: Pine64 RK3566 Quartz64-A Board can't get vref-supply: -2 rockchip_dnl_key_pressed: adc_channel_single_shot fail! Net: No ethernet found. Hit any key to stop autoboot: 0 starting USB... Bus usb@fcc00000: Port not available. Bus usb@fd000000: Port not available. Bus usb@fd800000: USB EHCI 1.00 Bus usb@fd840000: USB OHCI 1.0 Bus usb@fd880000: USB EHCI 1.00 Bus usb@fd8c0000: USB OHCI 1.0 scanning bus usb@fd800000 for devices... 1 USB Device(s) found scanning bus usb@fd840000 for devices... ERROR: USB-error: DEVICENOTRESPONDING: Device did not respond to token (IN) or did not provide a handshake (OUT) (5) ERROR: USB-error: DEVICENOTRESPONDING: Device did not respond to token (IN) or did not provide a handshake (OUT) (5) unable to get device descriptor (error=-1) 1 USB Device(s) found scanning bus usb@fd880000 for devices... 1 USB Device(s) found scanning bus usb@fd8c0000 for devices... 1 USB Device(s) found scanning usb for storage devices... 0 Storage Device(s) found
Device 0: unknown device Card did not respond to voltage select! : -110 switch to partitions #0, OK mmc0(part 0) is current device Scanning mmc 0:1... Found /boot/extlinux/extlinux.conf Retrieving file: /boot/extlinux/extlinux.conf 1: Armbian Retrieving file: /boot/uInitrd Retrieving file: /boot/Image append: root=UUID=7f9c9970-93ba-46ca-9f03-f3241712ead8 console=ttyS02,1500000 console=tty0 rw no_console_suspend consoleblank=0 fsck.fix=yes fsck.repair=yes net.ifnames=0 splash plymouth.ignore- serial-consoles Retrieving file: /boot/dtb/rockchip/rk3566-quartz64-a.dtb Moving Image from 0x2080000 to 0x2200000, end=3de0000 ## Loading init Ramdisk from Legacy Image at 0a200000 ... Image Name: uInitrd Image Type: AArch64 Linux RAMDisk Image (gzip compressed) Data Size: 34402446 Bytes = 32.8 MiB Load Address: 00000000 Entry Point: 00000000 Verifying Checksum ... OK ## Flattened Device Tree blob at 0a100000 Booting using the fdt blob at 0xa100000 Loading Ramdisk to 7be16000, end 7dee508e ... OK Loading Device Tree to 000000007bdf7000, end 000000007be158e2 ... OK
Starting kernel ...
efi_free_pool: illegal free 0x000000007cee7040 efi_free_pool: illegal free 0x000000007cee4040 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050] [ 0.000000] Linux version 6.2.0-rc6-media (root@d00a59921686) (aarch64-linux-gnu-gcc (GNU Toolchain for the A-profile Architecture 8.3-2019.03 (arm-rel-8.36)) 8.3.0, GNU ld (GNU Toolchain for the A-profile Architecture 8.3-2019.03 (arm-rel-8.36)) 2.32.0.20190321) #trunk.0252 SMP PREEMPT_DYNAMIC Sat Feb 11 22:41:21 UTC 2023 [ 0.000000] Machine model: Pine64 RK3566 Quartz64-A Board
Thanks!
Chris
Hi Jonas,
On Sat, 2023-10-14 at 21:22 +0200, Jonas Karlman wrote:
On 2023-10-14 20:58, Jonas Karlman wrote:
Hi Christopher,
On 2023-10-12 13:46, Christopher Obbard wrote:
Hi Jonas,
On Thu, 2023-10-12 at 10:51 +0100, Christopher Obbard wrote:
Hi Jonas,
Sorry for the late response, I've been meaning to test this for a while but not got around to it.
On Thu, 2023-08-17 at 23:56 +0000, Jonas Karlman wrote:
Hi Christopher,
On 2023-08-08 16:25, Christopher Obbard wrote:
Hi Jonas,
On Sun, 2023-07-23 at 15:04 +0000, Jonas Karlman wrote: > On 2023-07-23 16:55, Jonas Karlman wrote: > > The Pine64 Quartz64 Model A is a single-board computer based on the > > Rockchip RK3566 SoC. The board features USB3, SATA, PCIe, HDMI, USB2.0, > > CSI, DSI, eDP, eMMC, SD, and an e-paper parallel port, as well as a > > 20 pin GPIO header. > > > > Features tested on a Quartz64-A 8GB v2.0 2021-04-27: > > - SD-card boot > > - eMMC boot > > - PCIe/NVMe/AHCI > > - USB host > > > > Device tree is imported from linux v6.4. > > > > Co-developed-by: Nicolas Frattaroli frattaroli.nicolas@gmail.com > > Signed-off-by: Nicolas Frattaroli frattaroli.nicolas@gmail.com > > Signed-off-by: Jonas Karlman jonas@kwiboo.se > > --- > > [...] > > Boot log with ROCKCHIP_TPL=rk3566_ddr_1056MHz_v1.17.bin and > BL31=rk3568_bl31_v1.43.elf: > > [...] > > U-Boot 2023.07 (Jul 23 2023 - 12:42:18 +0000) > > Model: Pine64 RK3566 Quartz64-A Board > DRAM:Â 8 GiB (effective 7.7 GiB) > PMIC:Â RK8170 (on=0x10, off=0x00) > Core:Â 321 devices, 27 uclasses, devicetree: separate > MMC:Â Â rockchip_sdhci_probe clk set rate fail! > mmc@fe2b0000: 1, mmc@fe2c0000: 2, mmc@fe310000: 0 > Loading Environment from nowhere... OK > In:Â Â Â serial@fe660000 > Out:Â Â serial@fe660000 > Err:Â Â serial@fe660000 > Model: Pine64 RK3566 Quartz64-A Board > Net:Â Â No ethernet found. > > Hit any key to stop autoboot:Â 0 > =>
I just tried booting U-Boot v2023.10-rc2 with ROCKCHIP_TPL=rk3566_ddr_1056MHz_v1.17.bin and BL31=rk3568_bl31_v1.43.elf, on my Quartz64-A but it fails during loading of some parts. I removed the output of the RK TPL from my logs as there were no errors.
Try with latest rk3566_ddr_1056MHz_v1.18.bin and see if that makes any difference.
No difference.
I've also checked, there is no other maskrom bootable media such as SPI flash connected to the board.
This is when booting from eMMC.
Does it boot with SD-card or other eMMC modules?
Booting from SD card (without eMMC connected), everything works fine.
I also tried building your branch from https://github.com/Kwiboo/u-boot-rockchip/tree/rk3568-2023.10
Please try with a GitHub actions built u-boot-rockchip.bin based on my rk3568-2023.07.02 branch at https://github.com/Kwiboo/u-boot-build/actions/runs/5777761235
With that exact artifact, flashed with:
rkdeveloptool db rk356x_spl_loader_v1.18.113.bin rkdeveloptool ef rkdeveloptool wl 64 u-boot-rockchip.bin rkdeveloptool rd
it fails to boot with with:
DDR V1.18 f366f69a7d typ 23/07/17-15:48:58 ln LP4/4x derate en, other dram:1x trefi SRX ddrconfig:7 LPDDR4X, 324MHz BW=32 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 Size=8192MB
change to: 324MHz clk skew:0x60
change to: 528MHz clk skew:0x58
change to: 780MHz clk skew:0x58
change to: 1056MHz(final freq) clk skew:0x32 out
U-Boot SPL 2023.07.02-g09919887 (Aug 06 2023 - 16:59:31 +0000) Trying to boot from MMC1 spl: mmc init failed with error: -70 Trying to boot from MMC2 Card did not respond to voltage select! : -110 spl: mmc init failed with error: -95 Trying to boot from MMC1 mmc fail to send stop cmd mmc_load_image_raw_sector: mmc block read error SPL: failed to boot from all boot devices ### ERROR ### Please RESET the board ###
I also tried a second eMMC, but it also failed to boot with the same "mmc block read error" message.
I tried with your latest branch https://github.com/Kwiboo/u-boot-rockchip/commits/rk3568-2023.10
and this time a different error message, loading from the eMMC appears to get a bit further:
U-Boot SPL 2023.10-00054-gef68159087 (Oct 12 2023 - 12:14:22 +0100) Trying to boot from MMC1 ## Checking hash(es) for config config-1 ... OK ## Checking hash(es) for Image atf-1 ... sha256+ OK spl_load_simple_fit: can't load image loadables index 0 (ret = -5) mmc_load_image_raw_sector: mmc block read error Trying to boot from MMC2 Card did not respond to voltage select! : -110 spl: mmc init failed with error: -95 Trying to boot from MMC1 mmc_load_image_raw_sector: mmc block read error SPL: failed to boot from all boot devices ### ERROR ### Please RESET the board ###
So this is pointing to an issue reading from the MMC...
I found https://lists.denx.de/pipermail/u-boot/2023-April/514315.html%C2%A0(which is applied to your branch) and added the following to defconfig:
CONFIG_MMC_SDHCI_SDMA=y +# CONFIG_SPL_MMC_SDHCI_SDMA is not set
but this seemed to make the loading less reliable:
U-Boot SPL 2023.10-00054-gef68159087-dirty (Oct 12 2023 - 12:23:10 +0100) Trying to boot from MMC1 ## Checking hash(es) for config config-1 ... OK mmc fail to send stop cmd mmc_load_image_raw_sector: mmc block read error Trying to boot from MMC2 Card did not respond to voltage select! : -110 spl: mmc init failed with error: -95 Trying to boot from MMC1 mmc_load_image_raw_sector: mmc block read error SPL: failed to boot from all boot devices ### ERROR ### Please RESET the board ###
Thanks for testing different combinations.
I did find an issue with emmc write using ddr52 and hs400 modes on rk3568. On rk3588 emmc write only worked reliable after hs200 mode had been used.
Please try the changes from following commit, or my rk35xx-2024.01 work-in-progress branch:
WIP: rockchip: rk35xx: improve emmc write https://github.com/Kwiboo/u-boot-rockchip/commit/aa6156179bb2034e8ba26753e05...
Most rk356x boards currently default to ddr52 mode, and possible emmc read is also affected with similar issue as emmc write.
I have also discovered a strange issue on an Amlogic soc related to U-Boot mmc commands and gcc optimization, please see following patch: https://patchwork.ozlabs.org/patch/1839392/
Posted link to wrong patch, I meant the following patch:
[RFC] mmc: Remove alignment hole for cmdidx in struct mmc_cmd https://patchwork.ozlabs.org/patch/1841495/
I just tried with your branch & this patch on top, it still fails to boot and seems to be random how far it gets through the loading phase. Again I've removed the ddr training log. It seems to get further this time though...
Boot #1:
U-Boot SPL 2023.10-00055-g29313fff30 (Oct 17 2023 - 09:44:21 +0100) Trying to boot from MMC1 ## Checking hash(es) for config config-1 ... OK ## Checking hash(es) for Image atf-1 ... sha256+ OK ## Checking hash(es) for Image u-boot ... sha256+ OK
<crash>
Boot #2:
U-Boot SPL 2023.10-00055-g29313fff30 (Oct 17 2023 - 09:44:21 +0100) Trying to boot from MMC1 ## Checking hash(es) for config config-1 ... OK ## Checking hash(es) for Image atf-1 ... sha256+ OK ## Checking hash(es) for Image u-boot ... sha256+ OK ## Checking hash(es) for Image fdt-1 ... sha256+ OK ## Checking hash(es) for Image atf-2 ... sha256+ OK ## Checking hash(es) for Image atf-3 ... sha256+ OK ## Checking hash(es) for Image atf-4 ... sha256+ OK spl_load_simple_fit: can't load image loadables index 4 (ret = -5) mmc_load_image_raw_sector: mmc block read error Trying to boot from MMC2 Card did not respond to voltage select! : -110 spl: mmc init failed with error: -95 Trying to boot from MMC1 mmc_load_image_raw_sector: mmc block read error SPL: failed to boot from all boot devices ### ERROR ### Please RESET the board ###
Boot #3:
U-Boot SPL 2023.10-00055-g29313fff30 (Oct 17 2023 - 09:44:21 +0100) Trying to boot from MMC1 ## Checking hash(es) for config config-1 ... OK ## Checking hash(es) for Image atf-1 ... sha256+ OK ## Checking hash(es) for Image u-boot ... sha256+ OK ## Checking hash(es) for Image fdt-1 ... sha256+ OK ## Checking hash(es) for Image atf-2 ... sha256+ OK ## Checking hash(es) for Image atf-3 ... sha256+ OK ## Checking hash(es) for Image atf-4 ... sha256+ OK spl_load_simple_fit: can't load image loadables index 4 (ret = -5) mmc_load_image_raw_sector: mmc block read error Trying to boot from MMC2 Card did not respond to voltage select! : -110 spl: mmc init failed with error: -95 Trying to boot from MMC1 mmc_load_image_raw_sector: mmc block read error SPL: failed to boot from all boot devices ### ERROR ### Please RESET the board ###
For reference I am using gcc from Debian unstable:
$ aarch64-linux-gnu-gcc --version aarch64-linux-gnu-gcc (Debian 13.2.0-2) 13.2.0
I can test with alternative cross-compiler if that would be useful.
Thanks, Chris
Regards, Jonas
Please try with CONFIG_MMC_TRACE=y to see what commands fails on your device.
If above patches does not work also try with following options applied:
CONFIG_MMC_HS200_SUPPORT=y CONFIG_SPL_MMC_HS200_SUPPORT=y
Use of HS200 seem to be the most reliable option on rk35xx based on my limited testing.
...
What happens if you write u-boot-rockchip.bin to eMMC module usinga USB adapter:
dd if=u-boot-rockchip.bin of=/dev/<device> bs=32k seek=1 conv=fsync
or using U-Boot cmd when booted from a SD-card?
# Read u-boot-rockchip.bin from first partition of a SD card  load mmc 1:1 10000000 u-boot-rockchip.bin
# Change to eMMC Â mmc dev 0
# Write 10 MiB (0x5000 blocks) at sector 64 (0x40) Â mmc write $fileaddr 40 5000
Does that make any difference?
I don't think I have an eMMC writer for Pine64 eMMCs, I will try to get hold of one this week.
I have two USB writers. Anyway, the first boot, it fails with:
U-Boot SPL 2023.10-00054-gef68159087 (Oct 12 2023 - 12:30:14 +0100) Trying to boot from MMC1 ## Checking hash(es) for config config-1 ... OK ## Checking hash(es) for Image atf-1 ... sha256+ OK ## Checking hash(es) for Image u-boot ... sha256+ OK
<hang>
Then again after a reset:
U-Boot SPL 2023.10-00054-gef68159087 (Oct 12 2023 - 12:30:14 +0100) Trying to boot from MMC1 mmc fail to send stop cmd mmc_load_image_raw_sector: mmc block read error Trying to boot from MMC2 Card did not respond to voltage select! : -110 spl: mmc init failed with error: -95 Trying to boot from MMC1 mmc_load_image_raw_sector: mmc block read error SPL: failed to boot from all boot devices ### ERROR ### Please RESET the board ###
But it fails to write to the eMMC with:
=> load mmc 1:2 10000000 u-boot-rockchip.bin 9510400 bytes read in 791 ms (11.5 MiB/s)
=> mmc dev 0 switch to partitions #0, OK mmc0(part 0) is current device
=> mmc write $fileaddr 40 5000 MMC write: dev # 0, block # 64, count 20480 ... mmc write failed 0 blocks written: ERROR
=> mmc info Device: mmc@fe310000 Manufacturer ID: 45 OEM: 0 Name: DF4016 Bus Speed: 52000000 Mode: MMC DDR52 (52MHz) Rd Block Len: 512 MMC version 5.1 High Capacity: Yes Capacity: 14.7 GiB Bus Width: 8-bit DDR Erase Group Size: 512 KiB HC WP Group Size: 8 MiB User Capacity: 14.7 GiB WRREL Boot Capacity: 4 MiB ENH RPMB Capacity: 4 MiB ENH
I think this points to some issue with the mmc driver in U-Boot, or possibly some issue with my board. But I find that hard to believe because the Rockchip usbloader seems to write to the eMMC just fine ?
Probably related to sdhci driver and rx/tx tap and/or delay num etc.
Boot log (v2023.10-rc2):
U-Boot SPL 2023.10-rc2 (Aug 08 2023 - 14:02:34 +0100) rockchip_sdhci_probe clk set rate fail! Trying to boot from MMC1 spl: mmc init failed with error: -110 Trying to boot from MMC2 Card did not respond to voltage select! : -110 spl: mmc init failed with error: -95 Trying to boot from MMC1
Strange that second try of eMMC (MMC1) gets little bit longer.
## Checking hash(es) for config config-1 ... OK ## Checking hash(es) for Image atf-1 ... sha256+ OK spl_load_simple_fit: can't load image loadables index 0 (ret = -5) mmc_load_image_raw_sector: mmc block read error SPL: failed to boot from all boot devices ### ERROR ### Please RESET the board ###
Boot log (your branch):
U-Boot SPL 2023.10-rc1-00368-g16cb31d427 (Aug 08 2023 - 15:17:35 +0100) Trying to boot from MMC1 spl: mmc init failed with error: -70 Trying to boot from MMC2 Card did not respond to voltage select! : -110 spl: mmc init failed with error: -95 Trying to boot from MMC1 ## Checking hash(es) for config config-1 ... OK mmc_load_image_raw_sector: mmc block read error SPL: failed to boot from all boot devices ### ERROR ### Please RESET the board ###
I have not been able to reproduce this kind of issue on any of my two Quartz64-A boards, tested with different eMMC modules.
Does your eMMC module have some compatibility issue? Do you have any more details on the eMMC module you have tested with?
I have two eMMCs, one from FORESEE which came with a Pine64 and one marked SanDisk (which I posted the mmc info for above).
My eMMC modules is also FORESEE or SanDisk, from Pine64, Radxa and Hardkernel.
My hardware is marked Quartz64-RK3399-V2.0 2021-04-27 Maybe there is some difference with your board?
Should match my board, I have the hw revision where SATA port is removed. (boards with/without SATA have same version silk on the board)
I will also try an image with vendor u-boot as a next step.
I tried latest Armbian (which seems to use ) from https://github.com/armbian/build/releases/%C2%A0and flashed the eMMC with the USB writer. It ended up booting to Linux, which proves that the hardware I have is most likey in a good working order ;-)!
Hopefully the issue is related to the peephole2 optimization issue or the use of a not fully supported ddr52 mode.
Regards, Jonas
U-Boot SPL 2022.10-rc4-armbian (Feb 11 2023 - 22:25:16 +0000) saradc@fe720000: Can't update Vdd. Error: -38saradc@fe720000: Can't update Vss. Error: -38can't get vref-supply: -38 rockchip_dnl_key_pressed: adc_channel_single_shot fail! Trying to boot from MMC2 INFO:Â Â Â Preloader serial: 2 NOTICE:Â BL31: v2.3():v2.3-152-g4e725b15f:cl NOTICE:Â BL31: Built : 10:51:13, Jul 15 2021 INFO:Â Â Â GICv3 without legacy support detected. INFO:Â Â Â ARM GICv3 driver initialized in EL3 INFO:Â Â Â pmu v1 is valid INFO:Â Â Â dfs DDR fsp_param[0].freq_mhz= 1560MHz INFO:Â Â Â dfs DDR fsp_param[1].freq_mhz= 324MHz INFO:Â Â Â dfs DDR fsp_param[2].freq_mhz= 528MHz INFO:Â Â Â dfs DDR fsp_param[3].freq_mhz= 780MHz INFO:Â Â Â Using opteed sec cpu_context! INFO:Â Â Â boot cpu mask: 0 INFO:Â Â Â BL31: Initializing runtime services WARNING: No OPTEE provided by BL2 boot loader, Booting device without OPTEE initialization. SMC`s destined for OPTEE will return SMC_UNK ERROR:Â Â Error initializing runtime service opteed_fast INFO:Â Â Â BL31: Preparing for EL3 exit to normal world INFO:Â Â Â Entry point address = 0xa00000 INFO:Â Â Â SPSR = 0x3c9
U-Boot 2022.10-rc4-armbian (Feb 11 2023 - 22:25:16 +0000)
Model: Pine64 RK3566 Quartz64-A Board DRAM: 2 GiB PMIC: RK8170 (on=0x10, off=0x00) Core: 266 devices, 21 uclasses, devicetree: separate MMC:  mmc@fe2b0000: 1, mmc@fe310000: 0 Loading Environment from nowhere... OK In:   serial@fe660000 Out:  serial@fe660000 Err:  serial@fe660000 Model: Pine64 RK3566 Quartz64-A Board can't get vref-supply: -2 rockchip_dnl_key_pressed: adc_channel_single_shot fail! Net:  No ethernet found. Hit any key to stop autoboot: 0 starting USB... Bus usb@fcc00000: Port not available. Bus usb@fd000000: Port not available. Bus usb@fd800000: USB EHCI 1.00 Bus usb@fd840000: USB OHCI 1.0 Bus usb@fd880000: USB EHCI 1.00 Bus usb@fd8c0000: USB OHCI 1.0 scanning bus usb@fd800000 for devices... 1 USB Device(s) found scanning bus usb@fd840000 for devices... ERROR: USB-error: DEVICENOTRESPONDING: Device did not respond to token (IN) or did not provide a handshake (OUT) (5) ERROR: USB-error: DEVICENOTRESPONDING: Device did not respond to token (IN) or did not provide a handshake (OUT) (5) unable to get device descriptor (error=-1) 1 USB Device(s) found scanning bus usb@fd880000 for devices... 1 USB Device(s) found scanning bus usb@fd8c0000 for devices... 1 USB Device(s) found       scanning usb for storage devices... 0 Storage Device(s) found
Device 0: unknown device Card did not respond to voltage select! : -110 switch to partitions #0, OK mmc0(part 0) is current device Scanning mmc 0:1... Found /boot/extlinux/extlinux.conf Retrieving file: /boot/extlinux/extlinux.conf 1: Armbian Retrieving file: /boot/uInitrd Retrieving file: /boot/Image append: root=UUID=7f9c9970-93ba-46ca-9f03-f3241712ead8 console=ttyS02,1500000 console=tty0 rw no_console_suspend consoleblank=0 fsck.fix=yes fsck.repair=yes net.ifnames=0 splash plymouth.ignore- serial-consoles Retrieving file: /boot/dtb/rockchip/rk3566-quartz64-a.dtb Moving Image from 0x2080000 to 0x2200000, end=3de0000 ## Loading init Ramdisk from Legacy Image at 0a200000 ...   Image Name:  uInitrd   Image Type:  AArch64 Linux RAMDisk Image (gzip compressed)   Data Size:   34402446 Bytes = 32.8 MiB   Load Address: 00000000   Entry Point: 00000000   Verifying Checksum ... OK ## Flattened Device Tree blob at 0a100000   Booting using the fdt blob at 0xa100000   Loading Ramdisk to 7be16000, end 7dee508e ... OK   Loading Device Tree to 000000007bdf7000, end 000000007be158e2 ... OK
Starting kernel ...
efi_free_pool: illegal free 0x000000007cee7040 efi_free_pool: illegal free 0x000000007cee4040 [Â Â Â 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050] [Â Â Â 0.000000] Linux version 6.2.0-rc6-media (root@d00a59921686) (aarch64-linux-gnu-gcc (GNU Toolchain for the A-profile Architecture 8.3-2019.03 (arm-rel-8.36)) 8.3.0, GNU ld (GNU Toolchain for the A-profile Architecture 8.3-2019.03 (arm-rel-8.36)) 2.32.0.20190321) #trunk.0252 SMP PREEMPT_DYNAMIC Sat Feb 11 22:41:21 UTC 2023 [Â Â Â 0.000000] Machine model: Pine64 RK3566 Quartz64-A Board
Thanks!
Chris
Hi Jonas,
On Tue, 2023-10-17 at 10:02 +0100, Christopher Obbard wrote:
Hi Jonas,
On Sat, 2023-10-14 at 21:22 +0200, Jonas Karlman wrote:
On 2023-10-14 20:58, Jonas Karlman wrote:
Hi Christopher,
On 2023-10-12 13:46, Christopher Obbard wrote:
Hi Jonas,
On Thu, 2023-10-12 at 10:51 +0100, Christopher Obbard wrote:
Hi Jonas,
Sorry for the late response, I've been meaning to test this for a while but not got around to it.
On Thu, 2023-08-17 at 23:56 +0000, Jonas Karlman wrote:
Hi Christopher,
On 2023-08-08 16:25, Christopher Obbard wrote: > Hi Jonas, > > On Sun, 2023-07-23 at 15:04 +0000, Jonas Karlman wrote: > > On 2023-07-23 16:55, Jonas Karlman wrote: > > > The Pine64 Quartz64 Model A is a single-board computer based > > > on the > > > Rockchip RK3566 SoC. The board features USB3, SATA, PCIe, > > > HDMI, USB2.0, > > > CSI, DSI, eDP, eMMC, SD, and an e-paper parallel port, as > > > well as a > > > 20 pin GPIO header. > > > > > > Features tested on a Quartz64-A 8GB v2.0 2021-04-27: > > > - SD-card boot > > > - eMMC boot > > > - PCIe/NVMe/AHCI > > > - USB host > > > > > > Device tree is imported from linux v6.4. > > > > > > Co-developed-by: Nicolas Frattaroli > > > frattaroli.nicolas@gmail.com > > > Signed-off-by: Nicolas Frattaroli > > > frattaroli.nicolas@gmail.com > > > Signed-off-by: Jonas Karlman jonas@kwiboo.se > > > --- > > > > [...] > > > > Boot log with ROCKCHIP_TPL=rk3566_ddr_1056MHz_v1.17.bin and > > BL31=rk3568_bl31_v1.43.elf: > > > > [...] > > > > U-Boot 2023.07 (Jul 23 2023 - 12:42:18 +0000) > > > > Model: Pine64 RK3566 Quartz64-A Board > > DRAM:Â 8 GiB (effective 7.7 GiB) > > PMIC:Â RK8170 (on=0x10, off=0x00) > > Core:Â 321 devices, 27 uclasses, devicetree: separate > > MMC:Â Â rockchip_sdhci_probe clk set rate fail! > > mmc@fe2b0000: 1, mmc@fe2c0000: 2, mmc@fe310000: 0 > > Loading Environment from nowhere... OK > > In:Â Â Â serial@fe660000 > > Out:Â Â serial@fe660000 > > Err:Â Â serial@fe660000 > > Model: Pine64 RK3566 Quartz64-A Board > > Net:Â Â No ethernet found. > > > > Hit any key to stop autoboot:Â 0 > > => > > > I just tried booting U-Boot v2023.10-rc2 with > ROCKCHIP_TPL=rk3566_ddr_1056MHz_v1.17.bin and > BL31=rk3568_bl31_v1.43.elf, on my Quartz64-A but it fails during > loading of some parts. I removed the output of the RK TPL from > my logs as there were no errors.
Try with latest rk3566_ddr_1056MHz_v1.18.bin and see if that makes any difference.
No difference.
I've also checked, there is no other maskrom bootable media such as SPI flash connected to the board.
> This is when booting from eMMC.
Does it boot with SD-card or other eMMC modules?
Booting from SD card (without eMMC connected), everything works fine.
> I also tried building your branch from > https://github.com/Kwiboo/u-boot-rockchip/tree/rk3568-2023.10
Please try with a GitHub actions built u-boot-rockchip.bin based on my rk3568-2023.07.02 branch at https://github.com/Kwiboo/u-boot-build/actions/runs/5777761235
With that exact artifact, flashed with:
rkdeveloptool db rk356x_spl_loader_v1.18.113.bin rkdeveloptool ef rkdeveloptool wl 64 u-boot-rockchip.bin rkdeveloptool rd
it fails to boot with with:
DDR V1.18 f366f69a7d typ 23/07/17-15:48:58 ln LP4/4x derate en, other dram:1x trefi SRX ddrconfig:7 LPDDR4X, 324MHz BW=32 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 Size=8192MB
change to: 324MHz clk skew:0x60
change to: 528MHz clk skew:0x58
change to: 780MHz clk skew:0x58
change to: 1056MHz(final freq) clk skew:0x32 out
U-Boot SPL 2023.07.02-g09919887 (Aug 06 2023 - 16:59:31 +0000) Trying to boot from MMC1 spl: mmc init failed with error: -70 Trying to boot from MMC2 Card did not respond to voltage select! : -110 spl: mmc init failed with error: -95 Trying to boot from MMC1 mmc fail to send stop cmd mmc_load_image_raw_sector: mmc block read error SPL: failed to boot from all boot devices ### ERROR ### Please RESET the board ###
I also tried a second eMMC, but it also failed to boot with the same "mmc block read error" message.
I tried with your latest branch https://github.com/Kwiboo/u-boot-rockchip/commits/rk3568-2023.10
and this time a different error message, loading from the eMMC appears to get a bit further:
U-Boot SPL 2023.10-00054-gef68159087 (Oct 12 2023 - 12:14:22 +0100) Trying to boot from MMC1 ## Checking hash(es) for config config-1 ... OK ## Checking hash(es) for Image atf-1 ... sha256+ OK spl_load_simple_fit: can't load image loadables index 0 (ret = -5) mmc_load_image_raw_sector: mmc block read error Trying to boot from MMC2 Card did not respond to voltage select! : -110 spl: mmc init failed with error: -95 Trying to boot from MMC1 mmc_load_image_raw_sector: mmc block read error SPL: failed to boot from all boot devices ### ERROR ### Please RESET the board ###
So this is pointing to an issue reading from the MMC...
I found https://lists.denx.de/pipermail/u-boot/2023-April/514315.html%C2%A0(which is applied to your branch) and added the following to defconfig:
CONFIG_MMC_SDHCI_SDMA=y +# CONFIG_SPL_MMC_SDHCI_SDMA is not set
but this seemed to make the loading less reliable:
U-Boot SPL 2023.10-00054-gef68159087-dirty (Oct 12 2023 - 12:23:10 +0100) Trying to boot from MMC1 ## Checking hash(es) for config config-1 ... OK mmc fail to send stop cmd mmc_load_image_raw_sector: mmc block read error Trying to boot from MMC2 Card did not respond to voltage select! : -110 spl: mmc init failed with error: -95 Trying to boot from MMC1 mmc_load_image_raw_sector: mmc block read error SPL: failed to boot from all boot devices ### ERROR ### Please RESET the board ###
Thanks for testing different combinations.
I did find an issue with emmc write using ddr52 and hs400 modes on rk3568. On rk3588 emmc write only worked reliable after hs200 mode had been used.
Please try the changes from following commit, or my rk35xx-2024.01 work-in-progress branch:
WIP: rockchip: rk35xx: improve emmc write https://github.com/Kwiboo/u-boot-rockchip/commit/aa6156179bb2034e8ba26753e05...
Most rk356x boards currently default to ddr52 mode, and possible emmc read is also affected with similar issue as emmc write.
I have also discovered a strange issue on an Amlogic soc related to U-Boot mmc commands and gcc optimization, please see following patch: https://patchwork.ozlabs.org/patch/1839392/
Posted link to wrong patch, I meant the following patch:
[RFC] mmc: Remove alignment hole for cmdidx in struct mmc_cmd https://patchwork.ozlabs.org/patch/1841495/
I just tried with your branch & this patch on top, it still fails to boot and seems to be random how far it gets through the loading phase. Again I've removed the ddr training log. It seems to get further this time though...
Boot #1:
U-Boot SPL 2023.10-00055-g29313fff30 (Oct 17 2023 - 09:44:21 +0100) Trying to boot from MMC1 ## Checking hash(es) for config config-1 ... OK ## Checking hash(es) for Image atf-1 ... sha256+ OK ## Checking hash(es) for Image u-boot ... sha256+ OK
<crash>
Boot #2:
U-Boot SPL 2023.10-00055-g29313fff30 (Oct 17 2023 - 09:44:21 +0100) Trying to boot from MMC1 ## Checking hash(es) for config config-1 ... OK ## Checking hash(es) for Image atf-1 ... sha256+ OK ## Checking hash(es) for Image u-boot ... sha256+ OK ## Checking hash(es) for Image fdt-1 ... sha256+ OK ## Checking hash(es) for Image atf-2 ... sha256+ OK ## Checking hash(es) for Image atf-3 ... sha256+ OK ## Checking hash(es) for Image atf-4 ... sha256+ OK spl_load_simple_fit: can't load image loadables index 4 (ret = -5) mmc_load_image_raw_sector: mmc block read error Trying to boot from MMC2 Card did not respond to voltage select! : -110 spl: mmc init failed with error: -95 Trying to boot from MMC1 mmc_load_image_raw_sector: mmc block read error SPL: failed to boot from all boot devices ### ERROR ### Please RESET the board ###
Boot #3:
U-Boot SPL 2023.10-00055-g29313fff30 (Oct 17 2023 - 09:44:21 +0100) Trying to boot from MMC1 ## Checking hash(es) for config config-1 ... OK ## Checking hash(es) for Image atf-1 ... sha256+ OK ## Checking hash(es) for Image u-boot ... sha256+ OK ## Checking hash(es) for Image fdt-1 ... sha256+ OK ## Checking hash(es) for Image atf-2 ... sha256+ OK ## Checking hash(es) for Image atf-3 ... sha256+ OK ## Checking hash(es) for Image atf-4 ... sha256+ OK spl_load_simple_fit: can't load image loadables index 4 (ret = -5) mmc_load_image_raw_sector: mmc block read error Trying to boot from MMC2 Card did not respond to voltage select! : -110 spl: mmc init failed with error: -95 Trying to boot from MMC1 mmc_load_image_raw_sector: mmc block read error SPL: failed to boot from all boot devices ### ERROR ### Please RESET the board ###
For reference I am using gcc from Debian unstable:
$ aarch64-linux-gnu-gcc --version aarch64-linux-gnu-gcc (Debian 13.2.0-2) 13.2.0
I can test with alternative cross-compiler if that would be useful.
Sorry to revive an old thread, but I managed to do some more testing with this board. I found that my Quartz64-a booting from eMMC is still broken with U- Boot main branch, as well as your WIP branches on GitHub. It fails with e.g:
U-Boot SPL 2024.07-rc4-00480-g51c2936ec989 (Jul 05 2024 - 15:30:33 +0100) Trying to boot from MMC1 spl: mmc init failed with error: -110 Trying to boot from MMC2 Card did not respond to voltage select! : -110 spl: mmc init failed with error: -95 Trying to boot from MMC1 spl: mmc init failed with error: -70 SPL: failed to boot from all boot devices ### ERROR ### Please RESET the board ###
The only thing which I have found to work, is pgwipeout's U-Boot branch, with the following binary blobs (The same U-Boot branch doesn't seem to work with the latest version of the BL31 blob. Seems to need that specific BL31. This is very, very strange to me.)
The DDR bin seems to be unaffected, but I included a working version below anyway. https://github.com/rockchip-linux/rkbin/raw/6186debcac95553f6b311cee10669e12...
https://github.com/rockchip-linux/rkbin/raw/ddf03c1d80b33dac72a33c4f732fc584...
To make Peter's branch build, you need to set BL31 and move the DDR bin to ram_init.bin
I tried to forward-port some of the changes to U-Boot mainline, but the same error.
@Peter, can you try and confirm the error booting from eMMC on Quartz64-A with mainline U-Boot ?
Thanks, Chris
Regards, Jonas
Please try with CONFIG_MMC_TRACE=y to see what commands fails on your device.
If above patches does not work also try with following options applied:
CONFIG_MMC_HS200_SUPPORT=y CONFIG_SPL_MMC_HS200_SUPPORT=y
Use of HS200 seem to be the most reliable option on rk35xx based on my limited testing.
...
What happens if you write u-boot-rockchip.bin to eMMC module usinga USB adapter:
dd if=u-boot-rockchip.bin of=/dev/<device> bs=32k seek=1 conv=fsync
or using U-Boot cmd when booted from a SD-card?
# Read u-boot-rockchip.bin from first partition of a SD card  load mmc 1:1 10000000 u-boot-rockchip.bin
# Change to eMMC Â mmc dev 0
# Write 10 MiB (0x5000 blocks) at sector 64 (0x40) Â mmc write $fileaddr 40 5000
Does that make any difference?
I don't think I have an eMMC writer for Pine64 eMMCs, I will try to get hold of one this week.
I have two USB writers. Anyway, the first boot, it fails with:
U-Boot SPL 2023.10-00054-gef68159087 (Oct 12 2023 - 12:30:14 +0100) Trying to boot from MMC1 ## Checking hash(es) for config config-1 ... OK ## Checking hash(es) for Image atf-1 ... sha256+ OK ## Checking hash(es) for Image u-boot ... sha256+ OK
<hang>
Then again after a reset:
U-Boot SPL 2023.10-00054-gef68159087 (Oct 12 2023 - 12:30:14 +0100) Trying to boot from MMC1 mmc fail to send stop cmd mmc_load_image_raw_sector: mmc block read error Trying to boot from MMC2 Card did not respond to voltage select! : -110 spl: mmc init failed with error: -95 Trying to boot from MMC1 mmc_load_image_raw_sector: mmc block read error SPL: failed to boot from all boot devices ### ERROR ### Please RESET the board ###
But it fails to write to the eMMC with:
=> load mmc 1:2 10000000 u-boot-rockchip.bin 9510400 bytes read in 791 ms (11.5 MiB/s)
=> mmc dev 0 switch to partitions #0, OK mmc0(part 0) is current device
=> mmc write $fileaddr 40 5000 MMC write: dev # 0, block # 64, count 20480 ... mmc write failed 0 blocks written: ERROR
=> mmc info Device: mmc@fe310000 Manufacturer ID: 45 OEM: 0 Name: DF4016 Bus Speed: 52000000 Mode: MMC DDR52 (52MHz) Rd Block Len: 512 MMC version 5.1 High Capacity: Yes Capacity: 14.7 GiB Bus Width: 8-bit DDR Erase Group Size: 512 KiB HC WP Group Size: 8 MiB User Capacity: 14.7 GiB WRREL Boot Capacity: 4 MiB ENH RPMB Capacity: 4 MiB ENH
I think this points to some issue with the mmc driver in U-Boot, or possibly some issue with my board. But I find that hard to believe because the Rockchip usbloader seems to write to the eMMC just fine ?
Probably related to sdhci driver and rx/tx tap and/or delay num etc.
> > Boot log (v2023.10-rc2): > > U-Boot SPL 2023.10-rc2 (Aug 08 2023 - 14:02:34 +0100) > rockchip_sdhci_probe clk set rate fail! > Trying to boot from MMC1 > spl: mmc init failed with error: -110 > Trying to boot from MMC2 > Card did not respond to voltage select! : -110 > spl: mmc init failed with error: -95 > Trying to boot from MMC1
Strange that second try of eMMC (MMC1) gets little bit longer.
> ## Checking hash(es) for config config-1 ... OK > ## Checking hash(es) for Image atf-1 ... sha256+ OK > spl_load_simple_fit: can't load image loadables index 0 (ret = - > 5) > mmc_load_image_raw_sector: mmc block read error > SPL: failed to boot from all boot devices > ### ERROR ### Please RESET the board ### > > > Boot log (your branch): > > U-Boot SPL 2023.10-rc1-00368-g16cb31d427 (Aug 08 2023 - 15:17:35 > +0100) > Trying to boot from MMC1 > spl: mmc init failed with error: -70 > Trying to boot from MMC2 > Card did not respond to voltage select! : -110 > spl: mmc init failed with error: -95 > Trying to boot from MMC1 > ## Checking hash(es) for config config-1 ... OK > mmc_load_image_raw_sector: mmc block read error > SPL: failed to boot from all boot devices > ### ERROR ### Please RESET the board ###
I have not been able to reproduce this kind of issue on any of my two Quartz64-A boards, tested with different eMMC modules.
Does your eMMC module have some compatibility issue? Do you have any more details on the eMMC module you have tested with?
I have two eMMCs, one from FORESEE which came with a Pine64 and one marked SanDisk (which I posted the mmc info for above).
My eMMC modules is also FORESEE or SanDisk, from Pine64, Radxa and Hardkernel.
My hardware is marked Quartz64-RK3399-V2.0 2021-04-27 Maybe there is some difference with your board?
Should match my board, I have the hw revision where SATA port is removed. (boards with/without SATA have same version silk on the board)
I will also try an image with vendor u-boot as a next step.
I tried latest Armbian (which seems to use ) from https://github.com/armbian/build/releases/%C2%A0and flashed the eMMC with the USB writer. It ended up booting to Linux, which proves that the hardware I have is most likey in a good working order ;-)!
Hopefully the issue is related to the peephole2 optimization issue or the use of a not fully supported ddr52 mode.
Regards, Jonas
U-Boot SPL 2022.10-rc4-armbian (Feb 11 2023 - 22:25:16 +0000) saradc@fe720000: Can't update Vdd. Error: -38saradc@fe720000: Can't update Vss. Error: -38can't get vref-supply: -38 rockchip_dnl_key_pressed: adc_channel_single_shot fail! Trying to boot from MMC2 INFO:Â Â Â Preloader serial: 2 NOTICE:Â BL31: v2.3():v2.3-152-g4e725b15f:cl NOTICE:Â BL31: Built : 10:51:13, Jul 15 2021 INFO:Â Â Â GICv3 without legacy support detected. INFO:Â Â Â ARM GICv3 driver initialized in EL3 INFO:Â Â Â pmu v1 is valid INFO:Â Â Â dfs DDR fsp_param[0].freq_mhz= 1560MHz INFO:Â Â Â dfs DDR fsp_param[1].freq_mhz= 324MHz INFO:Â Â Â dfs DDR fsp_param[2].freq_mhz= 528MHz INFO:Â Â Â dfs DDR fsp_param[3].freq_mhz= 780MHz INFO:Â Â Â Using opteed sec cpu_context! INFO:Â Â Â boot cpu mask: 0 INFO:Â Â Â BL31: Initializing runtime services WARNING: No OPTEE provided by BL2 boot loader, Booting device without OPTEE initialization. SMC`s destined for OPTEE will return SMC_UNK ERROR:Â Â Error initializing runtime service opteed_fast INFO:Â Â Â BL31: Preparing for EL3 exit to normal world INFO:Â Â Â Entry point address = 0xa00000 INFO:Â Â Â SPSR = 0x3c9
U-Boot 2022.10-rc4-armbian (Feb 11 2023 - 22:25:16 +0000)
Model: Pine64 RK3566 Quartz64-A Board DRAM: 2 GiB PMIC: RK8170 (on=0x10, off=0x00) Core: 266 devices, 21 uclasses, devicetree: separate MMC:  mmc@fe2b0000: 1, mmc@fe310000: 0 Loading Environment from nowhere... OK In:   serial@fe660000 Out:  serial@fe660000 Err:  serial@fe660000 Model: Pine64 RK3566 Quartz64-A Board can't get vref-supply: -2 rockchip_dnl_key_pressed: adc_channel_single_shot fail! Net:  No ethernet found. Hit any key to stop autoboot: 0 starting USB... Bus usb@fcc00000: Port not available. Bus usb@fd000000: Port not available. Bus usb@fd800000: USB EHCI 1.00 Bus usb@fd840000: USB OHCI 1.0 Bus usb@fd880000: USB EHCI 1.00 Bus usb@fd8c0000: USB OHCI 1.0 scanning bus usb@fd800000 for devices... 1 USB Device(s) found scanning bus usb@fd840000 for devices... ERROR: USB-error: DEVICENOTRESPONDING: Device did not respond to token (IN) or did not provide a handshake (OUT) (5) ERROR: USB-error: DEVICENOTRESPONDING: Device did not respond to token (IN) or did not provide a handshake (OUT) (5) unable to get device descriptor (error=-1) 1 USB Device(s) found scanning bus usb@fd880000 for devices... 1 USB Device(s) found scanning bus usb@fd8c0000 for devices... 1 USB Device(s) found       scanning usb for storage devices... 0 Storage Device(s) found
Device 0: unknown device Card did not respond to voltage select! : -110 switch to partitions #0, OK mmc0(part 0) is current device Scanning mmc 0:1... Found /boot/extlinux/extlinux.conf Retrieving file: /boot/extlinux/extlinux.conf 1: Armbian Retrieving file: /boot/uInitrd Retrieving file: /boot/Image append: root=UUID=7f9c9970-93ba-46ca-9f03-f3241712ead8 console=ttyS02,1500000 console=tty0 rw no_console_suspend consoleblank=0 fsck.fix=yes fsck.repair=yes net.ifnames=0 splash plymouth.ignore- serial-consoles Retrieving file: /boot/dtb/rockchip/rk3566-quartz64-a.dtb Moving Image from 0x2080000 to 0x2200000, end=3de0000 ## Loading init Ramdisk from Legacy Image at 0a200000 ...   Image Name:  uInitrd   Image Type:  AArch64 Linux RAMDisk Image (gzip compressed)   Data Size:   34402446 Bytes = 32.8 MiB   Load Address: 00000000   Entry Point: 00000000   Verifying Checksum ... OK ## Flattened Device Tree blob at 0a100000   Booting using the fdt blob at 0xa100000   Loading Ramdisk to 7be16000, end 7dee508e ... OK   Loading Device Tree to 000000007bdf7000, end 000000007be158e2 ... OK
Starting kernel ...
efi_free_pool: illegal free 0x000000007cee7040 efi_free_pool: illegal free 0x000000007cee4040 [Â Â Â 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050] [Â Â Â 0.000000] Linux version 6.2.0-rc6-media (root@d00a59921686) (aarch64-linux-gnu-gcc (GNU Toolchain for the A-profile Architecture 8.3-2019.03 (arm-rel-8.36)) 8.3.0, GNU ld (GNU Toolchain for the A-profile Architecture 8.3-2019.03 (arm-rel-8.36)) 2.32.0.20190321) #trunk.0252 SMP PREEMPT_DYNAMIC Sat Feb 11 22:41:21 UTC 2023 [Â Â Â 0.000000] Machine model: Pine64 RK3566 Quartz64-A Board
Thanks!
Chris
On 2023/7/23 22:55, Jonas Karlman wrote:
The Pine64 Quartz64 Model A is a single-board computer based on the Rockchip RK3566 SoC. The board features USB3, SATA, PCIe, HDMI, USB2.0, CSI, DSI, eDP, eMMC, SD, and an e-paper parallel port, as well as a 20 pin GPIO header.
Features tested on a Quartz64-A 8GB v2.0 2021-04-27:
- SD-card boot
- eMMC boot
- PCIe/NVMe/AHCI
- USB host
Device tree is imported from linux v6.4.
Co-developed-by: Nicolas Frattaroli frattaroli.nicolas@gmail.com Signed-off-by: Nicolas Frattaroli frattaroli.nicolas@gmail.com Signed-off-by: Jonas Karlman jonas@kwiboo.se
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi | 55 ++ arch/arm/dts/rk3566-quartz64-a.dts | 839 ++++++++++++++++++ arch/arm/mach-rockchip/rk3568/Kconfig | 6 + board/pine64/quartz64_rk3566/Kconfig | 15 + board/pine64/quartz64_rk3566/MAINTAINERS | 9 + board/pine64/quartz64_rk3566/Makefile | 3 + .../pine64/quartz64_rk3566/quartz64-rk3566.c | 1 + configs/quartz64-a-rk3566_defconfig | 110 +++ doc/board/rockchip/rockchip.rst | 1 + include/configs/quartz64_rk3566.h | 10 + 11 files changed, 1050 insertions(+) create mode 100644 arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi create mode 100644 arch/arm/dts/rk3566-quartz64-a.dts create mode 100644 board/pine64/quartz64_rk3566/Kconfig create mode 100644 board/pine64/quartz64_rk3566/MAINTAINERS create mode 100644 board/pine64/quartz64_rk3566/Makefile create mode 100644 board/pine64/quartz64_rk3566/quartz64-rk3566.c create mode 100644 configs/quartz64-a-rk3566_defconfig create mode 100644 include/configs/quartz64_rk3566.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 6764ded580ab..45ef73fdf0ca 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -167,6 +167,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
dtb-$(CONFIG_ROCKCHIP_RK3568) += \ rk3566-anbernic-rgxx3.dtb \
- rk3566-quartz64-a.dtb \ rk3566-radxa-cm3-io.dtb \ rk3568-evb.dtb \ rk3568-odroid-m1.dtb \
diff --git a/arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi b/arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi new file mode 100644 index 000000000000..700c2d3edfe6 --- /dev/null +++ b/arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0+
+#include "rk356x-u-boot.dtsi"
+/ {
- chosen {
stdout-path = &uart2;- };
+};
+&gpio0 {
- bootph-all;
+};
+&pcie2x1 {
- pinctrl-0 = <&pcie20m2_pins &pcie_reset_h>;
+};
+&sdhci {
- cap-mmc-highspeed;
- mmc-ddr-1_8v;
- pinctrl-names = "default";
- pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
+};
+&sfc {
- bootph-pre-ram;
- u-boot,spl-sfc-no-dma;
- flash@0 {
bootph-pre-ram;- };
+};
+&uart2 {
- bootph-all;
- clock-frequency = <24000000>;
- status = "okay";
+};
+/*
- U-Boot does not support multiple regulators using the same gpio,
- use vcc5v0_usb20_host to fix use of USB 2.0 port
- */
+&usb2phy0_otg {
- phy-supply = <&vcc5v0_usb20_host>;
+};
+&vcc3v3_sd {
- bootph-pre-ram;
+};
+&vcc_sd_h {
- bootph-all;
+}; diff --git a/arch/arm/dts/rk3566-quartz64-a.dts b/arch/arm/dts/rk3566-quartz64-a.dts new file mode 100644 index 000000000000..25a8c781f4e7 --- /dev/null +++ b/arch/arm/dts/rk3566-quartz64-a.dts @@ -0,0 +1,839 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/soc/rockchip,vop2.h> +#include "rk3566.dtsi"
+/ {
- model = "Pine64 RK3566 Quartz64-A Board";
- compatible = "pine64,quartz64-a", "rockchip,rk3566";
- aliases {
ethernet0 = &gmac1;mmc0 = &sdmmc0;mmc1 = &sdhci;- };
- chosen: chosen {
stdout-path = "serial2:1500000n8";- };
- gmac1_clkin: external-gmac1-clock {
compatible = "fixed-clock";clock-frequency = <125000000>;clock-output-names = "gmac1_clkin";#clock-cells = <0>;- };
- fan: gpio_fan {
compatible = "gpio-fan";gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>;gpio-fan,speed-map = <0 04500 1>;pinctrl-names = "default";pinctrl-0 = <&fan_en_h>;#cooling-cells = <2>;- };
- hdmi-con {
compatible = "hdmi-connector";type = "a";port {hdmi_con_in: endpoint {remote-endpoint = <&hdmi_out_con>;};};- };
- leds {
compatible = "gpio-leds";led-work {label = "work-led";default-state = "off";gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>;pinctrl-names = "default";pinctrl-0 = <&work_led_enable_h>;retain-state-suspended;};led-diy {label = "diy-led";default-state = "on";gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;linux,default-trigger = "heartbeat";pinctrl-names = "default";pinctrl-0 = <&diy_led_enable_h>;retain-state-suspended;};- };
- rk817-sound {
compatible = "simple-audio-card";simple-audio-card,format = "i2s";simple-audio-card,name = "Analog RK817";simple-audio-card,mclk-fs = <256>;simple-audio-card,cpu {sound-dai = <&i2s1_8ch>;};simple-audio-card,codec {sound-dai = <&rk817>;};- };
- sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";clocks = <&rk817 1>;clock-names = "ext_clock";pinctrl-names = "default";pinctrl-0 = <&wifi_enable_h>;post-power-on-delay-ms = <100>;power-off-delay-us = <5000000>;reset-gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_LOW>;- };
- spdif_dit: spdif-dit {
compatible = "linux,spdif-dit";#sound-dai-cells = <0>;- };
- spdif_sound: spdif-sound {
compatible = "simple-audio-card";simple-audio-card,name = "SPDIF";simple-audio-card,cpu {sound-dai = <&spdif>;};simple-audio-card,codec {sound-dai = <&spdif_dit>;};- };
- vcc12v_dcin: vcc12v_dcin {
compatible = "regulator-fixed";regulator-name = "vcc12v_dcin";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <12000000>;regulator-max-microvolt = <12000000>;- };
- /* vbus feeds the rk817 usb input.
* With no battery attached, also feeds vcc_bat+* via ON/OFF_BAT jumper*/- vbus: vbus {
compatible = "regulator-fixed";regulator-name = "vbus";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <5000000>;regulator-max-microvolt = <5000000>;vin-supply = <&vcc12v_dcin>;- };
- vcc3v3_pcie_p: vcc3v3-pcie-p-regulator {
compatible = "regulator-fixed";enable-active-high;gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;pinctrl-names = "default";pinctrl-0 = <&pcie_enable_h>;regulator-name = "vcc3v3_pcie_p";regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;vin-supply = <&vcc_3v3>;- };
- vcc5v0_usb: vcc5v0_usb {
compatible = "regulator-fixed";regulator-name = "vcc5v0_usb";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <5000000>;regulator-max-microvolt = <5000000>;vin-supply = <&vcc12v_dcin>;- };
- /* all four ports are controlled by one gpio
* the host ports are sourced from vcc5v0_usb* the otg port is sourced from vcc5v0_midu*/- vcc5v0_usb20_host: vcc5v0_usb20_host {
compatible = "regulator-fixed";enable-active-high;gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>;pinctrl-names = "default";pinctrl-0 = <&vcc5v0_usb20_host_en>;regulator-name = "vcc5v0_usb20_host";regulator-min-microvolt = <5000000>;regulator-max-microvolt = <5000000>;vin-supply = <&vcc5v0_usb>;- };
- vcc5v0_usb20_otg: vcc5v0_usb20_otg {
compatible = "regulator-fixed";enable-active-high;gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>;regulator-name = "vcc5v0_usb20_otg";regulator-min-microvolt = <5000000>;regulator-max-microvolt = <5000000>;vin-supply = <&dcdc_boost>;- };
- vcc3v3_sd: vcc3v3_sd {
compatible = "regulator-fixed";gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;pinctrl-names = "default";pinctrl-0 = <&vcc_sd_h>;regulator-boot-on;regulator-name = "vcc3v3_sd";regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;vin-supply = <&vcc_3v3>;- };
- /* sourced from vbus and vcc_bat+ via rk817 sw5 */
- vcc_sys: vcc_sys {
compatible = "regulator-fixed";regulator-name = "vcc_sys";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <4400000>;regulator-max-microvolt = <4400000>;vin-supply = <&vbus>;- };
- /* sourced from vcc_sys, sdio module operates internally at 3.3v */
- vcc_wl: vcc_wl {
compatible = "regulator-fixed";regulator-name = "vcc_wl";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;vin-supply = <&vcc_sys>;- };
+};
+&combphy1 {
- status = "okay";
+};
+&combphy2 {
- status = "okay";
+};
+&cpu0 {
- cpu-supply = <&vdd_cpu>;
+};
+&cpu1 {
- cpu-supply = <&vdd_cpu>;
+};
+&cpu2 {
- cpu-supply = <&vdd_cpu>;
+};
+&cpu3 {
- cpu-supply = <&vdd_cpu>;
+};
+&cpu_thermal {
- trips {
cpu_hot: cpu_hot {temperature = <55000>;hysteresis = <2000>;type = "active";};- };
- cooling-maps {
map1 {trip = <&cpu_hot>;cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;};- };
+};
+&gmac1 {
- assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>;
- assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>, <&gmac1_clkin>;
- clock_in_out = "input";
- phy-supply = <&vcc_3v3>;
- phy-mode = "rgmii";
- pinctrl-names = "default";
- pinctrl-0 = <&gmac1m0_miim
&gmac1m0_tx_bus2&gmac1m0_rx_bus2&gmac1m0_rgmii_clk&gmac1m0_clkinout&gmac1m0_rgmii_bus>;- snps,reset-gpio = <&gpio0 RK_PC3 GPIO_ACTIVE_LOW>;
- snps,reset-active-low;
- /* Reset time is 20ms, 100ms for rtl8211f */
- snps,reset-delays-us = <0 20000 100000>;
- tx_delay = <0x30>;
- rx_delay = <0x10>;
- phy-handle = <&rgmii_phy1>;
- status = "okay";
+};
+&gpu {
- mali-supply = <&vdd_gpu>;
- status = "okay";
+};
+&hdmi {
- avdd-0v9-supply = <&vdda_0v9>;
- avdd-1v8-supply = <&vcc_1v8>;
- status = "okay";
+};
+&hdmi_in {
- hdmi_in_vp0: endpoint {
remote-endpoint = <&vp0_out_hdmi>;- };
+};
+&hdmi_out {
- hdmi_out_con: endpoint {
remote-endpoint = <&hdmi_con_in>;- };
+};
+&hdmi_sound {
- status = "okay";
+};
+&i2c0 {
- status = "okay";
- vdd_cpu: regulator@1c {
compatible = "tcs,tcs4525";reg = <0x1c>;fcs,suspend-voltage-selector = <1>;regulator-name = "vdd_cpu";regulator-min-microvolt = <800000>;regulator-max-microvolt = <1150000>;regulator-ramp-delay = <2300>;regulator-always-on;regulator-boot-on;vin-supply = <&vcc_sys>;regulator-state-mem {regulator-off-in-suspend;};- };
- rk817: pmic@20 {
compatible = "rockchip,rk817";reg = <0x20>;interrupt-parent = <&gpio0>;interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;assigned-clocks = <&cru I2S1_MCLKOUT_TX>;assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;clock-names = "mclk";clocks = <&cru I2S1_MCLKOUT_TX>;clock-output-names = "rk808-clkout1", "rk808-clkout2";#clock-cells = <1>;pinctrl-names = "default";pinctrl-0 = <&pmic_int_l>, <&i2s1m0_mclk>;rockchip,system-power-controller;#sound-dai-cells = <0>;wakeup-source;vcc1-supply = <&vcc_sys>;vcc2-supply = <&vcc_sys>;vcc3-supply = <&vcc_sys>;vcc4-supply = <&vcc_sys>;vcc5-supply = <&vcc_sys>;vcc6-supply = <&vcc_sys>;vcc7-supply = <&vcc_sys>;vcc8-supply = <&vcc_sys>;vcc9-supply = <&dcdc_boost>;regulators {vdd_logic: DCDC_REG1 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <500000>;regulator-max-microvolt = <1350000>;regulator-init-microvolt = <900000>;regulator-ramp-delay = <6001>;regulator-initial-mode = <0x2>;regulator-name = "vdd_logic";regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <900000>;};};vdd_gpu: DCDC_REG2 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <500000>;regulator-max-microvolt = <1350000>;regulator-init-microvolt = <900000>;regulator-ramp-delay = <6001>;regulator-initial-mode = <0x2>;regulator-name = "vdd_gpu";regulator-state-mem {regulator-off-in-suspend;};};vcc_ddr: DCDC_REG3 {regulator-always-on;regulator-boot-on;regulator-initial-mode = <0x2>;regulator-name = "vcc_ddr";regulator-state-mem {regulator-on-in-suspend;};};vcc_3v3: DCDC_REG4 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;regulator-initial-mode = <0x2>;regulator-name = "vcc_3v3";regulator-state-mem {regulator-off-in-suspend;};};vcca1v8_pmu: LDO_REG1 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-name = "vcca1v8_pmu";regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <1800000>;};};vdda_0v9: LDO_REG2 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <900000>;regulator-max-microvolt = <900000>;regulator-name = "vdda_0v9";regulator-state-mem {regulator-off-in-suspend;};};vdda0v9_pmu: LDO_REG3 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <900000>;regulator-max-microvolt = <900000>;regulator-name = "vdda0v9_pmu";regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <900000>;};};vccio_acodec: LDO_REG4 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;regulator-name = "vccio_acodec";regulator-state-mem {regulator-off-in-suspend;};};vccio_sd: LDO_REG5 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1800000>;regulator-max-microvolt = <3300000>;regulator-name = "vccio_sd";regulator-state-mem {regulator-off-in-suspend;};};vcc3v3_pmu: LDO_REG6 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;regulator-name = "vcc3v3_pmu";regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <3300000>;};};vcc_1v8: LDO_REG7 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-name = "vcc_1v8";regulator-state-mem {regulator-off-in-suspend;};};vcc1v8_dvp: LDO_REG8 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-name = "vcc1v8_dvp";regulator-state-mem {regulator-off-in-suspend;};};vcc2v8_dvp: LDO_REG9 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <2800000>;regulator-max-microvolt = <2800000>;regulator-name = "vcc2v8_dvp";regulator-state-mem {regulator-off-in-suspend;};};dcdc_boost: BOOST {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <5000000>;regulator-max-microvolt = <5000000>;regulator-name = "boost";regulator-state-mem {regulator-off-in-suspend;};};otg_switch: OTG_SWITCH {regulator-name = "otg_switch";regulator-state-mem {regulator-off-in-suspend;};};};- };
+};
+/* i2c3 is exposed on con40
- pin 3 - i2c3_sda_m0, pullup to vcc_3v3
- pin 5 - i2c3_scl_m0, pullup to vcc_3v3
- */
+&i2c3 {
- status = "okay";
+};
+&i2s0_8ch {
- status = "okay";
+};
+&i2s1_8ch {
- pinctrl-names = "default";
- pinctrl-0 = <&i2s1m0_sclktx
&i2s1m0_lrcktx&i2s1m0_sdi0&i2s1m0_sdo0>;- rockchip,trcm-sync-tx-only;
- status = "okay";
+};
+&mdio1 {
- rgmii_phy1: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";reg = <0>;- };
+};
+&pcie2x1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pcie_reset_h>;
- reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
- vpcie3v3-supply = <&vcc3v3_pcie_p>;
- status = "okay";
+};
+&pinctrl {
- bt {
bt_enable_h: bt-enable-h {rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;};bt_host_wake_l: bt-host-wake-l {rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_down>;};bt_wake_l: bt-wake-l {rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;};- };
- fan {
fan_en_h: fan-en-h {rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;};- };
- leds {
work_led_enable_h: work-led-enable-h {rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;};diy_led_enable_h: diy-led-enable-h {rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;};- };
- pcie {
pcie_enable_h: pcie-enable-h {rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;};pcie_reset_h: pcie-reset-h {rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;};- };
- pmic {
pmic_int_l: pmic-int-l {rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;};- };
- usb2 {
vcc5v0_usb20_host_en: vcc5v0-usb20-host-en {rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;};- };
- sdio-pwrseq {
wifi_enable_h: wifi-enable-h {rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;};- };
- vcc_sd {
vcc_sd_h: vcc-sd-h {rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;};- };
+};
+&pmu_io_domains {
- pmuio1-supply = <&vcc3v3_pmu>;
- pmuio2-supply = <&vcc3v3_pmu>;
- vccio1-supply = <&vccio_acodec>;
- vccio2-supply = <&vcc_1v8>;
- vccio3-supply = <&vccio_sd>;
- vccio4-supply = <&vcc_1v8>;
- vccio5-supply = <&vcc_3v3>;
- vccio6-supply = <&vcc1v8_dvp>;
- vccio7-supply = <&vcc_3v3>;
- status = "okay";
+};
+&sdhci {
- bus-width = <8>;
- mmc-hs200-1_8v;
- non-removable;
- vmmc-supply = <&vcc_3v3>;
- vqmmc-supply = <&vcc_1v8>;
- status = "okay";
+};
+&sdmmc0 {
- bus-width = <4>;
- cap-sd-highspeed;
- cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
- disable-wp;
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
- sd-uhs-sdr104;
- vmmc-supply = <&vcc3v3_sd>;
- vqmmc-supply = <&vccio_sd>;
- status = "okay";
+};
+&sdmmc1 {
- bus-width = <4>;
- cap-sd-highspeed;
- cap-sdio-irq;
- keep-power-in-suspend;
- mmc-pwrseq = <&sdio_pwrseq>;
- non-removable;
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>;
- sd-uhs-sdr104;
- vmmc-supply = <&vcc_wl>;
- vqmmc-supply = <&vcc_1v8>;
- status = "okay";
+};
+&sfc {
- pinctrl-0 = <&fspi_pins>;
- pinctrl-names = "default";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- flash@0 {
compatible = "jedec,spi-nor";reg = <0>;spi-max-frequency = <24000000>;spi-rx-bus-width = <4>;spi-tx-bus-width = <1>;- };
+};
+/* spdif is exposed on con40 pin 18 */ +&spdif {
- status = "okay";
+};
+/* spi1 is exposed on con40
- pin 11 - spi1_mosi_m1
- pin 13 - spi1_miso_m1
- pin 15 - spi1_clk_m1
- pin 17 - spi1_cs0_m1
- */
+&spi1 {
- pinctrl-names = "default";
- pinctrl-0 = <&spi1m1_cs0 &spi1m1_pins>;
+};
+&tsadc {
- /* tshut mode 0:CRU 1:GPIO */
- rockchip,hw-tshut-mode = <1>;
- /* tshut polarity 0:LOW 1:HIGH */
- rockchip,hw-tshut-polarity = <0>;
- status = "okay";
+};
+/* uart0 is exposed on con40
- pin 12 - uart0_tx
- pin 14 - uart0_rx
- */
+&uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_xfer>;
- status = "okay";
+};
+&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>;
- status = "okay";
- uart-has-rtscts;
- bluetooth {
compatible = "brcm,bcm43438-bt";clocks = <&rk817 1>;clock-names = "lpo";host-wakeup-gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>;device-wakeup-gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>;shutdown-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;pinctrl-names = "default";pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>;vbat-supply = <&vcc_sys>;vddio-supply = <&vcca1v8_pmu>;max-speed = <3000000>;- };
+};
+/* uart2 is exposed on con40
- pin 8 - uart2_tx_m0_debug
- pin 10 - uart2_rx_m0_debug
- */
+&uart2 {
- status = "okay";
+};
+&usb_host0_ehci {
- status = "okay";
+};
+&usb_host0_ohci {
- status = "okay";
+};
+&usb_host1_ehci {
- status = "okay";
+};
+&usb_host1_ohci {
- status = "okay";
+};
+&usb_host0_xhci {
- dr_mode = "host";
- status = "okay";
+};
+/* usb3 controller is muxed with sata1 */ +&usb_host1_xhci {
- status = "okay";
+};
+&usb2phy0 {
- status = "okay";
+};
+&usb2phy0_host {
- phy-supply = <&vcc5v0_usb20_host>;
- status = "okay";
+};
+&usb2phy0_otg {
- phy-supply = <&vcc5v0_usb20_otg>;
- status = "okay";
+};
+&usb2phy1 {
- status = "okay";
+};
+&usb2phy1_host {
- phy-supply = <&vcc5v0_usb20_host>;
- status = "okay";
+};
+&usb2phy1_otg {
- phy-supply = <&vcc5v0_usb20_host>;
- status = "okay";
+};
+&vop {
- assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
- assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
- status = "okay";
+};
+&vop_mmu {
- status = "okay";
+};
+&vp0 {
- vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
reg = <ROCKCHIP_VOP2_EP_HDMI0>;remote-endpoint = <&hdmi_in_vp0>;- };
+}; diff --git a/arch/arm/mach-rockchip/rk3568/Kconfig b/arch/arm/mach-rockchip/rk3568/Kconfig index f46be3d081fe..baa51349f4be 100644 --- a/arch/arm/mach-rockchip/rk3568/Kconfig +++ b/arch/arm/mach-rockchip/rk3568/Kconfig @@ -22,6 +22,11 @@ config TARGET_ODROID_M1_RK3568 help Hardkernel ODROID-M1 single board computer with a RK3568B2 SoC.
+config TARGET_QUARTZ64_RK3566
bool "Pine64 Quartz64"
help
Pine64 Quartz64 single board computer with a RK3566 SoC.endchoice
config ROCKCHIP_BOOT_MODE_REG
@@ -39,5 +44,6 @@ config SYS_MALLOC_F_LEN source "board/rockchip/evb_rk3568/Kconfig" source "board/anbernic/rgxx3_rk3566/Kconfig" source "board/hardkernel/odroid_m1/Kconfig" +source "board/pine64/quartz64_rk3566/Kconfig"
endif diff --git a/board/pine64/quartz64_rk3566/Kconfig b/board/pine64/quartz64_rk3566/Kconfig new file mode 100644 index 000000000000..3de1d8f7a993 --- /dev/null +++ b/board/pine64/quartz64_rk3566/Kconfig @@ -0,0 +1,15 @@ +if TARGET_QUARTZ64_RK3566
+config SYS_BOARD
- default "quartz64_rk3566"
+config SYS_VENDOR
- default "pine64"
+config SYS_CONFIG_NAME
- default "quartz64_rk3566"
+config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
+endif diff --git a/board/pine64/quartz64_rk3566/MAINTAINERS b/board/pine64/quartz64_rk3566/MAINTAINERS new file mode 100644 index 000000000000..dbc0dfbd9787 --- /dev/null +++ b/board/pine64/quartz64_rk3566/MAINTAINERS @@ -0,0 +1,9 @@ +QUARTZ64-RK3566 +M: Nicolas Frattaroli frattaroli.nicolas@gmail.com +R: Jonas Karlman jonas@kwiboo.se +S: Maintained +F: board/pine64/quartz64_rk3566/ +F: include/configs/quartz64_rk3566.h +F: configs/quartz64-a-rk3566_defconfig +F: arch/arm/dts/rk3566-quartz64-a.dts +F: arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi diff --git a/board/pine64/quartz64_rk3566/Makefile b/board/pine64/quartz64_rk3566/Makefile new file mode 100644 index 000000000000..c24a40e724d7 --- /dev/null +++ b/board/pine64/quartz64_rk3566/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0+
+obj-y += quartz64-rk3566.o diff --git a/board/pine64/quartz64_rk3566/quartz64-rk3566.c b/board/pine64/quartz64_rk3566/quartz64-rk3566.c new file mode 100644 index 000000000000..4c027f2a7af9 --- /dev/null +++ b/board/pine64/quartz64_rk3566/quartz64-rk3566.c @@ -0,0 +1 @@ +// SPDX-License-Identifier: GPL-2.0+ diff --git a/configs/quartz64-a-rk3566_defconfig b/configs/quartz64-a-rk3566_defconfig new file mode 100644 index 000000000000..d55b224feacd --- /dev/null +++ b/configs/quartz64-a-rk3566_defconfig @@ -0,0 +1,110 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_TEXT_BASE=0x00a00000 +CONFIG_SPL_GPIO=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 +CONFIG_SF_DEFAULT_SPEED=24000000 +CONFIG_SF_DEFAULT_MODE=0x2000 +CONFIG_DEFAULT_DEVICE_TREE="rk3566-quartz64-a" +CONFIG_ROCKCHIP_RK3568=y +CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y +CONFIG_ROCKCHIP_SPI_IMAGE=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_STACK_R_ADDR=0x600000 +CONFIG_TARGET_QUARTZ64_RK3566=y +CONFIG_SPL_STACK=0x400000 +CONFIG_DEBUG_UART_BASE=0xFE660000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI=y +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_PCI=y +CONFIG_DEBUG_UART=y +CONFIG_AHCI=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-quartz64-a.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x4000000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_POWER=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000 +CONFIG_SPL_ATF=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_SCSI_AHCI=y +CONFIG_AHCI_PCI=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_SF_DEFAULT_BUS=4 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_NVME_PCI=y +CONFIG_PCIE_DW_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_SPL_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_SPL_RAM=y +CONFIG_SCSI=y +CONFIG_DM_SCSI=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_ROCKCHIP_SFC=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_ERRNO_STR=y diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index b89f35954d33..c7d4c835db80 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -96,6 +96,7 @@ List of mainline supported Rockchip boards:
- rk3568
- Rockchip Evb-RK3568 (evb-rk3568)
- Hardkernel ODROID-M1 (odroid-m1-rk3568)
- Pine64 Quartz64-A Board (quartz64-a-rk3566_defconfig)
- rk3588
- Rockchip EVB (evb-rk3588)
diff --git a/include/configs/quartz64_rk3566.h b/include/configs/quartz64_rk3566.h new file mode 100644 index 000000000000..dfe0fee94cdb --- /dev/null +++ b/include/configs/quartz64_rk3566.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0+ */
+#ifndef __QUARTZ64_RK3566_H +#define __QUARTZ64_RK3566_H
+#define ROCKCHIP_DEVICE_SETTINGS
+#include <configs/rk3568_common.h>
+#endif
The Pine64 Quartz64 Model B is a credit-card sized single-board computer based on the Rockchip RK3566 SoC. The board features an M.2 PCIe slot, USB3, USB2, eMMC, SD, ethernet, HDMI, analog audio out, a 40 pin GPIO header and a DSI and CSI port, as well as on-board Wi-Fi.
Features tested on a Quartz64-B 4GB v1.4 2022-06-06: - SD-card boot - eMMC boot - SPI Flash boot - PCIe/NVMe - USB host
Device tree is imported from linux v6.4.
Co-developed-by: Nicolas Frattaroli frattaroli.nicolas@gmail.com Signed-off-by: Nicolas Frattaroli frattaroli.nicolas@gmail.com Signed-off-by: Jonas Karlman jonas@kwiboo.se --- arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3566-quartz64-b-u-boot.dtsi | 47 ++ arch/arm/dts/rk3566-quartz64-b.dts | 739 +++++++++++++++++++++ board/pine64/quartz64_rk3566/MAINTAINERS | 3 + configs/quartz64-b-rk3566_defconfig | 106 +++ doc/board/rockchip/rockchip.rst | 1 + 6 files changed, 897 insertions(+) create mode 100644 arch/arm/dts/rk3566-quartz64-b-u-boot.dtsi create mode 100644 arch/arm/dts/rk3566-quartz64-b.dts create mode 100644 configs/quartz64-b-rk3566_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 45ef73fdf0ca..3cc921e5cc1e 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -168,6 +168,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \ dtb-$(CONFIG_ROCKCHIP_RK3568) += \ rk3566-anbernic-rgxx3.dtb \ rk3566-quartz64-a.dtb \ + rk3566-quartz64-b.dtb \ rk3566-radxa-cm3-io.dtb \ rk3568-evb.dtb \ rk3568-odroid-m1.dtb \ diff --git a/arch/arm/dts/rk3566-quartz64-b-u-boot.dtsi b/arch/arm/dts/rk3566-quartz64-b-u-boot.dtsi new file mode 100644 index 000000000000..bdbb921c66e2 --- /dev/null +++ b/arch/arm/dts/rk3566-quartz64-b-u-boot.dtsi @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include "rk356x-u-boot.dtsi" + +/ { + chosen { + stdout-path = &uart2; + }; +}; + +&pcie2x1 { + pinctrl-0 = <&pcie20m2_pins &pcie_reset_h>; +}; + +&sdhci { + cap-mmc-highspeed; + mmc-ddr-1_8v; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; +}; + +&sfc { + bootph-pre-ram; + u-boot,spl-sfc-no-dma; + + flash@0 { + bootph-pre-ram; + }; +}; + +&uart2 { + bootph-all; + clock-frequency = <24000000>; + status = "okay"; +}; + +&usb_host0_xhci { + dr_mode = "host"; +}; + +&vcc5v0_usb30_host { + /delete-property/ regulator-always-on; +}; + +&vcc5v0_usb_otg { + /delete-property/ regulator-always-on; +}; diff --git a/arch/arm/dts/rk3566-quartz64-b.dts b/arch/arm/dts/rk3566-quartz64-b.dts new file mode 100644 index 000000000000..b276eb0810c7 --- /dev/null +++ b/arch/arm/dts/rk3566-quartz64-b.dts @@ -0,0 +1,739 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/soc/rockchip,vop2.h> +#include "rk3566.dtsi" + +/ { + model = "Pine64 RK3566 Quartz64-B Board"; + compatible = "pine64,quartz64-b", "rockchip,rk3566"; + + aliases { + ethernet0 = &gmac1; + mmc0 = &sdmmc0; + mmc1 = &sdhci; + mmc2 = &sdmmc1; + }; + + chosen: chosen { + stdout-path = "serial2:1500000n8"; + }; + + gmac1_clkin: external-gmac1-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "gmac1_clkin"; + #clock-cells = <0>; + }; + + hdmi-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-user { + label = "user-led"; + default-state = "on"; + gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + pinctrl-names = "default"; + pinctrl-0 = <&user_led_enable_h>; + retain-state-suspended; + }; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "Analog RK809"; + simple-audio-card,mclk-fs = <256>; + + simple-audio-card,cpu { + sound-dai = <&i2s1_8ch>; + }; + + simple-audio-card,codec { + sound-dai = <&rk809>; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + status = "okay"; + compatible = "mmc-pwrseq-simple"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + reset-gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_LOW>; + post-power-on-delay-ms = <100>; + power-off-delay-us = <5000000>; + }; + + vcc3v3_pcie_p: vcc3v3-pcie-p-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_enable_h>; + regulator-name = "vcc3v3_pcie_p"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3>; + }; + + vcc5v0_in: vcc5v0-in-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_in"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_in>; + }; + + vcc3v3_sys: vcc3v3-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_usb30_host: vcc5v0-usb30-host-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb30_host"; + enable-active-high; + gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_usb30_host_en_h>; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_usb_otg: vcc5v0-usb-otg-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb_otg"; + enable-active-high; + gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_usb_otg_en_h>; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&combphy1 { + status = "okay"; +}; + +&combphy2 { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; +}; + +&gmac1 { + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>, <&gmac1_clkin>; + clock_in_out = "input"; + phy-mode = "rgmii"; + phy-supply = <&vcc_3v3>; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m1_miim + &gmac1m1_tx_bus2 + &gmac1m1_rx_bus2 + &gmac1m1_rgmii_clk + &gmac1m1_clkinout + &gmac1m1_rgmii_bus>; + snps,reset-gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f, also works well here */ + snps,reset-delays-us = <0 20000 100000>; + tx_delay = <0x4f>; + rx_delay = <0x24>; + phy-handle = <&rgmii_phy1>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + avdd-0v9-supply = <&vdda0v9_image>; + avdd-1v8-supply = <&vcca1v8_image>; + status = "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&hdmi_sound { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + vdd_cpu: regulator@1c { + compatible = "tcs,tcs4525"; + reg = <0x1c>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-ramp-delay = <2300>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>; + assigned-clocks = <&cru I2S1_MCLKOUT_TX>; + assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>; + clock-names = "mclk"; + clocks = <&cru I2S1_MCLKOUT_TX>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int>, <&i2s1m0_mclk>; + rockchip,system-power-controller; + #sound-dai-cells = <0>; + wakeup-source; + #clock-cells = <1>; + + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + + regulators { + vdd_log: DCDC_REG1 { + regulator-name = "vdd_log"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-name = "vdd_gpu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-name = "vdd_npu"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1350000>; + regulator-initial-mode = <0x2>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-name = "vdda0v9_image"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-name = "vdda_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-name = "vdda0v9_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-name = "vccio_acodec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name = "vccio_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-name = "vcc3v3_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-name = "vcca_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-name = "vcca1v8_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca1v8_image: LDO_REG9 { + regulator-name = "vcca1v8_image"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-boot-on; + regulator-name = "vcc_3v3"; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-name = "vcc3v3_sd"; + }; + }; + }; +}; + +/* i2c2_m1 exposed on csi port, pulled up to vcc_3v3 */ +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2m1_xfer>; + status = "okay"; +}; + +/* i2c3_m1 exposed on dsi port, pulled up to vcc_3v3 */ +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3m1_xfer>; + status = "okay"; +}; + +/* + * i2c4_m0 is exposed on PI40, pulled up to vcc_3v3 + * pin 27 - i2c4_sda_m0 + * pin 28 - i2c4_scl_m0 + */ +&i2c4 { + status = "okay"; +}; + +/* + * i2c5_m0 is exposed on PI40 + * pin 29 - i2c5_scl_m0 + * pin 31 - i2c5_sda_m0 + */ +&i2c5 { + status = "disabled"; +}; + +&i2s0_8ch { + status = "okay"; +}; + +&i2s1_8ch { + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_sclktx + &i2s1m0_lrcktx + &i2s1m0_sdi0 + &i2s1m0_sdo0>; + rockchip,trcm-sync-tx-only; + status = "okay"; +}; + +&mdio1 { + rgmii_phy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + }; +}; + +&pcie2x1 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_reset_h>; + reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie_p>; + status = "okay"; +}; + +&pinctrl { + bt { + bt_enable_h: bt-enable-h { + rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_host_wake_l: bt-host-wake-l { + rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + bt_wake_l: bt-wake-l { + rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + leds { + user_led_enable_h: user-led-enable-h { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie { + pcie_enable_h: pcie-enable-h { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie_reset_h: pcie-reset-h { + rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int: pmic_int { + rockchip,pins = + <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + vcc5v0_usb30_host_en_h: vcc5v0-usb30-host-en_h { + rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_usb_otg_en_h: vcc5v0-usb-otg-en_h { + rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + status = "okay"; + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcca1v8_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio2-supply = <&vcc_1v8>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcca1v8_pmu>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_3v3>; + vccio7-supply = <&vcc_3v3>; +}; + +&saradc { + vref-supply = <&vcca_1v8>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + mmc-hs200-1_8v; + non-removable; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdmmc0 { + bus-width = <4>; + cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + sd-uhs-sdr50; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&sdmmc1 { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; + vmmc-supply = <&vcc3v3_sys>; + vqmmc-supply = <&vcca1v8_pmu>; + status = "okay"; +}; + +&sfc { + pinctrl-0 = <&fspi_pins>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <24000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + }; +}; + +&tsadc { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>; + status = "okay"; + uart-has-rtscts; + + bluetooth { + compatible = "brcm,bcm4345c5"; + clocks = <&rk809 1>; + clock-names = "lpo"; + device-wakeup-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>; + vbat-supply = <&vcc3v3_sys>; + vddio-supply = <&vcca1v8_pmu>; + }; +}; + +/* + * uart2_m0 is exposed on PI40 + * pin 8 - uart2_tx_m0 + * pin 10 - uart2_rx_m0 + */ +&uart2 { + status = "okay"; +}; + +&usb2phy0_host { + phy-supply = <&vcc5v0_usb30_host>; + status = "okay"; +}; + +&usb2phy0_otg { + phy-supply = <&vcc5v0_usb_otg>; + status = "okay"; +}; + +&usb2phy1_otg { + phy-supply = <&vcc5v0_usb30_host>; + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy1 { + status = "okay"; +}; + +&usb_host0_xhci { + status = "okay"; +}; + +&usb_host1_xhci { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&vop { + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = <ROCKCHIP_VOP2_EP_HDMI0>; + remote-endpoint = <&hdmi_in_vp0>; + }; +}; diff --git a/board/pine64/quartz64_rk3566/MAINTAINERS b/board/pine64/quartz64_rk3566/MAINTAINERS index dbc0dfbd9787..2e637bf51ba3 100644 --- a/board/pine64/quartz64_rk3566/MAINTAINERS +++ b/board/pine64/quartz64_rk3566/MAINTAINERS @@ -5,5 +5,8 @@ S: Maintained F: board/pine64/quartz64_rk3566/ F: include/configs/quartz64_rk3566.h F: configs/quartz64-a-rk3566_defconfig +F: configs/quartz64-b-rk3566_defconfig F: arch/arm/dts/rk3566-quartz64-a.dts F: arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi +F: arch/arm/dts/rk3566-quartz64-b.dts +F: arch/arm/dts/rk3566-quartz64-b-u-boot.dtsi diff --git a/configs/quartz64-b-rk3566_defconfig b/configs/quartz64-b-rk3566_defconfig new file mode 100644 index 000000000000..b98c81f9dcef --- /dev/null +++ b/configs/quartz64-b-rk3566_defconfig @@ -0,0 +1,106 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_TEXT_BASE=0x00a00000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 +CONFIG_SF_DEFAULT_SPEED=24000000 +CONFIG_SF_DEFAULT_MODE=0x2000 +CONFIG_DEFAULT_DEVICE_TREE="rk3566-quartz64-b" +CONFIG_ROCKCHIP_RK3568=y +CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y +CONFIG_ROCKCHIP_SPI_IMAGE=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_STACK_R_ADDR=0x600000 +CONFIG_TARGET_QUARTZ64_RK3566=y +CONFIG_SPL_STACK=0x400000 +CONFIG_DEBUG_UART_BASE=0xFE660000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI=y +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_PCI=y +CONFIG_DEBUG_UART=y +CONFIG_AHCI=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-quartz64-b.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x4000000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000 +CONFIG_SPL_ATF=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_SCSI_AHCI=y +CONFIG_AHCI_PCI=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_SF_DEFAULT_BUS=4 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_NVME_PCI=y +CONFIG_PCIE_DW_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_SPL_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_SPL_RAM=y +CONFIG_SCSI=y +CONFIG_DM_SCSI=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_ROCKCHIP_SFC=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_ERRNO_STR=y diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index c7d4c835db80..1c0e10c40607 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -97,6 +97,7 @@ List of mainline supported Rockchip boards: - Rockchip Evb-RK3568 (evb-rk3568) - Hardkernel ODROID-M1 (odroid-m1-rk3568) - Pine64 Quartz64-A Board (quartz64-a-rk3566_defconfig) + - Pine64 Quartz64-B Board (quartz64-b-rk3566_defconfig)
* rk3588 - Rockchip EVB (evb-rk3588)
On 2023-07-23 16:55, Jonas Karlman wrote:
The Pine64 Quartz64 Model B is a credit-card sized single-board computer based on the Rockchip RK3566 SoC. The board features an M.2 PCIe slot, USB3, USB2, eMMC, SD, ethernet, HDMI, analog audio out, a 40 pin GPIO header and a DSI and CSI port, as well as on-board Wi-Fi.
Features tested on a Quartz64-B 4GB v1.4 2022-06-06:
- SD-card boot
- eMMC boot
- SPI Flash boot
- PCIe/NVMe
- USB host
Device tree is imported from linux v6.4.
Co-developed-by: Nicolas Frattaroli frattaroli.nicolas@gmail.com Signed-off-by: Nicolas Frattaroli frattaroli.nicolas@gmail.com Signed-off-by: Jonas Karlman jonas@kwiboo.se
[...]
Boot log with ROCKCHIP_TPL=rk3566_ddr_1056MHz_v1.17.bin, BL31=rk3568_bl31_v1.43.elf and serial console on UART5: U-Boot SPL 2023.07 (Jul 23 2023 - 13:52:36 +0000) rockchip_sdhci_probe clk set rate fail! Trying to boot from MMC2 ## Checking hash(es) for config config-1 ... OK ## Checking hash(es) for Image atf-1 ... sha256+ OK ## Checking hash(es) for Image u-boot ... sha256+ OK ## Checking hash(es) for Image fdt-1 ... sha256+ OK ## Checking hash(es) for Image atf-2 ... sha256+ OK ## Checking hash(es) for Image atf-3 ... sha256+ OK ## Checking hash(es) for Image atf-4 ... sha256+ OK ## Checking hash(es) for Image atf-5 ... sha256+ OK ## Checking hash(es) for Image atf-6 ... sha256+ OK
U-Boot 2023.07 (Jul 23 2023 - 13:52:36 +0000)
Model: Pine64 RK3566 Quartz64-B Board DRAM: 4 GiB (effective 3.7 GiB) PMIC: RK8090 (on=0x40, off=0x00) Core: 321 devices, 30 uclasses, devicetree: separate MMC: rockchip_sdhci_probe clk set rate fail! mmc@fe2b0000: 1, mmc@fe2c0000: 2, mmc@fe310000: 0 Loading Environment from nowhere... OK In: serial@fe690000 Out: serial@fe690000 Err: serial@fe690000 Model: Pine64 RK3566 Quartz64-B Board Net: No ethernet found.
Hit any key to stop autoboot: 0 =>
Regards, Jonas
On 2023/7/23 22:55, Jonas Karlman wrote:
The Pine64 Quartz64 Model B is a credit-card sized single-board computer based on the Rockchip RK3566 SoC. The board features an M.2 PCIe slot, USB3, USB2, eMMC, SD, ethernet, HDMI, analog audio out, a 40 pin GPIO header and a DSI and CSI port, as well as on-board Wi-Fi.
Features tested on a Quartz64-B 4GB v1.4 2022-06-06:
- SD-card boot
- eMMC boot
- SPI Flash boot
- PCIe/NVMe
- USB host
Device tree is imported from linux v6.4.
Co-developed-by: Nicolas Frattaroli frattaroli.nicolas@gmail.com Signed-off-by: Nicolas Frattaroli frattaroli.nicolas@gmail.com Signed-off-by: Jonas Karlman jonas@kwiboo.se
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3566-quartz64-b-u-boot.dtsi | 47 ++ arch/arm/dts/rk3566-quartz64-b.dts | 739 +++++++++++++++++++++ board/pine64/quartz64_rk3566/MAINTAINERS | 3 + configs/quartz64-b-rk3566_defconfig | 106 +++ doc/board/rockchip/rockchip.rst | 1 + 6 files changed, 897 insertions(+) create mode 100644 arch/arm/dts/rk3566-quartz64-b-u-boot.dtsi create mode 100644 arch/arm/dts/rk3566-quartz64-b.dts create mode 100644 configs/quartz64-b-rk3566_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 45ef73fdf0ca..3cc921e5cc1e 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -168,6 +168,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \ dtb-$(CONFIG_ROCKCHIP_RK3568) += \ rk3566-anbernic-rgxx3.dtb \ rk3566-quartz64-a.dtb \
- rk3566-quartz64-b.dtb \ rk3566-radxa-cm3-io.dtb \ rk3568-evb.dtb \ rk3568-odroid-m1.dtb \
diff --git a/arch/arm/dts/rk3566-quartz64-b-u-boot.dtsi b/arch/arm/dts/rk3566-quartz64-b-u-boot.dtsi new file mode 100644 index 000000000000..bdbb921c66e2 --- /dev/null +++ b/arch/arm/dts/rk3566-quartz64-b-u-boot.dtsi @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0+
+#include "rk356x-u-boot.dtsi"
+/ {
- chosen {
stdout-path = &uart2;- };
+};
+&pcie2x1 {
- pinctrl-0 = <&pcie20m2_pins &pcie_reset_h>;
+};
+&sdhci {
- cap-mmc-highspeed;
- mmc-ddr-1_8v;
- pinctrl-names = "default";
- pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
+};
+&sfc {
- bootph-pre-ram;
- u-boot,spl-sfc-no-dma;
- flash@0 {
bootph-pre-ram;- };
+};
+&uart2 {
- bootph-all;
- clock-frequency = <24000000>;
- status = "okay";
+};
+&usb_host0_xhci {
- dr_mode = "host";
+};
+&vcc5v0_usb30_host {
- /delete-property/ regulator-always-on;
+};
+&vcc5v0_usb_otg {
- /delete-property/ regulator-always-on;
+}; diff --git a/arch/arm/dts/rk3566-quartz64-b.dts b/arch/arm/dts/rk3566-quartz64-b.dts new file mode 100644 index 000000000000..b276eb0810c7 --- /dev/null +++ b/arch/arm/dts/rk3566-quartz64-b.dts @@ -0,0 +1,739 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/soc/rockchip,vop2.h> +#include "rk3566.dtsi"
+/ {
- model = "Pine64 RK3566 Quartz64-B Board";
- compatible = "pine64,quartz64-b", "rockchip,rk3566";
- aliases {
ethernet0 = &gmac1;mmc0 = &sdmmc0;mmc1 = &sdhci;mmc2 = &sdmmc1;- };
- chosen: chosen {
stdout-path = "serial2:1500000n8";- };
- gmac1_clkin: external-gmac1-clock {
compatible = "fixed-clock";clock-frequency = <125000000>;clock-output-names = "gmac1_clkin";#clock-cells = <0>;- };
- hdmi-con {
compatible = "hdmi-connector";type = "a";port {hdmi_con_in: endpoint {remote-endpoint = <&hdmi_out_con>;};};- };
- leds {
compatible = "gpio-leds";led-user {label = "user-led";default-state = "on";gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;linux,default-trigger = "heartbeat";pinctrl-names = "default";pinctrl-0 = <&user_led_enable_h>;retain-state-suspended;};- };
- sound {
compatible = "simple-audio-card";simple-audio-card,format = "i2s";simple-audio-card,name = "Analog RK809";simple-audio-card,mclk-fs = <256>;simple-audio-card,cpu {sound-dai = <&i2s1_8ch>;};simple-audio-card,codec {sound-dai = <&rk809>;};- };
- sdio_pwrseq: sdio-pwrseq {
status = "okay";compatible = "mmc-pwrseq-simple";clocks = <&rk809 1>;clock-names = "ext_clock";pinctrl-names = "default";pinctrl-0 = <&wifi_enable_h>;reset-gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_LOW>;post-power-on-delay-ms = <100>;power-off-delay-us = <5000000>;- };
- vcc3v3_pcie_p: vcc3v3-pcie-p-regulator {
compatible = "regulator-fixed";enable-active-high;gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;pinctrl-names = "default";pinctrl-0 = <&pcie_enable_h>;regulator-name = "vcc3v3_pcie_p";regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;vin-supply = <&vcc_3v3>;- };
- vcc5v0_in: vcc5v0-in-regulator {
compatible = "regulator-fixed";regulator-name = "vcc5v0_in";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <5000000>;regulator-max-microvolt = <5000000>;- };
- vcc5v0_sys: vcc5v0-sys-regulator {
compatible = "regulator-fixed";regulator-name = "vcc5v0_sys";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <5000000>;regulator-max-microvolt = <5000000>;vin-supply = <&vcc5v0_in>;- };
- vcc3v3_sys: vcc3v3-sys-regulator {
compatible = "regulator-fixed";regulator-name = "vcc3v3_sys";regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;regulator-always-on;vin-supply = <&vcc5v0_sys>;- };
- vcc5v0_usb30_host: vcc5v0-usb30-host-regulator {
compatible = "regulator-fixed";regulator-name = "vcc5v0_usb30_host";enable-active-high;gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;pinctrl-names = "default";pinctrl-0 = <&vcc5v0_usb30_host_en_h>;regulator-always-on;regulator-min-microvolt = <5000000>;regulator-max-microvolt = <5000000>;vin-supply = <&vcc5v0_sys>;- };
- vcc5v0_usb_otg: vcc5v0-usb-otg-regulator {
compatible = "regulator-fixed";regulator-name = "vcc5v0_usb_otg";enable-active-high;gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;pinctrl-names = "default";pinctrl-0 = <&vcc5v0_usb_otg_en_h>;regulator-always-on;regulator-min-microvolt = <5000000>;regulator-max-microvolt = <5000000>;vin-supply = <&vcc5v0_sys>;- };
+};
+&combphy1 {
- status = "okay";
+};
+&combphy2 {
- status = "okay";
+};
+&cpu0 {
- cpu-supply = <&vdd_cpu>;
+};
+&cpu1 {
- cpu-supply = <&vdd_cpu>;
+};
+&cpu2 {
- cpu-supply = <&vdd_cpu>;
+};
+&cpu3 {
- cpu-supply = <&vdd_cpu>;
+};
+&gmac1 {
- assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>;
- assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>, <&gmac1_clkin>;
- clock_in_out = "input";
- phy-mode = "rgmii";
- phy-supply = <&vcc_3v3>;
- pinctrl-names = "default";
- pinctrl-0 = <&gmac1m1_miim
&gmac1m1_tx_bus2&gmac1m1_rx_bus2&gmac1m1_rgmii_clk&gmac1m1_clkinout&gmac1m1_rgmii_bus>;- snps,reset-gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>;
- snps,reset-active-low;
- /* Reset time is 20ms, 100ms for rtl8211f, also works well here */
- snps,reset-delays-us = <0 20000 100000>;
- tx_delay = <0x4f>;
- rx_delay = <0x24>;
- phy-handle = <&rgmii_phy1>;
- status = "okay";
+};
+&gpu {
- mali-supply = <&vdd_gpu>;
- status = "okay";
+};
+&hdmi {
- avdd-0v9-supply = <&vdda0v9_image>;
- avdd-1v8-supply = <&vcca1v8_image>;
- status = "okay";
+};
+&hdmi_in {
- hdmi_in_vp0: endpoint {
remote-endpoint = <&vp0_out_hdmi>;- };
+};
+&hdmi_out {
- hdmi_out_con: endpoint {
remote-endpoint = <&hdmi_con_in>;- };
+};
+&hdmi_sound {
- status = "okay";
+};
+&i2c0 {
- status = "okay";
- vdd_cpu: regulator@1c {
compatible = "tcs,tcs4525";reg = <0x1c>;fcs,suspend-voltage-selector = <1>;regulator-name = "vdd_cpu";regulator-min-microvolt = <800000>;regulator-max-microvolt = <1150000>;regulator-ramp-delay = <2300>;regulator-always-on;regulator-boot-on;vin-supply = <&vcc5v0_sys>;regulator-state-mem {regulator-off-in-suspend;};- };
- rk809: pmic@20 {
compatible = "rockchip,rk809";reg = <0x20>;interrupt-parent = <&gpio0>;interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;assigned-clocks = <&cru I2S1_MCLKOUT_TX>;assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;clock-names = "mclk";clocks = <&cru I2S1_MCLKOUT_TX>;clock-output-names = "rk808-clkout1", "rk808-clkout2";pinctrl-names = "default";pinctrl-0 = <&pmic_int>, <&i2s1m0_mclk>;rockchip,system-power-controller;#sound-dai-cells = <0>;wakeup-source;#clock-cells = <1>;vcc1-supply = <&vcc3v3_sys>;vcc2-supply = <&vcc3v3_sys>;vcc3-supply = <&vcc3v3_sys>;vcc4-supply = <&vcc3v3_sys>;vcc5-supply = <&vcc3v3_sys>;vcc6-supply = <&vcc3v3_sys>;vcc7-supply = <&vcc3v3_sys>;vcc8-supply = <&vcc3v3_sys>;vcc9-supply = <&vcc3v3_sys>;regulators {vdd_log: DCDC_REG1 {regulator-name = "vdd_log";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <500000>;regulator-max-microvolt = <1350000>;regulator-init-microvolt = <900000>;regulator-ramp-delay = <6001>;regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <900000>;};};vdd_gpu: DCDC_REG2 {regulator-name = "vdd_gpu";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <900000>;regulator-max-microvolt = <1350000>;regulator-init-microvolt = <900000>;regulator-ramp-delay = <6001>;regulator-state-mem {regulator-off-in-suspend;regulator-suspend-microvolt = <900000>;};};vcc_ddr: DCDC_REG3 {regulator-name = "vcc_ddr";regulator-always-on;regulator-boot-on;regulator-initial-mode = <0x2>;regulator-state-mem {regulator-on-in-suspend;};};vdd_npu: DCDC_REG4 {regulator-name = "vdd_npu";regulator-min-microvolt = <900000>;regulator-max-microvolt = <1350000>;regulator-initial-mode = <0x2>;regulator-state-mem {regulator-off-in-suspend;};};vcc_1v8: DCDC_REG5 {regulator-name = "vcc_1v8";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <1800000>;};};vdda0v9_image: LDO_REG1 {regulator-name = "vdda0v9_image";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <900000>;regulator-max-microvolt = <900000>;regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <900000>;};};vdda_0v9: LDO_REG2 {regulator-name = "vdda_0v9";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <900000>;regulator-max-microvolt = <900000>;regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <900000>;};};vdda0v9_pmu: LDO_REG3 {regulator-name = "vdda0v9_pmu";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <900000>;regulator-max-microvolt = <900000>;regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <900000>;};};vccio_acodec: LDO_REG4 {regulator-name = "vccio_acodec";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <3300000>;};};vccio_sd: LDO_REG5 {regulator-name = "vccio_sd";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1800000>;regulator-max-microvolt = <3300000>;regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <3300000>;};};vcc3v3_pmu: LDO_REG6 {regulator-name = "vcc3v3_pmu";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <3300000>;};};vcca_1v8: LDO_REG7 {regulator-name = "vcca_1v8";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <1800000>;};};vcca1v8_pmu: LDO_REG8 {regulator-name = "vcca1v8_pmu";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <1800000>;};};vcca1v8_image: LDO_REG9 {regulator-name = "vcca1v8_image";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <1800000>;};};vcc_3v3: SWITCH_REG1 {regulator-boot-on;regulator-name = "vcc_3v3";};vcc3v3_sd: SWITCH_REG2 {regulator-name = "vcc3v3_sd";};};- };
+};
+/* i2c2_m1 exposed on csi port, pulled up to vcc_3v3 */ +&i2c2 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c2m1_xfer>;
- status = "okay";
+};
+/* i2c3_m1 exposed on dsi port, pulled up to vcc_3v3 */ +&i2c3 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c3m1_xfer>;
- status = "okay";
+};
+/*
- i2c4_m0 is exposed on PI40, pulled up to vcc_3v3
- pin 27 - i2c4_sda_m0
- pin 28 - i2c4_scl_m0
- */
+&i2c4 {
- status = "okay";
+};
+/*
- i2c5_m0 is exposed on PI40
- pin 29 - i2c5_scl_m0
- pin 31 - i2c5_sda_m0
- */
+&i2c5 {
- status = "disabled";
+};
+&i2s0_8ch {
- status = "okay";
+};
+&i2s1_8ch {
- pinctrl-names = "default";
- pinctrl-0 = <&i2s1m0_sclktx
&i2s1m0_lrcktx&i2s1m0_sdi0&i2s1m0_sdo0>;- rockchip,trcm-sync-tx-only;
- status = "okay";
+};
+&mdio1 {
- rgmii_phy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";reg = <0x1>;- };
+};
+&pcie2x1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pcie_reset_h>;
- reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
- vpcie3v3-supply = <&vcc3v3_pcie_p>;
- status = "okay";
+};
+&pinctrl {
- bt {
bt_enable_h: bt-enable-h {rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;};bt_host_wake_l: bt-host-wake-l {rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_down>;};bt_wake_l: bt-wake-l {rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;};- };
- leds {
user_led_enable_h: user-led-enable-h {rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;};- };
- pcie {
pcie_enable_h: pcie-enable-h {rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;};pcie_reset_h: pcie-reset-h {rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;};- };
- pmic {
pmic_int: pmic_int {rockchip,pins =<0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;};- };
- sdio-pwrseq {
wifi_enable_h: wifi-enable-h {rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;};- };
- usb {
vcc5v0_usb30_host_en_h: vcc5v0-usb30-host-en_h {rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;};vcc5v0_usb_otg_en_h: vcc5v0-usb-otg-en_h {rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;};- };
+};
+&pmu_io_domains {
- status = "okay";
- pmuio1-supply = <&vcc3v3_pmu>;
- pmuio2-supply = <&vcca1v8_pmu>;
- vccio1-supply = <&vccio_acodec>;
- vccio2-supply = <&vcc_1v8>;
- vccio3-supply = <&vccio_sd>;
- vccio4-supply = <&vcca1v8_pmu>;
- vccio5-supply = <&vcc_3v3>;
- vccio6-supply = <&vcc_3v3>;
- vccio7-supply = <&vcc_3v3>;
+};
+&saradc {
- vref-supply = <&vcca_1v8>;
- status = "okay";
+};
+&sdhci {
- bus-width = <8>;
- mmc-hs200-1_8v;
- non-removable;
- vmmc-supply = <&vcc_3v3>;
- vqmmc-supply = <&vcc_1v8>;
- status = "okay";
+};
+&sdmmc0 {
- bus-width = <4>;
- cap-sd-highspeed;
- cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
- disable-wp;
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
- sd-uhs-sdr50;
- vmmc-supply = <&vcc3v3_sd>;
- vqmmc-supply = <&vccio_sd>;
- status = "okay";
+};
+&sdmmc1 {
- bus-width = <4>;
- cap-sd-highspeed;
- cap-sdio-irq;
- keep-power-in-suspend;
- mmc-pwrseq = <&sdio_pwrseq>;
- non-removable;
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>;
- vmmc-supply = <&vcc3v3_sys>;
- vqmmc-supply = <&vcca1v8_pmu>;
- status = "okay";
+};
+&sfc {
- pinctrl-0 = <&fspi_pins>;
- pinctrl-names = "default";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "okay";
- flash@0 {
compatible = "jedec,spi-nor";reg = <0>;spi-max-frequency = <24000000>;spi-rx-bus-width = <4>;spi-tx-bus-width = <1>;- };
+};
+&tsadc {
- status = "okay";
+};
+&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>;
- status = "okay";
- uart-has-rtscts;
- bluetooth {
compatible = "brcm,bcm4345c5";clocks = <&rk809 1>;clock-names = "lpo";device-wakeup-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;host-wakeup-gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;shutdown-gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>;pinctrl-names = "default";pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>;vbat-supply = <&vcc3v3_sys>;vddio-supply = <&vcca1v8_pmu>;- };
+};
+/*
- uart2_m0 is exposed on PI40
- pin 8 - uart2_tx_m0
- pin 10 - uart2_rx_m0
- */
+&uart2 {
- status = "okay";
+};
+&usb2phy0_host {
- phy-supply = <&vcc5v0_usb30_host>;
- status = "okay";
+};
+&usb2phy0_otg {
- phy-supply = <&vcc5v0_usb_otg>;
- status = "okay";
+};
+&usb2phy1_otg {
- phy-supply = <&vcc5v0_usb30_host>;
- status = "okay";
+};
+&usb2phy0 {
- status = "okay";
+};
+&usb2phy1 {
- status = "okay";
+};
+&usb_host0_xhci {
- status = "okay";
+};
+&usb_host1_xhci {
- status = "okay";
+};
+&usb_host0_ehci {
- status = "okay";
+};
+&usb_host0_ohci {
- status = "okay";
+};
+&vop {
- assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
- assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
- status = "okay";
+};
+&vop_mmu {
- status = "okay";
+};
+&vp0 {
- vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
reg = <ROCKCHIP_VOP2_EP_HDMI0>;remote-endpoint = <&hdmi_in_vp0>;- };
+}; diff --git a/board/pine64/quartz64_rk3566/MAINTAINERS b/board/pine64/quartz64_rk3566/MAINTAINERS index dbc0dfbd9787..2e637bf51ba3 100644 --- a/board/pine64/quartz64_rk3566/MAINTAINERS +++ b/board/pine64/quartz64_rk3566/MAINTAINERS @@ -5,5 +5,8 @@ S: Maintained F: board/pine64/quartz64_rk3566/ F: include/configs/quartz64_rk3566.h F: configs/quartz64-a-rk3566_defconfig +F: configs/quartz64-b-rk3566_defconfig F: arch/arm/dts/rk3566-quartz64-a.dts F: arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi +F: arch/arm/dts/rk3566-quartz64-b.dts +F: arch/arm/dts/rk3566-quartz64-b-u-boot.dtsi diff --git a/configs/quartz64-b-rk3566_defconfig b/configs/quartz64-b-rk3566_defconfig new file mode 100644 index 000000000000..b98c81f9dcef --- /dev/null +++ b/configs/quartz64-b-rk3566_defconfig @@ -0,0 +1,106 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_TEXT_BASE=0x00a00000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 +CONFIG_SF_DEFAULT_SPEED=24000000 +CONFIG_SF_DEFAULT_MODE=0x2000 +CONFIG_DEFAULT_DEVICE_TREE="rk3566-quartz64-b" +CONFIG_ROCKCHIP_RK3568=y +CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y +CONFIG_ROCKCHIP_SPI_IMAGE=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_STACK_R_ADDR=0x600000 +CONFIG_TARGET_QUARTZ64_RK3566=y +CONFIG_SPL_STACK=0x400000 +CONFIG_DEBUG_UART_BASE=0xFE660000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI=y +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_PCI=y +CONFIG_DEBUG_UART=y +CONFIG_AHCI=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-quartz64-b.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x4000000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000 +CONFIG_SPL_ATF=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_SCSI_AHCI=y +CONFIG_AHCI_PCI=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_SF_DEFAULT_BUS=4 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_NVME_PCI=y +CONFIG_PCIE_DW_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_SPL_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_SPL_RAM=y +CONFIG_SCSI=y +CONFIG_DM_SCSI=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_ROCKCHIP_SFC=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_ERRNO_STR=y diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index c7d4c835db80..1c0e10c40607 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -97,6 +97,7 @@ List of mainline supported Rockchip boards: - Rockchip Evb-RK3568 (evb-rk3568) - Hardkernel ODROID-M1 (odroid-m1-rk3568) - Pine64 Quartz64-A Board (quartz64-a-rk3566_defconfig)
- Pine64 Quartz64-B Board (quartz64-b-rk3566_defconfig)
- rk3588
- Rockchip EVB (evb-rk3588)
The Pine64 SOQuartz Model A board is a carrier board for the SOQuartz CM4-compatible compute module. It exposes PCIe, ethernet, USB, HDMI, CSI, DSI, eDP and a 40 pin GPIO header, and is powered by 12V DC.
Features tested with a SOQuartz 4GB v1.1 2022-07-11: - SD-card boot - eMMC boot - PCIe/NVMe/AHCI - USB host
Device tree is imported from linux v6.4.
Co-developed-by: Nicolas Frattaroli frattaroli.nicolas@gmail.com Signed-off-by: Nicolas Frattaroli frattaroli.nicolas@gmail.com Signed-off-by: Jonas Karlman jonas@kwiboo.se --- arch/arm/dts/Makefile | 1 + .../dts/rk3566-soquartz-model-a-u-boot.dtsi | 3 + arch/arm/dts/rk3566-soquartz-model-a.dts | 232 ++++++ arch/arm/dts/rk3566-soquartz-u-boot.dtsi | 30 + arch/arm/dts/rk3566-soquartz.dtsi | 688 ++++++++++++++++++ board/pine64/quartz64_rk3566/MAINTAINERS | 5 + configs/soquartz-model-a-rk3566_defconfig | 90 +++ doc/board/rockchip/rockchip.rst | 1 + 8 files changed, 1050 insertions(+) create mode 100644 arch/arm/dts/rk3566-soquartz-model-a-u-boot.dtsi create mode 100644 arch/arm/dts/rk3566-soquartz-model-a.dts create mode 100644 arch/arm/dts/rk3566-soquartz-u-boot.dtsi create mode 100644 arch/arm/dts/rk3566-soquartz.dtsi create mode 100644 configs/soquartz-model-a-rk3566_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 3cc921e5cc1e..aca2ec44a888 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -170,6 +170,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \ rk3566-quartz64-a.dtb \ rk3566-quartz64-b.dtb \ rk3566-radxa-cm3-io.dtb \ + rk3566-soquartz-model-a.dtb \ rk3568-evb.dtb \ rk3568-odroid-m1.dtb \ rk3568-rock-3a.dtb diff --git a/arch/arm/dts/rk3566-soquartz-model-a-u-boot.dtsi b/arch/arm/dts/rk3566-soquartz-model-a-u-boot.dtsi new file mode 100644 index 000000000000..0e662eafa4c7 --- /dev/null +++ b/arch/arm/dts/rk3566-soquartz-model-a-u-boot.dtsi @@ -0,0 +1,3 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include "rk3566-soquartz-u-boot.dtsi" diff --git a/arch/arm/dts/rk3566-soquartz-model-a.dts b/arch/arm/dts/rk3566-soquartz-model-a.dts new file mode 100644 index 000000000000..2208dbfb7f0a --- /dev/null +++ b/arch/arm/dts/rk3566-soquartz-model-a.dts @@ -0,0 +1,232 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include "rk3566-soquartz.dtsi" + +/ { + model = "PINE64 RK3566 SOQuartz on Model A carrier board"; + compatible = "pine64,soquartz-model-a", "pine64,soquartz", "rockchip,rk3566"; + + /* labeled DCIN_12V in schematic */ + vcc12v_dcin: vcc12v-dcin-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_usb: vcc5v0-usb-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + /* + * Labelled VCC3V0_SD in schematic to not conflict with PMIC + * regulator, it's 3.3v in actuality + */ + vcc3v0_sd: vcc3v0-sd-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v0_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc3v3_sys>; + }; + + vcc3v3_pcie: vcc3v3-pcie-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc12v_pcie: vcc12v-pcie-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_pcie"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + vin-supply = <&vcc12v_dcin>; + }; +}; + +/* phy for pcie */ +&combphy2 { + phy-supply = <&vcc3v3_sys>; + status = "okay"; +}; + +&gmac1 { + status = "okay"; +}; + +/* + * i2c1 is exposed on CM1 / Module1A + * pin 80 - SCL0 - i2c1_scl_m0, pullup to vcc3v3_pmu + * pin 82 - SDA0 - i2c1_sda_m0, pullup to vcc3v3_pmu + */ +&i2c1 { + status = "okay"; + + /* + * the rtc interrupt is tied to PMIC_PWRON, + * it will force reset the board if triggered. + */ + pcf85063: rtc@51 { + compatible = "nxp,pcf85063"; + reg = <0x51>; + }; +}; + +/* + * i2c2 is exposed on CM1 / Module1A - to PI40 + * pin 56 - GPIO3 - i2c2_scl_m1, pullup to vcc_3v3, shared with i2s1_8ch + * pin 58 - GPIO2 - i2c2_sda_m1, pullup to vcc_3v3 + */ +&i2c2 { + status = "disabled"; +}; + +/* + * i2c3 is exposed on CM1 / Module1A - to PI40 + * pin 35 - ID_SC(GPIO28) - i2c3_scl_m0, pullup to vcc_3v3 + * pin 36 - ID_SD(GPIO27) - i2c3_sda_m0, pullup to vcc_3v3 + */ +&i2c3 { + status = "disabled"; +}; + +/* + * i2c4 is exposed on CM2 / Module1B - to PI40 + * pin 45 - GPIO24 - i2c4_scl_m1 + * pin 47 - GPIO23 - i2c4_sda_m1 + */ +&i2c4 { + status = "disabled"; +}; + +/* + * i2s1_8ch is exposed on CM1 / Module1A - to PI40 + * pin 24 - GPIO26 - i2s1_sdi1_m1 + * pin 25 - GPIO21 - i2s1_sdo0_m1 + * pin 26 - GPIO19 - i2s1_lrck_tx_m1 + * pin 27 - GPIO20 - i2s1_sdi0_m1 + * pin 29 - GPIO16 - i2s1_sdi3_m1 + * pin 30 - GPIO6 - i2s1_sdi2_m1 + * pin 40 - GPIO9 - i2s1_sdo1_m1, shared with spi3 + * pin 41 - GPIO25 - i2s1_sdo2_m1 + * pin 49 - GPIO18 - i2s1_sclk_tx_m1 + * pin 50 - GPIO17 - i2s1_mclk_m1 + * pin 56 - GPIO3 - i2s1_sdo3_m1, shared with i2c2 + */ +&i2s1_8ch { + status = "disabled"; +}; + +&led_diy { + status = "okay"; +}; + +&led_work { + status = "okay"; +}; + +&pcie2x1 { + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + +&rgmii_phy1 { + status = "okay"; +}; + +&rgmii_phy1 { + status = "okay"; +}; + +/* + * saradc is exposed on CM1 / Module1A - to J2 + * pin 94 - AIN1 - saradc_vin3 + * pin 96 - AIN0 - saradc_vin2 + */ +&saradc { + status = "disabled"; +}; + +/* + * vmmc-supply is vcc3v3_sd on v1.0 and vcc3v0_sd on v1.1+ + * the soquartz SoM has SDMMC_PWR (CM1 pin 75) hardwired to vcc3v3_sys, + * so we use vcc3v3_sd here to ensure the regulator is enabled on older boards. + */ +&sdmmc0 { + vmmc-supply = <&vcc3v3_sd>; + status = "okay"; +}; + +/* + * spi3 is exposed on CM1 / Module1A - to PI40 + * pin 37 - GPIO7 - spi3_cs1_m0 + * pin 38 - GPIO11 - spi3_clk_m0 + * pin 39 - GPIO8 - spi3_cs0_m0 + * pin 40 - GPIO9 - spi3_miso_m0, shared with i2s1_8ch + * pin 44 - GPIO10 - spi3_mosi_m0 + */ +&spi3 { + status = "disabled"; +}; + +/* + * uart2 is exposed on CM1 / Module1A - to PI40 + * pin 51 - GPIO15 - uart2_rx_m0 + * pin 55 - GPIO14 - uart2_tx_m0 + */ +&uart2 { + status = "okay"; +}; + +/* + * uart7 is exposed on CM1 / Module1A - to PI40 + * pin 46 - GPIO22 - uart7_tx_m2 + * pin 47 - GPIO23 - uart7_rx_m2 + */ +&uart7 { + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy0_otg { + phy-supply = <&vcc5v0_usb>; + status = "okay"; +}; + +&usb_host0_xhci { + status = "okay"; +}; + +&vbus { + vin-supply = <&vcc5v0_usb>; +}; + +&vcc3v3_sd { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + status = "okay"; +}; diff --git a/arch/arm/dts/rk3566-soquartz-u-boot.dtsi b/arch/arm/dts/rk3566-soquartz-u-boot.dtsi new file mode 100644 index 000000000000..29aae242b07b --- /dev/null +++ b/arch/arm/dts/rk3566-soquartz-u-boot.dtsi @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include "rk356x-u-boot.dtsi" + +/ { + chosen { + stdout-path = &uart2; + }; +}; + +&pcie2x1 { + pinctrl-0 = <&pcie20m2_pins &pcie_reset_h>; +}; + +&sdhci { + cap-mmc-highspeed; + mmc-ddr-1_8v; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; +}; + +&uart2 { + bootph-all; + clock-frequency = <24000000>; + status = "okay"; +}; + +&usb_host0_xhci { + dr_mode = "host"; +}; diff --git a/arch/arm/dts/rk3566-soquartz.dtsi b/arch/arm/dts/rk3566-soquartz.dtsi new file mode 100644 index 000000000000..31aa2b8efe39 --- /dev/null +++ b/arch/arm/dts/rk3566-soquartz.dtsi @@ -0,0 +1,688 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/soc/rockchip,vop2.h> +#include "rk3566.dtsi" + +/ { + model = "Pine64 RK3566 SoQuartz SOM"; + compatible = "pine64,soquartz", "rockchip,rk3566"; + + aliases { + ethernet0 = &gmac1; + mmc0 = &sdmmc0; + mmc1 = &sdhci; + mmc2 = &sdmmc1; + }; + + chosen: chosen { + stdout-path = "serial2:1500000n8"; + }; + + gmac1_clkin: external-gmac1-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "gmac1_clkin"; + #clock-cells = <0>; + }; + + hdmi-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + led_diy: led-diy { + label = "diy-led"; + default-state = "on"; + gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + pinctrl-names = "default"; + pinctrl-0 = <&diy_led_enable_h>; + retain-state-suspended; + status = "disabled"; + }; + + led_work: led-work { + label = "work-led"; + default-state = "off"; + gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&work_led_enable_h>; + retain-state-suspended; + status = "disabled"; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + status = "okay"; + compatible = "mmc-pwrseq-simple"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + reset-gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_LOW>; + }; + + vbus: vbus-regulator { + compatible = "regulator-fixed"; + regulator-name = "vbus"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + /* sourced from vbus, vbus is provided by the carrier board */ + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vbus>; + }; + + vcc3v3_sys: vcc3v3-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; +}; + +&gmac1 { + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>, <&gmac1_clkin>; + clock_in_out = "input"; + phy-supply = <&vcc_3v3>; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m0_miim + &gmac1m0_tx_bus2 + &gmac1m0_rx_bus2 + &gmac1m0_rgmii_clk + &gmac1m0_clkinout + &gmac1m0_rgmii_bus>; + snps,reset-gpio = <&gpio0 RK_PC3 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f, also works well here */ + snps,reset-delays-us = <0 20000 100000>; + tx_delay = <0x30>; + rx_delay = <0x10>; + phy-handle = <&rgmii_phy1>; + status = "disabled"; +}; + +&gpio0 { + nextrst-hog { + gpio-hog; + /* + * GPIO_ACTIVE_LOW + output-low here means that the pin is set + * to high, because output-low decides the value pre-inversion. + */ + gpios = <RK_PA5 GPIO_ACTIVE_LOW>; + line-name = "nEXTRST"; + output-low; + }; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + avdd-0v9-supply = <&vdda0v9_image>; + avdd-1v8-supply = <&vcca1v8_image>; + status = "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&hdmi_sound { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + vdd_cpu: regulator@1c { + compatible = "tcs,tcs4525"; + reg = <0x1c>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-ramp-delay = <2300>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name = "vdd_logic"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-name = "vdd_gpu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_npu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda0v9_image"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda_0v9"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda0v9_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_acodec"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_pmu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_image: LDO_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_image"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-name = "vcc_3v3"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-name = "vcc3v3_sd"; + status = "disabled"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + }; + }; +}; + +/* + * i2c1 is exposed on CM1 / Module1A + * pin 80 - i2c1_scl_m0, pullup to vcc3v3_pmu + * pin 82 - i2c1_sda_m0, pullup to vcc3v3_pmu + */ +&i2c1 { + status = "disabled"; +}; + +/* + * i2c2 is exposed on CM1 / Module1A + * pin 56 - i2c2_scl_m1, pullup to vcc_3v3, shared with i2s1_8ch + * pin 58 - i2c2_sda_m1, pullup to vcc_3v3 + */ +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2m1_xfer>; + status = "disabled"; +}; + +/* + * i2c3 is exposed on CM1 / Module1A + * pin 35 - i2c3_scl_m0, pullup to vcc_3v3 + * pin 36 - i2c3_sda_m0, pullup to vcc_3v3 + */ +&i2c3 { + status = "disabled"; +}; + +/* + * i2c4 is exposed on CM2 / Module1B + * pin 45 - i2c4_scl_m1 + * pin 47 - i2c4_sda_m1 + */ +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m1_xfer>; + status = "disabled"; +}; + +&i2s0_8ch { + status = "okay"; +}; + +/* + * i2s1_8ch is exposed on CM1 / Module1A + * pin 24 - i2s1_sdi1_m1 + * pin 25 - i2s1_sdo0_m1 + * pin 26 - i2s1_lrck_tx_m1 + * pin 27 - i2s1_sdi0_m1 + * pin 29 - i2s1_sdi3_m1 + * pin 30 - i2s1_sdi2_m1 + * pin 40 - i2s1_sdo1_m1, shared with spi3 + * pin 41 - i2s1_sdo2_m1 + * pin 49 - i2s1_sclk_tx_m1 + * pin 50 - i2s1_mclk_m1 + * pin 56 - i2s1_sdo3_m1, shared with i2c2 + */ +&i2s1_8ch { + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m1_sclktx &i2s1m1_sclkrx + &i2s1m1_lrcktx &i2s1m1_lrckrx + &i2s1m1_sdi0 &i2s1m1_sdi1 + &i2s1m1_sdi2 &i2s1m1_sdi3 + &i2s1m1_sdo0 &i2s1m1_sdo1 + &i2s1m1_sdo2 &i2s1m1_sdo3>; + status = "disabled"; +}; + +&mdio1 { + rgmii_phy1: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + status = "disabled"; + }; +}; + +&pcie2x1 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_reset_h>; + reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; +}; + +&pinctrl { + bt { + bt_enable_h: bt-enable-h { + rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_host_wake_l: bt-host-wake-l { + rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + bt_wake_l: bt-wake-l { + rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + leds { + work_led_enable_h: work-led-enable-h { + rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + diy_led_enable_h: diy-led-enable-h { + rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie { + pcie_clkreq_h: pcie-clkreq-h { + rockchip,pins = <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + pcie_reset_h: pcie-reset-h { + rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vcc_3v3>; + vccio2-supply = <&vcc_1v8>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_3v3>; + vccio7-supply = <&vcc_3v3>; + status = "okay"; +}; + +/* + * saradc is exposed on CM1 / Module1A + * pin 94 - saradc_vin3 + * pin 96 - saradc_vin2 + */ +&saradc { + vref-supply = <&vcca_1v8>; + status = "disabled"; +}; + +&sdhci { + bus-width = <8>; + mmc-hs200-1_8v; + non-removable; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdmmc0 { + broken-cd; + bus-width = <4>; + cap-sd-highspeed; + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + vqmmc-supply = <&vccio_sd>; + status = "disabled"; +}; + +&sdmmc1 { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; + sd-uhs-sdr50; + vmmc-supply = <&vcc3v3_sys>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + +/* + * spi3 is exposed on CM1 / Module1A + * pin 37 - spi3_cs1_m0 + * pin 38 - spi3_clk_m0 + * pin 39 - spi3_cs0_m0 + * pin 40 - spi3_miso_m0, shared with i2s1_8ch + * pin 44 - spi3_mosi_m0 + */ +&spi3 { + status = "disabled"; +}; + +&tsadc { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + clocks = <&rk809 1>; + clock-names = "lpo"; + device-wakeup-gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>; + vbat-supply = <&vcc3v3_sys>; + vddio-supply = <&vcca1v8_pmu>; + }; +}; + +/* + * uart2 is exposed on CM1 / Module1A + * pin 51 - uart2_rx_m0 + * pin 55 - uart2_tx_m0 + */ +&uart2 { + status = "disabled"; +}; + +/* + * uart7 is exposed on CM1 / Module1A + * pin 46 - uart7_tx_m2 + * pin 47 - uart7_rx_m2 + */ +&uart7 { + pinctrl-names = "default"; + pinctrl-0 = <&uart7m2_xfer>; + status = "disabled"; +}; + +/* dwc3_otg is the only usb port available */ +&usb2phy0 { + status = "disabled"; +}; + +&usb2phy0_otg { + status = "disabled"; +}; + +&usb_host0_xhci { + status = "disabled"; +}; + +&vop { + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = <ROCKCHIP_VOP2_EP_HDMI0>; + remote-endpoint = <&hdmi_in_vp0>; + }; +}; diff --git a/board/pine64/quartz64_rk3566/MAINTAINERS b/board/pine64/quartz64_rk3566/MAINTAINERS index 2e637bf51ba3..748ff5033d93 100644 --- a/board/pine64/quartz64_rk3566/MAINTAINERS +++ b/board/pine64/quartz64_rk3566/MAINTAINERS @@ -6,7 +6,12 @@ F: board/pine64/quartz64_rk3566/ F: include/configs/quartz64_rk3566.h F: configs/quartz64-a-rk3566_defconfig F: configs/quartz64-b-rk3566_defconfig +F: configs/soquartz-model-a-rk3566_defconfig F: arch/arm/dts/rk3566-quartz64-a.dts F: arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi F: arch/arm/dts/rk3566-quartz64-b.dts F: arch/arm/dts/rk3566-quartz64-b-u-boot.dtsi +F: arch/arm/dts/rk3566-soquartz.dtsi +F: arch/arm/dts/rk3566-soquartz-u-boot.dtsi +F: arch/arm/dts/rk3566-soquartz-model-a.dts +F: arch/arm/dts/rk3566-soquartz-model-a-u-boot.dtsi diff --git a/configs/soquartz-model-a-rk3566_defconfig b/configs/soquartz-model-a-rk3566_defconfig new file mode 100644 index 000000000000..c3958579db73 --- /dev/null +++ b/configs/soquartz-model-a-rk3566_defconfig @@ -0,0 +1,90 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_TEXT_BASE=0x00a00000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 +CONFIG_DEFAULT_DEVICE_TREE="rk3566-soquartz-model-a" +CONFIG_ROCKCHIP_RK3568=y +CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_STACK_R_ADDR=0x600000 +CONFIG_TARGET_QUARTZ64_RK3566=y +CONFIG_SPL_STACK=0x400000 +CONFIG_DEBUG_UART_BASE=0xFE660000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_PCI=y +CONFIG_DEBUG_UART=y +CONFIG_AHCI=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-soquartz-model-a.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x4000000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_ATF=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_SCSI_AHCI=y +CONFIG_AHCI_PCI=y +CONFIG_SPL_CLK=y +CONFIG_GPIO_HOG=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_NVME_PCI=y +CONFIG_PCIE_DW_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_SPL_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_SPL_RAM=y +CONFIG_SCSI=y +CONFIG_DM_SCSI=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_ERRNO_STR=y diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index 1c0e10c40607..a17bcb2afc1a 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -98,6 +98,7 @@ List of mainline supported Rockchip boards: - Hardkernel ODROID-M1 (odroid-m1-rk3568) - Pine64 Quartz64-A Board (quartz64-a-rk3566_defconfig) - Pine64 Quartz64-B Board (quartz64-b-rk3566_defconfig) + - Pine64 SOQuartz on Model A (soquartz-model-a-rk3566_defconfig)
* rk3588 - Rockchip EVB (evb-rk3588)
On 2023-07-23 16:55, Jonas Karlman wrote:
The Pine64 SOQuartz Model A board is a carrier board for the SOQuartz CM4-compatible compute module. It exposes PCIe, ethernet, USB, HDMI, CSI, DSI, eDP and a 40 pin GPIO header, and is powered by 12V DC.
Features tested with a SOQuartz 4GB v1.1 2022-07-11:
- SD-card boot
- eMMC boot
- PCIe/NVMe/AHCI
- USB host
Device tree is imported from linux v6.4.
Co-developed-by: Nicolas Frattaroli frattaroli.nicolas@gmail.com Signed-off-by: Nicolas Frattaroli frattaroli.nicolas@gmail.com Signed-off-by: Jonas Karlman jonas@kwiboo.se
[...]
Boot log with ROCKCHIP_TPL=rk3566_ddr_1056MHz_v1.17.bin and BL31=rk3568_bl31_v1.43.elf: DDR V1.17 992b933606 typ 23/04/25-10:10:19 ln LP4/4x derate en, other dram:1x trefi ddrconfig:0 LPDDR4X, 324MHz BW=32 Col=10 Bk=8 CS0 Row=17 CS=1 Die BW=16 Size=4096MB tdqss: cs0 dqs0: 24ps, dqs1: -48ps, dqs2: -24ps, dqs3: -48ps,
change to: 324MHz clk skew:0x60
change to: 528MHz clk skew:0x58
change to: 780MHz clk skew:0x58
change to: 1056MHz(final freq) PHY drv:clk:36,ca:36,DQ:29,odt:60 vrefinner:16%, vrefout:22% dram drv:40,odt:80 vref_ca:00000071 clk skew:0x29 cs 0: the read training result: DQS0:0x3a, DQS1:0x3f, DQS2:0x3c, DQS3:0x39, min : 0x9 0x8 0x3 0x1 0x2 0x3 0x7 0x6 , 0x7 0x1 0x2 0x2 0x7 0xf 0x10 0xc , 0x7 0x6 0x6 0x6 0x5 0x1 0x5 0x4 , 0x1 0x2 0x7 0x2 0x7 0x6 0x6 0x4 , mid :0x27 0x27 0x22 0x1e 0x20 0x21 0x25 0x25 ,0x25 0x22 0x22 0x22 0x26 0x2e 0x2f 0x2b , 0x27 0x26 0x25 0x24 0x23 0x20 0x24 0x23 ,0x20 0x21 0x25 0x21 0x26 0x24 0x24 0x22 , max :0x46 0x47 0x41 0x3b 0x3f 0x40 0x44 0x45 ,0x44 0x43 0x42 0x43 0x46 0x4e 0x4e 0x4b , 0x47 0x46 0x45 0x43 0x42 0x40 0x44 0x43 ,0x40 0x40 0x44 0x40 0x45 0x42 0x42 0x40 , range:0x3d 0x3f 0x3e 0x3a 0x3d 0x3d 0x3d 0x3f ,0x3d 0x42 0x40 0x41 0x3f 0x3f 0x3e 0x3f , 0x40 0x40 0x3f 0x3d 0x3d 0x3f 0x3f 0x3f ,0x3f 0x3e 0x3d 0x3e 0x3e 0x3c 0x3c 0x3c , the write training result: DQS0:0x2c, DQS1:0x23, DQS2:0x26, DQS3:0x23, min :0x52 0x55 0x50 0x4d 0x4d 0x4e 0x53 0x54 0x54 ,0x43 0x3f 0x3f 0x41 0x46 0x4c 0x4c 0x4a 0x45 , 0x4a 0x4a 0x49 0x49 0x48 0x45 0x48 0x49 0x49 ,0x42 0x43 0x48 0x45 0x48 0x47 0x45 0x46 0x47 , mid :0x6f 0x72 0x6c 0x69 0x69 0x6a 0x6f 0x6f 0x70 ,0x5f 0x5c 0x5b 0x5d 0x62 0x69 0x68 0x66 0x61 , 0x67 0x67 0x66 0x66 0x64 0x61 0x63 0x65 0x66 ,0x5f 0x5f 0x65 0x61 0x65 0x64 0x61 0x63 0x64 , max :0x8c 0x8f 0x89 0x85 0x86 0x87 0x8c 0x8b 0x8d ,0x7c 0x7a 0x77 0x79 0x7e 0x86 0x84 0x83 0x7d , 0x85 0x84 0x83 0x83 0x80 0x7d 0x7f 0x82 0x83 ,0x7c 0x7c 0x83 0x7d 0x83 0x81 0x7e 0x80 0x81 , range:0x3a 0x3a 0x39 0x38 0x39 0x39 0x39 0x37 0x39 ,0x39 0x3b 0x38 0x38 0x38 0x3a 0x38 0x39 0x38 , 0x3b 0x3a 0x3a 0x3a 0x38 0x38 0x37 0x39 0x3a ,0x3a 0x39 0x3b 0x38 0x3b 0x3a 0x39 0x3a 0x3a , CA Training result: cs:0 min :0x3c 0x3a 0x36 0x37 0x38 0x30 0x38 ,0x3f 0x38 0x39 0x35 0x38 0x32 0x3a , cs:0 mid :0x7a 0x7c 0x73 0x77 0x75 0x71 0x67 ,0x7b 0x78 0x77 0x76 0x77 0x73 0x69 , cs:0 max :0xb8 0xbe 0xb1 0xb7 0xb3 0xb3 0x97 ,0xb7 0xb9 0xb5 0xb7 0xb6 0xb4 0x98 , cs:0 range:0x7c 0x84 0x7b 0x80 0x7b 0x83 0x5f ,0x78 0x81 0x7c 0x82 0x7e 0x82 0x5e , out
U-Boot SPL 2023.07 (Jul 23 2023 - 13:07:31 +0000) rockchip_sdhci_probe clk set rate fail! Trying to boot from MMC2 ## Checking hash(es) for config config-1 ... OK ## Checking hash(es) for Image atf-1 ... sha256+ OK ## Checking hash(es) for Image u-boot ... sha256+ OK ## Checking hash(es) for Image fdt-1 ... sha256+ OK ## Checking hash(es) for Image atf-2 ... sha256+ OK ## Checking hash(es) for Image atf-3 ... sha256+ OK ## Checking hash(es) for Image atf-4 ... sha256+ OK ## Checking hash(es) for Image atf-5 ... sha256+ OK ## Checking hash(es) for Image atf-6 ... sha256+ OK INFO: Preloader serial: 2 NOTICE: BL31: v2.3():v2.3-607-gbf602aff1:cl NOTICE: BL31: Built : 10:16:03, Jun 5 2023 INFO: GICv3 without legacy support detected. INFO: ARM GICv3 driver initialized in EL3 INFO: pmu v1 is valid 220114 INFO: dfs DDR fsp_param[0].freq_mhz= 1056MHz INFO: dfs DDR fsp_param[1].freq_mhz= 324MHz INFO: dfs DDR fsp_param[2].freq_mhz= 528MHz INFO: dfs DDR fsp_param[3].freq_mhz= 780MHz INFO: Using opteed sec cpu_context! INFO: boot cpu mask: 0 INFO: BL31: Initializing runtime services WARNING: No OPTEE provided by BL2 boot loader, Booting device without OPTEE initialization. SMC`s destined for OPTEE will return SMC_UNK ERROR: Error initializing runtime service opteed_fast INFO: BL31: Preparing for EL3 exit to normal world INFO: Entry point address = 0xa00000 INFO: SPSR = 0x3c9
U-Boot 2023.07 (Jul 23 2023 - 13:07:31 +0000)
Model: PINE64 RK3566 SOQuartz on Model A carrier board DRAM: 4 GiB (effective 3.7 GiB) PMIC: RK8090 (on=0x40, off=0x00) Core: 315 devices, 27 uclasses, devicetree: separate MMC: rockchip_sdhci_probe clk set rate fail! mmc@fe2b0000: 1, mmc@fe2c0000: 2, mmc@fe310000: 0 Loading Environment from nowhere... OK In: serial@fe660000 Out: serial@fe660000 Err: serial@fe660000 Model: PINE64 RK3566 SOQuartz on Model A carrier board Net: No ethernet found.
Hit any key to stop autoboot: 0 =>
Regards, Jonas
On 2023/7/23 22:55, Jonas Karlman wrote:
The Pine64 SOQuartz Model A board is a carrier board for the SOQuartz CM4-compatible compute module. It exposes PCIe, ethernet, USB, HDMI, CSI, DSI, eDP and a 40 pin GPIO header, and is powered by 12V DC.
Features tested with a SOQuartz 4GB v1.1 2022-07-11:
- SD-card boot
- eMMC boot
- PCIe/NVMe/AHCI
- USB host
Device tree is imported from linux v6.4.
Co-developed-by: Nicolas Frattaroli frattaroli.nicolas@gmail.com Signed-off-by: Nicolas Frattaroli frattaroli.nicolas@gmail.com Signed-off-by: Jonas Karlman jonas@kwiboo.se
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
arch/arm/dts/Makefile | 1 + .../dts/rk3566-soquartz-model-a-u-boot.dtsi | 3 + arch/arm/dts/rk3566-soquartz-model-a.dts | 232 ++++++ arch/arm/dts/rk3566-soquartz-u-boot.dtsi | 30 + arch/arm/dts/rk3566-soquartz.dtsi | 688 ++++++++++++++++++ board/pine64/quartz64_rk3566/MAINTAINERS | 5 + configs/soquartz-model-a-rk3566_defconfig | 90 +++ doc/board/rockchip/rockchip.rst | 1 + 8 files changed, 1050 insertions(+) create mode 100644 arch/arm/dts/rk3566-soquartz-model-a-u-boot.dtsi create mode 100644 arch/arm/dts/rk3566-soquartz-model-a.dts create mode 100644 arch/arm/dts/rk3566-soquartz-u-boot.dtsi create mode 100644 arch/arm/dts/rk3566-soquartz.dtsi create mode 100644 configs/soquartz-model-a-rk3566_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 3cc921e5cc1e..aca2ec44a888 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -170,6 +170,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \ rk3566-quartz64-a.dtb \ rk3566-quartz64-b.dtb \ rk3566-radxa-cm3-io.dtb \
- rk3566-soquartz-model-a.dtb \ rk3568-evb.dtb \ rk3568-odroid-m1.dtb \ rk3568-rock-3a.dtb
diff --git a/arch/arm/dts/rk3566-soquartz-model-a-u-boot.dtsi b/arch/arm/dts/rk3566-soquartz-model-a-u-boot.dtsi new file mode 100644 index 000000000000..0e662eafa4c7 --- /dev/null +++ b/arch/arm/dts/rk3566-soquartz-model-a-u-boot.dtsi @@ -0,0 +1,3 @@ +// SPDX-License-Identifier: GPL-2.0+
+#include "rk3566-soquartz-u-boot.dtsi" diff --git a/arch/arm/dts/rk3566-soquartz-model-a.dts b/arch/arm/dts/rk3566-soquartz-model-a.dts new file mode 100644 index 000000000000..2208dbfb7f0a --- /dev/null +++ b/arch/arm/dts/rk3566-soquartz-model-a.dts @@ -0,0 +1,232 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/dts-v1/;
+#include "rk3566-soquartz.dtsi"
+/ {
- model = "PINE64 RK3566 SOQuartz on Model A carrier board";
- compatible = "pine64,soquartz-model-a", "pine64,soquartz", "rockchip,rk3566";
- /* labeled DCIN_12V in schematic */
- vcc12v_dcin: vcc12v-dcin-regulator {
compatible = "regulator-fixed";regulator-name = "vcc12v_dcin";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <12000000>;regulator-max-microvolt = <12000000>;- };
- vcc5v0_usb: vcc5v0-usb-regulator {
compatible = "regulator-fixed";regulator-name = "vcc5v0_usb";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <5000000>;regulator-max-microvolt = <5000000>;vin-supply = <&vcc12v_dcin>;- };
- /*
* Labelled VCC3V0_SD in schematic to not conflict with PMIC* regulator, it's 3.3v in actuality*/- vcc3v0_sd: vcc3v0-sd-regulator {
compatible = "regulator-fixed";regulator-name = "vcc3v0_sd";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;vin-supply = <&vcc3v3_sys>;- };
- vcc3v3_pcie: vcc3v3-pcie-regulator {
compatible = "regulator-fixed";regulator-name = "vcc3v3_pcie";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;vin-supply = <&vcc12v_dcin>;- };
- vcc12v_pcie: vcc12v-pcie-regulator {
compatible = "regulator-fixed";regulator-name = "vcc12v_pcie";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <12000000>;regulator-max-microvolt = <12000000>;vin-supply = <&vcc12v_dcin>;- };
+};
+/* phy for pcie */ +&combphy2 {
- phy-supply = <&vcc3v3_sys>;
- status = "okay";
+};
+&gmac1 {
- status = "okay";
+};
+/*
- i2c1 is exposed on CM1 / Module1A
- pin 80 - SCL0 - i2c1_scl_m0, pullup to vcc3v3_pmu
- pin 82 - SDA0 - i2c1_sda_m0, pullup to vcc3v3_pmu
- */
+&i2c1 {
- status = "okay";
- /*
* the rtc interrupt is tied to PMIC_PWRON,* it will force reset the board if triggered.*/- pcf85063: rtc@51 {
compatible = "nxp,pcf85063";reg = <0x51>;- };
+};
+/*
- i2c2 is exposed on CM1 / Module1A - to PI40
- pin 56 - GPIO3 - i2c2_scl_m1, pullup to vcc_3v3, shared with i2s1_8ch
- pin 58 - GPIO2 - i2c2_sda_m1, pullup to vcc_3v3
- */
+&i2c2 {
- status = "disabled";
+};
+/*
- i2c3 is exposed on CM1 / Module1A - to PI40
- pin 35 - ID_SC(GPIO28) - i2c3_scl_m0, pullup to vcc_3v3
- pin 36 - ID_SD(GPIO27) - i2c3_sda_m0, pullup to vcc_3v3
- */
+&i2c3 {
- status = "disabled";
+};
+/*
- i2c4 is exposed on CM2 / Module1B - to PI40
- pin 45 - GPIO24 - i2c4_scl_m1
- pin 47 - GPIO23 - i2c4_sda_m1
- */
+&i2c4 {
- status = "disabled";
+};
+/*
- i2s1_8ch is exposed on CM1 / Module1A - to PI40
- pin 24 - GPIO26 - i2s1_sdi1_m1
- pin 25 - GPIO21 - i2s1_sdo0_m1
- pin 26 - GPIO19 - i2s1_lrck_tx_m1
- pin 27 - GPIO20 - i2s1_sdi0_m1
- pin 29 - GPIO16 - i2s1_sdi3_m1
- pin 30 - GPIO6 - i2s1_sdi2_m1
- pin 40 - GPIO9 - i2s1_sdo1_m1, shared with spi3
- pin 41 - GPIO25 - i2s1_sdo2_m1
- pin 49 - GPIO18 - i2s1_sclk_tx_m1
- pin 50 - GPIO17 - i2s1_mclk_m1
- pin 56 - GPIO3 - i2s1_sdo3_m1, shared with i2c2
- */
+&i2s1_8ch {
- status = "disabled";
+};
+&led_diy {
- status = "okay";
+};
+&led_work {
- status = "okay";
+};
+&pcie2x1 {
- vpcie3v3-supply = <&vcc3v3_pcie>;
- status = "okay";
+};
+&rgmii_phy1 {
- status = "okay";
+};
+&rgmii_phy1 {
- status = "okay";
+};
+/*
- saradc is exposed on CM1 / Module1A - to J2
- pin 94 - AIN1 - saradc_vin3
- pin 96 - AIN0 - saradc_vin2
- */
+&saradc {
- status = "disabled";
+};
+/*
- vmmc-supply is vcc3v3_sd on v1.0 and vcc3v0_sd on v1.1+
- the soquartz SoM has SDMMC_PWR (CM1 pin 75) hardwired to vcc3v3_sys,
- so we use vcc3v3_sd here to ensure the regulator is enabled on older boards.
- */
+&sdmmc0 {
- vmmc-supply = <&vcc3v3_sd>;
- status = "okay";
+};
+/*
- spi3 is exposed on CM1 / Module1A - to PI40
- pin 37 - GPIO7 - spi3_cs1_m0
- pin 38 - GPIO11 - spi3_clk_m0
- pin 39 - GPIO8 - spi3_cs0_m0
- pin 40 - GPIO9 - spi3_miso_m0, shared with i2s1_8ch
- pin 44 - GPIO10 - spi3_mosi_m0
- */
+&spi3 {
- status = "disabled";
+};
+/*
- uart2 is exposed on CM1 / Module1A - to PI40
- pin 51 - GPIO15 - uart2_rx_m0
- pin 55 - GPIO14 - uart2_tx_m0
- */
+&uart2 {
- status = "okay";
+};
+/*
- uart7 is exposed on CM1 / Module1A - to PI40
- pin 46 - GPIO22 - uart7_tx_m2
- pin 47 - GPIO23 - uart7_rx_m2
- */
+&uart7 {
- status = "okay";
+};
+&usb2phy0 {
- status = "okay";
+};
+&usb2phy0_otg {
- phy-supply = <&vcc5v0_usb>;
- status = "okay";
+};
+&usb_host0_xhci {
- status = "okay";
+};
+&vbus {
- vin-supply = <&vcc5v0_usb>;
+};
+&vcc3v3_sd {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- status = "okay";
+}; diff --git a/arch/arm/dts/rk3566-soquartz-u-boot.dtsi b/arch/arm/dts/rk3566-soquartz-u-boot.dtsi new file mode 100644 index 000000000000..29aae242b07b --- /dev/null +++ b/arch/arm/dts/rk3566-soquartz-u-boot.dtsi @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0+
+#include "rk356x-u-boot.dtsi"
+/ {
- chosen {
stdout-path = &uart2;- };
+};
+&pcie2x1 {
- pinctrl-0 = <&pcie20m2_pins &pcie_reset_h>;
+};
+&sdhci {
- cap-mmc-highspeed;
- mmc-ddr-1_8v;
- pinctrl-names = "default";
- pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
+};
+&uart2 {
- bootph-all;
- clock-frequency = <24000000>;
- status = "okay";
+};
+&usb_host0_xhci {
- dr_mode = "host";
+}; diff --git a/arch/arm/dts/rk3566-soquartz.dtsi b/arch/arm/dts/rk3566-soquartz.dtsi new file mode 100644 index 000000000000..31aa2b8efe39 --- /dev/null +++ b/arch/arm/dts/rk3566-soquartz.dtsi @@ -0,0 +1,688 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/soc/rockchip,vop2.h> +#include "rk3566.dtsi"
+/ {
- model = "Pine64 RK3566 SoQuartz SOM";
- compatible = "pine64,soquartz", "rockchip,rk3566";
- aliases {
ethernet0 = &gmac1;mmc0 = &sdmmc0;mmc1 = &sdhci;mmc2 = &sdmmc1;- };
- chosen: chosen {
stdout-path = "serial2:1500000n8";- };
- gmac1_clkin: external-gmac1-clock {
compatible = "fixed-clock";clock-frequency = <125000000>;clock-output-names = "gmac1_clkin";#clock-cells = <0>;- };
- hdmi-con {
compatible = "hdmi-connector";type = "a";port {hdmi_con_in: endpoint {remote-endpoint = <&hdmi_out_con>;};};- };
- leds {
compatible = "gpio-leds";led_diy: led-diy {label = "diy-led";default-state = "on";gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_LOW>;linux,default-trigger = "heartbeat";pinctrl-names = "default";pinctrl-0 = <&diy_led_enable_h>;retain-state-suspended;status = "disabled";};led_work: led-work {label = "work-led";default-state = "off";gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_LOW>;pinctrl-names = "default";pinctrl-0 = <&work_led_enable_h>;retain-state-suspended;status = "disabled";};- };
- sdio_pwrseq: sdio-pwrseq {
status = "okay";compatible = "mmc-pwrseq-simple";clocks = <&rk809 1>;clock-names = "ext_clock";pinctrl-names = "default";pinctrl-0 = <&wifi_enable_h>;reset-gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_LOW>;- };
- vbus: vbus-regulator {
compatible = "regulator-fixed";regulator-name = "vbus";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <5000000>;regulator-max-microvolt = <5000000>;- };
- /* sourced from vbus, vbus is provided by the carrier board */
- vcc5v0_sys: vcc5v0-sys-regulator {
compatible = "regulator-fixed";regulator-name = "vcc5v0_sys";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <5000000>;regulator-max-microvolt = <5000000>;vin-supply = <&vbus>;- };
- vcc3v3_sys: vcc3v3-sys-regulator {
compatible = "regulator-fixed";regulator-name = "vcc3v3_sys";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;vin-supply = <&vcc5v0_sys>;- };
+};
+&cpu0 {
- cpu-supply = <&vdd_cpu>;
+};
+&cpu1 {
- cpu-supply = <&vdd_cpu>;
+};
+&cpu2 {
- cpu-supply = <&vdd_cpu>;
+};
+&cpu3 {
- cpu-supply = <&vdd_cpu>;
+};
+&gmac1 {
- assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>;
- assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>, <&gmac1_clkin>;
- clock_in_out = "input";
- phy-supply = <&vcc_3v3>;
- phy-mode = "rgmii";
- pinctrl-names = "default";
- pinctrl-0 = <&gmac1m0_miim
&gmac1m0_tx_bus2&gmac1m0_rx_bus2&gmac1m0_rgmii_clk&gmac1m0_clkinout&gmac1m0_rgmii_bus>;- snps,reset-gpio = <&gpio0 RK_PC3 GPIO_ACTIVE_LOW>;
- snps,reset-active-low;
- /* Reset time is 20ms, 100ms for rtl8211f, also works well here */
- snps,reset-delays-us = <0 20000 100000>;
- tx_delay = <0x30>;
- rx_delay = <0x10>;
- phy-handle = <&rgmii_phy1>;
- status = "disabled";
+};
+&gpio0 {
- nextrst-hog {
gpio-hog;/** GPIO_ACTIVE_LOW + output-low here means that the pin is set* to high, because output-low decides the value pre-inversion.*/gpios = <RK_PA5 GPIO_ACTIVE_LOW>;line-name = "nEXTRST";output-low;- };
+};
+&gpu {
- mali-supply = <&vdd_gpu>;
- status = "okay";
+};
+&hdmi {
- avdd-0v9-supply = <&vdda0v9_image>;
- avdd-1v8-supply = <&vcca1v8_image>;
- status = "okay";
+};
+&hdmi_in {
- hdmi_in_vp0: endpoint {
remote-endpoint = <&vp0_out_hdmi>;- };
+};
+&hdmi_out {
- hdmi_out_con: endpoint {
remote-endpoint = <&hdmi_con_in>;- };
+};
+&hdmi_sound {
- status = "okay";
+};
+&i2c0 {
- status = "okay";
- vdd_cpu: regulator@1c {
compatible = "tcs,tcs4525";reg = <0x1c>;fcs,suspend-voltage-selector = <1>;regulator-name = "vdd_cpu";regulator-min-microvolt = <800000>;regulator-max-microvolt = <1150000>;regulator-ramp-delay = <2300>;regulator-always-on;regulator-boot-on;vin-supply = <&vcc5v0_sys>;regulator-state-mem {regulator-off-in-suspend;};- };
- rk809: pmic@20 {
compatible = "rockchip,rk809";reg = <0x20>;interrupt-parent = <&gpio0>;interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;#clock-cells = <1>;clock-output-names = "rk808-clkout1", "rk808-clkout2";pinctrl-names = "default";pinctrl-0 = <&pmic_int_l>;rockchip,system-power-controller;wakeup-source;vcc1-supply = <&vcc3v3_sys>;vcc2-supply = <&vcc3v3_sys>;vcc3-supply = <&vcc3v3_sys>;vcc4-supply = <&vcc3v3_sys>;vcc5-supply = <&vcc3v3_sys>;vcc6-supply = <&vcc3v3_sys>;vcc7-supply = <&vcc3v3_sys>;vcc8-supply = <&vcc3v3_sys>;vcc9-supply = <&vcc3v3_sys>;regulators {vdd_logic: DCDC_REG1 {regulator-name = "vdd_logic";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <500000>;regulator-max-microvolt = <1350000>;regulator-init-microvolt = <900000>;regulator-ramp-delay = <6001>;regulator-initial-mode = <0x2>;regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <900000>;};};vdd_gpu: DCDC_REG2 {regulator-name = "vdd_gpu";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <500000>;regulator-max-microvolt = <1350000>;regulator-init-microvolt = <900000>;regulator-ramp-delay = <6001>;regulator-initial-mode = <0x2>;regulator-state-mem {regulator-off-in-suspend;};};vcc_ddr: DCDC_REG3 {regulator-always-on;regulator-boot-on;regulator-initial-mode = <0x2>;regulator-name = "vcc_ddr";regulator-state-mem {regulator-on-in-suspend;};};vdd_npu: DCDC_REG4 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <500000>;regulator-max-microvolt = <1350000>;regulator-init-microvolt = <900000>;regulator-initial-mode = <0x2>;regulator-name = "vdd_npu";regulator-state-mem {regulator-off-in-suspend;};};vcc_1v8: DCDC_REG5 {regulator-name = "vcc_1v8";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <1800000>;};};vdda0v9_image: LDO_REG1 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <900000>;regulator-max-microvolt = <900000>;regulator-name = "vdda0v9_image";regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <900000>;};};vdda_0v9: LDO_REG2 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <900000>;regulator-max-microvolt = <900000>;regulator-name = "vdda_0v9";regulator-state-mem {regulator-off-in-suspend;};};vdda0v9_pmu: LDO_REG3 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <900000>;regulator-max-microvolt = <900000>;regulator-name = "vdda0v9_pmu";regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <900000>;};};vccio_acodec: LDO_REG4 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;regulator-name = "vccio_acodec";regulator-state-mem {regulator-off-in-suspend;};};vccio_sd: LDO_REG5 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1800000>;regulator-max-microvolt = <3300000>;regulator-name = "vccio_sd";regulator-state-mem {regulator-off-in-suspend;};};vcc3v3_pmu: LDO_REG6 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;regulator-name = "vcc3v3_pmu";regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <3300000>;};};vcca_1v8: LDO_REG7 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-name = "vcca_1v8";regulator-state-mem {regulator-off-in-suspend;};};vcca1v8_pmu: LDO_REG8 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-name = "vcca1v8_pmu";regulator-state-mem {regulator-off-in-suspend;};};vcca1v8_image: LDO_REG9 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-name = "vcca1v8_image";regulator-state-mem {regulator-off-in-suspend;};};vcc_3v3: SWITCH_REG1 {regulator-name = "vcc_3v3";regulator-state-mem {regulator-off-in-suspend;};};vcc3v3_sd: SWITCH_REG2 {regulator-name = "vcc3v3_sd";status = "disabled";regulator-state-mem {regulator-on-in-suspend;};};};- };
+};
+/*
- i2c1 is exposed on CM1 / Module1A
- pin 80 - i2c1_scl_m0, pullup to vcc3v3_pmu
- pin 82 - i2c1_sda_m0, pullup to vcc3v3_pmu
- */
+&i2c1 {
- status = "disabled";
+};
+/*
- i2c2 is exposed on CM1 / Module1A
- pin 56 - i2c2_scl_m1, pullup to vcc_3v3, shared with i2s1_8ch
- pin 58 - i2c2_sda_m1, pullup to vcc_3v3
- */
+&i2c2 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c2m1_xfer>;
- status = "disabled";
+};
+/*
- i2c3 is exposed on CM1 / Module1A
- pin 35 - i2c3_scl_m0, pullup to vcc_3v3
- pin 36 - i2c3_sda_m0, pullup to vcc_3v3
- */
+&i2c3 {
- status = "disabled";
+};
+/*
- i2c4 is exposed on CM2 / Module1B
- pin 45 - i2c4_scl_m1
- pin 47 - i2c4_sda_m1
- */
+&i2c4 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c4m1_xfer>;
- status = "disabled";
+};
+&i2s0_8ch {
- status = "okay";
+};
+/*
- i2s1_8ch is exposed on CM1 / Module1A
- pin 24 - i2s1_sdi1_m1
- pin 25 - i2s1_sdo0_m1
- pin 26 - i2s1_lrck_tx_m1
- pin 27 - i2s1_sdi0_m1
- pin 29 - i2s1_sdi3_m1
- pin 30 - i2s1_sdi2_m1
- pin 40 - i2s1_sdo1_m1, shared with spi3
- pin 41 - i2s1_sdo2_m1
- pin 49 - i2s1_sclk_tx_m1
- pin 50 - i2s1_mclk_m1
- pin 56 - i2s1_sdo3_m1, shared with i2c2
- */
+&i2s1_8ch {
- pinctrl-names = "default";
- pinctrl-0 = <&i2s1m1_sclktx &i2s1m1_sclkrx
&i2s1m1_lrcktx &i2s1m1_lrckrx&i2s1m1_sdi0 &i2s1m1_sdi1&i2s1m1_sdi2 &i2s1m1_sdi3&i2s1m1_sdo0 &i2s1m1_sdo1&i2s1m1_sdo2 &i2s1m1_sdo3>;- status = "disabled";
+};
+&mdio1 {
- rgmii_phy1: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";reg = <0>;status = "disabled";- };
+};
+&pcie2x1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pcie_reset_h>;
- reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
+};
+&pinctrl {
- bt {
bt_enable_h: bt-enable-h {rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;};bt_host_wake_l: bt-host-wake-l {rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_down>;};bt_wake_l: bt-wake-l {rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;};- };
- leds {
work_led_enable_h: work-led-enable-h {rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;};diy_led_enable_h: diy-led-enable-h {rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;};- };
- pcie {
pcie_clkreq_h: pcie-clkreq-h {rockchip,pins = <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;};pcie_reset_h: pcie-reset-h {rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;};- };
- pmic {
pmic_int_l: pmic-int-l {rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;};- };
- sdio-pwrseq {
wifi_enable_h: wifi-enable-h {rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;};- };
+};
+&pmu_io_domains {
- pmuio1-supply = <&vcc3v3_pmu>;
- pmuio2-supply = <&vcc3v3_pmu>;
- vccio1-supply = <&vcc_3v3>;
- vccio2-supply = <&vcc_1v8>;
- vccio3-supply = <&vccio_sd>;
- vccio4-supply = <&vcc_1v8>;
- vccio5-supply = <&vcc_3v3>;
- vccio6-supply = <&vcc_3v3>;
- vccio7-supply = <&vcc_3v3>;
- status = "okay";
+};
+/*
- saradc is exposed on CM1 / Module1A
- pin 94 - saradc_vin3
- pin 96 - saradc_vin2
- */
+&saradc {
- vref-supply = <&vcca_1v8>;
- status = "disabled";
+};
+&sdhci {
- bus-width = <8>;
- mmc-hs200-1_8v;
- non-removable;
- vmmc-supply = <&vcc_3v3>;
- vqmmc-supply = <&vcc_1v8>;
- status = "okay";
+};
+&sdmmc0 {
- broken-cd;
- bus-width = <4>;
- cap-sd-highspeed;
- disable-wp;
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
- vqmmc-supply = <&vccio_sd>;
- status = "disabled";
+};
+&sdmmc1 {
- bus-width = <4>;
- cap-sd-highspeed;
- cap-sdio-irq;
- keep-power-in-suspend;
- mmc-pwrseq = <&sdio_pwrseq>;
- non-removable;
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>;
- sd-uhs-sdr50;
- vmmc-supply = <&vcc3v3_sys>;
- vqmmc-supply = <&vcc_1v8>;
- status = "okay";
+};
+/*
- spi3 is exposed on CM1 / Module1A
- pin 37 - spi3_cs1_m0
- pin 38 - spi3_clk_m0
- pin 39 - spi3_cs0_m0
- pin 40 - spi3_miso_m0, shared with i2s1_8ch
- pin 44 - spi3_mosi_m0
- */
+&spi3 {
- status = "disabled";
+};
+&tsadc {
- status = "okay";
+};
+&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>;
- uart-has-rtscts;
- status = "okay";
- bluetooth {
compatible = "brcm,bcm43438-bt";clocks = <&rk809 1>;clock-names = "lpo";device-wakeup-gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>;host-wakeup-gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>;shutdown-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;pinctrl-names = "default";pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>;vbat-supply = <&vcc3v3_sys>;vddio-supply = <&vcca1v8_pmu>;- };
+};
+/*
- uart2 is exposed on CM1 / Module1A
- pin 51 - uart2_rx_m0
- pin 55 - uart2_tx_m0
- */
+&uart2 {
- status = "disabled";
+};
+/*
- uart7 is exposed on CM1 / Module1A
- pin 46 - uart7_tx_m2
- pin 47 - uart7_rx_m2
- */
+&uart7 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart7m2_xfer>;
- status = "disabled";
+};
+/* dwc3_otg is the only usb port available */ +&usb2phy0 {
- status = "disabled";
+};
+&usb2phy0_otg {
- status = "disabled";
+};
+&usb_host0_xhci {
- status = "disabled";
+};
+&vop {
- assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
- assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
- status = "okay";
+};
+&vop_mmu {
- status = "okay";
+};
+&vp0 {
- vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
reg = <ROCKCHIP_VOP2_EP_HDMI0>;remote-endpoint = <&hdmi_in_vp0>;- };
+}; diff --git a/board/pine64/quartz64_rk3566/MAINTAINERS b/board/pine64/quartz64_rk3566/MAINTAINERS index 2e637bf51ba3..748ff5033d93 100644 --- a/board/pine64/quartz64_rk3566/MAINTAINERS +++ b/board/pine64/quartz64_rk3566/MAINTAINERS @@ -6,7 +6,12 @@ F: board/pine64/quartz64_rk3566/ F: include/configs/quartz64_rk3566.h F: configs/quartz64-a-rk3566_defconfig F: configs/quartz64-b-rk3566_defconfig +F: configs/soquartz-model-a-rk3566_defconfig F: arch/arm/dts/rk3566-quartz64-a.dts F: arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi F: arch/arm/dts/rk3566-quartz64-b.dts F: arch/arm/dts/rk3566-quartz64-b-u-boot.dtsi +F: arch/arm/dts/rk3566-soquartz.dtsi +F: arch/arm/dts/rk3566-soquartz-u-boot.dtsi +F: arch/arm/dts/rk3566-soquartz-model-a.dts +F: arch/arm/dts/rk3566-soquartz-model-a-u-boot.dtsi diff --git a/configs/soquartz-model-a-rk3566_defconfig b/configs/soquartz-model-a-rk3566_defconfig new file mode 100644 index 000000000000..c3958579db73 --- /dev/null +++ b/configs/soquartz-model-a-rk3566_defconfig @@ -0,0 +1,90 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_TEXT_BASE=0x00a00000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 +CONFIG_DEFAULT_DEVICE_TREE="rk3566-soquartz-model-a" +CONFIG_ROCKCHIP_RK3568=y +CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_STACK_R_ADDR=0x600000 +CONFIG_TARGET_QUARTZ64_RK3566=y +CONFIG_SPL_STACK=0x400000 +CONFIG_DEBUG_UART_BASE=0xFE660000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_PCI=y +CONFIG_DEBUG_UART=y +CONFIG_AHCI=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-soquartz-model-a.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x4000000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_ATF=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_SCSI_AHCI=y +CONFIG_AHCI_PCI=y +CONFIG_SPL_CLK=y +CONFIG_GPIO_HOG=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_NVME_PCI=y +CONFIG_PCIE_DW_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_SPL_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_SPL_RAM=y +CONFIG_SCSI=y +CONFIG_DM_SCSI=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_ERRNO_STR=y diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index 1c0e10c40607..a17bcb2afc1a 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -98,6 +98,7 @@ List of mainline supported Rockchip boards: - Hardkernel ODROID-M1 (odroid-m1-rk3568) - Pine64 Quartz64-A Board (quartz64-a-rk3566_defconfig) - Pine64 Quartz64-B Board (quartz64-b-rk3566_defconfig)
- Pine64 SOQuartz on Model A (soquartz-model-a-rk3566_defconfig)
- rk3588
- Rockchip EVB (evb-rk3588)
The Pine64 SOQuartz Blade board is a carrier board for the SOQuartz CM4-compatible compute module. It features PoE, an M.2 slot, an SD card slot, HDMI, USB, serial and ethernet.
Features tested with a SOQuartz 4GB v1.1 2022-07-11: - SD-card boot - eMMC boot - PCIe/NVMe - USB host
Device tree is imported from linux v6.4.
Co-developed-by: Nicolas Frattaroli frattaroli.nicolas@gmail.com Signed-off-by: Nicolas Frattaroli frattaroli.nicolas@gmail.com Signed-off-by: Jonas Karlman jonas@kwiboo.se --- arch/arm/dts/Makefile | 1 + .../arm/dts/rk3566-soquartz-blade-u-boot.dtsi | 3 + arch/arm/dts/rk3566-soquartz-blade.dts | 194 ++++++++++++++++++ board/pine64/quartz64_rk3566/MAINTAINERS | 3 + configs/soquartz-blade-rk3566_defconfig | 90 ++++++++ doc/board/rockchip/rockchip.rst | 1 + 6 files changed, 292 insertions(+) create mode 100644 arch/arm/dts/rk3566-soquartz-blade-u-boot.dtsi create mode 100644 arch/arm/dts/rk3566-soquartz-blade.dts create mode 100644 configs/soquartz-blade-rk3566_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index aca2ec44a888..7a41675ef89d 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -170,6 +170,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \ rk3566-quartz64-a.dtb \ rk3566-quartz64-b.dtb \ rk3566-radxa-cm3-io.dtb \ + rk3566-soquartz-blade.dtb \ rk3566-soquartz-model-a.dtb \ rk3568-evb.dtb \ rk3568-odroid-m1.dtb \ diff --git a/arch/arm/dts/rk3566-soquartz-blade-u-boot.dtsi b/arch/arm/dts/rk3566-soquartz-blade-u-boot.dtsi new file mode 100644 index 000000000000..0e662eafa4c7 --- /dev/null +++ b/arch/arm/dts/rk3566-soquartz-blade-u-boot.dtsi @@ -0,0 +1,3 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include "rk3566-soquartz-u-boot.dtsi" diff --git a/arch/arm/dts/rk3566-soquartz-blade.dts b/arch/arm/dts/rk3566-soquartz-blade.dts new file mode 100644 index 000000000000..4e49bebf548b --- /dev/null +++ b/arch/arm/dts/rk3566-soquartz-blade.dts @@ -0,0 +1,194 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/pinctrl/rockchip.h> + +#include "rk3566-soquartz.dtsi" + +/ { + model = "PINE64 RK3566 SOQuartz on Blade carrier board"; + compatible = "pine64,soquartz-blade", "pine64,soquartz", "rockchip,rk3566"; + + /* labeled VCC3V0_SD in schematic to not conflict with PMIC regulator */ + vcc3v0_sd: vcc3v0-sd-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v0_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc3v3_sys>; + }; + + /* labeled VCC_SSD in schematic */ + vcc3v3_pcie_p: vcc3v3-pcie-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie_p"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vbus>; + }; + + vcc5v_dcin: vcc5v-dcin-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; +}; + +&combphy2 { + phy-supply = <&vcc3v3_sys>; + status = "okay"; +}; + +&gmac1 { + status = "okay"; +}; + +/* + * i2c1 is exposed on CM1 / Module1A + * pin 80 - SCL0 - i2c1_scl_m0, pullup to vcc3v3_pmu + * pin 82 - SDA0 - i2c1_sda_m0, pullup to vcc3v3_pmu + */ +&i2c1 { + status = "okay"; + +}; + +/* + * i2c2 is exposed on CM1 / Module1A - to PI40 + * pin 56 - GPIO3 - i2c2_scl_m1, pullup to vcc_3v3, shared with i2s1_8ch + * pin 58 - GPIO2 - i2c2_sda_m1, pullup to vcc_3v3 + */ +&i2c2 { + status = "disabled"; +}; + +/* + * i2c3 is exposed on CM1 / Module1A - to PI40 + * pin 35 - ID_SC(GPIO28) - i2c3_scl_m0, pullup to vcc_3v3 + * pin 36 - ID_SD(GPIO27) - i2c3_sda_m0, pullup to vcc_3v3 + */ +&i2c3 { + status = "disabled"; +}; + +/* + * i2c4 is exposed on CM2 / Module1B - to PI40 + * pin 45 - GPIO24 - i2c4_scl_m1 + * pin 47 - GPIO23 - i2c4_sda_m1 + */ +&i2c4 { + status = "disabled"; +}; + +/* + * i2s1_8ch is exposed on CM1 / Module1A - to PI40 + * pin 24 - GPIO26 - i2s1_sdi1_m1 + * pin 25 - GPIO21 - i2s1_sdo0_m1 + * pin 26 - GPIO19 - i2s1_lrck_tx_m1 + * pin 27 - GPIO20 - i2s1_sdi0_m1 + * pin 29 - GPIO16 - i2s1_sdi3_m1 + * pin 30 - GPIO6 - i2s1_sdi2_m1 + * pin 40 - GPIO9 - i2s1_sdo1_m1, shared with spi3 + * pin 41 - GPIO25 - i2s1_sdo2_m1 + * pin 49 - GPIO18 - i2s1_sclk_tx_m1 + * pin 50 - GPIO17 - i2s1_mclk_m1 + * pin 56 - GPIO3 - i2s1_sdo3_m1, shared with i2c2 + */ +&i2s1_8ch { + status = "disabled"; +}; + +&led_diy { + color = <LED_COLOR_ID_RED>; + function = LED_FUNCTION_DISK_ACTIVITY; + linux,default-trigger = "disk-activity"; + status = "okay"; +}; + +&led_work { + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_STATUS; + linux,default-trigger = "heartbeat"; + status = "okay"; +}; + +&pcie2x1 { + vpcie3v3-supply = <&vcc3v3_pcie_p>; + status = "okay"; +}; + +&rgmii_phy1 { + status = "okay"; +}; + +/* + * saradc is exposed on CM1 / Module1A - to J2 + * pin 94 - AIN1 - saradc_vin3 + * pin 96 - AIN0 - saradc_vin2 + */ +&saradc { + status = "disabled"; +}; + +&sdmmc0 { + vmmc-supply = <&vcc3v0_sd>; + status = "okay"; +}; + +/* + * spi3 is exposed on CM1 / Module1A - to PI40 + * pin 37 - GPIO7 - spi3_cs1_m0 + * pin 38 - GPIO11 - spi3_clk_m0 + * pin 39 - GPIO8 - spi3_cs0_m0 + * pin 40 - GPIO9 - spi3_miso_m0, shared with i2s1_8ch + * pin 44 - GPIO10 - spi3_mosi_m0 + */ +&spi3 { + status = "disabled"; +}; + +/* + * uart2 is exposed on CM1 / Module1A - to PI40 + * pin 51 - GPIO15 - uart2_rx_m0 + * pin 55 - GPIO14 - uart2_tx_m0 + */ +&uart2 { + status = "okay"; +}; + +/* + * uart7 is exposed on CM1 / Module1A - to PI40 + * pin 46 - GPIO22 - uart7_tx_m2 + * pin 47 - GPIO23 - uart7_rx_m2 + */ +&uart7 { + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy0_otg { + phy-supply = <&vbus>; + status = "okay"; +}; + +&usb_host0_xhci { + status = "okay"; +}; + +&vbus { + vin-supply = <&vcc5v_dcin>; +}; diff --git a/board/pine64/quartz64_rk3566/MAINTAINERS b/board/pine64/quartz64_rk3566/MAINTAINERS index 748ff5033d93..603d2ee9d5e9 100644 --- a/board/pine64/quartz64_rk3566/MAINTAINERS +++ b/board/pine64/quartz64_rk3566/MAINTAINERS @@ -6,6 +6,7 @@ F: board/pine64/quartz64_rk3566/ F: include/configs/quartz64_rk3566.h F: configs/quartz64-a-rk3566_defconfig F: configs/quartz64-b-rk3566_defconfig +F: configs/soquartz-blade-rk3566_defconfig F: configs/soquartz-model-a-rk3566_defconfig F: arch/arm/dts/rk3566-quartz64-a.dts F: arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi @@ -13,5 +14,7 @@ F: arch/arm/dts/rk3566-quartz64-b.dts F: arch/arm/dts/rk3566-quartz64-b-u-boot.dtsi F: arch/arm/dts/rk3566-soquartz.dtsi F: arch/arm/dts/rk3566-soquartz-u-boot.dtsi +F: arch/arm/dts/rk3566-soquartz-blade.dts +F: arch/arm/dts/rk3566-soquartz-blade-u-boot.dtsi F: arch/arm/dts/rk3566-soquartz-model-a.dts F: arch/arm/dts/rk3566-soquartz-model-a-u-boot.dtsi diff --git a/configs/soquartz-blade-rk3566_defconfig b/configs/soquartz-blade-rk3566_defconfig new file mode 100644 index 000000000000..181c284e73e9 --- /dev/null +++ b/configs/soquartz-blade-rk3566_defconfig @@ -0,0 +1,90 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_TEXT_BASE=0x00a00000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 +CONFIG_DEFAULT_DEVICE_TREE="rk3566-soquartz-blade" +CONFIG_ROCKCHIP_RK3568=y +CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_STACK_R_ADDR=0x600000 +CONFIG_TARGET_QUARTZ64_RK3566=y +CONFIG_SPL_STACK=0x400000 +CONFIG_DEBUG_UART_BASE=0xFE660000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_PCI=y +CONFIG_DEBUG_UART=y +CONFIG_AHCI=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-soquartz-blade.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x4000000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_ATF=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_SCSI_AHCI=y +CONFIG_AHCI_PCI=y +CONFIG_SPL_CLK=y +CONFIG_GPIO_HOG=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_NVME_PCI=y +CONFIG_PCIE_DW_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_SPL_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_SPL_RAM=y +CONFIG_SCSI=y +CONFIG_DM_SCSI=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_ERRNO_STR=y diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index a17bcb2afc1a..254a68b43eaf 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -98,6 +98,7 @@ List of mainline supported Rockchip boards: - Hardkernel ODROID-M1 (odroid-m1-rk3568) - Pine64 Quartz64-A Board (quartz64-a-rk3566_defconfig) - Pine64 Quartz64-B Board (quartz64-b-rk3566_defconfig) + - Pine64 SOQuartz on Blade (soquartz-blade-rk3566_defconfig) - Pine64 SOQuartz on Model A (soquartz-model-a-rk3566_defconfig)
* rk3588
On 2023-07-23 16:55, Jonas Karlman wrote:
The Pine64 SOQuartz Blade board is a carrier board for the SOQuartz CM4-compatible compute module. It features PoE, an M.2 slot, an SD card slot, HDMI, USB, serial and ethernet.
Features tested with a SOQuartz 4GB v1.1 2022-07-11:
- SD-card boot
- eMMC boot
- PCIe/NVMe
- USB host
Device tree is imported from linux v6.4.
Co-developed-by: Nicolas Frattaroli frattaroli.nicolas@gmail.com Signed-off-by: Nicolas Frattaroli frattaroli.nicolas@gmail.com Signed-off-by: Jonas Karlman jonas@kwiboo.se
[...]
Boot log with ROCKCHIP_TPL=rk3566_ddr_1056MHz_v1.17.bin and BL31=rk3568_bl31_v1.43.elf: DDR V1.17 992b933606 typ 23/04/25-10:10:19 ln LP4/4x derate en, other dram:1x trefi ddrconfig:0 LPDDR4X, 324MHz BW=32 Col=10 Bk=8 CS0 Row=17 CS=1 Die BW=16 Size=4096MB tdqss: cs0 dqs0: -24ps, dqs1: -72ps, dqs2: -24ps, dqs3: -72ps,
change to: 324MHz clk skew:0x61
change to: 528MHz clk skew:0x58
change to: 780MHz clk skew:0x58
change to: 1056MHz(final freq) PHY drv:clk:36,ca:36,DQ:29,odt:60 vrefinner:16%, vrefout:22% dram drv:40,odt:80 vref_ca:00000071 clk skew:0x2c cs 0: the read training result: DQS0:0x3a, DQS1:0x3c, DQS2:0x3b, DQS3:0x38, min : 0xa 0x9 0x5 0x1 0x3 0x4 0x9 0x7 , 0x6 0x2 0x2 0x2 0x8 0xe 0xe 0xb , 0x8 0x7 0x8 0x6 0x5 0x1 0x5 0x6 , 0x2 0x2 0x7 0x2 0x7 0x4 0x3 0x2 , mid :0x28 0x27 0x23 0x1f 0x21 0x22 0x27 0x25 ,0x24 0x20 0x21 0x21 0x25 0x2c 0x2c 0x29 , 0x27 0x26 0x25 0x24 0x23 0x20 0x23 0x24 ,0x20 0x20 0x24 0x20 0x25 0x22 0x22 0x21 , max :0x46 0x46 0x41 0x3d 0x40 0x40 0x45 0x44 ,0x43 0x3f 0x40 0x41 0x43 0x4b 0x4b 0x48 , 0x46 0x45 0x43 0x43 0x41 0x3f 0x42 0x42 ,0x3f 0x3e 0x42 0x3e 0x43 0x41 0x41 0x40 , range:0x3c 0x3d 0x3c 0x3c 0x3d 0x3c 0x3c 0x3d ,0x3d 0x3d 0x3e 0x3f 0x3b 0x3d 0x3d 0x3d , 0x3e 0x3e 0x3b 0x3d 0x3c 0x3e 0x3d 0x3c ,0x3d 0x3c 0x3b 0x3c 0x3c 0x3d 0x3e 0x3e , the write training result: DQS0:0x29, DQS1:0x23, DQS2:0x29, DQS3:0x23, min :0x51 0x55 0x4e 0x4c 0x4d 0x4d 0x52 0x52 0x54 ,0x46 0x43 0x43 0x46 0x49 0x4e 0x4f 0x4e 0x49 , 0x4d 0x4d 0x4e 0x4d 0x4b 0x48 0x4c 0x4e 0x4d ,0x44 0x46 0x48 0x46 0x4a 0x47 0x46 0x47 0x48 , mid :0x6e 0x71 0x6a 0x67 0x68 0x69 0x6e 0x6d 0x6f ,0x62 0x60 0x5f 0x62 0x65 0x6b 0x6b 0x6a 0x66 , 0x6a 0x6a 0x6a 0x69 0x67 0x65 0x68 0x69 0x69 ,0x60 0x61 0x65 0x62 0x66 0x64 0x62 0x63 0x64 , max :0x8b 0x8d 0x86 0x83 0x84 0x85 0x8a 0x89 0x8b ,0x7f 0x7d 0x7b 0x7e 0x82 0x88 0x88 0x86 0x83 , 0x88 0x87 0x86 0x86 0x84 0x82 0x84 0x85 0x86 ,0x7d 0x7c 0x82 0x7e 0x83 0x82 0x7e 0x80 0x80 , range:0x3a 0x38 0x38 0x37 0x37 0x38 0x38 0x37 0x37 ,0x39 0x3a 0x38 0x38 0x39 0x3a 0x39 0x38 0x3a , 0x3b 0x3a 0x38 0x39 0x39 0x3a 0x38 0x37 0x39 ,0x39 0x36 0x3a 0x38 0x39 0x3b 0x38 0x39 0x38 , CA Training result: cs:0 min :0x3d 0x3d 0x35 0x36 0x38 0x31 0x39 ,0x3c 0x36 0x39 0x35 0x39 0x32 0x3b , cs:0 mid :0x7b 0x7d 0x73 0x77 0x76 0x72 0x68 ,0x79 0x77 0x77 0x76 0x76 0x73 0x69 , cs:0 max :0xba 0xbe 0xb1 0xb8 0xb4 0xb3 0x97 ,0xb7 0xb8 0xb5 0xb7 0xb4 0xb4 0x98 , cs:0 range:0x7d 0x81 0x7c 0x82 0x7c 0x82 0x5e ,0x7b 0x82 0x7c 0x82 0x7b 0x82 0x5d , out
U-Boot SPL 2023.07 (Jul 23 2023 - 13:08:34 +0000) rockchip_sdhci_probe clk set rate fail! Trying to boot from MMC2 ## Checking hash(es) for config config-1 ... OK ## Checking hash(es) for Image atf-1 ... sha256+ OK ## Checking hash(es) for Image u-boot ... sha256+ OK ## Checking hash(es) for Image fdt-1 ... sha256+ OK ## Checking hash(es) for Image atf-2 ... sha256+ OK ## Checking hash(es) for Image atf-3 ... sha256+ OK ## Checking hash(es) for Image atf-4 ... sha256+ OK ## Checking hash(es) for Image atf-5 ... sha256+ OK ## Checking hash(es) for Image atf-6 ... sha256+ OK INFO: Preloader serial: 2 NOTICE: BL31: v2.3():v2.3-607-gbf602aff1:cl NOTICE: BL31: Built : 10:16:03, Jun 5 2023 INFO: GICv3 without legacy support detected. INFO: ARM GICv3 driver initialized in EL3 INFO: pmu v1 is valid 220114 INFO: dfs DDR fsp_param[0].freq_mhz= 1056MHz INFO: dfs DDR fsp_param[1].freq_mhz= 324MHz INFO: dfs DDR fsp_param[2].freq_mhz= 528MHz INFO: dfs DDR fsp_param[3].freq_mhz= 780MHz INFO: Using opteed sec cpu_context! INFO: boot cpu mask: 0 INFO: BL31: Initializing runtime services WARNING: No OPTEE provided by BL2 boot loader, Booting device without OPTEE initialization. SMC`s destined for OPTEE will return SMC_UNK ERROR: Error initializing runtime service opteed_fast INFO: BL31: Preparing for EL3 exit to normal world INFO: Entry point address = 0xa00000 INFO: SPSR = 0x3c9
U-Boot 2023.07 (Jul 23 2023 - 13:08:34 +0000)
Model: PINE64 RK3566 SOQuartz on Blade carrier board DRAM: 4 GiB (effective 3.7 GiB) PMIC: RK8090 (on=0x40, off=0x00) Core: 312 devices, 27 uclasses, devicetree: separate MMC: rockchip_sdhci_probe clk set rate fail! mmc@fe2b0000: 1, mmc@fe2c0000: 2, mmc@fe310000: 0 Loading Environment from nowhere... OK In: serial@fe660000 Out: serial@fe660000 Err: serial@fe660000 Model: PINE64 RK3566 SOQuartz on Blade carrier board Net: No ethernet found.
Hit any key to stop autoboot: 0 =>
Regards, Jonas
On 2023/7/23 22:55, Jonas Karlman wrote:
The Pine64 SOQuartz Blade board is a carrier board for the SOQuartz CM4-compatible compute module. It features PoE, an M.2 slot, an SD card slot, HDMI, USB, serial and ethernet.
Features tested with a SOQuartz 4GB v1.1 2022-07-11:
- SD-card boot
- eMMC boot
- PCIe/NVMe
- USB host
Device tree is imported from linux v6.4.
Co-developed-by: Nicolas Frattaroli frattaroli.nicolas@gmail.com Signed-off-by: Nicolas Frattaroli frattaroli.nicolas@gmail.com Signed-off-by: Jonas Karlman jonas@kwiboo.se
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
arch/arm/dts/Makefile | 1 + .../arm/dts/rk3566-soquartz-blade-u-boot.dtsi | 3 + arch/arm/dts/rk3566-soquartz-blade.dts | 194 ++++++++++++++++++ board/pine64/quartz64_rk3566/MAINTAINERS | 3 + configs/soquartz-blade-rk3566_defconfig | 90 ++++++++ doc/board/rockchip/rockchip.rst | 1 + 6 files changed, 292 insertions(+) create mode 100644 arch/arm/dts/rk3566-soquartz-blade-u-boot.dtsi create mode 100644 arch/arm/dts/rk3566-soquartz-blade.dts create mode 100644 configs/soquartz-blade-rk3566_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index aca2ec44a888..7a41675ef89d 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -170,6 +170,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \ rk3566-quartz64-a.dtb \ rk3566-quartz64-b.dtb \ rk3566-radxa-cm3-io.dtb \
- rk3566-soquartz-blade.dtb \ rk3566-soquartz-model-a.dtb \ rk3568-evb.dtb \ rk3568-odroid-m1.dtb \
diff --git a/arch/arm/dts/rk3566-soquartz-blade-u-boot.dtsi b/arch/arm/dts/rk3566-soquartz-blade-u-boot.dtsi new file mode 100644 index 000000000000..0e662eafa4c7 --- /dev/null +++ b/arch/arm/dts/rk3566-soquartz-blade-u-boot.dtsi @@ -0,0 +1,3 @@ +// SPDX-License-Identifier: GPL-2.0+
+#include "rk3566-soquartz-u-boot.dtsi" diff --git a/arch/arm/dts/rk3566-soquartz-blade.dts b/arch/arm/dts/rk3566-soquartz-blade.dts new file mode 100644 index 000000000000..4e49bebf548b --- /dev/null +++ b/arch/arm/dts/rk3566-soquartz-blade.dts @@ -0,0 +1,194 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/pinctrl/rockchip.h>
+#include "rk3566-soquartz.dtsi"
+/ {
- model = "PINE64 RK3566 SOQuartz on Blade carrier board";
- compatible = "pine64,soquartz-blade", "pine64,soquartz", "rockchip,rk3566";
- /* labeled VCC3V0_SD in schematic to not conflict with PMIC regulator */
- vcc3v0_sd: vcc3v0-sd-regulator {
compatible = "regulator-fixed";regulator-name = "vcc3v0_sd";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;vin-supply = <&vcc3v3_sys>;- };
- /* labeled VCC_SSD in schematic */
- vcc3v3_pcie_p: vcc3v3-pcie-regulator {
compatible = "regulator-fixed";regulator-name = "vcc3v3_pcie_p";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;vin-supply = <&vbus>;- };
- vcc5v_dcin: vcc5v-dcin-regulator {
compatible = "regulator-fixed";regulator-name = "vcc5v_dcin";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <5000000>;regulator-max-microvolt = <5000000>;- };
+};
+&combphy2 {
- phy-supply = <&vcc3v3_sys>;
- status = "okay";
+};
+&gmac1 {
- status = "okay";
+};
+/*
- i2c1 is exposed on CM1 / Module1A
- pin 80 - SCL0 - i2c1_scl_m0, pullup to vcc3v3_pmu
- pin 82 - SDA0 - i2c1_sda_m0, pullup to vcc3v3_pmu
- */
+&i2c1 {
- status = "okay";
+};
+/*
- i2c2 is exposed on CM1 / Module1A - to PI40
- pin 56 - GPIO3 - i2c2_scl_m1, pullup to vcc_3v3, shared with i2s1_8ch
- pin 58 - GPIO2 - i2c2_sda_m1, pullup to vcc_3v3
- */
+&i2c2 {
- status = "disabled";
+};
+/*
- i2c3 is exposed on CM1 / Module1A - to PI40
- pin 35 - ID_SC(GPIO28) - i2c3_scl_m0, pullup to vcc_3v3
- pin 36 - ID_SD(GPIO27) - i2c3_sda_m0, pullup to vcc_3v3
- */
+&i2c3 {
- status = "disabled";
+};
+/*
- i2c4 is exposed on CM2 / Module1B - to PI40
- pin 45 - GPIO24 - i2c4_scl_m1
- pin 47 - GPIO23 - i2c4_sda_m1
- */
+&i2c4 {
- status = "disabled";
+};
+/*
- i2s1_8ch is exposed on CM1 / Module1A - to PI40
- pin 24 - GPIO26 - i2s1_sdi1_m1
- pin 25 - GPIO21 - i2s1_sdo0_m1
- pin 26 - GPIO19 - i2s1_lrck_tx_m1
- pin 27 - GPIO20 - i2s1_sdi0_m1
- pin 29 - GPIO16 - i2s1_sdi3_m1
- pin 30 - GPIO6 - i2s1_sdi2_m1
- pin 40 - GPIO9 - i2s1_sdo1_m1, shared with spi3
- pin 41 - GPIO25 - i2s1_sdo2_m1
- pin 49 - GPIO18 - i2s1_sclk_tx_m1
- pin 50 - GPIO17 - i2s1_mclk_m1
- pin 56 - GPIO3 - i2s1_sdo3_m1, shared with i2c2
- */
+&i2s1_8ch {
- status = "disabled";
+};
+&led_diy {
- color = <LED_COLOR_ID_RED>;
- function = LED_FUNCTION_DISK_ACTIVITY;
- linux,default-trigger = "disk-activity";
- status = "okay";
+};
+&led_work {
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_STATUS;
- linux,default-trigger = "heartbeat";
- status = "okay";
+};
+&pcie2x1 {
- vpcie3v3-supply = <&vcc3v3_pcie_p>;
- status = "okay";
+};
+&rgmii_phy1 {
- status = "okay";
+};
+/*
- saradc is exposed on CM1 / Module1A - to J2
- pin 94 - AIN1 - saradc_vin3
- pin 96 - AIN0 - saradc_vin2
- */
+&saradc {
- status = "disabled";
+};
+&sdmmc0 {
- vmmc-supply = <&vcc3v0_sd>;
- status = "okay";
+};
+/*
- spi3 is exposed on CM1 / Module1A - to PI40
- pin 37 - GPIO7 - spi3_cs1_m0
- pin 38 - GPIO11 - spi3_clk_m0
- pin 39 - GPIO8 - spi3_cs0_m0
- pin 40 - GPIO9 - spi3_miso_m0, shared with i2s1_8ch
- pin 44 - GPIO10 - spi3_mosi_m0
- */
+&spi3 {
- status = "disabled";
+};
+/*
- uart2 is exposed on CM1 / Module1A - to PI40
- pin 51 - GPIO15 - uart2_rx_m0
- pin 55 - GPIO14 - uart2_tx_m0
- */
+&uart2 {
- status = "okay";
+};
+/*
- uart7 is exposed on CM1 / Module1A - to PI40
- pin 46 - GPIO22 - uart7_tx_m2
- pin 47 - GPIO23 - uart7_rx_m2
- */
+&uart7 {
- status = "okay";
+};
+&usb2phy0 {
- status = "okay";
+};
+&usb2phy0_otg {
- phy-supply = <&vbus>;
- status = "okay";
+};
+&usb_host0_xhci {
- status = "okay";
+};
+&vbus {
- vin-supply = <&vcc5v_dcin>;
+}; diff --git a/board/pine64/quartz64_rk3566/MAINTAINERS b/board/pine64/quartz64_rk3566/MAINTAINERS index 748ff5033d93..603d2ee9d5e9 100644 --- a/board/pine64/quartz64_rk3566/MAINTAINERS +++ b/board/pine64/quartz64_rk3566/MAINTAINERS @@ -6,6 +6,7 @@ F: board/pine64/quartz64_rk3566/ F: include/configs/quartz64_rk3566.h F: configs/quartz64-a-rk3566_defconfig F: configs/quartz64-b-rk3566_defconfig +F: configs/soquartz-blade-rk3566_defconfig F: configs/soquartz-model-a-rk3566_defconfig F: arch/arm/dts/rk3566-quartz64-a.dts F: arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi @@ -13,5 +14,7 @@ F: arch/arm/dts/rk3566-quartz64-b.dts F: arch/arm/dts/rk3566-quartz64-b-u-boot.dtsi F: arch/arm/dts/rk3566-soquartz.dtsi F: arch/arm/dts/rk3566-soquartz-u-boot.dtsi +F: arch/arm/dts/rk3566-soquartz-blade.dts +F: arch/arm/dts/rk3566-soquartz-blade-u-boot.dtsi F: arch/arm/dts/rk3566-soquartz-model-a.dts F: arch/arm/dts/rk3566-soquartz-model-a-u-boot.dtsi diff --git a/configs/soquartz-blade-rk3566_defconfig b/configs/soquartz-blade-rk3566_defconfig new file mode 100644 index 000000000000..181c284e73e9 --- /dev/null +++ b/configs/soquartz-blade-rk3566_defconfig @@ -0,0 +1,90 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_TEXT_BASE=0x00a00000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 +CONFIG_DEFAULT_DEVICE_TREE="rk3566-soquartz-blade" +CONFIG_ROCKCHIP_RK3568=y +CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_STACK_R_ADDR=0x600000 +CONFIG_TARGET_QUARTZ64_RK3566=y +CONFIG_SPL_STACK=0x400000 +CONFIG_DEBUG_UART_BASE=0xFE660000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_PCI=y +CONFIG_DEBUG_UART=y +CONFIG_AHCI=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-soquartz-blade.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x4000000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_ATF=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_SCSI_AHCI=y +CONFIG_AHCI_PCI=y +CONFIG_SPL_CLK=y +CONFIG_GPIO_HOG=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_NVME_PCI=y +CONFIG_PCIE_DW_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_SPL_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_SPL_RAM=y +CONFIG_SCSI=y +CONFIG_DM_SCSI=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_ERRNO_STR=y diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index a17bcb2afc1a..254a68b43eaf 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -98,6 +98,7 @@ List of mainline supported Rockchip boards: - Hardkernel ODROID-M1 (odroid-m1-rk3568) - Pine64 Quartz64-A Board (quartz64-a-rk3566_defconfig) - Pine64 Quartz64-B Board (quartz64-b-rk3566_defconfig)
- Pine64 SOQuartz on Blade (soquartz-blade-rk3566_defconfig) - Pine64 SOQuartz on Model A (soquartz-model-a-rk3566_defconfig)
- rk3588
The Pine64 SOQuartz compute module is mostly pin-compatible with the RPi CM4 form factor. Therefore, it can slot into the official Raspberry Pi CM4 IO carrier board. Add this configuration to U-Boot.
Features tested with a SOQuartz 4GB v1.1 2022-07-11: - SD-card boot - eMMC boot - USB host
Device tree is imported from linux v6.4.
Co-developed-by: Nicolas Frattaroli frattaroli.nicolas@gmail.com Signed-off-by: Nicolas Frattaroli frattaroli.nicolas@gmail.com Signed-off-by: Jonas Karlman jonas@kwiboo.se --- arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3566-soquartz-cm4-u-boot.dtsi | 3 + arch/arm/dts/rk3566-soquartz-cm4.dts | 192 +++++++++++++++++++ board/pine64/quartz64_rk3566/MAINTAINERS | 3 + configs/soquartz-cm4-rk3566_defconfig | 90 +++++++++ doc/board/rockchip/rockchip.rst | 1 + 6 files changed, 290 insertions(+) create mode 100644 arch/arm/dts/rk3566-soquartz-cm4-u-boot.dtsi create mode 100644 arch/arm/dts/rk3566-soquartz-cm4.dts create mode 100644 configs/soquartz-cm4-rk3566_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 7a41675ef89d..dabbf116914c 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -171,6 +171,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \ rk3566-quartz64-b.dtb \ rk3566-radxa-cm3-io.dtb \ rk3566-soquartz-blade.dtb \ + rk3566-soquartz-cm4.dtb \ rk3566-soquartz-model-a.dtb \ rk3568-evb.dtb \ rk3568-odroid-m1.dtb \ diff --git a/arch/arm/dts/rk3566-soquartz-cm4-u-boot.dtsi b/arch/arm/dts/rk3566-soquartz-cm4-u-boot.dtsi new file mode 100644 index 000000000000..0e662eafa4c7 --- /dev/null +++ b/arch/arm/dts/rk3566-soquartz-cm4-u-boot.dtsi @@ -0,0 +1,3 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include "rk3566-soquartz-u-boot.dtsi" diff --git a/arch/arm/dts/rk3566-soquartz-cm4.dts b/arch/arm/dts/rk3566-soquartz-cm4.dts new file mode 100644 index 000000000000..cddf6cd2fecb --- /dev/null +++ b/arch/arm/dts/rk3566-soquartz-cm4.dts @@ -0,0 +1,192 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include "rk3566-soquartz.dtsi" + +/ { + model = "Pine64 RK3566 SoQuartz with CM4-IO Carrier Board"; + compatible = "pine64,soquartz-cm4io", "pine64,soquartz", "rockchip,rk3566"; + + /* labeled +12v in schematic */ + vcc12v_dcin: vcc12v-dcin-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + /* labeled +5v in schematic */ + vcc_5v: vcc-5v-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_5v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc_sd_pwr: vcc-sd-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_sd_pwr"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc3v3_sys>; + }; +}; + +/* phy for pcie */ +&combphy2 { + phy-supply = <&vcc3v3_sys>; + status = "okay"; +}; + +&gmac1 { + status = "okay"; +}; + +/* + * i2c1 is exposed on CM1 / Module1A + * pin 80 - SCL0 - i2c1_scl_m0, pullup to vcc3v3_pmu + * pin 82 - SDA0 - i2c1_sda_m0, pullup to vcc3v3_pmu + */ +&i2c1 { + status = "okay"; + + /* + * the rtc interrupt is tied to PMIC_PWRON, + * it will force reset the board if triggered. + */ + pcf85063: rtc@51 { + compatible = "nxp,pcf85063"; + reg = <0x51>; + }; +}; + +/* + * i2c2 is exposed on CM1 / Module1A - to PI40 + * pin 56 - GPIO3 - i2c2_scl_m1, pullup to vcc_3v3, shared with i2s1_8ch + * pin 58 - GPIO2 - i2c2_sda_m1, pullup to vcc_3v3 + */ +&i2c2 { + status = "disabled"; +}; + +/* + * i2c3 is exposed on CM1 / Module1A - to PI40 + * pin 35 - ID_SC(GPIO28) - i2c3_scl_m0, pullup to vcc_3v3 + * pin 36 - ID_SD(GPIO27) - i2c3_sda_m0, pullup to vcc_3v3 + */ +&i2c3 { + status = "disabled"; +}; + +/* + * i2c4 is exposed on CM2 / Module1B - to PI40 + * pin 45 - GPIO24 - i2c4_scl_m1 + * pin 47 - GPIO23 - i2c4_sda_m1 + */ +&i2c4 { + status = "disabled"; +}; + +/* + * i2s1_8ch is exposed on CM1 / Module1A - to PI40 + * pin 24 - GPIO26 - i2s1_sdi1_m1 + * pin 25 - GPIO21 - i2s1_sdo0_m1 + * pin 26 - GPIO19 - i2s1_lrck_tx_m1 + * pin 27 - GPIO20 - i2s1_sdi0_m1 + * pin 29 - GPIO16 - i2s1_sdi3_m1 + * pin 30 - GPIO6 - i2s1_sdi2_m1 + * pin 40 - GPIO9 - i2s1_sdo1_m1, shared with spi3 + * pin 41 - GPIO25 - i2s1_sdo2_m1 + * pin 49 - GPIO18 - i2s1_sclk_tx_m1 + * pin 50 - GPIO17 - i2s1_mclk_m1 + * pin 56 - GPIO3 - i2s1_sdo3_m1, shared with i2c2 + */ +&i2s1_8ch { + status = "disabled"; +}; + +&led_diy { + status = "okay"; +}; + +&led_work { + status = "okay"; +}; + +&pcie2x1 { + vpcie3v3-supply = <&vcc_3v3>; + status = "okay"; +}; + +&rgmii_phy1 { + status = "okay"; +}; + +/* + * saradc is exposed on CM1 / Module1A - to J2 + * pin 94 - AIN1 - saradc_vin3 + * pin 96 - AIN0 - saradc_vin2 + */ +&saradc { + status = "disabled"; +}; + +&sdmmc0 { + vmmc-supply = <&vcc_sd_pwr>; + status = "okay"; +}; + +/* + * spi3 is exposed on CM1 / Module1A - to PI40 + * pin 37 - GPIO7 - spi3_cs1_m0 + * pin 38 - GPIO11 - spi3_clk_m0 + * pin 39 - GPIO8 - spi3_cs0_m0 + * pin 40 - GPIO9 - spi3_miso_m0, shared with i2s1_8ch + * pin 44 - GPIO10 - spi3_mosi_m0 + */ +&spi3 { + status = "disabled"; +}; + +/* + * uart2 is exposed on CM1 / Module1A - to PI40 + * pin 51 - GPIO15 - uart2_rx_m0 + * pin 55 - GPIO14 - uart2_tx_m0 + */ +&uart2 { + status = "okay"; +}; + +/* + * uart7 is exposed on CM1 / Module1A - to PI40 + * pin 46 - GPIO22 - uart7_tx_m2 + * pin 47 - GPIO23 - uart7_rx_m2 + */ +&uart7 { + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy0_otg { + phy-supply = <&vcc_5v>; + status = "okay"; +}; + +&usb_host0_xhci { + status = "okay"; +}; + +&vbus { + vin-supply = <&vcc_5v>; +}; diff --git a/board/pine64/quartz64_rk3566/MAINTAINERS b/board/pine64/quartz64_rk3566/MAINTAINERS index 603d2ee9d5e9..6b75b35a1243 100644 --- a/board/pine64/quartz64_rk3566/MAINTAINERS +++ b/board/pine64/quartz64_rk3566/MAINTAINERS @@ -7,6 +7,7 @@ F: include/configs/quartz64_rk3566.h F: configs/quartz64-a-rk3566_defconfig F: configs/quartz64-b-rk3566_defconfig F: configs/soquartz-blade-rk3566_defconfig +F: configs/soquartz-cm4-rk3566_defconfig F: configs/soquartz-model-a-rk3566_defconfig F: arch/arm/dts/rk3566-quartz64-a.dts F: arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi @@ -16,5 +17,7 @@ F: arch/arm/dts/rk3566-soquartz.dtsi F: arch/arm/dts/rk3566-soquartz-u-boot.dtsi F: arch/arm/dts/rk3566-soquartz-blade.dts F: arch/arm/dts/rk3566-soquartz-blade-u-boot.dtsi +F: arch/arm/dts/rk3566-soquartz-cm4.dts +F: arch/arm/dts/rk3566-soquartz-cm4-u-boot.dtsi F: arch/arm/dts/rk3566-soquartz-model-a.dts F: arch/arm/dts/rk3566-soquartz-model-a-u-boot.dtsi diff --git a/configs/soquartz-cm4-rk3566_defconfig b/configs/soquartz-cm4-rk3566_defconfig new file mode 100644 index 000000000000..7e290351477e --- /dev/null +++ b/configs/soquartz-cm4-rk3566_defconfig @@ -0,0 +1,90 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_TEXT_BASE=0x00a00000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 +CONFIG_DEFAULT_DEVICE_TREE="rk3566-soquartz-cm4" +CONFIG_ROCKCHIP_RK3568=y +CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_STACK_R_ADDR=0x600000 +CONFIG_TARGET_QUARTZ64_RK3566=y +CONFIG_SPL_STACK=0x400000 +CONFIG_DEBUG_UART_BASE=0xFE660000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_PCI=y +CONFIG_DEBUG_UART=y +CONFIG_AHCI=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-soquartz-cm4.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x4000000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_ATF=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_SCSI_AHCI=y +CONFIG_AHCI_PCI=y +CONFIG_SPL_CLK=y +CONFIG_GPIO_HOG=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_NVME_PCI=y +CONFIG_PCIE_DW_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_SPL_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_SPL_RAM=y +CONFIG_SCSI=y +CONFIG_DM_SCSI=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_ERRNO_STR=y diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index 254a68b43eaf..3cd5de55120b 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -99,6 +99,7 @@ List of mainline supported Rockchip boards: - Pine64 Quartz64-A Board (quartz64-a-rk3566_defconfig) - Pine64 Quartz64-B Board (quartz64-b-rk3566_defconfig) - Pine64 SOQuartz on Blade (soquartz-blade-rk3566_defconfig) + - Pine64 SOQuartz on CM4-IO (soquartz-cm4-rk3566_defconfig) - Pine64 SOQuartz on Model A (soquartz-model-a-rk3566_defconfig)
* rk3588
On 2023-07-23 16:55, Jonas Karlman wrote:
The Pine64 SOQuartz compute module is mostly pin-compatible with the RPi CM4 form factor. Therefore, it can slot into the official Raspberry Pi CM4 IO carrier board. Add this configuration to U-Boot.
Features tested with a SOQuartz 4GB v1.1 2022-07-11:
- SD-card boot
- eMMC boot
- USB host
Device tree is imported from linux v6.4.
Co-developed-by: Nicolas Frattaroli frattaroli.nicolas@gmail.com Signed-off-by: Nicolas Frattaroli frattaroli.nicolas@gmail.com Signed-off-by: Jonas Karlman jonas@kwiboo.se
[...]
Boot log with ROCKCHIP_TPL=rk3566_ddr_1056MHz_v1.17.bin and BL31=rk3568_bl31_v1.43.elf:
DDR V1.17 992b933606 typ 23/04/25-10:10:19 ln LP4/4x derate en, other dram:1x trefi ddrconfig:0 LPDDR4X, 324MHz BW=32 Col=10 Bk=8 CS0 Row=17 CS=1 Die BW=16 Size=4096MB tdqss: cs0 dqs0: -24ps, dqs1: -72ps, dqs2: -24ps, dqs3: -72ps,
change to: 324MHz clk skew:0x61
change to: 528MHz clk skew:0x58
change to: 780MHz clk skew:0x58
change to: 1056MHz(final freq) PHY drv:clk:36,ca:36,DQ:29,odt:60 vrefinner:16%, vrefout:22% dram drv:40,odt:80 vref_ca:00000071 clk skew:0x2c cs 0: the read training result: DQS0:0x3a, DQS1:0x3c, DQS2:0x3b, DQS3:0x37, min : 0xa 0x9 0x5 0x1 0x4 0x4 0x9 0x7 , 0x6 0x2 0x2 0x1 0x8 0xe 0xe 0xb , 0x8 0x6 0x8 0x6 0x5 0x2 0x5 0x6 , 0x1 0x1 0x6 0x1 0x6 0x3 0x3 0x2 , mid :0x28 0x28 0x23 0x1f 0x22 0x22 0x27 0x25 ,0x24 0x20 0x21 0x21 0x25 0x2c 0x2d 0x29 , 0x27 0x25 0x25 0x24 0x23 0x20 0x23 0x24 ,0x20 0x1f 0x24 0x1f 0x24 0x22 0x21 0x20 , max :0x46 0x47 0x41 0x3d 0x40 0x40 0x45 0x44 ,0x43 0x3f 0x40 0x41 0x43 0x4b 0x4c 0x48 , 0x46 0x45 0x43 0x43 0x41 0x3f 0x42 0x42 ,0x3f 0x3d 0x42 0x3d 0x42 0x41 0x40 0x3e , range:0x3c 0x3e 0x3c 0x3c 0x3c 0x3c 0x3c 0x3d ,0x3d 0x3d 0x3e 0x40 0x3b 0x3d 0x3e 0x3d , 0x3e 0x3f 0x3b 0x3d 0x3c 0x3d 0x3d 0x3c ,0x3e 0x3c 0x3c 0x3c 0x3c 0x3e 0x3d 0x3c , the write training result: DQS0:0x29, DQS1:0x23, DQS2:0x29, DQS3:0x23, min :0x51 0x55 0x4e 0x4b 0x4d 0x4d 0x52 0x53 0x55 ,0x46 0x43 0x43 0x46 0x49 0x4e 0x4f 0x4e 0x49 , 0x4d 0x4d 0x4e 0x4d 0x4b 0x48 0x4c 0x4e 0x4d ,0x44 0x46 0x48 0x46 0x4a 0x47 0x46 0x47 0x49 , mid :0x6e 0x71 0x6a 0x67 0x69 0x69 0x6e 0x6e 0x70 ,0x62 0x60 0x5f 0x62 0x65 0x6b 0x6b 0x6a 0x66 , 0x6a 0x6a 0x6a 0x69 0x67 0x65 0x68 0x69 0x69 ,0x60 0x61 0x65 0x62 0x66 0x64 0x62 0x63 0x65 , max :0x8b 0x8d 0x86 0x83 0x85 0x85 0x8a 0x89 0x8b ,0x7f 0x7d 0x7b 0x7e 0x82 0x88 0x88 0x86 0x83 , 0x88 0x87 0x86 0x86 0x84 0x82 0x84 0x85 0x86 ,0x7c 0x7c 0x83 0x7e 0x83 0x81 0x7e 0x80 0x81 , range:0x3a 0x38 0x38 0x38 0x38 0x38 0x38 0x36 0x36 ,0x39 0x3a 0x38 0x38 0x39 0x3a 0x39 0x38 0x3a , 0x3b 0x3a 0x38 0x39 0x39 0x3a 0x38 0x37 0x39 ,0x38 0x36 0x3b 0x38 0x39 0x3a 0x38 0x39 0x38 , CA Training result: cs:0 min :0x3c 0x3c 0x35 0x36 0x37 0x30 0x39 ,0x3b 0x36 0x39 0x36 0x38 0x33 0x3b , cs:0 mid :0x7a 0x7c 0x73 0x77 0x75 0x71 0x68 ,0x79 0x77 0x77 0x76 0x75 0x73 0x69 , cs:0 max :0xb9 0xbd 0xb1 0xb8 0xb4 0xb3 0x97 ,0xb7 0xb8 0xb5 0xb7 0xb3 0xb4 0x98 , cs:0 range:0x7d 0x81 0x7c 0x82 0x7d 0x83 0x5e ,0x7c 0x82 0x7c 0x81 0x7b 0x81 0x5d , out
U-Boot SPL 2023.07 (Jul 23 2023 - 13:39:45 +0000) rockchip_sdhci_probe clk set rate fail! Trying to boot from MMC2 ## Checking hash(es) for config config-1 ... OK ## Checking hash(es) for Image atf-1 ... sha256+ OK ## Checking hash(es) for Image u-boot ... sha256+ OK ## Checking hash(es) for Image fdt-1 ... sha256+ OK ## Checking hash(es) for Image atf-2 ... sha256+ OK ## Checking hash(es) for Image atf-3 ... sha256+ OK ## Checking hash(es) for Image atf-4 ... sha256+ OK ## Checking hash(es) for Image atf-5 ... sha256+ OK ## Checking hash(es) for Image atf-6 ... sha256+ OK INFO: Preloader serial: 2 NOTICE: BL31: v2.3():v2.3-607-gbf602aff1:cl NOTICE: BL31: Built : 10:16:03, Jun 5 2023 INFO: GICv3 without legacy support detected. INFO: ARM GICv3 driver initialized in EL3 INFO: pmu v1 is valid 220114 INFO: dfs DDR fsp_param[0].freq_mhz= 1056MHz INFO: dfs DDR fsp_param[1].freq_mhz= 324MHz INFO: dfs DDR fsp_param[2].freq_mhz= 528MHz INFO: dfs DDR fsp_param[3].freq_mhz= 780MHz INFO: Using opteed sec cpu_context! INFO: boot cpu mask: 0 INFO: BL31: Initializing runtime services WARNING: No OPTEE provided by BL2 boot loader, Booting device without OPTEE initialization. SMC`s destined for OPTEE will return SMC_UNK ERROR: Error initializing runtime service opteed_fast INFO: BL31: Preparing for EL3 exit to normal world INFO: Entry point address = 0xa00000 INFO: SPSR = 0x3c9
U-Boot 2023.07 (Jul 23 2023 - 13:39:45 +0000)
Model: Pine64 RK3566 SoQuartz with CM4-IO Carrier Board DRAM: 4 GiB (effective 3.7 GiB) PMIC: RK8090 (on=0x40, off=0x00) Core: 312 devices, 27 uclasses, devicetree: separate MMC: rockchip_sdhci_probe clk set rate fail! mmc@fe2b0000: 1, mmc@fe2c0000: 2, mmc@fe310000: 0 Loading Environment from nowhere... OK In: serial@fe660000 Out: serial@fe660000 Err: serial@fe660000 Model: Pine64 RK3566 SoQuartz with CM4-IO Carrier Board Net: No ethernet found.
Hit any key to stop autoboot: 0 =>
Regards, Jonas
On 2023/7/23 22:55, Jonas Karlman wrote:
The Pine64 SOQuartz compute module is mostly pin-compatible with the RPi CM4 form factor. Therefore, it can slot into the official Raspberry Pi CM4 IO carrier board. Add this configuration to U-Boot.
Features tested with a SOQuartz 4GB v1.1 2022-07-11:
- SD-card boot
- eMMC boot
- USB host
Device tree is imported from linux v6.4.
Co-developed-by: Nicolas Frattaroli frattaroli.nicolas@gmail.com Signed-off-by: Nicolas Frattaroli frattaroli.nicolas@gmail.com Signed-off-by: Jonas Karlman jonas@kwiboo.se
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3566-soquartz-cm4-u-boot.dtsi | 3 + arch/arm/dts/rk3566-soquartz-cm4.dts | 192 +++++++++++++++++++ board/pine64/quartz64_rk3566/MAINTAINERS | 3 + configs/soquartz-cm4-rk3566_defconfig | 90 +++++++++ doc/board/rockchip/rockchip.rst | 1 + 6 files changed, 290 insertions(+) create mode 100644 arch/arm/dts/rk3566-soquartz-cm4-u-boot.dtsi create mode 100644 arch/arm/dts/rk3566-soquartz-cm4.dts create mode 100644 configs/soquartz-cm4-rk3566_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 7a41675ef89d..dabbf116914c 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -171,6 +171,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \ rk3566-quartz64-b.dtb \ rk3566-radxa-cm3-io.dtb \ rk3566-soquartz-blade.dtb \
- rk3566-soquartz-cm4.dtb \ rk3566-soquartz-model-a.dtb \ rk3568-evb.dtb \ rk3568-odroid-m1.dtb \
diff --git a/arch/arm/dts/rk3566-soquartz-cm4-u-boot.dtsi b/arch/arm/dts/rk3566-soquartz-cm4-u-boot.dtsi new file mode 100644 index 000000000000..0e662eafa4c7 --- /dev/null +++ b/arch/arm/dts/rk3566-soquartz-cm4-u-boot.dtsi @@ -0,0 +1,3 @@ +// SPDX-License-Identifier: GPL-2.0+
+#include "rk3566-soquartz-u-boot.dtsi" diff --git a/arch/arm/dts/rk3566-soquartz-cm4.dts b/arch/arm/dts/rk3566-soquartz-cm4.dts new file mode 100644 index 000000000000..cddf6cd2fecb --- /dev/null +++ b/arch/arm/dts/rk3566-soquartz-cm4.dts @@ -0,0 +1,192 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/dts-v1/;
+#include "rk3566-soquartz.dtsi"
+/ {
- model = "Pine64 RK3566 SoQuartz with CM4-IO Carrier Board";
- compatible = "pine64,soquartz-cm4io", "pine64,soquartz", "rockchip,rk3566";
- /* labeled +12v in schematic */
- vcc12v_dcin: vcc12v-dcin-regulator {
compatible = "regulator-fixed";regulator-name = "vcc12v_dcin";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <12000000>;regulator-max-microvolt = <12000000>;- };
- /* labeled +5v in schematic */
- vcc_5v: vcc-5v-regulator {
compatible = "regulator-fixed";regulator-name = "vcc_5v";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <5000000>;regulator-max-microvolt = <5000000>;vin-supply = <&vcc12v_dcin>;- };
- vcc_sd_pwr: vcc-sd-pwr-regulator {
compatible = "regulator-fixed";regulator-name = "vcc_sd_pwr";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;vin-supply = <&vcc3v3_sys>;- };
+};
+/* phy for pcie */ +&combphy2 {
- phy-supply = <&vcc3v3_sys>;
- status = "okay";
+};
+&gmac1 {
- status = "okay";
+};
+/*
- i2c1 is exposed on CM1 / Module1A
- pin 80 - SCL0 - i2c1_scl_m0, pullup to vcc3v3_pmu
- pin 82 - SDA0 - i2c1_sda_m0, pullup to vcc3v3_pmu
- */
+&i2c1 {
- status = "okay";
- /*
* the rtc interrupt is tied to PMIC_PWRON,* it will force reset the board if triggered.*/- pcf85063: rtc@51 {
compatible = "nxp,pcf85063";reg = <0x51>;- };
+};
+/*
- i2c2 is exposed on CM1 / Module1A - to PI40
- pin 56 - GPIO3 - i2c2_scl_m1, pullup to vcc_3v3, shared with i2s1_8ch
- pin 58 - GPIO2 - i2c2_sda_m1, pullup to vcc_3v3
- */
+&i2c2 {
- status = "disabled";
+};
+/*
- i2c3 is exposed on CM1 / Module1A - to PI40
- pin 35 - ID_SC(GPIO28) - i2c3_scl_m0, pullup to vcc_3v3
- pin 36 - ID_SD(GPIO27) - i2c3_sda_m0, pullup to vcc_3v3
- */
+&i2c3 {
- status = "disabled";
+};
+/*
- i2c4 is exposed on CM2 / Module1B - to PI40
- pin 45 - GPIO24 - i2c4_scl_m1
- pin 47 - GPIO23 - i2c4_sda_m1
- */
+&i2c4 {
- status = "disabled";
+};
+/*
- i2s1_8ch is exposed on CM1 / Module1A - to PI40
- pin 24 - GPIO26 - i2s1_sdi1_m1
- pin 25 - GPIO21 - i2s1_sdo0_m1
- pin 26 - GPIO19 - i2s1_lrck_tx_m1
- pin 27 - GPIO20 - i2s1_sdi0_m1
- pin 29 - GPIO16 - i2s1_sdi3_m1
- pin 30 - GPIO6 - i2s1_sdi2_m1
- pin 40 - GPIO9 - i2s1_sdo1_m1, shared with spi3
- pin 41 - GPIO25 - i2s1_sdo2_m1
- pin 49 - GPIO18 - i2s1_sclk_tx_m1
- pin 50 - GPIO17 - i2s1_mclk_m1
- pin 56 - GPIO3 - i2s1_sdo3_m1, shared with i2c2
- */
+&i2s1_8ch {
- status = "disabled";
+};
+&led_diy {
- status = "okay";
+};
+&led_work {
- status = "okay";
+};
+&pcie2x1 {
- vpcie3v3-supply = <&vcc_3v3>;
- status = "okay";
+};
+&rgmii_phy1 {
- status = "okay";
+};
+/*
- saradc is exposed on CM1 / Module1A - to J2
- pin 94 - AIN1 - saradc_vin3
- pin 96 - AIN0 - saradc_vin2
- */
+&saradc {
- status = "disabled";
+};
+&sdmmc0 {
- vmmc-supply = <&vcc_sd_pwr>;
- status = "okay";
+};
+/*
- spi3 is exposed on CM1 / Module1A - to PI40
- pin 37 - GPIO7 - spi3_cs1_m0
- pin 38 - GPIO11 - spi3_clk_m0
- pin 39 - GPIO8 - spi3_cs0_m0
- pin 40 - GPIO9 - spi3_miso_m0, shared with i2s1_8ch
- pin 44 - GPIO10 - spi3_mosi_m0
- */
+&spi3 {
- status = "disabled";
+};
+/*
- uart2 is exposed on CM1 / Module1A - to PI40
- pin 51 - GPIO15 - uart2_rx_m0
- pin 55 - GPIO14 - uart2_tx_m0
- */
+&uart2 {
- status = "okay";
+};
+/*
- uart7 is exposed on CM1 / Module1A - to PI40
- pin 46 - GPIO22 - uart7_tx_m2
- pin 47 - GPIO23 - uart7_rx_m2
- */
+&uart7 {
- status = "okay";
+};
+&usb2phy0 {
- status = "okay";
+};
+&usb2phy0_otg {
- phy-supply = <&vcc_5v>;
- status = "okay";
+};
+&usb_host0_xhci {
- status = "okay";
+};
+&vbus {
- vin-supply = <&vcc_5v>;
+}; diff --git a/board/pine64/quartz64_rk3566/MAINTAINERS b/board/pine64/quartz64_rk3566/MAINTAINERS index 603d2ee9d5e9..6b75b35a1243 100644 --- a/board/pine64/quartz64_rk3566/MAINTAINERS +++ b/board/pine64/quartz64_rk3566/MAINTAINERS @@ -7,6 +7,7 @@ F: include/configs/quartz64_rk3566.h F: configs/quartz64-a-rk3566_defconfig F: configs/quartz64-b-rk3566_defconfig F: configs/soquartz-blade-rk3566_defconfig +F: configs/soquartz-cm4-rk3566_defconfig F: configs/soquartz-model-a-rk3566_defconfig F: arch/arm/dts/rk3566-quartz64-a.dts F: arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi @@ -16,5 +17,7 @@ F: arch/arm/dts/rk3566-soquartz.dtsi F: arch/arm/dts/rk3566-soquartz-u-boot.dtsi F: arch/arm/dts/rk3566-soquartz-blade.dts F: arch/arm/dts/rk3566-soquartz-blade-u-boot.dtsi +F: arch/arm/dts/rk3566-soquartz-cm4.dts +F: arch/arm/dts/rk3566-soquartz-cm4-u-boot.dtsi F: arch/arm/dts/rk3566-soquartz-model-a.dts F: arch/arm/dts/rk3566-soquartz-model-a-u-boot.dtsi diff --git a/configs/soquartz-cm4-rk3566_defconfig b/configs/soquartz-cm4-rk3566_defconfig new file mode 100644 index 000000000000..7e290351477e --- /dev/null +++ b/configs/soquartz-cm4-rk3566_defconfig @@ -0,0 +1,90 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_TEXT_BASE=0x00a00000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 +CONFIG_DEFAULT_DEVICE_TREE="rk3566-soquartz-cm4" +CONFIG_ROCKCHIP_RK3568=y +CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_STACK_R_ADDR=0x600000 +CONFIG_TARGET_QUARTZ64_RK3566=y +CONFIG_SPL_STACK=0x400000 +CONFIG_DEBUG_UART_BASE=0xFE660000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_PCI=y +CONFIG_DEBUG_UART=y +CONFIG_AHCI=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-soquartz-cm4.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x4000000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_ATF=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_SCSI_AHCI=y +CONFIG_AHCI_PCI=y +CONFIG_SPL_CLK=y +CONFIG_GPIO_HOG=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_NVME_PCI=y +CONFIG_PCIE_DW_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_SPL_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_SPL_RAM=y +CONFIG_SCSI=y +CONFIG_DM_SCSI=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_ERRNO_STR=y diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index 254a68b43eaf..3cd5de55120b 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -99,6 +99,7 @@ List of mainline supported Rockchip boards: - Pine64 Quartz64-A Board (quartz64-a-rk3566_defconfig) - Pine64 Quartz64-B Board (quartz64-b-rk3566_defconfig) - Pine64 SOQuartz on Blade (soquartz-blade-rk3566_defconfig)
- Pine64 SOQuartz on CM4-IO (soquartz-cm4-rk3566_defconfig) - Pine64 SOQuartz on Model A (soquartz-model-a-rk3566_defconfig)
- rk3588
On 2023/7/23 22:55, Jonas Karlman wrote:
This series was created in collaboration with Nicolas Frattaroli and add support for Pine64 Quartz64 and SOQuartz boards with a RK3566 SoC.
- Pine64 Quartz64-A Board
- Pine64 Quartz64-B Board
- Pine64 SOQuartz on Model A
- Pine64 SOQuartz on Blade
- Pine64 SOQuartz on CM4-IO
Device trees have been imported from linux v6.4.
This series have loose dependencies on the following series:
- rockchip: Fix PCIe and NVMe support on RK3568 [1]
- rockchip: rk3568: Use dwc3-generic driver [2]
This patch is still waiting for review, and this patchset may need to update once it get merged.
Thanks, - Kever
- rockchip: rk3568: Fix alloc space exhausted in SPL [3]
- rockchip: rk3568: Device Tree updates [4]
- rockchip: rk35xx: Fix SPI Flash alias [5]
- board: rockchip: Add Hardkernel ODROID-M1 [6]
A copy of this series with above dependencies can be found at [7].
[1] https://patchwork.ozlabs.org/project/uboot/list/?series=365195 [2] https://patchwork.ozlabs.org/project/uboot/list/?series=364127 [3] https://patchwork.ozlabs.org/project/uboot/list/?series=361999 [4] https://patchwork.ozlabs.org/project/uboot/list/?series=362030 [5] https://patchwork.ozlabs.org/project/uboot/list/?series=363527 [6] https://patchwork.ozlabs.org/project/uboot/list/?series=365198 [7] https://github.com/Kwiboo/u-boot-rockchip/commits/rk3568-quartz64-v1
Jonas Karlman (5): board: rockchip: Add Pine64 Quartz64-A Board board: rockchip: Add Pine64 Quartz64-B Board board: rockchip: Add Pine64 SOQuartz on Model A board: rockchip: Add Pine64 SOQuartz on Blade board: rockchip: Add Pine64 SOQuartz on CM4-IO
arch/arm/dts/Makefile | 5 + arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi | 55 ++ arch/arm/dts/rk3566-quartz64-a.dts | 839 ++++++++++++++++++ arch/arm/dts/rk3566-quartz64-b-u-boot.dtsi | 47 + arch/arm/dts/rk3566-quartz64-b.dts | 739 +++++++++++++++ .../arm/dts/rk3566-soquartz-blade-u-boot.dtsi | 3 + arch/arm/dts/rk3566-soquartz-blade.dts | 194 ++++ arch/arm/dts/rk3566-soquartz-cm4-u-boot.dtsi | 3 + arch/arm/dts/rk3566-soquartz-cm4.dts | 192 ++++ .../dts/rk3566-soquartz-model-a-u-boot.dtsi | 3 + arch/arm/dts/rk3566-soquartz-model-a.dts | 232 +++++ arch/arm/dts/rk3566-soquartz-u-boot.dtsi | 30 + arch/arm/dts/rk3566-soquartz.dtsi | 688 ++++++++++++++ arch/arm/mach-rockchip/rk3568/Kconfig | 6 + board/pine64/quartz64_rk3566/Kconfig | 15 + board/pine64/quartz64_rk3566/MAINTAINERS | 23 + board/pine64/quartz64_rk3566/Makefile | 3 + .../pine64/quartz64_rk3566/quartz64-rk3566.c | 1 + configs/quartz64-a-rk3566_defconfig | 110 +++ configs/quartz64-b-rk3566_defconfig | 106 +++ configs/soquartz-blade-rk3566_defconfig | 90 ++ configs/soquartz-cm4-rk3566_defconfig | 90 ++ configs/soquartz-model-a-rk3566_defconfig | 90 ++ doc/board/rockchip/rockchip.rst | 5 + include/configs/quartz64_rk3566.h | 10 + 25 files changed, 3579 insertions(+) create mode 100644 arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi create mode 100644 arch/arm/dts/rk3566-quartz64-a.dts create mode 100644 arch/arm/dts/rk3566-quartz64-b-u-boot.dtsi create mode 100644 arch/arm/dts/rk3566-quartz64-b.dts create mode 100644 arch/arm/dts/rk3566-soquartz-blade-u-boot.dtsi create mode 100644 arch/arm/dts/rk3566-soquartz-blade.dts create mode 100644 arch/arm/dts/rk3566-soquartz-cm4-u-boot.dtsi create mode 100644 arch/arm/dts/rk3566-soquartz-cm4.dts create mode 100644 arch/arm/dts/rk3566-soquartz-model-a-u-boot.dtsi create mode 100644 arch/arm/dts/rk3566-soquartz-model-a.dts create mode 100644 arch/arm/dts/rk3566-soquartz-u-boot.dtsi create mode 100644 arch/arm/dts/rk3566-soquartz.dtsi create mode 100644 board/pine64/quartz64_rk3566/Kconfig create mode 100644 board/pine64/quartz64_rk3566/MAINTAINERS create mode 100644 board/pine64/quartz64_rk3566/Makefile create mode 100644 board/pine64/quartz64_rk3566/quartz64-rk3566.c create mode 100644 configs/quartz64-a-rk3566_defconfig create mode 100644 configs/quartz64-b-rk3566_defconfig create mode 100644 configs/soquartz-blade-rk3566_defconfig create mode 100644 configs/soquartz-cm4-rk3566_defconfig create mode 100644 configs/soquartz-model-a-rk3566_defconfig create mode 100644 include/configs/quartz64_rk3566.h
On 2023-07-28 13:02, Kever Yang wrote:
On 2023/7/23 22:55, Jonas Karlman wrote:
This series was created in collaboration with Nicolas Frattaroli and add support for Pine64 Quartz64 and SOQuartz boards with a RK3566 SoC.
- Pine64 Quartz64-A Board
- Pine64 Quartz64-B Board
- Pine64 SOQuartz on Model A
- Pine64 SOQuartz on Blade
- Pine64 SOQuartz on CM4-IO
Device trees have been imported from linux v6.4.
This series have loose dependencies on the following series:
- rockchip: Fix PCIe and NVMe support on RK3568 [1]
- rockchip: rk3568: Use dwc3-generic driver [2]
This patch is still waiting for review, and this patchset may need to update once it get merged.
Thanks, I have re-sent the following series that I hope should help you with applying. - "rockchip: rk3568: Device Tree updates" v2 - "rockchip: rk35xx: Fix SPI Flash alias" v2 - "rockchip: rk3568: Use dwc3-generic driver" v4
There may only be a runtime depend on the patch "usb: dwc3-generic: Relax unsupported dr_mode check" of the "rockchip: rk3568: Use dwc3-generic driver" series. Or it may not be since we define dr_mode = "host" on some of these boards. Our runtime testing has however been done with all the mentioned series applied.
Will re-send this series if needed :-)
Regards, Jonas
Thanks,
- Kever
- rockchip: rk3568: Fix alloc space exhausted in SPL [3]
- rockchip: rk3568: Device Tree updates [4]
- rockchip: rk35xx: Fix SPI Flash alias [5]
- board: rockchip: Add Hardkernel ODROID-M1 [6]
A copy of this series with above dependencies can be found at [7].
[1] https://patchwork.ozlabs.org/project/uboot/list/?series=365195 [2] https://patchwork.ozlabs.org/project/uboot/list/?series=364127 [3] https://patchwork.ozlabs.org/project/uboot/list/?series=361999 [4] https://patchwork.ozlabs.org/project/uboot/list/?series=362030 [5] https://patchwork.ozlabs.org/project/uboot/list/?series=363527 [6] https://patchwork.ozlabs.org/project/uboot/list/?series=365198 [7] https://github.com/Kwiboo/u-boot-rockchip/commits/rk3568-quartz64-v1
Jonas Karlman (5): board: rockchip: Add Pine64 Quartz64-A Board board: rockchip: Add Pine64 Quartz64-B Board board: rockchip: Add Pine64 SOQuartz on Model A board: rockchip: Add Pine64 SOQuartz on Blade board: rockchip: Add Pine64 SOQuartz on CM4-IO
arch/arm/dts/Makefile | 5 + arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi | 55 ++ arch/arm/dts/rk3566-quartz64-a.dts | 839 ++++++++++++++++++ arch/arm/dts/rk3566-quartz64-b-u-boot.dtsi | 47 + arch/arm/dts/rk3566-quartz64-b.dts | 739 +++++++++++++++ .../arm/dts/rk3566-soquartz-blade-u-boot.dtsi | 3 + arch/arm/dts/rk3566-soquartz-blade.dts | 194 ++++ arch/arm/dts/rk3566-soquartz-cm4-u-boot.dtsi | 3 + arch/arm/dts/rk3566-soquartz-cm4.dts | 192 ++++ .../dts/rk3566-soquartz-model-a-u-boot.dtsi | 3 + arch/arm/dts/rk3566-soquartz-model-a.dts | 232 +++++ arch/arm/dts/rk3566-soquartz-u-boot.dtsi | 30 + arch/arm/dts/rk3566-soquartz.dtsi | 688 ++++++++++++++ arch/arm/mach-rockchip/rk3568/Kconfig | 6 + board/pine64/quartz64_rk3566/Kconfig | 15 + board/pine64/quartz64_rk3566/MAINTAINERS | 23 + board/pine64/quartz64_rk3566/Makefile | 3 + .../pine64/quartz64_rk3566/quartz64-rk3566.c | 1 + configs/quartz64-a-rk3566_defconfig | 110 +++ configs/quartz64-b-rk3566_defconfig | 106 +++ configs/soquartz-blade-rk3566_defconfig | 90 ++ configs/soquartz-cm4-rk3566_defconfig | 90 ++ configs/soquartz-model-a-rk3566_defconfig | 90 ++ doc/board/rockchip/rockchip.rst | 5 + include/configs/quartz64_rk3566.h | 10 + 25 files changed, 3579 insertions(+) create mode 100644 arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi create mode 100644 arch/arm/dts/rk3566-quartz64-a.dts create mode 100644 arch/arm/dts/rk3566-quartz64-b-u-boot.dtsi create mode 100644 arch/arm/dts/rk3566-quartz64-b.dts create mode 100644 arch/arm/dts/rk3566-soquartz-blade-u-boot.dtsi create mode 100644 arch/arm/dts/rk3566-soquartz-blade.dts create mode 100644 arch/arm/dts/rk3566-soquartz-cm4-u-boot.dtsi create mode 100644 arch/arm/dts/rk3566-soquartz-cm4.dts create mode 100644 arch/arm/dts/rk3566-soquartz-model-a-u-boot.dtsi create mode 100644 arch/arm/dts/rk3566-soquartz-model-a.dts create mode 100644 arch/arm/dts/rk3566-soquartz-u-boot.dtsi create mode 100644 arch/arm/dts/rk3566-soquartz.dtsi create mode 100644 board/pine64/quartz64_rk3566/Kconfig create mode 100644 board/pine64/quartz64_rk3566/MAINTAINERS create mode 100644 board/pine64/quartz64_rk3566/Makefile create mode 100644 board/pine64/quartz64_rk3566/quartz64-rk3566.c create mode 100644 configs/quartz64-a-rk3566_defconfig create mode 100644 configs/quartz64-b-rk3566_defconfig create mode 100644 configs/soquartz-blade-rk3566_defconfig create mode 100644 configs/soquartz-cm4-rk3566_defconfig create mode 100644 configs/soquartz-model-a-rk3566_defconfig create mode 100644 include/configs/quartz64_rk3566.h
participants (3)
-
Christopher Obbard -
Jonas Karlman -
Kever Yang