For some CPUs, having malloc() available very early is useful. There is no reason to delay this since early malloc is allocated before board_init_f() is called.

Move early malloc() init nearer to the start of the init sequence.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v2: None

common/board_f.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/common/board_f.c b/common/board_f.c index 23d8f64..f81f70d 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -812,6 +812,7 @@ static init_fnc_t init_sequence_f[] = { setup_mon_len, setup_fdt, trace_early_init, + initf_malloc, #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) /* TODO: can this go into arch_cpu_init()? */ probecpu, @@ -826,7 +827,6 @@ static init_fnc_t init_sequence_f[] = { #ifdef CONFIG_OF_CONTROL fdtdec_check_fdt, #endif - initf_malloc, initf_dm, #if defined(CONFIG_BOARD_EARLY_INIT_F) board_early_init_f,

Sometimes an array can be of variable size up to a maximum. Add a helper function to decode this.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v2: None

include/fdtdec.h | 16 ++++++++++++++++ lib/fdtdec.c | 20 ++++++++++++++++++++ 2 files changed, 36 insertions(+)

diff --git a/include/fdtdec.h b/include/fdtdec.h index 4ae77be..6b40006 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -445,6 +445,22 @@ int fdtdec_get_int_array(const void *blob, int node, const char *prop_name, u32 *array, int count);

/** + * Look up a property in a node and return its contents in an integer + * array of given length. The property must exist but may have less data that + * expected (4*count bytes). It may have more, but this will be ignored. + * + * @param blob FDT blob + * @param node node to examine + * @param prop_name name of property to find + * @param array array to fill with data + * @param count number of array elements + * @return number of array elements if ok, or -FDT_ERR_NOTFOUND if the + * property is not found + */ +int fdtdec_get_int_array_count(const void *blob, int node, + const char *prop_name, u32 *array, int count); + +/** * Look up a property in a node and return a pointer to its contents as a * unsigned int array of given length. The property must have at least enough * data for the array ('count' cells). It may have more, but this will be diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 9714620..4aa227a 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -485,6 +485,26 @@ int fdtdec_get_int_array(const void *blob, int node, const char *prop_name, return err; }

+int fdtdec_get_int_array_count(const void *blob, int node, + const char *prop_name, u32 *array, int count) +{ + const u32 *cell; + int len, elems; + int i; + + debug("%s: %s\n", __func__, prop_name); + cell = fdt_getprop(blob, node, prop_name, &len); + if (!cell) + return -FDT_ERR_NOTFOUND; + elems = len / sizeof(u32); + if (count > elems) + count = elems; + for (i = 0; i < count; i++) + array[i] = fdt32_to_cpu(cell[i]); + + return count; +} + const u32 *fdtdec_locate_array(const void *blob, int node, const char *prop_name, int count) {

In general we can't store things in the data section until we have inited SDRAM. Some platforms allow this (e.g. those with SPL) but some don't. Move the pointer to global_data so that it will work on all platforms.

Without this fix the serial port will not work prior to relocation with driver model on some platforms.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v2: None

drivers/serial/serial-uclass.c | 35 +++++++++++++++++++---------------- include/asm-generic/global_data.h | 1 + 2 files changed, 20 insertions(+), 16 deletions(-)

diff --git a/drivers/serial/serial-uclass.c b/drivers/serial/serial-uclass.c index 71f1a5c..0f019c8 100644 --- a/drivers/serial/serial-uclass.c +++ b/drivers/serial/serial-uclass.c @@ -19,15 +19,14 @@

DECLARE_GLOBAL_DATA_PTR;

-/* The currently-selected console serial device */ -struct udevice *cur_dev __attribute__ ((section(".data"))); - #ifndef CONFIG_SYS_MALLOC_F_LEN #error "Serial is required before relocation - define CONFIG_SYS_MALLOC_F_LEN to make this work" #endif

static void serial_find_console_or_panic(void) { + struct udevice *dev; + #ifdef CONFIG_OF_CONTROL int node;

@@ -35,18 +34,21 @@ static void serial_find_console_or_panic(void) node = fdtdec_get_chosen_node(gd->fdt_blob, "stdout-path"); if (node < 0) node = fdtdec_get_alias_node(gd->fdt_blob, "console"); - if (!uclass_get_device_by_of_offset(UCLASS_SERIAL, node, &cur_dev)) + if (!uclass_get_device_by_of_offset(UCLASS_SERIAL, node, &dev)) { + gd->cur_serial_dev = dev; return; + }

/* * If the console is not marked to be bound before relocation, bind * it anyway. */ if (node > 0 && - !lists_bind_fdt(gd->dm_root, gd->fdt_blob, node, &cur_dev)) { - if (!device_probe(cur_dev)) + !lists_bind_fdt(gd->dm_root, gd->fdt_blob, node, &dev)) { + if (!device_probe(dev)) { + gd->cur_serial_dev = dev; return; - cur_dev = NULL; + } } #endif /* @@ -61,11 +63,12 @@ static void serial_find_console_or_panic(void) #else #define INDEX 0 #endif - if (uclass_get_device_by_seq(UCLASS_SERIAL, INDEX, &cur_dev) && - uclass_get_device(UCLASS_SERIAL, INDEX, &cur_dev) && - (uclass_first_device(UCLASS_SERIAL, &cur_dev) || !cur_dev)) + if (uclass_get_device_by_seq(UCLASS_SERIAL, INDEX, &dev) && + uclass_get_device(UCLASS_SERIAL, INDEX, &dev) && + (uclass_first_device(UCLASS_SERIAL, &dev) || !dev)) panic("No serial driver found"); #undef INDEX + gd->cur_serial_dev = dev; }

/* Called prior to relocation */ @@ -127,30 +130,30 @@ static int _serial_tstc(struct udevice *dev)

void serial_putc(char ch) { - _serial_putc(cur_dev, ch); + _serial_putc(gd->cur_serial_dev, ch); }

void serial_puts(const char *str) { - _serial_puts(cur_dev, str); + _serial_puts(gd->cur_serial_dev, str); }

int serial_getc(void) { - return _serial_getc(cur_dev); + return _serial_getc(gd->cur_serial_dev); }

int serial_tstc(void) { - return _serial_tstc(cur_dev); + return _serial_tstc(gd->cur_serial_dev); }

void serial_setbrg(void) { - struct dm_serial_ops *ops = serial_get_ops(cur_dev); + struct dm_serial_ops *ops = serial_get_ops(gd->cur_serial_dev);

if (ops->setbrg) - ops->setbrg(cur_dev, gd->baudrate); + ops->setbrg(gd->cur_serial_dev, gd->baudrate); }

void serial_stdio_init(void) diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h index 74df210..f61acbc 100644 --- a/include/asm-generic/global_data.h +++ b/include/asm-generic/global_data.h @@ -91,6 +91,7 @@ typedef struct global_data { unsigned long malloc_limit; /* limit address */ unsigned long malloc_ptr; /* current address */ #endif + struct udevice *cur_serial_dev; /* current serial device */ struct arch_global_data arch; /* architecture-specific data */ } gd_t; #endif

For board IDs a common approach is to set aside several GPIOs for use in determining the board ID. This can provide information about board features and the revision.

Add a function that turns a list of GPIOs into an integer by assigning each GPIO to a single bit.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v2: None

drivers/gpio/gpio-uclass.c | 19 +++++++++++++++++++ include/asm-generic/gpio.h | 11 ++++++++++- 2 files changed, 29 insertions(+), 1 deletion(-)

diff --git a/drivers/gpio/gpio-uclass.c b/drivers/gpio/gpio-uclass.c index 45e9a5a..255700a 100644 --- a/drivers/gpio/gpio-uclass.c +++ b/drivers/gpio/gpio-uclass.c @@ -390,6 +390,25 @@ int gpio_get_status(struct udevice *dev, int offset, char *buf, int buffsize) return 0; }

+/* + * get a number comprised of multiple GPIO values. gpio_num_array points to + * the array of gpio pin numbers to scan, terminated by -1. + */ +unsigned gpio_get_values_as_int(const int *gpio_num_array) +{ + int gpio; + unsigned bitmask = 1; + unsigned vector = 0; + + while (bitmask && + ((gpio = *gpio_num_array++) != -1)) { + if (gpio_get_value(gpio)) + vector |= bitmask; + bitmask <<= 1; + } + return vector; +} + /* We need to renumber the GPIOs when any driver is probed/removed */ static int gpio_renumber(struct udevice *removed_dev) { diff --git a/include/asm-generic/gpio.h b/include/asm-generic/gpio.h index f81b51a..36a36c6 100644 --- a/include/asm-generic/gpio.h +++ b/include/asm-generic/gpio.h @@ -257,6 +257,15 @@ const char *gpio_get_bank_info(struct udevice *dev, int *offset_count); int gpio_lookup_name(const char *name, struct udevice **devp, unsigned int *offsetp, unsigned int *gpiop);

-int name_to_gpio(const char *name); +/** + * get_gpios() - Turn the values of a list of GPIOs into an integer + * + * This puts the value of the first GPIO into bit 0, the second into bit 1, + * etc. then returns the resulting integer. + * + * @gpio_list: List of GPIOs to collect + * @return resulting integer value + */ +unsigned gpio_get_values_as_int(const int *gpio_list);

#endif /* _ASM_GENERIC_GPIO_H_ */

Newer Intel chips require a Management Engine which requires a particular format for the SPI flash that contains the boot loader. Add a tool that supports creating and modifying these ROM images.

This tool is from Chrome OS but has been cleaned up to use U-Boot style and to add comments. A few features have been added also.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v2: None

tools/Makefile | 2 + tools/ifdtool.c | 1039 +++++++++++++++++++++++++++++++++++++++++++++++++++++++ tools/ifdtool.h | 88 +++++ 3 files changed, 1129 insertions(+) create mode 100644 tools/ifdtool.c create mode 100644 tools/ifdtool.h

diff --git a/tools/Makefile b/tools/Makefile index 3b95964..55f25c0 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -126,6 +126,8 @@ hostprogs-$(CONFIG_EXYNOS5250) += mkexynosspl hostprogs-$(CONFIG_EXYNOS5420) += mkexynosspl HOSTCFLAGS_mkexynosspl.o := -pedantic

+hostprogs-$(CONFIG_X86) += ifdtool + hostprogs-$(CONFIG_MX23) += mxsboot hostprogs-$(CONFIG_MX28) += mxsboot HOSTCFLAGS_mxsboot.o := -pedantic diff --git a/tools/ifdtool.c b/tools/ifdtool.c new file mode 100644 index 0000000..2c9bbda --- /dev/null +++ b/tools/ifdtool.c @@ -0,0 +1,1039 @@ +/* + * ifdtool - Manage Intel Firmware Descriptor information + * + * Copyright 2014 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0 + * + * From Coreboot project, but it got a serious code clean-up + * and a few new features + */ + +#include <assert.h> +#include <fcntl.h> +#include <getopt.h> +#include <stdlib.h> +#include <stdio.h> +#include <string.h> +#include <unistd.h> +#include <sys/types.h> +#include <sys/stat.h> +#include "ifdtool.h" + +#undef DEBUG + +#ifdef DEBUG +#define debug(fmt, args...) printf(fmt, ##args) +#else +#define debug(fmt, args...) +#endif + +#define FD_SIGNATURE 0x0FF0A55A +#define FLREG_BASE(reg) ((reg & 0x00000fff) << 12); +#define FLREG_LIMIT(reg) (((reg & 0x0fff0000) >> 4) | 0xfff); + +/** + * find_fd() - Find the flash description in the ROM image + * + * @image: Pointer to image + * @size: Size of image in bytes + * @return pointer to structure, or NULL if not found + */ +static struct fdbar_t *find_fd(char *image, int size) +{ + uint32_t *ptr, *end; + + /* Scan for FD signature */ + for (ptr = (uint32_t *)image, end = ptr + size / 4; ptr < end; ptr++) { + if (*ptr == FD_SIGNATURE) + break; + } + + if (ptr == end) { + printf("No Flash Descriptor found in this image\n"); + return NULL; + } + + debug("Found Flash Descriptor signature at 0x%08x\n", i); + + return (struct fdbar_t *)ptr; +} + +/** + * get_region() - Get information about the selected region + * + * @frba: Flash region list + * @region_type: Type of region (0..MAX_REGIONS-1) + * @region: Region information is written here + * @return 0 if OK, else -ve + */ +static int get_region(struct frba_t *frba, int region_type, + struct region_t *region) +{ + if (region_type >= MAX_REGIONS) { + fprintf(stderr, "Invalid region type.\n"); + return -1; + } + + region->base = FLREG_BASE(frba->flreg[region_type]); + region->limit = FLREG_LIMIT(frba->flreg[region_type]); + region->size = region->limit - region->base + 1; + + return 0; +} + +static const char *region_name(int region_type) +{ + static const char *const regions[] = { + "Flash Descriptor", + "BIOS", + "Intel ME", + "GbE", + "Platform Data" + }; + + assert(region_type < MAX_REGIONS); + + return regions[region_type]; +} + +static const char *region_filename(int region_type) +{ + static const char *const region_filenames[] = { + "flashregion_0_flashdescriptor.bin", + "flashregion_1_bios.bin", + "flashregion_2_intel_me.bin", + "flashregion_3_gbe.bin", + "flashregion_4_platform_data.bin" + }; + + assert(region_type < MAX_REGIONS); + + return region_filenames[region_type]; +} + +static int dump_region(int num, struct frba_t *frba) +{ + struct region_t region; + int ret; + + ret = get_region(frba, num, &region); + if (ret) + return ret; + + printf(" Flash Region %d (%s): %08x - %08x %s\n", + num, region_name(num), region.base, region.limit, + region.size < 1 ? "(unused)" : ""); + + return ret; +} + +static void dump_frba(struct frba_t *frba) +{ + int i; + + printf("Found Region Section\n"); + for (i = 0; i < MAX_REGIONS; i++) { + printf("FLREG%d: 0x%08x\n", i, frba->flreg[i]); + dump_region(i, frba); + } +} + +static void decode_spi_frequency(unsigned int freq) +{ + switch (freq) { + case SPI_FREQUENCY_20MHZ: + printf("20MHz"); + break; + case SPI_FREQUENCY_33MHZ: + printf("33MHz"); + break; + case SPI_FREQUENCY_50MHZ: + printf("50MHz"); + break; + default: + printf("unknown<%x>MHz", freq); + } +} + +static void decode_component_density(unsigned int density) +{ + switch (density) { + case COMPONENT_DENSITY_512KB: + printf("512KiB"); + break; + case COMPONENT_DENSITY_1MB: + printf("1MiB"); + break; + case COMPONENT_DENSITY_2MB: + printf("2MiB"); + break; + case COMPONENT_DENSITY_4MB: + printf("4MiB"); + break; + case COMPONENT_DENSITY_8MB: + printf("8MiB"); + break; + case COMPONENT_DENSITY_16MB: + printf("16MiB"); + break; + default: + printf("unknown<%x>MiB", density); + } +} + +static void dump_fcba(struct fcba_t *fcba) +{ + printf("\nFound Component Section\n"); + printf("FLCOMP 0x%08x\n", fcba->flcomp); + printf(" Dual Output Fast Read Support: %ssupported\n", + (fcba->flcomp & (1 << 30)) ? "" : "not "); + printf(" Read ID/Read Status Clock Frequency: "); + decode_spi_frequency((fcba->flcomp >> 27) & 7); + printf("\n Write/Erase Clock Frequency: "); + decode_spi_frequency((fcba->flcomp >> 24) & 7); + printf("\n Fast Read Clock Frequency: "); + decode_spi_frequency((fcba->flcomp >> 21) & 7); + printf("\n Fast Read Support: %ssupported", + (fcba->flcomp & (1 << 20)) ? "" : "not "); + printf("\n Read Clock Frequency: "); + decode_spi_frequency((fcba->flcomp >> 17) & 7); + printf("\n Component 2 Density: "); + decode_component_density((fcba->flcomp >> 3) & 7); + printf("\n Component 1 Density: "); + decode_component_density(fcba->flcomp & 7); + printf("\n"); + printf("FLILL 0x%08x\n", fcba->flill); + printf(" Invalid Instruction 3: 0x%02x\n", + (fcba->flill >> 24) & 0xff); + printf(" Invalid Instruction 2: 0x%02x\n", + (fcba->flill >> 16) & 0xff); + printf(" Invalid Instruction 1: 0x%02x\n", + (fcba->flill >> 8) & 0xff); + printf(" Invalid Instruction 0: 0x%02x\n", + fcba->flill & 0xff); + printf("FLPB 0x%08x\n", fcba->flpb); + printf(" Flash Partition Boundary Address: 0x%06x\n\n", + (fcba->flpb & 0xfff) << 12); +} + +static void dump_fpsba(struct fpsba_t *fpsba) +{ + int i; + + printf("Found PCH Strap Section\n"); + for (i = 0; i < MAX_STRAPS; i++) + printf("PCHSTRP%-2d: 0x%08x\n", i, fpsba->pchstrp[i]); +} + +static const char *get_enabled(int flag) +{ + return flag ? "enabled" : "disabled"; +} + +static void decode_flmstr(uint32_t flmstr) +{ + printf(" Platform Data Region Write Access: %s\n", + get_enabled(flmstr & (1 << 28))); + printf(" GbE Region Write Access: %s\n", + get_enabled(flmstr & (1 << 27))); + printf(" Intel ME Region Write Access: %s\n", + get_enabled(flmstr & (1 << 26))); + printf(" Host CPU/BIOS Region Write Access: %s\n", + get_enabled(flmstr & (1 << 25))); + printf(" Flash Descriptor Write Access: %s\n", + get_enabled(flmstr & (1 << 24))); + + printf(" Platform Data Region Read Access: %s\n", + get_enabled(flmstr & (1 << 20))); + printf(" GbE Region Read Access: %s\n", + get_enabled(flmstr & (1 << 19))); + printf(" Intel ME Region Read Access: %s\n", + get_enabled(flmstr & (1 << 18))); + printf(" Host CPU/BIOS Region Read Access: %s\n", + get_enabled(flmstr & (1 << 17))); + printf(" Flash Descriptor Read Access: %s\n", + get_enabled(flmstr & (1 << 16))); + + printf(" Requester ID: 0x%04x\n\n", + flmstr & 0xffff); +} + +static void dump_fmba(struct fmba_t *fmba) +{ + printf("Found Master Section\n"); + printf("FLMSTR1: 0x%08x (Host CPU/BIOS)\n", fmba->flmstr1); + decode_flmstr(fmba->flmstr1); + printf("FLMSTR2: 0x%08x (Intel ME)\n", fmba->flmstr2); + decode_flmstr(fmba->flmstr2); + printf("FLMSTR3: 0x%08x (GbE)\n", fmba->flmstr3); + decode_flmstr(fmba->flmstr3); +} + +static void dump_fmsba(struct fmsba_t *fmsba) +{ + int i; + + printf("Found Processor Strap Section\n"); + for (i = 0; i < 4; i++) + printf("????: 0x%08x\n", fmsba->data[0]); +} + +static void dump_jid(uint32_t jid) +{ + printf(" SPI Component Device ID 1: 0x%02x\n", + (jid >> 16) & 0xff); + printf(" SPI Component Device ID 0: 0x%02x\n", + (jid >> 8) & 0xff); + printf(" SPI Component Vendor ID: 0x%02x\n", + jid & 0xff); +} + +static void dump_vscc(uint32_t vscc) +{ + printf(" Lower Erase Opcode: 0x%02x\n", + vscc >> 24); + printf(" Lower Write Enable on Write Status: 0x%02x\n", + vscc & (1 << 20) ? 0x06 : 0x50); + printf(" Lower Write Status Required: %s\n", + vscc & (1 << 19) ? "Yes" : "No"); + printf(" Lower Write Granularity: %d bytes\n", + vscc & (1 << 18) ? 64 : 1); + printf(" Lower Block / Sector Erase Size: "); + switch ((vscc >> 16) & 0x3) { + case 0: + printf("256 Byte\n"); + break; + case 1: + printf("4KB\n"); + break; + case 2: + printf("8KB\n"); + break; + case 3: + printf("64KB\n"); + break; + } + + printf(" Upper Erase Opcode: 0x%02x\n", + (vscc >> 8) & 0xff); + printf(" Upper Write Enable on Write Status: 0x%02x\n", + vscc & (1 << 4) ? 0x06 : 0x50); + printf(" Upper Write Status Required: %s\n", + vscc & (1 << 3) ? "Yes" : "No"); + printf(" Upper Write Granularity: %d bytes\n", + vscc & (1 << 2) ? 64 : 1); + printf(" Upper Block / Sector Erase Size: "); + switch (vscc & 0x3) { + case 0: + printf("256 Byte\n"); + break; + case 1: + printf("4KB\n"); + break; + case 2: + printf("8KB\n"); + break; + case 3: + printf("64KB\n"); + break; + } +} + +static void dump_vtba(struct vtba_t *vtba, int vtl) +{ + int i; + int num = (vtl >> 1) < 8 ? (vtl >> 1) : 8; + + printf("ME VSCC table:\n"); + for (i = 0; i < num; i++) { + printf(" JID%d: 0x%08x\n", i, vtba->entry[i].jid); + dump_jid(vtba->entry[i].jid); + printf(" VSCC%d: 0x%08x\n", i, vtba->entry[i].vscc); + dump_vscc(vtba->entry[i].vscc); + } + printf("\n"); +} + +static void dump_oem(uint8_t *oem) +{ + int i, j; + printf("OEM Section:\n"); + for (i = 0; i < 4; i++) { + printf("%02x:", i << 4); + for (j = 0; j < 16; j++) + printf(" %02x", oem[(i<<4)+j]); + printf("\n"); + } + printf("\n"); +} + +/** + * dump_fd() - Display a dump of the full flash description + * + * @image: Pointer to image + * @size: Size of image in bytes + * @return 0 if OK, -1 on error + */ +static int dump_fd(char *image, int size) +{ + struct fdbar_t *fdb = find_fd(image, size); + + if (!fdb) + return -1; + + printf("FLMAP0: 0x%08x\n", fdb->flmap0); + printf(" NR: %d\n", (fdb->flmap0 >> 24) & 7); + printf(" FRBA: 0x%x\n", ((fdb->flmap0 >> 16) & 0xff) << 4); + printf(" NC: %d\n", ((fdb->flmap0 >> 8) & 3) + 1); + printf(" FCBA: 0x%x\n", ((fdb->flmap0) & 0xff) << 4); + + printf("FLMAP1: 0x%08x\n", fdb->flmap1); + printf(" ISL: 0x%02x\n", (fdb->flmap1 >> 24) & 0xff); + printf(" FPSBA: 0x%x\n", ((fdb->flmap1 >> 16) & 0xff) << 4); + printf(" NM: %d\n", (fdb->flmap1 >> 8) & 3); + printf(" FMBA: 0x%x\n", ((fdb->flmap1) & 0xff) << 4); + + printf("FLMAP2: 0x%08x\n", fdb->flmap2); + printf(" PSL: 0x%04x\n", (fdb->flmap2 >> 8) & 0xffff); + printf(" FMSBA: 0x%x\n", ((fdb->flmap2) & 0xff) << 4); + + printf("FLUMAP1: 0x%08x\n", fdb->flumap1); + printf(" Intel ME VSCC Table Length (VTL): %d\n", + (fdb->flumap1 >> 8) & 0xff); + printf(" Intel ME VSCC Table Base Address (VTBA): 0x%06x\n\n", + (fdb->flumap1 & 0xff) << 4); + dump_vtba((struct vtba_t *) + (image + ((fdb->flumap1 & 0xff) << 4)), + (fdb->flumap1 >> 8) & 0xff); + dump_oem((uint8_t *)image + 0xf00); + dump_frba((struct frba_t *)(image + (((fdb->flmap0 >> 16) & 0xff) + << 4))); + dump_fcba((struct fcba_t *)(image + (((fdb->flmap0) & 0xff) << 4))); + dump_fpsba((struct fpsba_t *) + (image + (((fdb->flmap1 >> 16) & 0xff) << 4))); + dump_fmba((struct fmba_t *)(image + (((fdb->flmap1) & 0xff) << 4))); + dump_fmsba((struct fmsba_t *)(image + (((fdb->flmap2) & 0xff) << 4))); + + return 0; +} + +/** + * write_regions() - Write each region from an image to its own file + * + * The filename to use in each case is fixed - see region_filename() + * + * @image: Pointer to image + * @size: Size of image in bytes + * @return 0 if OK, -ve on error + */ +static int write_regions(char *image, int size) +{ + struct fdbar_t *fdb; + struct frba_t *frba; + int ret = 0; + int i; + + fdb = find_fd(image, size); + if (!fdb) + return -1; + + frba = (struct frba_t *)(image + (((fdb->flmap0 >> 16) & 0xff) << 4)); + + for (i = 0; i < MAX_REGIONS; i++) { + struct region_t region; + int region_fd; + + ret = get_region(frba, i, &region); + if (ret) + return ret; + dump_region(i, frba); + if (region.size == 0) + continue; + region_fd = open(region_filename(i), + O_WRONLY | O_CREAT | O_TRUNC, S_IRUSR | + S_IWUSR | S_IRGRP | S_IROTH); + if (write(region_fd, image + region.base, region.size) != + region.size) { + perror("Error while writing"); + ret = -1; + } + close(region_fd); + } + + return ret; +} + +/** + * write_image() - Write the image to a file + * + * @filename: Filename to use for the image + * @image: Pointer to image + * @size: Size of image in bytes + * @return 0 if OK, -ve on error + */ +static int write_image(char *filename, char *image, int size) +{ + int new_fd; + + debug("Writing new image to %s\n", filename); + + new_fd = open(filename, O_WRONLY | O_CREAT | O_TRUNC, S_IRUSR | + S_IWUSR | S_IRGRP | S_IROTH); + if (write(new_fd, image, size) != size) { + perror("Error while writing"); + return -1; + } + close(new_fd); + + return 0; +} + +/** + * set_spi_frequency() - Set the SPI frequency to use when booting + * + * Several frequencies are supported, some of which work with fast devices. + * For SPI emulators, the slowest (SPI_FREQUENCY_20MHZ) is often used. The + * Intel boot system uses this information somehow on boot. + * + * The image is updated with the supplied value + * + * @image: Pointer to image + * @size: Size of image in bytes + * @freq: SPI frequency to use + */ +static void set_spi_frequency(char *image, int size, enum spi_frequency freq) +{ + struct fdbar_t *fdb = find_fd(image, size); + struct fcba_t *fcba; + + fcba = (struct fcba_t *)(image + (((fdb->flmap0) & 0xff) << 4)); + + /* clear bits 21-29 */ + fcba->flcomp &= ~0x3fe00000; + /* Read ID and Read Status Clock Frequency */ + fcba->flcomp |= freq << 27; + /* Write and Erase Clock Frequency */ + fcba->flcomp |= freq << 24; + /* Fast Read Clock Frequency */ + fcba->flcomp |= freq << 21; +} + +/** + * set_em100_mode() - Set a SPI frequency that will work with Dediprog EM100 + * + * @image: Pointer to image + * @size: Size of image in bytes + */ +static void set_em100_mode(char *image, int size) +{ + struct fdbar_t *fdb = find_fd(image, size); + struct fcba_t *fcba; + + fcba = (struct fcba_t *)(image + (((fdb->flmap0) & 0xff) << 4)); + fcba->flcomp &= ~(1 << 30); + set_spi_frequency(image, size, SPI_FREQUENCY_20MHZ); +} + +/** + * lock_descriptor() - Lock the NE descriptor so it cannot be updated + * + * @image: Pointer to image + * @size: Size of image in bytes + */ +static void lock_descriptor(char *image, int size) +{ + struct fdbar_t *fdb = find_fd(image, size); + struct fmba_t *fmba; + + /* + * TODO: Dynamically take Platform Data Region and GbE Region into + * account. + */ + fmba = (struct fmba_t *)(image + (((fdb->flmap1) & 0xff) << 4)); + fmba->flmstr1 = 0x0a0b0000; + fmba->flmstr2 = 0x0c0d0000; + fmba->flmstr3 = 0x08080118; +} + +/** + * unlock_descriptor() - Lock the NE descriptor so it can be updated + * + * @image: Pointer to image + * @size: Size of image in bytes + */ +static void unlock_descriptor(char *image, int size) +{ + struct fdbar_t *fdb = find_fd(image, size); + struct fmba_t *fmba; + + fmba = (struct fmba_t *)(image + (((fdb->flmap1) & 0xff) << 4)); + fmba->flmstr1 = 0xffff0000; + fmba->flmstr2 = 0xffff0000; + fmba->flmstr3 = 0x08080118; +} + +/** + * open_for_read() - Open a file for reading + * + * @fname: Filename to open + * @sizep: Returns file size in bytes + * @return 0 if OK, -1 on error + */ +int open_for_read(const char *fname, int *sizep) +{ + int fd = open(fname, O_RDONLY); + struct stat buf; + + if (fd == -1) { + perror("Could not open file"); + return -1; + } + if (fstat(fd, &buf) == -1) { + perror("Could not stat file"); + return -1; + } + *sizep = buf.st_size; + debug("File %s is %d bytes\n", fname, *sizep); + + return fd; +} + +/** + * inject_region() - Add a file to an image region + * + * This puts a file into a particular region of the flash. Several pre-defined + * regions are used. + * + * @image: Pointer to image + * @size: Size of image in bytes + * @region_type: Region where the file should be added + * @region_fname: Filename to add to the image + * @return 0 if OK, -ve on error + */ +int inject_region(char *image, int size, int region_type, char *region_fname) +{ + struct fdbar_t *fdb = find_fd(image, size); + struct region_t region; + struct frba_t *frba; + int region_size; + int offset = 0; + int region_fd; + int ret; + + if (!fdb) + exit(EXIT_FAILURE); + frba = (struct frba_t *)(image + (((fdb->flmap0 >> 16) & 0xff) << 4)); + + ret = get_region(frba, region_type, &region); + if (ret) + return -1; + if (region.size <= 0xfff) { + fprintf(stderr, "Region %s is disabled in target. Not injecting.\n", + region_name(region_type)); + return -1; + } + + region_fd = open_for_read(region_fname, &region_size); + if (region_fd < 0) + return region_fd; + + if ((region_size > region.size) || + ((region_type != 1) && (region_size > region.size))) { + fprintf(stderr, "Region %s is %d(0x%x) bytes. File is %d(0x%x) bytes. Not injecting.\n", + region_name(region_type), region.size, + region.size, region_size, region_size); + return -1; + } + + if ((region_type == 1) && (region_size < region.size)) { + fprintf(stderr, "Region %s is %d(0x%x) bytes. File is %d(0x%x) bytes. Padding before injecting.\n", + region_name(region_type), region.size, + region.size, region_size, region_size); + offset = region.size - region_size; + memset(image + region.base, 0xff, offset); + } + + if (size < region.base + offset + region_size) { + fprintf(stderr, "Output file is too small. (%d < %d)\n", + size, region.base + offset + region_size); + return -1; + } + + if (read(region_fd, image + region.base + offset, region_size) + != region_size) { + perror("Could not read file"); + return -1; + } + + close(region_fd); + + debug("Adding %s as the %s section\n", region_fname, + region_name(region_type)); + + return 0; +} + +/** + * write_data() - Write some raw data into a region + * + * This puts a file into a particular place in the flash, ignoring the + * regions. Be careful not to overwrite something important. + * + * @image: Pointer to image + * @size: Size of image in bytes + * @addr: x86 ROM address to put file. The ROM ends at + * 0xffffffff so use an address relative to that. For an + * 8MB ROM the start address is 0xfff80000. + * @write_fname: Filename to add to the image + * @return 0 if OK, -ve on error + */ +static int write_data(char *image, int size, unsigned int addr, + const char *write_fname) +{ + int write_fd, write_size; + int offset; + + write_fd = open_for_read(write_fname, &write_size); + if (write_fd < 0) + return write_fd; + + offset = addr + size; + debug("Writing %s to offset %#x\n", write_fname, offset); + + if (offset < 0 || offset + write_size > size) { + fprintf(stderr, "Output file is too small. (%d < %d)\n", + size, offset + write_size); + return -1; + } + + if (read(write_fd, image + offset, write_size) != write_size) { + perror("Could not read file"); + return -1; + } + + close(write_fd); + + return 0; +} + +static void print_version(void) +{ + printf("ifdtool v%s -- ", IFDTOOL_VERSION); + printf("Copyright (C) 2014 Google Inc.\n\n"); + printf("SPDX-License-Identifier: GPL-2.0+\n"); +} + +static void print_usage(const char *name) +{ + printf("usage: %s [-vhdix?] <filename> [<outfile>]\n", name); + printf("\n" + " -d | --dump: dump intel firmware descriptor\n" + " -x | --extract: extract intel fd modules\n" + " -i | --inject <region>:<module> inject file <module> into region <region>\n" + " -w | --write <addr>:<file> write file to appear at memory address <addr>\n" + " -s | --spifreq <20|33|50> set the SPI frequency\n" + " -e | --em100 set SPI frequency to 20MHz and disable\n" + " Dual Output Fast Read Support\n" + " -l | --lock Lock firmware descriptor and ME region\n" + " -u | --unlock Unlock firmware descriptor and ME region\n" + " -r | --romsize Specify ROM size\n" + " -D | --write-descriptor <file> Write descriptor at base\n" + " -c | --create Create a new empty image\n" + " -v | --version: print the version\n" + " -h | --help: print this help\n\n" + "<region> is one of Descriptor, BIOS, ME, GbE, Platform\n" + "\n"); +} + +/** + * get_two_words() - Convert a string into two words separated by : + * + * The supplied string is split at ':', two substrings are allocated and + * returned. + * + * @str: String to split + * @firstp: Returns first string + * @secondp: Returns second string + * @return 0 if OK, -ve if @str does not have a : + */ +static int get_two_words(const char *str, char **firstp, char **secondp) +{ + const char *p; + + p = strchr(str, ':'); + if (!p) + return -1; + *firstp = strdup(str); + (*firstp)[p - str] = '\0'; + *secondp = strdup(p + 1); + + return 0; +} + +int main(int argc, char *argv[]) +{ + int opt, option_index = 0; + int mode_dump = 0, mode_extract = 0, mode_inject = 0; + int mode_spifreq = 0, mode_em100 = 0, mode_locked = 0; + int mode_unlocked = 0, mode_write = 0, mode_write_descriptor = 0; + int create = 0; + char *region_type_string = NULL, *src_fname = NULL; + char *addr_str = NULL; + int region_type = -1, inputfreq = 0; + enum spi_frequency spifreq = SPI_FREQUENCY_20MHZ; + unsigned int addr = 0; + int rom_size = -1; + bool write_it; + char *filename; + char *outfile = NULL; + struct stat buf; + int size = 0; + int bios_fd; + char *image; + int ret; + static struct option long_options[] = { + {"create", 0, NULL, 'c'}, + {"dump", 0, NULL, 'd'}, + {"descriptor", 1, NULL, 'D'}, + {"em100", 0, NULL, 'e'}, + {"extract", 0, NULL, 'x'}, + {"inject", 1, NULL, 'i'}, + {"lock", 0, NULL, 'l'}, + {"romsize", 1, NULL, 'r'}, + {"spifreq", 1, NULL, 's'}, + {"unlock", 0, NULL, 'u'}, + {"write", 1, NULL, 'w'}, + {"version", 0, NULL, 'v'}, + {"help", 0, NULL, 'h'}, + {0, 0, 0, 0} + }; + + while ((opt = getopt_long(argc, argv, "cdD:ehi:lr:s:uvw:x?", + long_options, &option_index)) != EOF) { + switch (opt) { + case 'c': + create = 1; + break; + case 'd': + mode_dump = 1; + break; + case 'D': + mode_write_descriptor = 1; + src_fname = optarg; + break; + case 'e': + mode_em100 = 1; + break; + case 'i': + if (get_two_words(optarg, &region_type_string, + &src_fname)) { + print_usage(argv[0]); + exit(EXIT_FAILURE); + } + if (!strcasecmp("Descriptor", region_type_string)) + region_type = 0; + else if (!strcasecmp("BIOS", region_type_string)) + region_type = 1; + else if (!strcasecmp("ME", region_type_string)) + region_type = 2; + else if (!strcasecmp("GbE", region_type_string)) + region_type = 3; + else if (!strcasecmp("Platform", region_type_string)) + region_type = 4; + if (region_type == -1) { + fprintf(stderr, "No such region type: '%s'\n\n", + region_type_string); + print_usage(argv[0]); + exit(EXIT_FAILURE); + } + mode_inject = 1; + break; + case 'l': + mode_locked = 1; + break; + case 'r': + rom_size = strtol(optarg, NULL, 0); + debug("ROM size %d\n", rom_size); + break; + case 's': + /* Parse the requested SPI frequency */ + inputfreq = strtol(optarg, NULL, 0); + switch (inputfreq) { + case 20: + spifreq = SPI_FREQUENCY_20MHZ; + break; + case 33: + spifreq = SPI_FREQUENCY_33MHZ; + break; + case 50: + spifreq = SPI_FREQUENCY_50MHZ; + break; + default: + fprintf(stderr, "Invalid SPI Frequency: %d\n", + inputfreq); + print_usage(argv[0]); + exit(EXIT_FAILURE); + } + mode_spifreq = 1; + break; + case 'u': + mode_unlocked = 1; + break; + case 'v': + print_version(); + exit(EXIT_SUCCESS); + break; + case 'w': + mode_write = 1; + if (get_two_words(optarg, &addr_str, &src_fname)) { + print_usage(argv[0]); + exit(EXIT_FAILURE); + } + addr = strtol(optarg, NULL, 0); + break; + case 'x': + mode_extract = 1; + break; + case 'h': + case '?': + default: + print_usage(argv[0]); + exit(EXIT_SUCCESS); + break; + } + } + + if (mode_locked == 1 && mode_unlocked == 1) { + fprintf(stderr, "Locking/Unlocking FD and ME are mutually exclusive\n"); + exit(EXIT_FAILURE); + } + + if (mode_inject == 1 && mode_write == 1) { + fprintf(stderr, "Inject/Write are mutually exclusive\n"); + exit(EXIT_FAILURE); + } + + if ((mode_dump + mode_extract + mode_inject + + (mode_spifreq | mode_em100 | mode_unlocked | + mode_locked)) > 1) { + fprintf(stderr, "You may not specify more than one mode.\n\n"); + print_usage(argv[0]); + exit(EXIT_FAILURE); + } + + if ((mode_dump + mode_extract + mode_inject + mode_spifreq + + mode_em100 + mode_locked + mode_unlocked + mode_write + + mode_write_descriptor) == 0) { + fprintf(stderr, "You need to specify a mode.\n\n"); + print_usage(argv[0]); + exit(EXIT_FAILURE); + } + + if (create && rom_size == -1) { + fprintf(stderr, "You need to specify a rom size when creating.\n\n"); + exit(EXIT_FAILURE); + } + + if (optind + 1 != argc) { + fprintf(stderr, "You need to specify a file.\n\n"); + print_usage(argv[0]); + exit(EXIT_FAILURE); + } + + filename = argv[optind]; + if (optind + 2 != argc) + outfile = argv[optind + 1]; + + if (create) + bios_fd = open(filename, O_WRONLY | O_CREAT, 0666); + else + bios_fd = open(filename, outfile ? O_RDONLY : O_RDWR); + + if (bios_fd == -1) { + perror("Could not open file"); + exit(EXIT_FAILURE); + } + + if (!create) { + if (fstat(bios_fd, &buf) == -1) { + perror("Could not stat file"); + exit(EXIT_FAILURE); + } + size = buf.st_size; + } + + debug("File %s is %d bytes\n", filename, size); + + if (rom_size == -1) + rom_size = size; + + image = malloc(rom_size); + if (!image) { + printf("Out of memory.\n"); + exit(EXIT_FAILURE); + } + + memset(image, '\xff', rom_size); + if (!create && read(bios_fd, image, size) != size) { + perror("Could not read file"); + exit(EXIT_FAILURE); + } + if (size != rom_size) { + debug("ROM size changed to %d bytes\n", rom_size); + size = rom_size; + } + + write_it = true; + ret = 0; + if (mode_dump) { + ret = dump_fd(image, size); + write_it = false; + } + + if (mode_extract) { + ret = write_regions(image, size); + write_it = false; + } + + if (mode_write_descriptor) + ret = write_data(image, size, -size, src_fname); + + if (mode_inject) + ret = inject_region(image, size, region_type, src_fname); + + if (mode_write) + ret = write_data(image, size, addr, src_fname); + + if (mode_spifreq) + set_spi_frequency(image, size, spifreq); + + if (mode_em100) + set_em100_mode(image, size); + + if (mode_locked) + lock_descriptor(image, size); + + if (mode_unlocked) + unlock_descriptor(image, size); + + if (write_it) { + if (outfile) { + ret = write_image(outfile, image, size); + } else { + if (lseek(bios_fd, 0, SEEK_SET)) { + perror("Error while seeking"); + ret = -1; + } + if (write(bios_fd, image, size) != size) { + perror("Error while writing"); + ret = -1; + } + } + } + + free(image); + close(bios_fd); + + return ret ? 1 : 0; +} diff --git a/tools/ifdtool.h b/tools/ifdtool.h new file mode 100644 index 0000000..fbec421 --- /dev/null +++ b/tools/ifdtool.h @@ -0,0 +1,88 @@ +/* + * ifdtool - Manage Intel Firmware Descriptor information + * + * Copyright (C) 2011 The ChromiumOS Authors. + * + * SPDX-License-Identifier: GPL-2.0 + * + * From Coreboot project + */ + +#include <stdint.h> + +#define __packed __attribute__((packed)) + +#define IFDTOOL_VERSION "1.1-U-Boot" + +enum spi_frequency { + SPI_FREQUENCY_20MHZ = 0, + SPI_FREQUENCY_33MHZ = 1, + SPI_FREQUENCY_50MHZ = 4, +}; + +enum component_density { + COMPONENT_DENSITY_512KB = 0, + COMPONENT_DENSITY_1MB = 1, + COMPONENT_DENSITY_2MB = 2, + COMPONENT_DENSITY_4MB = 3, + COMPONENT_DENSITY_8MB = 4, + COMPONENT_DENSITY_16MB = 5, +}; + +/* flash descriptor */ +struct __packed fdbar_t { + uint32_t flvalsig; + uint32_t flmap0; + uint32_t flmap1; + uint32_t flmap2; + uint8_t reserved[0xefc - 0x20]; + uint32_t flumap1; +}; + +#define MAX_REGIONS 5 + +/* regions */ +struct __packed frba_t { + uint32_t flreg[MAX_REGIONS]; +}; + +/* component section */ +struct __packed fcba_t { + uint32_t flcomp; + uint32_t flill; + uint32_t flpb; +}; + +#define MAX_STRAPS 18 + +/* pch strap */ +struct __packed fpsba_t { + uint32_t pchstrp[MAX_STRAPS]; +}; + +/* master */ +struct __packed fmba_t { + uint32_t flmstr1; + uint32_t flmstr2; + uint32_t flmstr3; +}; + +/* processor strap */ +struct __packed fmsba_t { + uint32_t data[8]; +}; + +/* ME VSCC */ +struct vscc_t { + uint32_t jid; + uint32_t vscc; +}; + +struct vtba_t { + /* Actual number of entries specified in vtl */ + struct vscc_t entry[8]; +}; + +struct region_t { + int base, limit, size; +};

Many of the x86 CONFIG options will be common across different boards. Move them to a common file.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v2: - Move some features out of the common file

include/configs/coreboot.h | 265 ++----------------------------------------- include/configs/x86-common.h | 251 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 260 insertions(+), 256 deletions(-) create mode 100644 include/configs/x86-common.h

diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h index fef267f..2581380 100644 --- a/include/configs/coreboot.h +++ b/include/configs/coreboot.h @@ -6,7 +6,6 @@ * SPDX-License-Identifier: GPL-2.0+ */

-#include <asm/ibmpc.h> /* * board/config.h - configuration options, board specific */ @@ -14,27 +13,23 @@ #ifndef __CONFIG_H #define __CONFIG_H

+#include <configs/x86-common.h> + /* * High Level Configuration Options * (easy to change) */ #define CONFIG_SYS_COREBOOT -#define CONFIG_SHOW_BOOT_PROGRESS #define CONFIG_LAST_STAGE_INIT -#define CONFIG_SYS_VSNPRINTF -#define CONFIG_ZBOOT_32 -#define CONFIG_PHYSMEM #define CONFIG_SYS_EARLY_PCI_INIT -#define CONFIG_DISPLAY_BOARDINFO_LATE -#define CONFIG_DISPLAY_CPUINFO

-#define CONFIG_DM -#define CONFIG_CMD_DM -#define CONFIG_DM_GPIO -#define CONFIG_DM_SERIAL +#define CONFIG_SYS_CAR_ADDR 0x19200000 +#define CONFIG_SYS_CAR_SIZE (16 * 1024) +#define CONFIG_SYS_MONITOR_LEN (256 * 1024)

-#define CONFIG_LMB -#define CONFIG_OF_LIBFDT +#define CONFIG_TRACE_EARLY_SIZE (8 << 20) +#define CONFIG_TRACE_EARLY +#define CONFIG_TRACE_EARLY_ADDR 0x01400000

#define CONFIG_BOOTSTAGE #define CONFIG_BOOTSTAGE_REPORT @@ -45,26 +40,6 @@ #define CONFIG_BOOTSTAGE_STASH_SIZE 0x7fc #define CONFIG_BOOTSTAGE_USER_COUNT 60

-#define CONFIG_LZO -#define CONFIG_FIT -#undef CONFIG_ZLIB -#undef CONFIG_GZIP -#define CONFIG_SYS_BOOTM_LEN (16 << 20) - -/*----------------------------------------------------------------------- - * Watchdog Configuration - */ -#undef CONFIG_WATCHDOG -#undef CONFIG_HW_WATCHDOG - -/* SATA AHCI storage */ - -#define CONFIG_SCSI_AHCI - -#ifdef CONFIG_SCSI_AHCI -#define CONFIG_LIBATA -#define CONFIG_SYS_64BIT_LBA -#define CONFIG_SATA_INTEL 1 #define CONFIG_SCSI_DEV_LIST {PCI_VENDOR_ID_INTEL, \ PCI_DEVICE_ID_INTEL_NM10_AHCI}, \ {PCI_VENDOR_ID_INTEL, \ @@ -74,249 +49,27 @@ {PCI_VENDOR_ID_INTEL, \ PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE}

-#define CONFIG_SYS_SCSI_MAX_SCSI_ID 2 -#define CONFIG_SYS_SCSI_MAX_LUN 1 -#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ - CONFIG_SYS_SCSI_MAX_LUN) -#endif - -/* Generic TPM interfaced through LPC bus */ -#define CONFIG_TPM -#define CONFIG_TPM_TIS_LPC -#define CONFIG_TPM_TIS_BASE_ADDRESS 0xfed40000 - -/*----------------------------------------------------------------------- - * Real Time Clock Configuration - */ -#define CONFIG_RTC_MC146818 -#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0 -#define CONFIG_SYS_ISA_IO CONFIG_SYS_ISA_IO_BASE_ADDRESS - -/*----------------------------------------------------------------------- - * Serial Configuration - */ #define CONFIG_COREBOOT_SERIAL -#define CONFIG_SYS_NS16550 -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE {300, 600, 1200, 2400, 4800, \ - 9600, 19200, 38400, 115200} -#define CONFIG_SYS_NS16550_PORT_MAPPED

#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,vga,serial\0" \ "stdout=vga,serial,cbmem\0" \ "stderr=vga,serial,cbmem\0"

-#define CONFIG_CONSOLE_MUX -#define CONFIG_SYS_CONSOLE_IS_IN_ENV -#define CONFIG_SYS_STDIO_DEREGISTER #define CONFIG_CBMEM_CONSOLE

-#define CONFIG_CMDLINE_EDITING -#define CONFIG_COMMAND_HISTORY -#define CONFIG_AUTO_COMPLETE -#define CONFIG_SYS_HUSH_PARSER - -#define CONFIG_SUPPORT_VFAT -/************************************************************ - * ATAPI support (experimental) - ************************************************************/ -#define CONFIG_ATAPI - -/************************************************************ - * DISK Partition support - ************************************************************/ -#define CONFIG_EFI_PARTITION -#define CONFIG_DOS_PARTITION -#define CONFIG_MAC_PARTITION -#define CONFIG_ISO_PARTITION /* Experimental */ - -#define CONFIG_CMD_PART -#define CONFIG_CMD_CBFS -#define CONFIG_CMD_EXT4 -#define CONFIG_CMD_EXT4_WRITE -#define CONFIG_PARTITION_UUIDS - -/*----------------------------------------------------------------------- - * Video Configuration - */ -#define CONFIG_VIDEO #define CONFIG_VIDEO_COREBOOT -#define CONFIG_VIDEO_SW_CURSOR -#define VIDEO_FB_16BPP_WORD_SWAP -#define CONFIG_I8042_KBD -#define CONFIG_CFB_CONSOLE -#define CONFIG_SYS_CONSOLE_INFO_QUIET

-/* x86 GPIOs are accessed through a PCI device */ -#define CONFIG_INTEL_ICH6_GPIO - -/*----------------------------------------------------------------------- - * Command line configuration. - */ -#include <config_cmd_default.h> +#define CONFIG_NR_DRAM_BANKS 4

#define CONFIG_TRACE #define CONFIG_CMD_TRACE #define CONFIG_TRACE_BUFFER_SIZE (16 << 20) -#define CONFIG_TRACE_EARLY_SIZE (8 << 20) -#define CONFIG_TRACE_EARLY -#define CONFIG_TRACE_EARLY_ADDR 0x01400000 - -#define CONFIG_CMD_BDI -#define CONFIG_CMD_BOOTD -#define CONFIG_CMD_CONSOLE -#define CONFIG_CMD_DATE -#define CONFIG_CMD_ECHO -#undef CONFIG_CMD_FLASH -#define CONFIG_CMD_FPGA -#define CONFIG_CMD_FPGA_LOADMK -#define CONFIG_CMD_GPIO -#define CONFIG_CMD_IMI -#undef CONFIG_CMD_IMLS -#define CONFIG_CMD_IO -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_ITEST -#define CONFIG_CMD_LOADB -#define CONFIG_CMD_LOADS -#define CONFIG_CMD_MEMORY -#define CONFIG_CMD_MISC -#define CONFIG_CMD_NET -#undef CONFIG_CMD_NFS -#define CONFIG_CMD_PCI -#define CONFIG_CMD_PING -#define CONFIG_CMD_RUN -#define CONFIG_CMD_SAVEENV -#define CONFIG_CMD_SETGETDCR -#define CONFIG_CMD_SOURCE -#define CONFIG_CMD_TIME -#define CONFIG_CMD_GETTIME -#define CONFIG_CMD_XIMG -#define CONFIG_CMD_SCSI - -#define CONFIG_CMD_FAT -#define CONFIG_CMD_EXT2 - -#define CONFIG_CMD_ZBOOT -#define CONFIG_CMD_ELF

#define CONFIG_BOOTDELAY 2 -#define CONFIG_BOOTARGS \ - "root=/dev/sdb3 init=/sbin/init rootwait ro" -#define CONFIG_BOOTCOMMAND \ - "ext2load scsi 0:3 01000000 /boot/vmlinuz; zboot 01000000" - - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 115200 -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP -#define CONFIG_SYS_CBSIZE 512 -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + \ - 16) -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -#define CONFIG_SYS_MEMTEST_START 0x00100000 -#define CONFIG_SYS_MEMTEST_END 0x01000000 -#define CONFIG_SYS_LOAD_ADDR 0x20000000 - -/*----------------------------------------------------------------------- - * SDRAM Configuration - */ -#define CONFIG_NR_DRAM_BANKS 4 - -/* CONFIG_SYS_SDRAM_DRCTMCTL Overrides the following*/ -#undef CONFIG_SYS_SDRAM_PRECHARGE_DELAY -#undef CONFIG_SYS_SDRAM_RAS_CAS_DELAY -#undef CONFIG_SYS_SDRAM_CAS_LATENCY_2T -#undef CONFIG_SYS_SDRAM_CAS_LATENCY_3T - -/*----------------------------------------------------------------------- - * CPU Features - */ - -#define CONFIG_SYS_X86_TSC_TIMER -#define CONFIG_SYS_PCAT_INTERRUPTS -#define CONFIG_SYS_PCAT_TIMER -#define CONFIG_SYS_NUM_IRQS 16 - -/*----------------------------------------------------------------------- - * Memory organization: - * 32kB Stack - * 16kB Cache-As-RAM @ 0x19200000 - * 256kB Monitor - * (128kB + Environment Sector Size) malloc pool - */ -#define CONFIG_SYS_STACK_SIZE (32 * 1024) -#define CONFIG_SYS_CAR_ADDR 0x19200000 -#define CONFIG_SYS_CAR_SIZE (16 * 1024) -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) -#define CONFIG_SYS_MALLOC_LEN (0x20000 + 128 * 1024) -#define CONFIG_SYS_MALLOC_F_LEN (1 << 10) - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -/*----------------------------------------------------------------------- - * FLASH configuration - */ -#define CONFIG_ICH_SPI -#define CONFIG_SPI_FLASH -#define CONFIG_SPI_FLASH_MACRONIX -#define CONFIG_SPI_FLASH_WINBOND -#define CONFIG_SPI_FLASH_GIGADEVICE -#define CONFIG_SYS_NO_FLASH -#define CONFIG_CMD_SF -#define CONFIG_CMD_SF_TEST -#define CONFIG_CMD_SPI -#define CONFIG_SPI - -/*----------------------------------------------------------------------- - * Environment configuration - */ -#define CONFIG_ENV_IS_NOWHERE -#define CONFIG_ENV_SIZE 0x01000 - -/*----------------------------------------------------------------------- - * PCI configuration - */ -#define CONFIG_PCI

#define CONFIG_CROS_EC #define CONFIG_CROS_EC_LPC #define CONFIG_CMD_CROS_EC #define CONFIG_ARCH_EARLY_INIT_R

-/*----------------------------------------------------------------------- - * USB configuration - */ -#define CONFIG_USB_EHCI -#define CONFIG_USB_EHCI_PCI -#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 12 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#define CONFIG_USB_STORAGE -#define CONFIG_USB_KEYBOARD -#define CONFIG_SYS_USB_EVENT_POLL - -#define CONFIG_USB_HOST_ETHER -#define CONFIG_USB_ETHER_ASIX -#define CONFIG_USB_ETHER_SMSC95XX -#define CONFIG_TFTP_TSIZE -#define CONFIG_CMD_DHCP -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -#define CONFIG_CMD_USB - -#define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_STD_DEVICES_SETTINGS - #endif /* __CONFIG_H */ diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h new file mode 100644 index 0000000..825e9f7 --- /dev/null +++ b/include/configs/x86-common.h @@ -0,0 +1,251 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * (C) Copyright 2008 + * Graeme Russ, graeme.russ@gmail.com. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/ibmpc.h> + +#ifndef __CONFIG_X86_COMMON_H +#define __CONFIG_X86_COMMON_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_SHOW_BOOT_PROGRESS +#define CONFIG_SYS_VSNPRINTF +#define CONFIG_ZBOOT_32 +#define CONFIG_PHYSMEM +#define CONFIG_DISPLAY_BOARDINFO_LATE +#define CONFIG_DISPLAY_CPUINFO + +#define CONFIG_DM +#define CONFIG_CMD_DM +#define CONFIG_DM_GPIO +#define CONFIG_DM_SERIAL + +#define CONFIG_LMB +#define CONFIG_OF_LIBFDT + +#define CONFIG_LZO +#define CONFIG_FIT +#undef CONFIG_ZLIB +#undef CONFIG_GZIP +#define CONFIG_SYS_BOOTM_LEN (16 << 20) + +/* SATA AHCI storage */ + +#define CONFIG_SCSI_AHCI +#define CONFIG_SATA_INTEL +#ifdef CONFIG_SCSI_AHCI +#define CONFIG_LIBATA +#define CONFIG_SYS_64BIT_LBA + +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 2 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ + CONFIG_SYS_SCSI_MAX_LUN) +#endif + +/* Generic TPM interfaced through LPC bus */ +#define CONFIG_TPM +#define CONFIG_TPM_TIS_LPC +#define CONFIG_TPM_TIS_BASE_ADDRESS 0xfed40000 + +/*----------------------------------------------------------------------- + * Real Time Clock Configuration + */ +#define CONFIG_RTC_MC146818 +#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0 +#define CONFIG_SYS_ISA_IO CONFIG_SYS_ISA_IO_BASE_ADDRESS + +/*----------------------------------------------------------------------- + * Serial Configuration + */ +#define CONFIG_SYS_NS16550 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {300, 600, 1200, 2400, 4800, \ + 9600, 19200, 38400, 115200} +#define CONFIG_SYS_NS16550_PORT_MAPPED + +#define CONFIG_CONSOLE_MUX +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_SYS_STDIO_DEREGISTER + +#define CONFIG_CMDLINE_EDITING +#define CONFIG_COMMAND_HISTORY +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_HUSH_PARSER + +#define CONFIG_SUPPORT_VFAT +/************************************************************ + * ATAPI support (experimental) + ************************************************************/ +#define CONFIG_ATAPI + +/************************************************************ + * DISK Partition support + ************************************************************/ +#define CONFIG_EFI_PARTITION +#define CONFIG_DOS_PARTITION +#define CONFIG_MAC_PARTITION +#define CONFIG_ISO_PARTITION /* Experimental */ + +#define CONFIG_CMD_PART +#define CONFIG_CMD_CBFS +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_EXT4_WRITE +#define CONFIG_PARTITION_UUIDS + +#define CONFIG_SYS_CONSOLE_INFO_QUIET + +/* x86 GPIOs are accessed through a PCI device */ +#define CONFIG_INTEL_ICH6_GPIO + +/*----------------------------------------------------------------------- + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_BDI +#define CONFIG_CMD_BOOTD +#define CONFIG_CMD_CONSOLE +#define CONFIG_CMD_DATE +#define CONFIG_CMD_ECHO +#undef CONFIG_CMD_FLASH +#define CONFIG_CMD_FPGA +#define CONFIG_CMD_FPGA_LOADMK +#define CONFIG_CMD_GPIO +#define CONFIG_CMD_IMI +#undef CONFIG_CMD_IMLS +#define CONFIG_CMD_IO +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_ITEST +#define CONFIG_CMD_LOADB +#define CONFIG_CMD_LOADS +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_MISC +#define CONFIG_CMD_NET +#undef CONFIG_CMD_NFS +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PING +#define CONFIG_CMD_RUN +#define CONFIG_CMD_SAVEENV +#define CONFIG_CMD_SETGETDCR +#define CONFIG_CMD_SOURCE +#define CONFIG_CMD_TIME +#define CONFIG_CMD_GETTIME +#define CONFIG_CMD_XIMG +#define CONFIG_CMD_SCSI + +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 + +#define CONFIG_CMD_ZBOOT +#define CONFIG_CMD_ELF + +#define CONFIG_BOOTARGS \ + "root=/dev/sdb3 init=/sbin/init rootwait ro" +#define CONFIG_BOOTCOMMAND \ + "ext2load scsi 0:3 01000000 /boot/vmlinuz; zboot 01000000" + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 115200 +#endif + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_CBSIZE 512 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + \ + 16) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_SYS_MEMTEST_START 0x00100000 +#define CONFIG_SYS_MEMTEST_END 0x01000000 +#define CONFIG_SYS_LOAD_ADDR 0x20000000 + +/*----------------------------------------------------------------------- + * Video Configuration + */ +#define CONFIG_VIDEO +#define CONFIG_VIDEO_SW_CURSOR +#define VIDEO_FB_16BPP_WORD_SWAP +#define CONFIG_I8042_KBD +#define CONFIG_CFB_CONSOLE + +/*----------------------------------------------------------------------- + * CPU Features + */ + +#define CONFIG_SYS_X86_TSC_TIMER +#define CONFIG_SYS_PCAT_INTERRUPTS +#define CONFIG_SYS_PCAT_TIMER +#define CONFIG_SYS_NUM_IRQS 16 + +#define CONFIG_SYS_STACK_SIZE (32 * 1024) +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_MALLOC_LEN 0x200000 +#define CONFIG_SYS_MALLOC_F_LEN (1 << 10) + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +/*----------------------------------------------------------------------- + * FLASH configuration + */ +#define CONFIG_ICH_SPI +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_MACRONIX +#define CONFIG_SPI_FLASH_WINBOND +#define CONFIG_SPI_FLASH_GIGADEVICE +#define CONFIG_SYS_NO_FLASH +#define CONFIG_CMD_SF +#define CONFIG_CMD_SF_TEST +#define CONFIG_CMD_SPI +#define CONFIG_SPI + +/*----------------------------------------------------------------------- + * Environment configuration + */ +#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_SIZE 0x01000 + +/*----------------------------------------------------------------------- + * PCI configuration + */ +#define CONFIG_PCI + +/*----------------------------------------------------------------------- + * USB configuration + */ +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_PCI +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 12 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#define CONFIG_USB_STORAGE +#define CONFIG_USB_KEYBOARD +#define CONFIG_SYS_USB_EVENT_POLL + +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_USB_ETHER_SMSC95XX +#define CONFIG_TFTP_TSIZE +#define CONFIG_CMD_DHCP +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +#define CONFIG_CMD_USB + +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_STD_DEVICES_SETTINGS + +#endif /* __CONFIG_H */

These are no-longer needed so drop them.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v2: - Remove definition of find_fdt() also - Remove prepare_fdt() also

arch/x86/include/asm/init_helpers.h | 2 -- arch/x86/lib/init_helpers.c | 27 --------------------------- common/board_f.c | 5 ----- 3 files changed, 34 deletions(-)

diff --git a/arch/x86/include/asm/init_helpers.h b/arch/x86/include/asm/init_helpers.h index b07887e..8cbe08e 100644 --- a/arch/x86/include/asm/init_helpers.h +++ b/arch/x86/include/asm/init_helpers.h @@ -13,7 +13,5 @@ int calculate_relocation_address(void); int init_cache_f_r(void); int init_bd_struct_r(void); int init_func_spi(void); -int find_fdt(void); -int prepare_fdt(void);

#endif /* !_INIT_HELPERS_H_ */ diff --git a/arch/x86/lib/init_helpers.c b/arch/x86/lib/init_helpers.c index b5d937f..be4eb12 100644 --- a/arch/x86/lib/init_helpers.c +++ b/arch/x86/lib/init_helpers.c @@ -87,30 +87,3 @@ int init_func_spi(void) puts("ready\n"); return 0; } - -int find_fdt(void) -{ -#ifdef CONFIG_OF_EMBED - /* Get a pointer to the FDT */ - gd->fdt_blob = __dtb_dt_begin; -#elif defined CONFIG_OF_SEPARATE - /* FDT is at end of image */ - gd->fdt_blob = (ulong *)&_end; -#endif - /* Allow the early environment to override the fdt address */ - gd->fdt_blob = (void *)getenv_ulong("fdtcontroladdr", 16, - (uintptr_t)gd->fdt_blob); - - return 0; -} - -int prepare_fdt(void) -{ - /* For now, put this check after the console is ready */ - if (fdtdec_prepare_fdt()) { - panic("** CONFIG_OF_CONTROL defined but no FDT - please see " - "doc/README.fdt-control"); - } - - return 0; -} diff --git a/common/board_f.c b/common/board_f.c index f81f70d..6e6a1a2 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -818,11 +818,6 @@ static init_fnc_t init_sequence_f[] = { probecpu, #endif arch_cpu_init, /* basic arch cpu dependent setup */ -#ifdef CONFIG_X86 -# ifdef CONFIG_OF_CONTROL - find_fdt, /* TODO(sjg@chromium.org): remove */ -# endif -#endif mark_bootstage, #ifdef CONFIG_OF_CONTROL fdtdec_check_fdt,

We can use an MSR to obtain the time base. Add this back in and consolidate the code.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v2: - Add new patch to tidy up timer code for Intel core architecture

arch/x86/cpu/interrupts.c | 28 ---------------------------- arch/x86/lib/tsc_timer.c | 16 +++++++++++++++- 2 files changed, 15 insertions(+), 29 deletions(-)

diff --git a/arch/x86/cpu/interrupts.c b/arch/x86/cpu/interrupts.c index 51e2c59..4822c11 100644 --- a/arch/x86/cpu/interrupts.c +++ b/arch/x86/cpu/interrupts.c @@ -603,31 +603,3 @@ asm(".globl irq_common_entry\n" \ DECLARE_INTERRUPT(253) \ DECLARE_INTERRUPT(254) \ DECLARE_INTERRUPT(255)); - -#if defined(CONFIG_INTEL_CORE_ARCH) -/* - * Get the number of CPU time counter ticks since it was read first time after - * restart. This yields a free running counter guaranteed to take almost 6 - * years to wrap around even at 100GHz clock rate. - */ -u64 get_ticks(void) -{ - u64 now_tick = rdtsc(); - - if (!gd->arch.tsc_base) - gd->arch.tsc_base = now_tick; - - return now_tick - gd->arch.tsc_base; -} - -#define PLATFORM_INFO_MSR 0xce - -unsigned long get_tbclk(void) -{ - u32 ratio; - u64 platform_info = native_read_msr(PLATFORM_INFO_MSR); - - ratio = (platform_info >> 8) & 0xff; - return 100 * 1000 * 1000 * ratio; /* 100MHz times Max Non Turbo ratio */ -} -#endif diff --git a/arch/x86/lib/tsc_timer.c b/arch/x86/lib/tsc_timer.c index f091c91..3936b36 100644 --- a/arch/x86/lib/tsc_timer.c +++ b/arch/x86/lib/tsc_timer.c @@ -180,6 +180,20 @@ static inline int pit_expect_msb(unsigned char val, u64 *tscp, return count > 5; }

+#define PLATFORM_INFO_MSR 0xce + +/* Get the speed of the TSC timer in MHz */ +unsigned __attribute__((no_instrument_function)) + long get_tbclk_mhz_from_msr(void) +{ + u32 ratio; + u64 platform_info = native_read_msr(PLATFORM_INFO_MSR); + + /* 100MHz times Max Non Turbo ratio */ + ratio = (platform_info >> 8) & 0xff; + return 100 * ratio; +} + /* * How many MSB values do we want to see? We aim for * a maximum error rate of 500ppm (in practice the @@ -302,7 +316,7 @@ unsigned __attribute__((no_instrument_function)) long get_tbclk_mhz(void)

fast_calibrate = quick_pit_calibrate(); if (!fast_calibrate) - panic("TSC frequency is ZERO"); + fast_calibrate = get_tbclk_mhz_from_msr();

gd->arch.tsc_mhz = fast_calibrate; return fast_calibrate;

This board is a 'bare' version of the existing 'link 'board. It does not require coreboot to run, but is intended to start directly from the reset vector.

This initial commit has place holders for a wide range of features. These will be added in follow-on patches and series. So far it cannot be booted as there is no ROM image produced, but it does build without errors.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v2: - Add a common early_init file - Adjust config to deal with changed x86-common.h - Correct 'peripheral controller hub' to 'platform controller hub'

arch/x86/Kconfig | 23 +++++ arch/x86/cpu/coreboot/coreboot.c | 8 ++ arch/x86/cpu/ivybridge/Kconfig | 157 +++++++++++++++++++++++++++++ arch/x86/cpu/ivybridge/Makefile | 9 ++ arch/x86/cpu/ivybridge/car.S | 20 ++++ arch/x86/cpu/ivybridge/cpu.c | 42 ++++++++ arch/x86/cpu/ivybridge/sdram.c | 20 ++++ arch/x86/dts/Makefile | 1 + arch/x86/dts/chromebook_link.dts | 1 + arch/x86/include/asm/arch-ivybridge/gpio.h | 10 ++ board/google/chromebook_link/Kconfig | 15 +++ board/google/chromebook_link/MAINTAINERS | 6 ++ board/google/chromebook_link/Makefile | 15 +++ board/google/chromebook_link/link.c | 17 ++++ board/google/common/Makefile | 7 ++ board/google/common/early_init.S | 10 ++ configs/chromebook_link_defconfig | 10 ++ include/configs/chromebook_link.h | 60 +++++++++++ 18 files changed, 431 insertions(+) create mode 100644 arch/x86/cpu/ivybridge/Kconfig create mode 100644 arch/x86/cpu/ivybridge/Makefile create mode 100644 arch/x86/cpu/ivybridge/car.S create mode 100644 arch/x86/cpu/ivybridge/cpu.c create mode 100644 arch/x86/cpu/ivybridge/sdram.c create mode 120000 arch/x86/dts/chromebook_link.dts create mode 100644 arch/x86/include/asm/arch-ivybridge/gpio.h create mode 100644 board/google/chromebook_link/Kconfig create mode 100644 board/google/chromebook_link/MAINTAINERS create mode 100644 board/google/chromebook_link/Makefile create mode 100644 board/google/chromebook_link/link.c create mode 100644 board/google/common/Makefile create mode 100644 board/google/common/early_init.S create mode 100644 configs/chromebook_link_defconfig create mode 100644 include/configs/chromebook_link.h

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 0dba8ac..a5f24d0 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -12,9 +12,32 @@ choice

config TARGET_COREBOOT bool "Support coreboot" + help + This target is used for running U-Boot on top of Coreboot. In + this case Coreboot does the early inititalisation, and U-Boot + takes over once the RAM, video and CPU are fully running. + U-Boot is loaded as a fallback payload from Coreboot, in + Coreboot terminology. This method was used for the Chromebook + Pixel when launched. + +config TARGET_CHROMEBOOK_LINK + bool "Support Chromebook link" + help + This is the Chromebook Pixel released in 2013. It uses an Intel + i5 Ivybridge which is a die-shrink of Sandybridge, with 4GB of + SDRAM. It has a Panther Point platform controller hub, PCIe + WiFi and Bluetooth. It also includes a 720p webcam, USB SD + reader, microphone and speakers, display port and 32GB SATA + solid state drive. There is a Chrome OS EC connected on LPC, + and it provides a 2560x1700 high resolution touch-enabled LCD + display.

endchoice

+source "arch/x86/cpu/ivybridge/Kconfig" + source "board/chromebook-x86/coreboot/Kconfig"

+source "board/google/chromebook_link/Kconfig" + endmenu diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c index 5527183..874b59d 100644 --- a/arch/x86/cpu/coreboot/coreboot.c +++ b/arch/x86/cpu/coreboot/coreboot.c @@ -13,6 +13,7 @@ #include <ns16550.h> #include <asm/msr.h> #include <asm/cache.h> +#include <asm/cpu.h> #include <asm/io.h> #include <asm/arch-coreboot/tables.h> #include <asm/arch-coreboot/sysinfo.h> @@ -129,3 +130,10 @@ void panic_puts(const char *str) while (*str) NS16550_putc(port, *str++); } + +int print_cpuinfo(void) +{ + printf("CPU: %s\n", cpu_has_64bit() ? "x86_64" : "x86"); + + return 0; +} diff --git a/arch/x86/cpu/ivybridge/Kconfig b/arch/x86/cpu/ivybridge/Kconfig new file mode 100644 index 0000000..030d813 --- /dev/null +++ b/arch/x86/cpu/ivybridge/Kconfig @@ -0,0 +1,157 @@ +# +# From Coreboot src/northbridge/intel/sandybridge/Kconfig +# +# Copyright (C) 2010 Google Inc. +# +# SPDX-License-Identifier: GPL-2.0 + + +config NORTHBRIDGE_INTEL_SANDYBRIDGE + bool + select CACHE_MRC_BIN + select CPU_INTEL_MODEL_206AX + +config NORTHBRIDGE_INTEL_IVYBRIDGE + bool + select CACHE_MRC_BIN + select CPU_INTEL_MODEL_306AX + +if NORTHBRIDGE_INTEL_SANDYBRIDGE + +config VGA_BIOS_ID + string + default "8086,0106" + +config CACHE_MRC_SIZE_KB + int + default 256 + +config MRC_CACHE_BASE + hex + default 0xff800000 + +config MRC_CACHE_LOCATION + hex + depends on !CHROMEOS + default 0x1ec000 + +config MRC_CACHE_SIZE + hex + depends on !CHROMEOS + default 0x10000 + +config DCACHE_RAM_BASE + hex + default 0xff7f0000 + +config DCACHE_RAM_SIZE + hex + default 0x10000 + +endif + +if NORTHBRIDGE_INTEL_IVYBRIDGE + +config VGA_BIOS_ID + string + default "8086,0166" + +config EXTERNAL_MRC_BLOB + bool + default n + +config CACHE_MRC_SIZE_KB + int + default 512 + +config MRC_CACHE_BASE + hex + default 0xff800000 + +config MRC_CACHE_LOCATION + hex + depends on !CHROMEOS + default 0x370000 + +config MRC_CACHE_SIZE + hex + depends on !CHROMEOS + default 0x10000 + +config DCACHE_RAM_BASE + hex + default 0xff7e0000 + +config DCACHE_RAM_SIZE + hex + default 0x20000 + +endif + +if NORTHBRIDGE_INTEL_SANDYBRIDGE || NORTHBRIDGE_INTEL_IVYBRIDGE + +config HAVE_MRC + bool "Add a System Agent binary" + help + Select this option to add a System Agent binary to + the resulting U-Boot image. MRC stands for Memory Reference Code. + It is a binary blob which U-Boot uses to set up SDRAM. + + Note: Without this binary U-Boot will not be able to set up its + SDRAM so will not boot. + +config DCACHE_RAM_MRC_VAR_SIZE + hex + default 0x4000 + help + This is the amount of CAR (Cache as RAM) reserved for use by the + memory reference code. This should be set to 16KB (0x4000 hex) + so that MRC has enough space to run. + +config MRC_FILE + string "Intel System Agent path and filename" + depends on HAVE_MRC + default "systemagent-ivybridge.bin" if NORTHBRIDGE_INTEL_IVYBRIDGE + default "systemagent-sandybridge.bin" if NORTHBRIDGE_INTEL_SANDYBRIDGE + help + The path and filename of the file to use as System Agent + binary. + +config CPU_SPECIFIC_OPTIONS + def_bool y + select SMM_TSEG + select ARCH_BOOTBLOCK_X86_32 + select ARCH_ROMSTAGE_X86_32 + select ARCH_RAMSTAGE_X86_32 + select SMP + select SSE2 + select UDELAY_LAPIC + select CPU_MICROCODE_IN_CBFS + select TSC_SYNC_MFENCE + +config SMM_TSEG_SIZE + hex + default 0x800000 + +config ENABLE_VMX + bool "Enable VMX for virtualization" + default n + +endif + +config CPU_INTEL_SOCKET_RPGA989 + bool + +if CPU_INTEL_SOCKET_RPGA989 + +config SOCKET_SPECIFIC_OPTIONS # dummy + def_bool y + select MMX + select SSE + select CACHE_AS_RAM + +config CACHE_MRC_BIN + bool + default n + +endif diff --git a/arch/x86/cpu/ivybridge/Makefile b/arch/x86/cpu/ivybridge/Makefile new file mode 100644 index 0000000..dbcd4bd --- /dev/null +++ b/arch/x86/cpu/ivybridge/Makefile @@ -0,0 +1,9 @@ +# +# Copyright (c) 2014 Google, Inc +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += car.o +obj-y += cpu.o +obj-y += sdram.o diff --git a/arch/x86/cpu/ivybridge/car.S b/arch/x86/cpu/ivybridge/car.S new file mode 100644 index 0000000..0480813 --- /dev/null +++ b/arch/x86/cpu/ivybridge/car.S @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2014 Google, Inc + * + * From Coreboot file cpu/intel/model_206ax/cache_as_ram.inc + * + * Copyright (C) 2000,2007 Ronald G. Minnich rminnich@gmail.com + * Copyright (C) 2005 Tyan (written by Yinghai Lu for Tyan) + * Copyright (C) 2007-2008 coresystems GmbH + * Copyright (C) 2012 Kyösti Mälkki kyosti.malkki@gmail.com + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> + + /* Note: ebp must not be touched in this code */ +.globl car_init +car_init: + /* TODO: Add cache-as-RAM init here */ + jmp car_init_ret diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c new file mode 100644 index 0000000..1cbdaaf --- /dev/null +++ b/arch/x86/cpu/ivybridge/cpu.c @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2014 Google, Inc + * (C) Copyright 2008 + * Graeme Russ, graeme.russ@gmail.com. + * + * Some portions from coreboot src/mainboard/google/link/romstage.c + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2011 Google Inc. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <asm/cpu.h> +#include <asm/processor.h> + +DECLARE_GLOBAL_DATA_PTR; + +int arch_cpu_init(void) +{ + int ret; + + timer_set_base(rdtsc()); + + ret = x86_cpu_init_f(); + if (ret) + return ret; + + return 0; +} + +int print_cpuinfo(void) +{ + char processor_name[CPU_MAX_NAME_LEN]; + const char *name; + + /* Print processor name */ + name = cpu_get_name(processor_name); + printf("CPU: %s\n", name); + + return 0; +} diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c new file mode 100644 index 0000000..5f9ae5e --- /dev/null +++ b/arch/x86/cpu/ivybridge/sdram.c @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * (C) Copyright 2010,2011 + * Graeme Russ, graeme.russ@gmail.com + * + * Portions from Coreboot mainboard/google/link/romstage.c + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2011 Google Inc. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> + +int dram_init(void) +{ + /* TODO: Set up DRAM */ + + return 0; +} diff --git a/arch/x86/dts/Makefile b/arch/x86/dts/Makefile index 48265ef..bb3b116 100644 --- a/arch/x86/dts/Makefile +++ b/arch/x86/dts/Makefile @@ -1,4 +1,5 @@ dtb-y += link.dtb \ + chromebook_link.dtb \ alex.dtb

targets += $(dtb-y) diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts new file mode 120000 index 0000000..6f8c5cd --- /dev/null +++ b/arch/x86/dts/chromebook_link.dts @@ -0,0 +1 @@ +link.dts \ No newline at end of file diff --git a/arch/x86/include/asm/arch-ivybridge/gpio.h b/arch/x86/include/asm/arch-ivybridge/gpio.h new file mode 100644 index 0000000..4951a8c --- /dev/null +++ b/arch/x86/include/asm/arch-ivybridge/gpio.h @@ -0,0 +1,10 @@ +/* + * Copyright (c) 2014, Google Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _X86_ARCH_GPIO_H_ +#define _X86_ARCH_GPIO_H_ + +#endif /* _X86_ARCH_GPIO_H_ */ diff --git a/board/google/chromebook_link/Kconfig b/board/google/chromebook_link/Kconfig new file mode 100644 index 0000000..975d557 --- /dev/null +++ b/board/google/chromebook_link/Kconfig @@ -0,0 +1,15 @@ +if TARGET_CHROMEBOOK_LINK + +config SYS_BOARD + default "chromebook_link" + +config SYS_VENDOR + default "google" + +config SYS_SOC + default "ivybridge" + +config SYS_CONFIG_NAME + default "chromebook_link" + +endif diff --git a/board/google/chromebook_link/MAINTAINERS b/board/google/chromebook_link/MAINTAINERS new file mode 100644 index 0000000..bc253a2 --- /dev/null +++ b/board/google/chromebook_link/MAINTAINERS @@ -0,0 +1,6 @@ +CHROMEBOOK LINK BOARD +M: Simon Glass sjg@chromium.org +S: Maintained +F: board/google/chromebook_link/ +F: include/configs/chromebook_link.h +F: configs/chromebook_link_defconfig diff --git a/board/google/chromebook_link/Makefile b/board/google/chromebook_link/Makefile new file mode 100644 index 0000000..a133c2e --- /dev/null +++ b/board/google/chromebook_link/Makefile @@ -0,0 +1,15 @@ +# +# Copyright (c) 2011 The Chromium OS Authors. +# (C) Copyright 2008 +# Graeme Russ, graeme.russ@gmail.com. +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2002 +# Daniel Engström, Omicron Ceti AB, daniel@omicron.se. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += link.o diff --git a/board/google/chromebook_link/link.c b/board/google/chromebook_link/link.c new file mode 100644 index 0000000..ffa9d60 --- /dev/null +++ b/board/google/chromebook_link/link.c @@ -0,0 +1,17 @@ +/* + * Copyright (C) 2014 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> + +int arch_early_init_r(void) +{ + return 0; +} + +int board_early_init_r(void) +{ + return 0; +} diff --git a/board/google/common/Makefile b/board/google/common/Makefile new file mode 100644 index 0000000..b38bc14 --- /dev/null +++ b/board/google/common/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (c) 2014 Google, Inc +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += early_init.o diff --git a/board/google/common/early_init.S b/board/google/common/early_init.S new file mode 100644 index 0000000..cf70ae4 --- /dev/null +++ b/board/google/common/early_init.S @@ -0,0 +1,10 @@ +/* + * Copyright (c) 2014 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +.globl early_board_init +early_board_init: + /* No 32-bit board specific initialisation */ + jmp early_board_init_ret diff --git a/configs/chromebook_link_defconfig b/configs/chromebook_link_defconfig new file mode 100644 index 0000000..b83803e --- /dev/null +++ b/configs/chromebook_link_defconfig @@ -0,0 +1,10 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xfff00000" +CONFIG_X86=y +CONFIG_TARGET_CHROMEBOOK_LINK=y +CONFIG_OF_CONTROL=y +CONFIG_OF_SEPARATE=y +CONFIG_DEFAULT_DEVICE_TREE="chromebook_link" +CONFIG_HAVE_MRC=y +CONFIG_SMM_TSEG_SIZE=0x800000 +CONFIG_FRAMEBUFFER_SET_VESA_MODE=y +CONFIG_FRAMEBUFFER_VESA_MODE_11A=y diff --git a/include/configs/chromebook_link.h b/include/configs/chromebook_link.h new file mode 100644 index 0000000..394e27b --- /dev/null +++ b/include/configs/chromebook_link.h @@ -0,0 +1,60 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * (C) Copyright 2008 + * Graeme Russ, graeme.russ@gmail.com. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <configs/x86-common.h> + +#define CONFIG_SYS_CAR_ADDR 0xff7e0000 +#define CONFIG_SYS_CAR_SIZE (128 * 1024) +#define CONFIG_SYS_MONITOR_LEN (1 << 20) +#define CONFIG_BOARD_EARLY_INIT_R + +#define CONFIG_NR_DRAM_BANKS 8 + +#define CONFIG_COREBOOT_SERIAL + +#define CONFIG_SCSI_DEV_LIST {PCI_VENDOR_ID_INTEL, \ + PCI_DEVICE_ID_INTEL_NM10_AHCI}, \ + {PCI_VENDOR_ID_INTEL, \ + PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_MOBILE}, \ + {PCI_VENDOR_ID_INTEL, \ + PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_SERIES6}, \ + {PCI_VENDOR_ID_INTEL, \ + PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE} + +/* + * These common x86 features are not yet supported, but are added in + * follow-on patches in this series. Add undefs here to avoid every patch + * having to put things back into x86-common.h + */ +#undef CONFIG_INTEL_ICH6_GPIO +#undef CONFIG_DM_GPIO +#undef CONFIG_CMD_GPIO +#undef CONFIG_VIDEO +#undef CONFIG_CFB_CONSOLE +#undef CONFIG_SYS_EARLY_PCI_INIT +#undef CONFIG_PCI +#undef CONFIG_ICH_SPI +#undef CONFIG_SPI +#undef CONFIG_CMD_SPI +#undef CONFIG_CMD_SF +#undef CONFIG_USB_EHCI +#undef CONFIG_CMD_USB +#undef CONFIG_CMD_SCSI + +#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,vga,serial\0" \ + "stdout=vga,serial\0" \ + "stderr=vga,serial\0" + +#endif /* __CONFIG_H */

On x86 it is common to use 'post codes' which are 8-bit hex values emitted from the code and visible to the user. Traditionally two 7-segment displays were made available on the motherboard to show the last post code that was emitted. This allows diagnosis of a boot problem since it is possible to see where the code got to before it died.

On modern hardware these codes are not normally visible. On Chromebooks they are displayed by the Embedded Controller (EC), so it is useful to emit them. We must enable this feature for the EC to see the codes, so add an option for this.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v2: - Move early init code into early_board_init

arch/x86/cpu/coreboot/coreboot.c | 3 ++- arch/x86/cpu/start.S | 4 ++++ arch/x86/include/asm/post.h | 32 ++++++++++++++++++++++++++++++++ board/google/chromebook_link/Kconfig | 4 ++++ board/google/common/early_init.S | 21 ++++++++++++++++++++- 5 files changed, 62 insertions(+), 2 deletions(-) create mode 100644 arch/x86/include/asm/post.h

diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c index 874b59d..d9662d9 100644 --- a/arch/x86/cpu/coreboot/coreboot.c +++ b/arch/x86/cpu/coreboot/coreboot.c @@ -15,6 +15,7 @@ #include <asm/cache.h> #include <asm/cpu.h> #include <asm/io.h> +#include <asm/post.h> #include <asm/arch-coreboot/tables.h> #include <asm/arch-coreboot/sysinfo.h> #include <asm/arch/timestamp.h> @@ -70,7 +71,7 @@ void show_boot_progress(int val) gd->arch.tsc_prev = now; } #endif - outb(val, 0x80); + outb(val, POST_PORT); }

int last_stage_init(void) diff --git a/arch/x86/cpu/start.S b/arch/x86/cpu/start.S index b18f320..1b738f9 100644 --- a/arch/x86/cpu/start.S +++ b/arch/x86/cpu/start.S @@ -13,6 +13,7 @@ #include <config.h> #include <version.h> #include <asm/global_data.h> +#include <asm/post.h> #include <asm/processor.h> #include <asm/processor-flags.h> #include <generated/generic-asm-offsets.h> @@ -67,6 +68,7 @@ _start: jmp early_board_init .globl early_board_init_ret early_board_init_ret: + post_code(POST_START)

/* Initialise Cache-As-RAM */ jmp car_init @@ -96,6 +98,7 @@ car_init_ret:

/* Align global data to 16-byte boundary */ andl $0xfffffff0, %esp + post_code(POST_START_STACK)

/* Zero the global data since it won't happen later */ xorl %eax, %eax @@ -131,6 +134,7 @@ car_init_ret: call setup_gdt

/* Set parameter to board_init_f() to boot flags */ + post_code(POST_START_DONE) xorl %eax, %eax

/* Enter, U-boot! */ diff --git a/arch/x86/include/asm/post.h b/arch/x86/include/asm/post.h new file mode 100644 index 0000000..3371185 --- /dev/null +++ b/arch/x86/include/asm/post.h @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2014 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _post_h +#define _post_h + +/* port to use for post codes */ +#define POST_PORT 0x80 + +/* post codes which represent various stages of init */ +#define POST_START 0x1e +#define POST_CAR_START 0x1f + +#define POST_START_STACK 0x29 +#define POST_START_DONE 0x2a + +/* Output a post code using al - value must be 0 to 0xff */ +#ifdef __ASSEMBLY__ +#define post_code(value) \ + movb $value, %al; \ + outb %al, $POST_PORT +#else +static inline void post_code(int code) +{ + outb(code, POST_PORT); +} +#endif + +#endif diff --git a/board/google/chromebook_link/Kconfig b/board/google/chromebook_link/Kconfig index 975d557..9c715ba 100644 --- a/board/google/chromebook_link/Kconfig +++ b/board/google/chromebook_link/Kconfig @@ -12,4 +12,8 @@ config SYS_SOC config SYS_CONFIG_NAME default "chromebook_link"

+config EARLY_POST_CROS_EC + bool "Enable early post to Chrome OS EC" + default y + endif diff --git a/board/google/common/early_init.S b/board/google/common/early_init.S index cf70ae4..15f2ff2 100644 --- a/board/google/common/early_init.S +++ b/board/google/common/early_init.S @@ -6,5 +6,24 @@

.globl early_board_init early_board_init: - /* No 32-bit board specific initialisation */ + /* Enable post codes to EC */ +#ifdef CONFIG_EARLY_POST_CROS_EC + mov $0x1b, %ecx + rdmsr + and $0x100, %eax + test %eax, %eax + je 2f + + mov $0x8000f8f0, %eax + mov $0xcf8, %dx + out %eax, (%dx) + mov $0xfed1c001, %eax + mov $0xcfc, %dx + out %eax, (%dx) + mov $0xfed1f410, %esp + mov (%esp), %eax + and $0xfffffffb, %eax + mov %eax, (%esp) +2: +#endif jmp early_board_init_ret

Add support for CAR so that we have memory to use prior to DRAM init. On link there is a total of 128KB of CAR available, although some is used for the memory reference code.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v2: - Expand the comment about preserving ebp - Move SIPI code to after CAR init - Use capitals for all #define declarations

arch/x86/Kconfig | 16 ++++ arch/x86/cpu/ivybridge/car.S | 162 ++++++++++++++++++++++++++++++++++- arch/x86/cpu/ivybridge/cpu.c | 2 + arch/x86/include/asm/mtrr.h | 121 ++++++++++++++++++++++++++ arch/x86/include/asm/post.h | 13 ++- board/google/chromebook_link/Kconfig | 12 +++ 6 files changed, 323 insertions(+), 3 deletions(-) create mode 100644 arch/x86/include/asm/mtrr.h

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 580d6a4..995ffa6 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -34,6 +34,22 @@ config TARGET_CHROMEBOOK_LINK

endchoice

+config RAMBASE + hex + default 0x100000 + +config RAMTOP + hex + default 0x200000 + +config XIP_ROM_SIZE + hex + default 0x10000 + +config CPU_ADDR_BITS + int + default 36 + config ROM_SIZE hex default 0x800000 diff --git a/arch/x86/cpu/ivybridge/car.S b/arch/x86/cpu/ivybridge/car.S index 0480813..dca68e4 100644 --- a/arch/x86/cpu/ivybridge/car.S +++ b/arch/x86/cpu/ivybridge/car.S @@ -12,9 +12,167 @@ */

#include <common.h> +#include <asm/mtrr.h> +#include <asm/post.h> +#include <asm/processor-flags.h>

- /* Note: ebp must not be touched in this code */ +#define MTRR_PHYS_BASE_MSR(reg) (0x200 + 2 * (reg)) +#define MTRR_PHYS_MASK_MSR(reg) (0x200 + 2 * (reg) + 1) + +#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE +#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE + +/* Cache 4GB - MRC_SIZE_KB for MRC */ +#define CACHE_MRC_BYTES ((CONFIG_CACHE_MRC_SIZE_KB << 10) - 1) +#define CACHE_MRC_BASE (0xFFFFFFFF - CACHE_MRC_BYTES) +#define CACHE_MRC_MASK (~CACHE_MRC_BYTES) + +#define CPU_PHYSMASK_HI (1 << (CONFIG_CPU_ADDR_BITS - 32) - 1) + +#define NOEVICTMOD_MSR 0x2e0 + + /* + * Note: ebp must not be touched in this code as it holds the BIST + * value (built-in self test). We preserve this value until it can + * be written to global_data when CAR is ready for use. + */ .globl car_init car_init: - /* TODO: Add cache-as-RAM init here */ + post_code(POST_CAR_START) + + /* Send INIT IPI to all excluding ourself */ + movl $0x000C4500, %eax + movl $0xFEE00300, %esi + movl %eax, (%esi) + + post_code(POST_CAR_SIPI) + /* Zero out all fixed range and variable range MTRRs */ + movl $mtrr_table, %esi + movl $((mtrr_table_end - mtrr_table) / 2), %edi + xorl %eax, %eax + xorl %edx, %edx +clear_mtrrs: + movw (%esi), %bx + movzx %bx, %ecx + wrmsr + add $2, %esi + dec %edi + jnz clear_mtrrs + + post_code(POST_CAR_MTRR) + /* Configure the default memory type to uncacheable */ + movl $MTRRdefType_MSR, %ecx + rdmsr + andl $(~0x00000cff), %eax + wrmsr + + post_code(POST_CAR_UNCACHEABLE) + /* Set Cache-as-RAM base address */ + movl $(MTRR_PHYS_BASE_MSR(0)), %ecx + movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax + xorl %edx, %edx + wrmsr + + post_code(POST_CAR_BASE_ADDRESS) + /* Set Cache-as-RAM mask */ + movl $(MTRR_PHYS_MASK_MSR(0)), %ecx + movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax + movl $CPU_PHYSMASK_HI, %edx + wrmsr + + post_code(POST_CAR_MASK) + + /* Enable MTRR */ + movl $MTRRdefType_MSR, %ecx + rdmsr + orl $MTRRdefTypeEn, %eax + wrmsr + + /* Enable cache (CR0.CD = 0, CR0.NW = 0) */ + movl %cr0, %eax + andl $(~(X86_CR0_CD | X86_CR0_NW)), %eax + invd + movl %eax, %cr0 + + /* enable the 'no eviction' mode */ + movl $NOEVICTMOD_MSR, %ecx + rdmsr + orl $1, %eax + andl $~2, %eax + wrmsr + + /* Clear the cache memory region. This will also fill up the cache */ + movl $CACHE_AS_RAM_BASE, %esi + movl %esi, %edi + movl $(CACHE_AS_RAM_SIZE / 4), %ecx + xorl %eax, %eax + rep stosl + + /* enable the 'no eviction run' state */ + movl $NOEVICTMOD_MSR, %ecx + rdmsr + orl $3, %eax + wrmsr + + post_code(POST_CAR_FILL) + /* Enable Cache-as-RAM mode by disabling cache */ + movl %cr0, %eax + orl $X86_CR0_CD, %eax + movl %eax, %cr0 + + /* Enable cache for our code in Flash because we do XIP here */ + movl $MTRR_PHYS_BASE_MSR(1), %ecx + xorl %edx, %edx + movl $car_init_ret, %eax + andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax + orl $MTRR_TYPE_WRPROT, %eax + wrmsr + + movl $MTRR_PHYS_MASK_MSR(1), %ecx + movl $CPU_PHYSMASK_HI, %edx + movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax + wrmsr + + post_code(POST_CAR_ROM_CACHE) +#ifdef CONFIG_CACHE_MRC_BIN + /* Enable caching for ram init code to run faster */ + movl $MTRR_PHYS_BASE_MSR(2), %ecx + movl $(CACHE_MRC_BASE | MTRR_TYPE_WRPROT), %eax + xorl %edx, %edx + wrmsr + movl $MTRR_PHYS_MASK_MSR(2), %ecx + movl $(CACHE_MRC_MASK | MTRRphysMaskValid), %eax + movl $CPU_PHYSMASK_HI, %edx + wrmsr +#endif + + post_code(POST_CAR_MRC_CACHE) + /* Enable cache */ + movl %cr0, %eax + andl $(~(X86_CR0_CD | X86_CR0_NW)), %eax + movl %eax, %cr0 + + post_code(POST_CAR_CPU_CACHE) + + /* All CPUs need to be in Wait for SIPI state */ +wait_for_sipi: + movl (%esi), %eax + bt $12, %eax + jc wait_for_sipi + + /* return */ jmp car_init_ret + +mtrr_table: + /* Fixed MTRRs */ + .word 0x250, 0x258, 0x259 + .word 0x268, 0x269, 0x26A + .word 0x26B, 0x26C, 0x26D + .word 0x26E, 0x26F + /* Variable MTRRs */ + .word 0x200, 0x201, 0x202, 0x203 + .word 0x204, 0x205, 0x206, 0x207 + .word 0x208, 0x209, 0x20A, 0x20B + .word 0x20C, 0x20D, 0x20E, 0x20F + .word 0x210, 0x211, 0x212, 0x213 +mtrr_table_end: diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c index 1cbdaaf..5863811 100644 --- a/arch/x86/cpu/ivybridge/cpu.c +++ b/arch/x86/cpu/ivybridge/cpu.c @@ -12,6 +12,7 @@

#include <common.h> #include <asm/cpu.h> +#include <asm/post.h> #include <asm/processor.h>

DECLARE_GLOBAL_DATA_PTR; @@ -20,6 +21,7 @@ int arch_cpu_init(void) { int ret;

+ post_code(POST_CPU_INIT); timer_set_base(rdtsc());

ret = x86_cpu_init_f(); diff --git a/arch/x86/include/asm/mtrr.h b/arch/x86/include/asm/mtrr.h new file mode 100644 index 0000000..5f05a48 --- /dev/null +++ b/arch/x86/include/asm/mtrr.h @@ -0,0 +1,121 @@ +/* + * Copyright (c) 2014 Google, Inc + * + * From Coreboot file of the same name + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_MTRR_H +#define _ASM_MTRR_H + +/* These are the region types */ +#define MTRR_TYPE_UNCACHEABLE 0 +#define MTRR_TYPE_WRCOMB 1 +/*#define MTRR_TYPE_ 2*/ +/*#define MTRR_TYPE_ 3*/ +#define MTRR_TYPE_WRTHROUGH 4 +#define MTRR_TYPE_WRPROT 5 +#define MTRR_TYPE_WRBACK 6 +#define MTRR_NUM_TYPES 7 + +#define MTRRcap_MSR 0x0fe +#define MTRRdefType_MSR 0x2ff + +#define MTRRdefTypeEn (1 << 11) +#define MTRRdefTypeFixEn (1 << 10) + +#define SMRRphysBase_MSR 0x1f2 +#define SMRRphysMask_MSR 0x1f3 + +#define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg)) +#define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1) + +#define MTRRphysMaskValid (1 << 11) + +#define NUM_FIXED_RANGES 88 +#define RANGES_PER_FIXED_MTRR 8 +#define MTRRfix64K_00000_MSR 0x250 +#define MTRRfix16K_80000_MSR 0x258 +#define MTRRfix16K_A0000_MSR 0x259 +#define MTRRfix4K_C0000_MSR 0x268 +#define MTRRfix4K_C8000_MSR 0x269 +#define MTRRfix4K_D0000_MSR 0x26a +#define MTRRfix4K_D8000_MSR 0x26b +#define MTRRfix4K_E0000_MSR 0x26c +#define MTRRfix4K_E8000_MSR 0x26d +#define MTRRfix4K_F0000_MSR 0x26e +#define MTRRfix4K_F8000_MSR 0x26f + +#if !defined(__ASSEMBLER__) + +/* + * The MTRR code has some side effects that the callers should be aware for. + * 1. The call sequence matters. x86_setup_mtrrs() calls + * x86_setup_fixed_mtrrs_no_enable() then enable_fixed_mtrrs() (equivalent + * of x86_setup_fixed_mtrrs()) then x86_setup_var_mtrrs(). If the callers + * want to call the components of x86_setup_mtrrs() because of other + * rquirements the ordering should still preserved. + * 2. enable_fixed_mtrr() will enable both variable and fixed MTRRs because + * of the nature of the global MTRR enable flag. Therefore, all direct + * or indirect callers of enable_fixed_mtrr() should ensure that the + * variable MTRR MSRs do not contain bad ranges. + * 3. If CONFIG_CACHE_ROM is selected an MTRR is allocated for enabling + * the caching of the ROM. However, it is set to uncacheable (UC). It + * is the responsiblity of the caller to enable it by calling + * x86_mtrr_enable_rom_caching(). + */ +void x86_setup_mtrrs(void); +/* + * x86_setup_var_mtrrs() parameters: + * address_bits - number of physical address bits supported by cpu + * above4gb - 2 means dynamically detect number of variable MTRRs available. + * non-zero means handle memory ranges above 4GiB. + * 0 means ignore memory ranges above 4GiB + */ +void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb); +void enable_fixed_mtrr(void); +void x86_setup_fixed_mtrrs(void); +/* Set up fixed MTRRs but do not enable them. */ +void x86_setup_fixed_mtrrs_no_enable(void); +int x86_mtrr_check(void); +/* ROM caching can be used after variable MTRRs are set up. Beware that + * enabling CONFIG_CACHE_ROM will eat through quite a few MTRRs based on + * one's IO hole size and WRCOMB resources. Be sure to check the console + * log when enabling CONFIG_CACHE_ROM or adding WRCOMB resources. Beware that + * on CPUs with core-scoped MTRR registers such as hyperthreaded CPUs the + * rom caching will be disabled if all threads run the MTRR code. Therefore, + * one needs to call x86_mtrr_enable_rom_caching() after all threads of the + * same core have run the MTRR code. */ +#if CONFIG_CACHE_ROM +void x86_mtrr_enable_rom_caching(void); +void x86_mtrr_disable_rom_caching(void); +/* Return the variable range MTRR index of the ROM cache. */ +long x86_mtrr_rom_cache_var_index(void); +#else +static inline void x86_mtrr_enable_rom_caching(void) {} +static inline void x86_mtrr_disable_rom_caching(void) {} +static inline long x86_mtrr_rom_cache_var_index(void) { return -1; } +#endif /* CONFIG_CACHE_ROM */ + +#endif + +#if !defined(CONFIG_RAMTOP) +# error "CONFIG_RAMTOP not defined" +#endif + +#if ((CONFIG_XIP_ROM_SIZE & (CONFIG_XIP_ROM_SIZE - 1)) != 0) +# error "CONFIG_XIP_ROM_SIZE is not a power of 2" +#endif + +#if ((CONFIG_CACHE_ROM_SIZE & (CONFIG_CACHE_ROM_SIZE - 1)) != 0) +# error "CONFIG_CACHE_ROM_SIZE is not a power of 2" +#endif + +#define CACHE_ROM_BASE (((1 << 20) - (CONFIG_CACHE_ROM_SIZE >> 12)) << 12) + +#if (CONFIG_RAMTOP & (CONFIG_RAMTOP - 1)) != 0 +# error "CONFIG_RAMTOP must be a power of 2" +#endif + +#endif diff --git a/arch/x86/include/asm/post.h b/arch/x86/include/asm/post.h index 3371185..b203dc9 100644 --- a/arch/x86/include/asm/post.h +++ b/arch/x86/include/asm/post.h @@ -13,9 +13,18 @@ /* post codes which represent various stages of init */ #define POST_START 0x1e #define POST_CAR_START 0x1f - +#define POST_CAR_SIPI 0x20 +#define POST_CAR_MTRR 0x21 +#define POST_CAR_UNCACHEABLE 0x22 +#define POST_CAR_BASE_ADDRESS 0x23 +#define POST_CAR_MASK 0x24 +#define POST_CAR_FILL 0x25 +#define POST_CAR_ROM_CACHE 0x26 +#define POST_CAR_MRC_CACHE 0x27 +#define POST_CAR_CPU_CACHE 0x28 #define POST_START_STACK 0x29 #define POST_START_DONE 0x2a +#define POST_CPU_INIT 0x2b

/* Output a post code using al - value must be 0 to 0xff */ #ifdef __ASSEMBLY__ @@ -23,6 +32,8 @@ movb $value, %al; \ outb %al, $POST_PORT #else +#include <asm/io.h> + static inline void post_code(int code) { outb(code, POST_PORT); diff --git a/board/google/chromebook_link/Kconfig b/board/google/chromebook_link/Kconfig index 9c715ba..3a4f557 100644 --- a/board/google/chromebook_link/Kconfig +++ b/board/google/chromebook_link/Kconfig @@ -12,6 +12,18 @@ config SYS_SOC config SYS_CONFIG_NAME default "chromebook_link"

+config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select CPU_INTEL_SOCKET_RPGA989 + select NORTHBRIDGE_INTEL_IVYBRIDGE + select SOUTHBRIDGE_INTEL_C216 + select HAVE_ACPI_RESUME + select MARK_GRAPHICS_MEM_WRCOMB + +config MMCONF_BASE_ADDRESS + hex + default 0xf0000000 + config EARLY_POST_CROS_EC bool "Enable early post to Chrome OS EC" default y

Add support for using PCI before SDRAM is available, using early malloc() and global_data.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v2: - Split out new patch to support use fo PCI before relocation

arch/x86/cpu/pci.c | 20 ++++++++++++++++++++ arch/x86/include/asm/global_data.h | 1 + arch/x86/include/asm/pci.h | 9 +++++++++ 3 files changed, 30 insertions(+)

diff --git a/arch/x86/cpu/pci.c b/arch/x86/cpu/pci.c index 030cbbc..096a053 100644 --- a/arch/x86/cpu/pci.c +++ b/arch/x86/cpu/pci.c @@ -10,15 +10,35 @@ */

#include <common.h> +#include <errno.h> +#include <malloc.h> #include <pci.h> #include <asm/pci.h>

static struct pci_controller x86_hose;

+int pci_early_init_hose(struct pci_controller **hosep) +{ + struct pci_controller *hose; + + hose = calloc(1, sizeof(struct pci_controller)); + if (!hose) + return -ENOMEM; + + board_pci_setup_hose(hose); + gd->arch.hose = hose; + *hosep = hose; + + return 0; +} + void pci_init_board(void) { struct pci_controller *hose = &x86_hose;

+ /* Stop using the early hose */ + gd->arch.hose = NULL; + board_pci_setup_hose(hose); pci_register_hose(hose);

diff --git a/arch/x86/include/asm/global_data.h b/arch/x86/include/asm/global_data.h index 186b97e..d32987b 100644 --- a/arch/x86/include/asm/global_data.h +++ b/arch/x86/include/asm/global_data.h @@ -24,6 +24,7 @@ struct arch_global_data { uint32_t tsc_mhz; /* TSC frequency in MHz */ void *new_fdt; /* Relocated FDT */ uint32_t bist; /* Built-in self test value */ + struct pci_controller *hose; /* PCI hose for early use */ };

#endif diff --git a/arch/x86/include/asm/pci.h b/arch/x86/include/asm/pci.h index c160707..6e70a99 100644 --- a/arch/x86/include/asm/pci.h +++ b/arch/x86/include/asm/pci.h @@ -24,4 +24,13 @@ void pci_setup_type1(struct pci_controller *hose); * store things in 'hose' and not in BSS variables. */ void board_pci_setup_hose(struct pci_controller *hose); + +/** + * pci_early_init_hose() - Set up PCI host before relocation + * + * This allocates memory for, sets up and returns the PCI hose. It can be + * called before relocation. The hose will be stored in gd->arch.hose for + * later use, but will become invalid one DRAM is available. + */ +int pci_early_init_hose(struct pci_controller **hosep); #endif

Add simple PCI access routines for x86 which permit use before relocation. The normal PCI stack is still used, but for pre-relocation use there can only ever be a single hose. After relocation, fall back to the normal access, although even then on x86 machines there is normally only a single PCI bus.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v2: None

arch/x86/cpu/pci.c | 50 ++++++++++++++++++++++++++++++++++++++++++++++ arch/x86/include/asm/pci.h | 13 ++++++++++++ 2 files changed, 63 insertions(+)

diff --git a/arch/x86/cpu/pci.c b/arch/x86/cpu/pci.c index 096a053..36057c6 100644 --- a/arch/x86/cpu/pci.c +++ b/arch/x86/cpu/pci.c @@ -44,3 +44,53 @@ void pci_init_board(void)

pci_hose_scan(hose); } + +static struct pci_controller *get_hose(void) +{ + if (gd->arch.hose) + return gd->arch.hose; + + return pci_bus_to_hose(0); +} + +unsigned int pci_read_config8(pci_dev_t dev, unsigned where) +{ + uint8_t value; + + pci_hose_read_config_byte(get_hose(), dev, where, &value); + + return value; +} + +unsigned int pci_read_config16(pci_dev_t dev, unsigned where) +{ + uint16_t value; + + pci_hose_read_config_word(get_hose(), dev, where, &value); + + return value; +} + +unsigned int pci_read_config32(pci_dev_t dev, unsigned where) +{ + uint32_t value; + + pci_hose_read_config_dword(get_hose(), dev, where, &value); + + return value; +} + +void pci_write_config8(pci_dev_t dev, unsigned where, unsigned value) +{ + pci_hose_write_config_byte(get_hose(), dev, where, value); +} + +void pci_write_config16(pci_dev_t dev, unsigned where, unsigned value) +{ + pci_hose_write_config_word(get_hose(), dev, where, value); +} + +void pci_write_config32(pci_dev_t dev, unsigned where, unsigned value) +{ + pci_hose_write_config_dword(get_hose(), dev, where, value); +} diff --git a/arch/x86/include/asm/pci.h b/arch/x86/include/asm/pci.h index 6e70a99..98817aa 100644 --- a/arch/x86/include/asm/pci.h +++ b/arch/x86/include/asm/pci.h @@ -33,4 +33,17 @@ void board_pci_setup_hose(struct pci_controller *hose); * later use, but will become invalid one DRAM is available. */ int pci_early_init_hose(struct pci_controller **hosep); + +/* + * Simple PCI access routines - these work from either the early PCI hose + * or the 'real' one, created after U-Boot has memory available + */ +unsigned int pci_read_config8(pci_dev_t dev, unsigned where); +unsigned int pci_read_config16(pci_dev_t dev, unsigned where); +unsigned int pci_read_config32(pci_dev_t dev, unsigned where); + +void pci_write_config8(pci_dev_t dev, unsigned where, unsigned value); +void pci_write_config16(pci_dev_t dev, unsigned where, unsigned value); +void pci_write_config32(pci_dev_t dev, unsigned where, unsigned value); + #endif

There is no need to explicitly write 'arch-coreboot' when including headers, as when the arch directory points to coreboot the correct files will be used.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v2: None

arch/x86/cpu/coreboot/coreboot.c | 4 ++-- arch/x86/cpu/coreboot/ipchecksum.c | 2 +- arch/x86/cpu/coreboot/tables.c | 6 +++--- 3 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c index d9662d9..d615e87 100644 --- a/arch/x86/cpu/coreboot/coreboot.c +++ b/arch/x86/cpu/coreboot/coreboot.c @@ -16,8 +16,8 @@ #include <asm/cpu.h> #include <asm/io.h> #include <asm/post.h> -#include <asm/arch-coreboot/tables.h> -#include <asm/arch-coreboot/sysinfo.h> +#include <asm/arch/tables.h> +#include <asm/arch/sysinfo.h> #include <asm/arch/timestamp.h>

DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/x86/cpu/coreboot/ipchecksum.c b/arch/x86/cpu/coreboot/ipchecksum.c index 57733d8..5f6c009 100644 --- a/arch/x86/cpu/coreboot/ipchecksum.c +++ b/arch/x86/cpu/coreboot/ipchecksum.c @@ -30,7 +30,7 @@ */

#include <compiler.h> -#include <asm/arch-coreboot/ipchecksum.h> +#include <asm/arch/ipchecksum.h>

unsigned short ipchksum(const void *vptr, unsigned long nbytes) { diff --git a/arch/x86/cpu/coreboot/tables.c b/arch/x86/cpu/coreboot/tables.c index 0d91adc..92b7528 100644 --- a/arch/x86/cpu/coreboot/tables.c +++ b/arch/x86/cpu/coreboot/tables.c @@ -8,9 +8,9 @@ */

#include <common.h> -#include <asm/arch-coreboot/ipchecksum.h> -#include <asm/arch-coreboot/sysinfo.h> -#include <asm/arch-coreboot/tables.h> +#include <asm/arch/ipchecksum.h> +#include <asm/arch/sysinfo.h> +#include <asm/arch/tables.h>

/* * This needs to be in the .data section so that it's copied over during

It is convenient to be able to adjust MSRs with a structure that splits the two 32-bit halves into separate fields, as they are often dealt with separately. Add a few functions to support this.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v2: None

arch/x86/include/asm/msr.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+)

diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h index 3b5915d..df43983 100644 --- a/arch/x86/include/asm/msr.h +++ b/arch/x86/include/asm/msr.h @@ -175,6 +175,25 @@ static inline int wrmsr_safe_regs(u32 regs[8]) return native_wrmsr_safe_regs(regs); }

+typedef struct msr_t { + uint32_t lo; + uint32_t hi; +} msr_t; + +static inline struct msr_t msr_read(unsigned msr_num) +{ + struct msr_t msr; + + rdmsr(msr_num, msr.lo, msr.hi); + + return msr; +} + +static inline void msr_write(unsigned msr_num, msr_t msr) +{ + wrmsr(msr_num, msr.lo, msr.hi); +} + #define rdtscl(low) \ ((low) = (u32)__native_read_tsc())

The built-in self test value should be checked before we continue booting. Refuse to continue if there is something wrong.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v2: None

arch/x86/cpu/ivybridge/cpu.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+)

diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c index ab708dd..6a242d7 100644 --- a/arch/x86/cpu/ivybridge/cpu.c +++ b/arch/x86/cpu/ivybridge/cpu.c @@ -179,10 +179,26 @@ int arch_cpu_init(void) return 0; }

+static int report_bist_failure(void) +{ + if (gd->arch.bist != 0) { + printf("BIST failed: %08x\n", gd->arch.bist); + return -EFAULT; + } + + return 0; +} + int print_cpuinfo(void) { char processor_name[CPU_MAX_NAME_LEN]; const char *name; + int ret; + + /* Halt if there was a built in self test failure */ + ret = report_bist_failure(); + if (ret) + return ret;

/* Print processor name */ name = cpu_get_name(processor_name);

Add two microcode updates that are provided for this CPU. The updates have been converted to a device tree form.

Note: SPDX submission has been done. If this license is approved I will convert the files to use SPDX.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v2: - Change commit message to indicate that SPDX license request is submitted

arch/x86/dts/link.dts | 10 + arch/x86/dts/m12206a7_00000028.dtsi | 622 ++++++++++++++++++++++++++++++ arch/x86/dts/m12306a9_00000017.dtsi | 750 ++++++++++++++++++++++++++++++++++++ 3 files changed, 1382 insertions(+) create mode 100644 arch/x86/dts/m12206a7_00000028.dtsi create mode 100644 arch/x86/dts/m12306a9_00000017.dtsi

diff --git a/arch/x86/dts/link.dts b/arch/x86/dts/link.dts index 63933aa..f1b7bf0 100644 --- a/arch/x86/dts/link.dts +++ b/arch/x86/dts/link.dts @@ -67,4 +67,14 @@ }; }; }; + + microcode { + update@0 { +#include "m12206a7_00000028.dtsi" + }; + update@1 { +#include "m12306a9_00000017.dtsi" + }; + }; + }; diff --git a/arch/x86/dts/m12206a7_00000028.dtsi b/arch/x86/dts/m12206a7_00000028.dtsi new file mode 100644 index 0000000..bcd5248 --- /dev/null +++ b/arch/x86/dts/m12206a7_00000028.dtsi @@ -0,0 +1,622 @@ +/* + * Copyright (c) <1995-2013>, Intel Corporation. + * All rights reserved. + * + * Redistribution. Redistribution and use in binary form, without modification, are + * permitted provided that the following conditions are met: + * .Redistributions must reproduce the above copyright notice and the following + * disclaimer in the documentation and/or other materials provided with the + * distribution. + * Neither the name of Intel Corporation nor the names of its suppliers may be used + * to endorse or promote products derived from this software without specific prior + * written permission. + * .No reverse engineering, decompilation, or disassembly of this software is + * permitted. + * ."Binary form" includes any format commonly used for electronic conveyance + * which is a reversible, bit-exact translation of binary representation to ASCII or + * ISO text, for example, "uuencode." + * + * DISCLAIMER. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + *--- + * This is a device tree fragment. Use #include to add these properties to a + * node. + */ + +compatible = "intel,microcode"; +intel,header-version = <1>; +intel,update-revision = <0x28>; +intel,date-code = <0x04242012>; +intel,processor-signature = <0x000206a7>; +intel,checksum = <0xf3e9935d>; +intel,loader-revision = <1>; +intel,processor-flags = <0x12>; + +/* The 48-byte public header is omitted. */ +data = < + 0x00000000 0x000000a1 0x00020001 0x00000028 + 0x00000000 0x00000000 0x20120423 0x000008f1 + 0x00000001 0x000206a7 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000008f1 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x52b813ac 0xdb8994c7 0x70e9f6bb 0x9d6db2ff + 0xf4d70f5d 0x5b1eccf6 0xac59106f 0x0ae2e2c1 + 0x1a7bbeb1 0x355a1d62 0x2e7eb594 0x09f8dea9 + 0x432a49e4 0xbf520253 0xdafa4010 0x893a858a + 0x766e0efb 0xd91e196d 0x838bd2ef 0xe5146494 + 0xd515f413 0x29704828 0xe85598b6 0xdcbe6c51 + 0x88eabbfa 0xa1e8909f 0xd8931721 0x35386554 + 0x089a78a7 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* All rights reserved. + * + * Redistribution. Redistribution and use in binary form, without modification, are + * permitted provided that the following conditions are met: + * .Redistributions must reproduce the above copyright notice and the following + * disclaimer in the documentation and/or other materials provided with the + * distribution. + * Neither the name of Intel Corporation nor the names of its suppliers may be used + * to endorse or promote products derived from this software without specific prior + * written permission. + * .No reverse engineering, decompilation, or disassembly of this software is + * permitted. + * ."Binary form" includes any format commonly used for electronic conveyance + * which is a reversible, bit-exact translation of binary representation to ASCII or + * ISO text, for example, "uuencode." + * + * DISCLAIMER. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + *--- + * This is a device tree fragment. Use #include to add these properties to a + * node. + */ + +compatible = "intel,microcode"; +intel,header-version = <1>; +intel,update-revision = <0x17>; +intel,date-code = <0x01092013>; +intel,processor-signature = <0x000306a9>; +intel,checksum = <0x3546450b>; +intel,loader-revision = <1>; +intel,processor-flags = <0x12>; + +/* The 48-byte public header is omitted. */ +data = < + 0x00000000 0x000000a1 0x00020001 0x00000017 + 0x00000000 0x00000000 0x20130107 0x00000a61 + 0x00000001 0x000306a9 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x86c5b0d4 0xf6978804 0x7f4f5870 0x6319dc3c + 0xbb3b7d61 0x33cf9075 0xe8424658 0xf611a357 + 0x5a3401db 0x42caecce 0xb4d8e75e 0xe6dbaf24 + 0x7861b35f 0x6bd717bc 0x23b9b731 0x82ec1ac8 + 0x20337b64 0x5396dbf1 0x59973bff 0x724bc7e9 + 0x5237193b 0x0b8647c1 0x6a0d0e16 0xbf9ddb5b + 0xace2cc1c 0xad707638 0x056f102f 0xa37e60f8 + 0x76255642 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0xf0ee3325 0x63f2e126 0x5ec4c67b + 0x2ca782cc 0xcaf20d04 0x8b59d515 0x3212aa33 + 0x335ca0c3 0x6f9e0cdd 0x4d4bf189 0x44d2fa0c + 0x5abe9396 0x492794ee 0x10dcfcb1 0x9acda9bd + 0xe8aa2803 0x3f1b9605 0x3e2ecb5a 0x971bfa8a + 0xcbf141d2 0x0afafe10 0x2fc906a6 0xefad20c0 + 0x9e922581 0xe69142cc 0xc9c0ba82 0xc069e640 + 0xb99c08b6 0x4b62ca1f 0xf3c5767a 0x6ab088c7 + 0x8f0f0c0b 0x6726f64a 0x9711a3cd 0x46462571 + 0x3a58350e 0xa2561911 0xe24dfdfe 0x97443fdc + 0xf80540be 0x069978bf 0xb38a359b 0x8e574f62 + 0x69aea75c 0xdc753fcb 0x2a74002c 0xced027b4 + 0xda993254 0x03409b83 0xf827331d 0x75fb3271 + 0x01ad839d 0x68520842 0xca65c45c 0x1a3db5a0 + 0x91d37dd3 0x6168c0fb 0x935f5a08 0x002007c3 + 0x42eb4760 0xdab3a804 0x72a6297e 0x905c32d9 + 0x81abcfa9 0x1b21d04a 0x5a1289ae 0x424e7183 + 0xc207906c 0x31fe9134 0x5eb2e5af 0xc9253fc7 + 0xc32be24f 0xe5474cbd 0xeff6e1b0 0x710e5e69 + 0xe6c4c538 0x96b5f1de 0x2abc9c35 0xddbd1a92 + 0x8aca40d7 0xe359c238 0x954718f4 0x18b157e5 + 0xeeed790e 0x6948a963 0x24e70bfb 0x4d681547 + 0xf68369a7 0x5b54409a 0x1f0b787a 0xc2610047 + 0x0f8bd269 0xd7c8c154 0x9dee62d9 0xd4738ed8 + 0x1a66c6b1 0x5bad5a5b 0xb110311a 0xfaec6802 + 0x6b750f2d 0xcbf8d0e0 0x11edaf4b 0xf64a07bb + 0x422e7c15 0xb1732663 0x1ff404f0 0x2d5052b0 + 0x6e45356c 0x7e2201e8 0x7c5ebcd1 0x1cb4425a + 0xb1539a64 0xa2e4459f 0xcf1ade8a 0xfc476473 + 0xf4147deb 0x2afbdd77 0xff01fabc 0x6597408a + 0x0951220b 0x6750f3ec 0x0a242763 0xf3d71c05 + 0x84cb1c26 0xdb7a81bd 0x7aea1a5d 0x7e719a48 + 0xc5c12fe1 0x0ce2e988 0x29ecc6f0 0x5ede901a + 0xda8399b1 0x31c05d6b 0xe1956aff 0x59ed7c3d + 0x60832637 0x9bcb7cac 0x63c530d1 0x14c677de + 0x9225ed18 0x065327c9 0xd1ff6a0e 0x5516517e + 0x53c6f5c2 0xed5983cf 0xaa1d18b9 0xbe300d7f + 0xadc525a7 0x07ea81b6 0xfc517a09 0x4ead3f86 + 0x45435f41 0x2efa58df 0x02348ebc 0x30ed6783 + 0x190b4fb9 0x85c55d6e 0xc9ed8896 0x416ee113 + 0x9b3536d9 0x30577cc0 0xbc4b88c8 0xcda59612 + 0xdfe2bd89 0xd60cde71 0x98843881 0xcc1f32f2 + 0x18b3f643 0x671a14ca 0xd6482a47 0xac6a7d38 + 0x1897da16 0x91b6fcb3 0xf199bb35 0xd38c00ba + 0xa8c946b6 0x52a1ad37 0xd38ed2d4 0xa1d6f81d + 0x5af6865b 0xebdb858f 0xb844b110 0x53201ea2 + 0x08870945 0x10c869de 0x19849613 0xdb35d3ed + 0xd68ebd6e 0x1056fd48 0xf1a0e305 0xe3982ebd + 0x6f7cc391 0x5956374a 0xf414a5a2 0x325119ab + 0x99ee1f96 0x6f044bd9 0x8374805b 0xb55c366c + 0xa2c77051 0x68f199e5 0xd36a9714 0x878f847b + 0xec0394ae 0x86d0584b 0xf4df66b9 0x451cd039 + 0xf4de06ae 0x35dd0554 0x818a342f 0xeefdbfc9 + 0x5b4e9edd 0x22d9313a 0x3b710d60 0x6deaeb4c + 0xa9e26512 0x98d31867 0x3c2c2d61 0x7eb5ce41 + 0x40890db6 0x7a3aa660 0x3ef4f306 0x7322881f + 0x49dac4d5 0x96efe685 0x27bb7f49 0xbb955283 + 0x79c5f2b7 0xff599c28 0x28ee7f5e 0x9f324b73 + 0x45edb7cf 0x39a8b79c 0xd0919c6e 0xe149b29d + 0x62f5f82e 0xebcfa23e 0xd4d68937 0x54270090 + 0x958af0d4 0xa1e4e799 0xaf68ac19 0x82a84f4e + 0x50f67b84 0xd5e59629 0xf5fdf24c 0xab1d63c5 + 0x30835807 0x431fce5f 0xe5f96f4d 0x3f6b4802 + 0x14010be8 0xdca45ae5 0xc82709af 0xff76ce2c + 0x8b222c22 0x73a2d948 0xa8d59cea 0x8c31849e + 0x469c2e5f 0x3777ee84 0x5fdfa5da 0x02ef9bb2 + 0x792d3194 0xbed63f21 0x0b6dc5f1 0xc9d7fe08 + 0x6df7883d 0x366566cf 0xef772769 0x37826465 + 0x1cdc3086 0xa69ff7b6 0x235012ea 0x292f7e75 + 0x30bdd0fd 0xffdc9df1 0x95c6d570 0xec206204 + 0xc6cd42cb 0xc0d6dfd9 0xb7a16b71 0x17fa527e + 0x295f2c79 0x990f9820 0x8b8f447d 0x193f9ad1 + 0xebddb2af 0x5dd532eb 0xf1bbd8e8 0x3444a3f4 + 0x18ccce93 0x05edeb4f 0xc4a6b935 0xba37aab0 + 0x96076ba4 0x250dc2f7 0xc4093548 0x030e777d + 0x7ea40933 0x8da7b1dd 0x59c0b79f 0x807d437c + 0xf5233ddf 0x54c1983f 0xfc18771b 0xe74b85f0 + 0xdbd725b5 0x70cdd153 0x4ffe300c 0xfda4bdae + 0xf4ac75d2 0x91c4e15a 0x34d92b97 0x16356a79 + >;

When not relying on Coreboot for GPIO init the GPIOs must be set up correctly. This is currently done statically through a rather ugly method. As the GPIOs are figured out they can be moved to the device tree and set up as needed rather than all at the start.

In this implementation, board files should call ich_gpio_set_gpio_map() before the GPIO driver is used in order to provide the GPIO information. We use the early PCI interface so that this driver can now be used before relocation.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v2: None

arch/x86/include/asm/arch-coreboot/gpio.h | 5 -- arch/x86/include/asm/arch-ivybridge/pch.h | 16 ++++ arch/x86/include/asm/global_data.h | 1 + arch/x86/include/asm/gpio.h | 142 +++++++++++++++++++++++++++++- drivers/gpio/intel_ich6_gpio.c | 79 ++++++++++++++--- 5 files changed, 227 insertions(+), 16 deletions(-)

diff --git a/arch/x86/include/asm/arch-coreboot/gpio.h b/arch/x86/include/asm/arch-coreboot/gpio.h index 3ec1816..4951a8c 100644 --- a/arch/x86/include/asm/arch-coreboot/gpio.h +++ b/arch/x86/include/asm/arch-coreboot/gpio.h @@ -7,9 +7,4 @@ #ifndef _X86_ARCH_GPIO_H_ #define _X86_ARCH_GPIO_H_

-struct ich6_bank_platdata { - uint32_t base_addr; - const char *bank_name; -}; - #endif /* _X86_ARCH_GPIO_H_ */ diff --git a/arch/x86/include/asm/arch-ivybridge/pch.h b/arch/x86/include/asm/arch-ivybridge/pch.h index 290a737..ae338e3 100644 --- a/arch/x86/include/asm/arch-ivybridge/pch.h +++ b/arch/x86/include/asm/arch-ivybridge/pch.h @@ -142,6 +142,22 @@ #define FD2 0x3428 /* 32bit */ #define CG 0x341c /* 32bit */

+/* ICH7 GPIOBASE */ +#define GPIO_USE_SEL 0x00 +#define GP_IO_SEL 0x04 +#define GP_LVL 0x0c +#define GPO_BLINK 0x18 +#define GPI_INV 0x2c +#define GPIO_USE_SEL2 0x30 +#define GP_IO_SEL2 0x34 +#define GP_LVL2 0x38 +#define GPIO_USE_SEL3 0x40 +#define GP_IO_SEL3 0x44 +#define GP_LVL3 0x48 +#define GP_RST_SEL1 0x60 +#define GP_RST_SEL2 0x64 +#define GP_RST_SEL3 0x68 + /* ICH7 PMBASE */ #define PM1_STS 0x00 #define WAK_STS (1 << 15) diff --git a/arch/x86/include/asm/global_data.h b/arch/x86/include/asm/global_data.h index ff9574c..4ea46d7 100644 --- a/arch/x86/include/asm/global_data.h +++ b/arch/x86/include/asm/global_data.h @@ -33,6 +33,7 @@ struct arch_global_data { uint32_t bist; /* Built-in self test value */ struct pci_controller *hose; /* PCI hose for early use */ enum pei_boot_mode_t pei_boot_mode; + const struct pch_gpio_map *gpio_map; /* board GPIO map */ };

#endif diff --git a/arch/x86/include/asm/gpio.h b/arch/x86/include/asm/gpio.h index 8bda414..5540d42 100644 --- a/arch/x86/include/asm/gpio.h +++ b/arch/x86/include/asm/gpio.h @@ -1,12 +1,152 @@ /* * Copyright (c) 2012, Google Inc. All rights reserved. - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0 */

#ifndef _X86_GPIO_H_ #define _X86_GPIO_H_

+#include <linux/compiler.h> #include <asm/arch/gpio.h> #include <asm-generic/gpio.h>

+struct ich6_bank_platdata { + uint32_t base_addr; + const char *bank_name; +}; + +#define GPIO_MODE_NATIVE 0 +#define GPIO_MODE_GPIO 1 +#define GPIO_MODE_NONE 1 + +#define GPIO_DIR_OUTPUT 0 +#define GPIO_DIR_INPUT 1 + +#define GPIO_NO_INVERT 0 +#define GPIO_INVERT 1 + +#define GPIO_LEVEL_LOW 0 +#define GPIO_LEVEL_HIGH 1 + +#define GPIO_NO_BLINK 0 +#define GPIO_BLINK 1 + +#define GPIO_RESET_PWROK 0 +#define GPIO_RESET_RSMRST 1 + +struct pch_gpio_set1 { + u32 gpio0:1; + u32 gpio1:1; + u32 gpio2:1; + u32 gpio3:1; + u32 gpio4:1; + u32 gpio5:1; + u32 gpio6:1; + u32 gpio7:1; + u32 gpio8:1; + u32 gpio9:1; + u32 gpio10:1; + u32 gpio11:1; + u32 gpio12:1; + u32 gpio13:1; + u32 gpio14:1; + u32 gpio15:1; + u32 gpio16:1; + u32 gpio17:1; + u32 gpio18:1; + u32 gpio19:1; + u32 gpio20:1; + u32 gpio21:1; + u32 gpio22:1; + u32 gpio23:1; + u32 gpio24:1; + u32 gpio25:1; + u32 gpio26:1; + u32 gpio27:1; + u32 gpio28:1; + u32 gpio29:1; + u32 gpio30:1; + u32 gpio31:1; +} __packed; + +struct pch_gpio_set2 { + u32 gpio32:1; + u32 gpio33:1; + u32 gpio34:1; + u32 gpio35:1; + u32 gpio36:1; + u32 gpio37:1; + u32 gpio38:1; + u32 gpio39:1; + u32 gpio40:1; + u32 gpio41:1; + u32 gpio42:1; + u32 gpio43:1; + u32 gpio44:1; + u32 gpio45:1; + u32 gpio46:1; + u32 gpio47:1; + u32 gpio48:1; + u32 gpio49:1; + u32 gpio50:1; + u32 gpio51:1; + u32 gpio52:1; + u32 gpio53:1; + u32 gpio54:1; + u32 gpio55:1; + u32 gpio56:1; + u32 gpio57:1; + u32 gpio58:1; + u32 gpio59:1; + u32 gpio60:1; + u32 gpio61:1; + u32 gpio62:1; + u32 gpio63:1; +} __packed; + +struct pch_gpio_set3 { + u32 gpio64:1; + u32 gpio65:1; + u32 gpio66:1; + u32 gpio67:1; + u32 gpio68:1; + u32 gpio69:1; + u32 gpio70:1; + u32 gpio71:1; + u32 gpio72:1; + u32 gpio73:1; + u32 gpio74:1; + u32 gpio75:1; +} __packed; + +/* + * This hilariously complex structure came from Coreboot. The + * setup_pch_gpios() function uses it. It could be move to device tree, or + * adjust to use masks instead of bitfields. + */ +struct pch_gpio_map { + struct { + const struct pch_gpio_set1 *mode; + const struct pch_gpio_set1 *direction; + const struct pch_gpio_set1 *level; + const struct pch_gpio_set1 *reset; + const struct pch_gpio_set1 *invert; + const struct pch_gpio_set1 *blink; + } set1; + struct { + const struct pch_gpio_set2 *mode; + const struct pch_gpio_set2 *direction; + const struct pch_gpio_set2 *level; + const struct pch_gpio_set2 *reset; + } set2; + struct { + const struct pch_gpio_set3 *mode; + const struct pch_gpio_set3 *direction; + const struct pch_gpio_set3 *level; + const struct pch_gpio_set3 *reset; + } set3; +}; + +void ich_gpio_set_gpio_map(const struct pch_gpio_map *map); + #endif /* _X86_GPIO_H_ */ diff --git a/drivers/gpio/intel_ich6_gpio.c b/drivers/gpio/intel_ich6_gpio.c index d3381b0..b095d17 100644 --- a/drivers/gpio/intel_ich6_gpio.c +++ b/drivers/gpio/intel_ich6_gpio.c @@ -33,6 +33,11 @@ #include <pci.h> #include <asm/gpio.h> #include <asm/io.h> +#include <asm/pci.h> +#ifdef CONFIG_X86_RESET_VECTOR +#include <asm/arch/pch.h> +#define SUPPORT_GPIO_SETUP +#endif

#define GPIO_PER_BANK 32

@@ -46,6 +51,53 @@ struct ich6_bank_priv { uint32_t lvl; };

+#ifdef SUPPORT_GPIO_SETUP +static void setup_pch_gpios(const struct pch_gpio_map *gpio) +{ + u16 gpiobase = pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc; + + /* GPIO Set 1 */ + if (gpio->set1.level) + outl(*((u32 *)gpio->set1.level), gpiobase + GP_LVL); + if (gpio->set1.mode) + outl(*((u32 *)gpio->set1.mode), gpiobase + GPIO_USE_SEL); + if (gpio->set1.direction) + outl(*((u32 *)gpio->set1.direction), gpiobase + GP_IO_SEL); + if (gpio->set1.reset) + outl(*((u32 *)gpio->set1.reset), gpiobase + GP_RST_SEL1); + if (gpio->set1.invert) + outl(*((u32 *)gpio->set1.invert), gpiobase + GPI_INV); + if (gpio->set1.blink) + outl(*((u32 *)gpio->set1.blink), gpiobase + GPO_BLINK); + + /* GPIO Set 2 */ + if (gpio->set2.level) + outl(*((u32 *)gpio->set2.level), gpiobase + GP_LVL2); + if (gpio->set2.mode) + outl(*((u32 *)gpio->set2.mode), gpiobase + GPIO_USE_SEL2); + if (gpio->set2.direction) + outl(*((u32 *)gpio->set2.direction), gpiobase + GP_IO_SEL2); + if (gpio->set2.reset) + outl(*((u32 *)gpio->set2.reset), gpiobase + GP_RST_SEL2); + + /* GPIO Set 3 */ + if (gpio->set3.level) + outl(*((u32 *)gpio->set3.level), gpiobase + GP_LVL3); + if (gpio->set3.mode) + outl(*((u32 *)gpio->set3.mode), gpiobase + GPIO_USE_SEL3); + if (gpio->set3.direction) + outl(*((u32 *)gpio->set3.direction), gpiobase + GP_IO_SEL3); + if (gpio->set3.reset) + outl(*((u32 *)gpio->set3.reset), gpiobase + GP_RST_SEL3); +} + +/* TODO: Move this to device tree, or platform data */ +void ich_gpio_set_gpio_map(const struct pch_gpio_map *map) +{ + gd->arch.gpio_map = map; +} +#endif /* SUPPORT_GPIO_SETUP */ + static int gpio_ich6_ofdata_to_platdata(struct udevice *dev) { struct ich6_bank_platdata *plat = dev_get_platdata(dev); @@ -60,13 +112,13 @@ static int gpio_ich6_ofdata_to_platdata(struct udevice *dev) pci_dev = PCI_BDF(0, 0x1f, 0);

/* Is the device present? */ - pci_read_config_word(pci_dev, PCI_VENDOR_ID, &tmpword); + tmpword = pci_read_config16(pci_dev, PCI_VENDOR_ID); if (tmpword != PCI_VENDOR_ID_INTEL) { debug("%s: wrong VendorID\n", __func__); return -ENODEV; }

- pci_read_config_word(pci_dev, PCI_DEVICE_ID, &tmpword); + tmpword = pci_read_config16(pci_dev, PCI_DEVICE_ID); debug("Found %04x:%04x\n", PCI_VENDOR_ID_INTEL, tmpword); /* * We'd like to validate the Device ID too, but pretty much any @@ -76,34 +128,34 @@ static int gpio_ich6_ofdata_to_platdata(struct udevice *dev) */

/* I/O should already be enabled (it's a RO bit). */ - pci_read_config_word(pci_dev, PCI_COMMAND, &tmpword); + tmpword = pci_read_config16(pci_dev, PCI_COMMAND); if (!(tmpword & PCI_COMMAND_IO)) { debug("%s: device IO not enabled\n", __func__); return -ENODEV; }

/* Header Type must be normal (bits 6-0 only; see spec.) */ - pci_read_config_byte(pci_dev, PCI_HEADER_TYPE, &tmpbyte); + tmpbyte = pci_read_config8(pci_dev, PCI_HEADER_TYPE); if ((tmpbyte & 0x7f) != PCI_HEADER_TYPE_NORMAL) { debug("%s: invalid Header type\n", __func__); return -ENODEV; }

/* Base Class must be a bridge device */ - pci_read_config_byte(pci_dev, PCI_CLASS_CODE, &tmpbyte); + tmpbyte = pci_read_config8(pci_dev, PCI_CLASS_CODE); if (tmpbyte != PCI_CLASS_CODE_BRIDGE) { debug("%s: invalid class\n", __func__); return -ENODEV; } /* Sub Class must be ISA */ - pci_read_config_byte(pci_dev, PCI_CLASS_SUB_CODE, &tmpbyte); + tmpbyte = pci_read_config8(pci_dev, PCI_CLASS_SUB_CODE); if (tmpbyte != PCI_CLASS_SUB_CODE_BRIDGE_ISA) { debug("%s: invalid subclass\n", __func__); return -ENODEV; }

/* Programming Interface must be 0x00 (no others exist) */ - pci_read_config_byte(pci_dev, PCI_CLASS_PROG, &tmpbyte); + tmpbyte = pci_read_config8(pci_dev, PCI_CLASS_PROG); if (tmpbyte != 0x00) { debug("%s: invalid interface type\n", __func__); return -ENODEV; @@ -114,7 +166,7 @@ static int gpio_ich6_ofdata_to_platdata(struct udevice *dev) * that it was unused (or undocumented). Check that it looks * okay: not all ones or zeros, and mapped to I/O space (bit 0). */ - pci_read_config_dword(pci_dev, PCI_CFG_GPIOBASE, &tmplong); + tmplong = pci_read_config32(pci_dev, PCI_CFG_GPIOBASE); if (tmplong == 0x00000000 || tmplong == 0xffffffff || !(tmplong & 0x00000001)) { debug("%s: unexpected GPIOBASE value\n", __func__); @@ -140,12 +192,18 @@ static int gpio_ich6_ofdata_to_platdata(struct udevice *dev) return 0; }

-int ich6_gpio_probe(struct udevice *dev) +static int ich6_gpio_probe(struct udevice *dev) { struct ich6_bank_platdata *plat = dev_get_platdata(dev); struct gpio_dev_priv *uc_priv = dev->uclass_priv; struct ich6_bank_priv *bank = dev_get_priv(dev);

+#ifdef SUPPORT_GPIO_SETUP + if (gd->arch.gpio_map) { + setup_pch_gpios(gd->arch.gpio_map); + gd->arch.gpio_map = NULL; + } +#endif uc_priv->gpio_count = GPIO_PER_BANK; uc_priv->bank_name = plat->bank_name; bank->use_sel = plat->base_addr; @@ -155,7 +213,8 @@ int ich6_gpio_probe(struct udevice *dev) return 0; }

-int ich6_gpio_request(struct udevice *dev, unsigned offset, const char *label) +static int ich6_gpio_request(struct udevice *dev, unsigned offset, + const char *label) { struct ich6_bank_priv *bank = dev_get_priv(dev); u32 tmplong;

This function can probably be used on all x86 boards, so move it into the common file.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v2: None

arch/x86/cpu/coreboot/coreboot.c | 24 ------------------------ arch/x86/cpu/cpu.c | 24 ++++++++++++++++++++++++ 2 files changed, 24 insertions(+), 24 deletions(-)

diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c index d615e87..d8ce768 100644 --- a/arch/x86/cpu/coreboot/coreboot.c +++ b/arch/x86/cpu/coreboot/coreboot.c @@ -15,7 +15,6 @@ #include <asm/cache.h> #include <asm/cpu.h> #include <asm/io.h> -#include <asm/post.h> #include <asm/arch/tables.h> #include <asm/arch/sysinfo.h> #include <asm/arch/timestamp.h> @@ -51,29 +50,6 @@ int board_early_init_r(void) return 0; }

-void show_boot_progress(int val) -{ -#if MIN_PORT80_KCLOCKS_DELAY - /* - * Scale the time counter reading to avoid using 64 bit arithmetics. - * Can't use get_timer() here becuase it could be not yet - * initialized or even implemented. - */ - if (!gd->arch.tsc_prev) { - gd->arch.tsc_base_kclocks = rdtsc() / 1000; - gd->arch.tsc_prev = 0; - } else { - uint32_t now; - - do { - now = rdtsc() / 1000 - gd->arch.tsc_base_kclocks; - } while (now < (gd->arch.tsc_prev + MIN_PORT80_KCLOCKS_DELAY)); - gd->arch.tsc_prev = now; - } -#endif - outb(val, POST_PORT); -} - int last_stage_init(void) { if (gd->flags & GD_FLG_COLD_BOOT) diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c index 0d75941..ae9f2b2 100644 --- a/arch/x86/cpu/cpu.c +++ b/arch/x86/cpu/cpu.c @@ -25,6 +25,7 @@ #include <malloc.h> #include <asm/control_regs.h> #include <asm/cpu.h> +#include <asm/post.h> #include <asm/processor.h> #include <asm/processor-flags.h> #include <asm/interrupt.h> @@ -566,3 +567,26 @@ int cpu_jump_to_64bit(ulong setup_base, ulong target)

return -EFAULT; } + +void show_boot_progress(int val) +{ +#if MIN_PORT80_KCLOCKS_DELAY + /* + * Scale the time counter reading to avoid using 64 bit arithmetics. + * Can't use get_timer() here becuase it could be not yet + * initialized or even implemented. + */ + if (!gd->arch.tsc_prev) { + gd->arch.tsc_base_kclocks = rdtsc() / 1000; + gd->arch.tsc_prev = 0; + } else { + uint32_t now; + + do { + now = rdtsc() / 1000 - gd->arch.tsc_base_kclocks; + } while (now < (gd->arch.tsc_prev + MIN_PORT80_KCLOCKS_DELAY)); + gd->arch.tsc_prev = now; + } +#endif + outb(val, POST_PORT); +}

Implement SDRAM init using the Memory Reference Code (mrc.bin) provided in the board directory and the SDRAM SPD information in the device tree. This also needs the Intel Management Engine (me.bin) to work. Binary blobs everywhere: so far we have MRC, ME and microcode.

SDRAM init works by setting up various parameters and calling the MRC. This in turn does some sort of magic to work out how much memory there is and the timing parameters to use. It also sets up the DRAM controllers. When the MRC returns, we use the information it provides to map out the available memory in U-Boot.

U-Boot normally moves itself to the top of RAM. On x86 the RAM is not generally contiguous, and anyway some RAM may be above 4GB which doesn't work in 32-bit mode. So we relocate to the top of the largest block of RAM we can find below 4GB. Memory above 4GB is accessible with special functions (see physmem).

It would be possible to build U-Boot in 64-bit mode but this wouldn't necessarily provide any more memory, since the largest block is often below 4GB. Anyway U-Boot doesn't need huge amounts of memory - even a very large ramdisk seldom exceeds 100-200MB. U-Boot has support for booting 64-bit kernels directly so this does not pose a limitation in that area. Also there are probably parts of U-Boot that will not work correctly in 64-bit mode. The MRC is one.

There is some work remaining in this area. Since memory init is very slow (over 500ms) it is possible to save the parameters in SPI flash to speed it up next time. Suspend/resume support is not fully implemented, or at least it is not efficient.

With this patch, link boots to a prompt.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v2: - Add mrc.bin dependency for u-boot.rom build rule - Adjust to use asm/cpu.h header for cpuid - Drop patch to move coreboot PCI into common cpu area - Drop patch which removes the early_board_init() feature - Fix incorrect subl mnemonic in start.S - Remove use of PCI_CPU_DEVICE and use PCH_DEV instead

Makefile | 9 +- arch/x86/Kconfig | 11 + arch/x86/cpu/ivybridge/Makefile | 3 + arch/x86/cpu/ivybridge/early_me.c | 191 ++++++++ arch/x86/cpu/ivybridge/me_status.c | 195 ++++++++ arch/x86/cpu/ivybridge/report_platform.c | 98 ++++ arch/x86/cpu/ivybridge/sdram.c | 553 +++++++++++++++++++++- arch/x86/cpu/start.S | 10 +- arch/x86/dts/link.dts | 111 +++++ arch/x86/include/asm/arch-ivybridge/me.h | 356 ++++++++++++++ arch/x86/include/asm/arch-ivybridge/pch.h | 113 +++++ arch/x86/include/asm/arch-ivybridge/pei_data.h | 121 +++++ arch/x86/include/asm/arch-ivybridge/sandybridge.h | 2 + arch/x86/include/asm/config.h | 1 + arch/x86/include/asm/global_data.h | 13 + arch/x86/include/asm/post.h | 5 + arch/x86/include/asm/u-boot-x86.h | 2 + arch/x86/lib/Makefile | 1 + arch/x86/lib/ramtest.c | 79 ++++ include/configs/chromebook_link.h | 4 + include/configs/x86-common.h | 2 +- include/fdtdec.h | 1 + lib/fdtdec.c | 1 + 23 files changed, 1875 insertions(+), 7 deletions(-) create mode 100644 arch/x86/cpu/ivybridge/early_me.c create mode 100644 arch/x86/cpu/ivybridge/me_status.c create mode 100644 arch/x86/cpu/ivybridge/report_platform.c create mode 100644 arch/x86/include/asm/arch-ivybridge/me.h create mode 100644 arch/x86/include/asm/arch-ivybridge/pei_data.h create mode 100644 arch/x86/lib/ramtest.c

diff --git a/Makefile b/Makefile index 86d0510..7406451 100644 --- a/Makefile +++ b/Makefile @@ -953,12 +953,19 @@ ifneq ($(CONFIG_X86_RESET_VECTOR),) rom: u-boot.rom FORCE

u-boot.rom: u-boot-x86-16bit.bin u-boot-dtb.bin \ - $(srctree)/board/$(BOARDDIR)/descriptor.bin + $(srctree)/board/$(BOARDDIR)/mrc.bin \ + $(srctree)/board/$(BOARDDIR)/descriptor.bin \ + $(srctree)/board/$(BOARDDIR)/me.bin $(objtree)/tools/ifdtool -c -r $(CONFIG_ROM_SIZE) \ -D $(srctree)/board/$(BOARDDIR)/descriptor.bin u-boot.tmp + $(objtree)/tools/ifdtool \ + -i ME:$(srctree)/board/$(BOARDDIR)/me.bin u-boot.tmp $(objtree)/tools/ifdtool -w \ $(CONFIG_SYS_TEXT_BASE):$(objtree)/u-boot-dtb.bin u-boot.tmp $(objtree)/tools/ifdtool -w \ + $(CONFIG_X86_MRC_START):$(srctree)/board/$(BOARDDIR)/mrc.bin \ + u-boot.tmp + $(objtree)/tools/ifdtool -w \ $(CONFIG_SYS_X86_START16):$(objtree)/u-boot-x86-16bit.bin \ u-boot.tmp mv u-boot.tmp $@ diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 995ffa6..46e316f 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -50,6 +50,17 @@ config CPU_ADDR_BITS int default 36

+config HPET_ADDRESS + hex + default 0xfed00000 if !HPET_ADDRESS_OVERRIDE + +config SMM_TSEG + bool + default n + +config SMM_TSEG_SIZE + hex + config ROM_SIZE hex default 0x800000 diff --git a/arch/x86/cpu/ivybridge/Makefile b/arch/x86/cpu/ivybridge/Makefile index e5c0751..721b37e 100644 --- a/arch/x86/cpu/ivybridge/Makefile +++ b/arch/x86/cpu/ivybridge/Makefile @@ -7,7 +7,10 @@ obj-y += car.o obj-y += cpu.o obj-y += early_init.o +obj-y += early_me.o obj-y += lpc.o +obj-y += me_status.o obj-y += microcode_intel.o obj-y += pci.o +obj-y += report_platform.o obj-y += sdram.o diff --git a/arch/x86/cpu/ivybridge/early_me.c b/arch/x86/cpu/ivybridge/early_me.c new file mode 100644 index 0000000..b24dea1 --- /dev/null +++ b/arch/x86/cpu/ivybridge/early_me.c @@ -0,0 +1,191 @@ +/* + * From Coreboot src/southbridge/intel/bd82x6x/early_me.c + * + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <errno.h> +#include <asm/pci.h> +#include <asm/processor.h> +#include <asm/arch/me.h> +#include <asm/arch/pch.h> +#include <asm/io.h> + +static const char *const me_ack_values[] = { + [ME_HFS_ACK_NO_DID] = "No DID Ack received", + [ME_HFS_ACK_RESET] = "Non-power cycle reset", + [ME_HFS_ACK_PWR_CYCLE] = "Power cycle reset", + [ME_HFS_ACK_S3] = "Go to S3", + [ME_HFS_ACK_S4] = "Go to S4", + [ME_HFS_ACK_S5] = "Go to S5", + [ME_HFS_ACK_GBL_RESET] = "Global Reset", + [ME_HFS_ACK_CONTINUE] = "Continue to boot" +}; + +static inline void pci_read_dword_ptr(void *ptr, int offset) +{ + u32 dword; + + dword = pci_read_config32(PCH_ME_DEV, offset); + memcpy(ptr, &dword, sizeof(dword)); +} + +static inline void pci_write_dword_ptr(void *ptr, int offset) +{ + u32 dword = 0; + memcpy(&dword, ptr, sizeof(dword)); + pci_write_config32(PCH_ME_DEV, offset, dword); +} + +void intel_early_me_status(void) +{ + struct me_hfs hfs; + struct me_gmes gmes; + + pci_read_dword_ptr(&hfs, PCI_ME_HFS); + pci_read_dword_ptr(&gmes, PCI_ME_GMES); + + intel_me_status(&hfs, &gmes); +} + +int intel_early_me_init(void) +{ + int count; + struct me_uma uma; + struct me_hfs hfs; + + debug("Intel ME early init\n"); + + /* Wait for ME UMA SIZE VALID bit to be set */ + for (count = ME_RETRY; count > 0; --count) { + pci_read_dword_ptr(&uma, PCI_ME_UMA); + if (uma.valid) + break; + udelay(ME_DELAY); + } + if (!count) { + printf("ERROR: ME is not ready!\n"); + return -EBUSY; + } + + /* Check for valid firmware */ + pci_read_dword_ptr(&hfs, PCI_ME_HFS); + if (hfs.fpt_bad) { + printf("WARNING: ME has bad firmware\n"); + return -EBADF; + } + + debug("Intel ME firmware is ready\n"); + + return 0; +} + +int intel_early_me_uma_size(void) +{ + struct me_uma uma; + + pci_read_dword_ptr(&uma, PCI_ME_UMA); + if (uma.valid) { + debug("ME: Requested %uMB UMA\n", uma.size); + return uma.size; + } + + debug("ME: Invalid UMA size\n"); + return -EINVAL; +} + +static inline void set_global_reset(int enable) +{ + u32 etr3; + + etr3 = pci_read_config32(PCH_LPC_DEV, ETR3); + + /* Clear CF9 Without Resume Well Reset Enable */ + etr3 &= ~ETR3_CWORWRE; + + /* CF9GR indicates a Global Reset */ + if (enable) + etr3 |= ETR3_CF9GR; + else + etr3 &= ~ETR3_CF9GR; + + pci_write_config32(PCH_LPC_DEV, ETR3, etr3); +} + +int intel_early_me_init_done(u8 status) +{ + u8 reset; + int count; + u32 mebase_l, mebase_h; + struct me_hfs hfs; + struct me_did did = { + .init_done = ME_INIT_DONE, + .status = status + }; + + /* MEBASE from MESEG_BASE[35:20] */ + mebase_l = pci_read_config32(PCH_DEV, PCI_CPU_MEBASE_L); + mebase_h = pci_read_config32(PCH_DEV, PCI_CPU_MEBASE_H); + mebase_h &= 0xf; + did.uma_base = (mebase_l >> 20) | (mebase_h << 12); + + /* Send message to ME */ + debug("ME: Sending Init Done with status: %d, UMA base: 0x%04x\n", + status, did.uma_base); + + pci_write_dword_ptr(&did, PCI_ME_H_GS); + + /* Must wait for ME acknowledgement */ + for (count = ME_RETRY; count > 0; --count) { + pci_read_dword_ptr(&hfs, PCI_ME_HFS); + if (hfs.bios_msg_ack) + break; + udelay(ME_DELAY); + } + if (!count) { + printf("ERROR: ME failed to respond\n"); + return -1; + } + + /* Return the requested BIOS action */ + debug("ME: Requested BIOS Action: %s\n", me_ack_values[hfs.ack_data]); + + /* Check status after acknowledgement */ + intel_early_me_status(); + + reset = 0; + switch (hfs.ack_data) { + case ME_HFS_ACK_CONTINUE: + /* Continue to boot */ + return 0; + case ME_HFS_ACK_RESET: + /* Non-power cycle reset */ + set_global_reset(0); + reset = 0x06; + break; + case ME_HFS_ACK_PWR_CYCLE: + /* Power cycle reset */ + set_global_reset(0); + reset = 0x0e; + break; + case ME_HFS_ACK_GBL_RESET: + /* Global reset */ + set_global_reset(1); + reset = 0x0e; + break; + case ME_HFS_ACK_S3: + case ME_HFS_ACK_S4: + case ME_HFS_ACK_S5: + break; + } + + /* Perform the requested reset */ + if (reset) { + outb(reset, 0xcf9); + cpu_hlt(); + } + return -1; +} diff --git a/arch/x86/cpu/ivybridge/me_status.c b/arch/x86/cpu/ivybridge/me_status.c new file mode 100644 index 0000000..15cf69f --- /dev/null +++ b/arch/x86/cpu/ivybridge/me_status.c @@ -0,0 +1,195 @@ +/* + * From Coreboot src/southbridge/intel/bd82x6x/me_status.c + * + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <asm/arch/me.h> + +/* HFS1[3:0] Current Working State Values */ +static const char *const me_cws_values[] = { + [ME_HFS_CWS_RESET] = "Reset", + [ME_HFS_CWS_INIT] = "Initializing", + [ME_HFS_CWS_REC] = "Recovery", + [ME_HFS_CWS_NORMAL] = "Normal", + [ME_HFS_CWS_WAIT] = "Platform Disable Wait", + [ME_HFS_CWS_TRANS] = "OP State Transition", + [ME_HFS_CWS_INVALID] = "Invalid CPU Plugged In" +}; + +/* HFS1[8:6] Current Operation State Values */ +static const char *const me_opstate_values[] = { + [ME_HFS_STATE_PREBOOT] = "Preboot", + [ME_HFS_STATE_M0_UMA] = "M0 with UMA", + [ME_HFS_STATE_M3] = "M3 without UMA", + [ME_HFS_STATE_M0] = "M0 without UMA", + [ME_HFS_STATE_BRINGUP] = "Bring up", + [ME_HFS_STATE_ERROR] = "M0 without UMA but with error" +}; + +/* HFS[19:16] Current Operation Mode Values */ +static const char *const me_opmode_values[] = { + [ME_HFS_MODE_NORMAL] = "Normal", + [ME_HFS_MODE_DEBUG] = "Debug", + [ME_HFS_MODE_DIS] = "Soft Temporary Disable", + [ME_HFS_MODE_OVER_JMPR] = "Security Override via Jumper", + [ME_HFS_MODE_OVER_MEI] = "Security Override via MEI Message" +}; + +/* HFS[15:12] Error Code Values */ +static const char *const me_error_values[] = { + [ME_HFS_ERROR_NONE] = "No Error", + [ME_HFS_ERROR_UNCAT] = "Uncategorized Failure", + [ME_HFS_ERROR_IMAGE] = "Image Failure", + [ME_HFS_ERROR_DEBUG] = "Debug Failure" +}; + +/* GMES[31:28] ME Progress Code */ +static const char *const me_progress_values[] = { + [ME_GMES_PHASE_ROM] = "ROM Phase", + [ME_GMES_PHASE_BUP] = "BUP Phase", + [ME_GMES_PHASE_UKERNEL] = "uKernel Phase", + [ME_GMES_PHASE_POLICY] = "Policy Module", + [ME_GMES_PHASE_MODULE] = "Module Loading", + [ME_GMES_PHASE_UNKNOWN] = "Unknown", + [ME_GMES_PHASE_HOST] = "Host Communication" +}; + +/* GMES[27:24] Power Management Event */ +static const char *const me_pmevent_values[] = { + [0x00] = "Clean Moff->Mx wake", + [0x01] = "Moff->Mx wake after an error", + [0x02] = "Clean global reset", + [0x03] = "Global reset after an error", + [0x04] = "Clean Intel ME reset", + [0x05] = "Intel ME reset due to exception", + [0x06] = "Pseudo-global reset", + [0x07] = "S0/M0->Sx/M3", + [0x08] = "Sx/M3->S0/M0", + [0x09] = "Non-power cycle reset", + [0x0a] = "Power cycle reset through M3", + [0x0b] = "Power cycle reset through Moff", + [0x0c] = "Sx/Mx->Sx/Moff" +}; + +/* Progress Code 0 states */ +static const char *const me_progress_rom_values[] = { + [0x00] = "BEGIN", + [0x06] = "DISABLE" +}; + +/* Progress Code 1 states */ +static const char *const me_progress_bup_values[] = { + [0x00] = "Initialization starts", + [0x01] = "Disable the host wake event", + [0x04] = "Flow determination start process", + [0x08] = "Error reading/matching the VSCC table in the descriptor", + [0x0a] = "Check to see if straps say ME DISABLED", + [0x0b] = "Timeout waiting for PWROK", + [0x0d] = "Possibly handle BUP manufacturing override strap", + [0x11] = "Bringup in M3", + [0x12] = "Bringup in M0", + [0x13] = "Flow detection error", + [0x15] = "M3 clock switching error", + [0x18] = "M3 kernel load", + [0x1c] = "T34 missing - cannot program ICC", + [0x1f] = "Waiting for DID BIOS message", + [0x20] = "Waiting for DID BIOS message failure", + [0x21] = "DID reported an error", + [0x22] = "Enabling UMA", + [0x23] = "Enabling UMA error", + [0x24] = "Sending DID Ack to BIOS", + [0x25] = "Sending DID Ack to BIOS error", + [0x26] = "Switching clocks in M0", + [0x27] = "Switching clocks in M0 error", + [0x28] = "ME in temp disable", + [0x32] = "M0 kernel load", +}; + +/* Progress Code 3 states */ +static const char *const me_progress_policy_values[] = { + [0x00] = "Entery into Policy Module", + [0x03] = "Received S3 entry", + [0x04] = "Received S4 entry", + [0x05] = "Received S5 entry", + [0x06] = "Received UPD entry", + [0x07] = "Received PCR entry", + [0x08] = "Received NPCR entry", + [0x09] = "Received host wake", + [0x0a] = "Received AC<>DC switch", + [0x0b] = "Received DRAM Init Done", + [0x0c] = "VSCC Data not found for flash device", + [0x0d] = "VSCC Table is not valid", + [0x0e] = "Flash Partition Boundary is outside address space", + [0x0f] = "ME cannot access the chipset descriptor region", + [0x10] = "Required VSCC values for flash parts do not match", +}; + +void intel_me_status(struct me_hfs *hfs, struct me_gmes *gmes) +{ + /* Check Current States */ + debug("ME: FW Partition Table : %s\n", + hfs->fpt_bad ? "BAD" : "OK"); + debug("ME: Bringup Loader Failure : %s\n", + hfs->ft_bup_ld_flr ? "YES" : "NO"); + debug("ME: Firmware Init Complete : %s\n", + hfs->fw_init_complete ? "YES" : "NO"); + debug("ME: Manufacturing Mode : %s\n", + hfs->mfg_mode ? "YES" : "NO"); + debug("ME: Boot Options Present : %s\n", + hfs->boot_options_present ? "YES" : "NO"); + debug("ME: Update In Progress : %s\n", + hfs->update_in_progress ? "YES" : "NO"); + debug("ME: Current Working State : %s\n", + me_cws_values[hfs->working_state]); + debug("ME: Current Operation State : %s\n", + me_opstate_values[hfs->operation_state]); + debug("ME: Current Operation Mode : %s\n", + me_opmode_values[hfs->operation_mode]); + debug("ME: Error Code : %s\n", + me_error_values[hfs->error_code]); + debug("ME: Progress Phase : %s\n", + me_progress_values[gmes->progress_code]); + debug("ME: Power Management Event : %s\n", + me_pmevent_values[gmes->current_pmevent]); + + debug("ME: Progress Phase State : "); + switch (gmes->progress_code) { + case ME_GMES_PHASE_ROM: /* ROM Phase */ + debug("%s", me_progress_rom_values[gmes->current_state]); + break; + + case ME_GMES_PHASE_BUP: /* Bringup Phase */ + if (gmes->current_state < ARRAY_SIZE(me_progress_bup_values) && + me_progress_bup_values[gmes->current_state]) + debug("%s", + me_progress_bup_values[gmes->current_state]); + else + debug("0x%02x", gmes->current_state); + break; + + case ME_GMES_PHASE_POLICY: /* Policy Module Phase */ + if (gmes->current_state < + ARRAY_SIZE(me_progress_policy_values) && + me_progress_policy_values[gmes->current_state]) + debug("%s", + me_progress_policy_values[gmes->current_state]); + else + debug("0x%02x", gmes->current_state); + break; + + case ME_GMES_PHASE_HOST: /* Host Communication Phase */ + if (!gmes->current_state) + debug("Host communication established"); + else + debug("0x%02x", gmes->current_state); + break; + + default: + debug("Unknown 0x%02x", gmes->current_state); + } + debug("\n"); +} diff --git a/arch/x86/cpu/ivybridge/report_platform.c b/arch/x86/cpu/ivybridge/report_platform.c new file mode 100644 index 0000000..503a12f --- /dev/null +++ b/arch/x86/cpu/ivybridge/report_platform.c @@ -0,0 +1,98 @@ +/* + * From Coreboot src/northbridge/intel/sandybridge/report_platform.c + * + * Copyright (C) 2012 Google Inc. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <asm/cpu.h> +#include <asm/pci.h> +#include <asm/arch/pch.h> + +static void report_cpu_info(void) +{ + struct cpuid_result cpuidr; + u32 i, index; + char cpu_string[50], *cpu_name = cpu_string; /* 48 bytes are reported */ + int vt, txt, aes; + const char *mode[] = {"NOT ", ""}; + + index = 0x80000000; + cpuidr = cpuid(index); + if (cpuidr.eax < 0x80000004) { + strcpy(cpu_string, "Platform info not available"); + } else { + u32 *p = (u32 *)cpu_string; + for (i = 2; i <= 4 ; i++) { + cpuidr = cpuid(index + i); + *p++ = cpuidr.eax; + *p++ = cpuidr.ebx; + *p++ = cpuidr.ecx; + *p++ = cpuidr.edx; + } + } + /* Skip leading spaces in CPU name string */ + while (cpu_name[0] == ' ') + cpu_name++; + + cpuidr = cpuid(1); + debug("CPU id(%x): %s\n", cpuidr.eax, cpu_name); + aes = (cpuidr.ecx & (1 << 25)) ? 1 : 0; + txt = (cpuidr.ecx & (1 << 6)) ? 1 : 0; + vt = (cpuidr.ecx & (1 << 5)) ? 1 : 0; + debug("AES %ssupported, TXT %ssupported, VT %ssupported\n", + mode[aes], mode[txt], mode[vt]); +} + +/* The PCI id name match comes from Intel document 472178 */ +static struct { + u16 dev_id; + const char *dev_name; +} pch_table[] = { + {0x1E41, "Desktop Sample"}, + {0x1E42, "Mobile Sample"}, + {0x1E43, "SFF Sample"}, + {0x1E44, "Z77"}, + {0x1E45, "H71"}, + {0x1E46, "Z75"}, + {0x1E47, "Q77"}, + {0x1E48, "Q75"}, + {0x1E49, "B75"}, + {0x1E4A, "H77"}, + {0x1E53, "C216"}, + {0x1E55, "QM77"}, + {0x1E56, "QS77"}, + {0x1E58, "UM77"}, + {0x1E57, "HM77"}, + {0x1E59, "HM76"}, + {0x1E5D, "HM75"}, + {0x1E5E, "HM70"}, + {0x1E5F, "NM70"}, +}; + +static void report_pch_info(void) +{ + const char *pch_type = "Unknown"; + int i; + u16 dev_id; + uint8_t rev_id; + + dev_id = pci_read_config16(PCH_LPC_DEV, 2); + for (i = 0; i < ARRAY_SIZE(pch_table); i++) { + if (pch_table[i].dev_id == dev_id) { + pch_type = pch_table[i].dev_name; + break; + } + } + rev_id = pci_read_config8(PCH_LPC_DEV, 8); + debug("PCH type: %s, device id: %x, rev id %x\n", pch_type, dev_id, + rev_id); +} + +void report_platform_info(void) +{ + report_cpu_info(); + report_pch_info(); +} diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c index 5f9ae5e..df2b990 100644 --- a/arch/x86/cpu/ivybridge/sdram.c +++ b/arch/x86/cpu/ivybridge/sdram.c @@ -11,10 +11,561 @@ */

#include <common.h> +#include <errno.h> +#include <fdtdec.h> +#include <malloc.h> +#include <asm/processor.h> +#include <asm/gpio.h> +#include <asm/global_data.h> +#include <asm/pci.h> +#include <asm/arch/me.h> +#include <asm/arch/pei_data.h> +#include <asm/arch/pch.h> +#include <asm/post.h> +#include <asm/arch/sandybridge.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* + * This function looks for the highest region of memory lower than 4GB which + * has enough space for U-Boot where U-Boot is aligned on a page boundary. + * It overrides the default implementation found elsewhere which simply + * picks the end of ram, wherever that may be. The location of the stack, + * the relocation address, and how far U-Boot is moved by relocation are + * set in the global data structure. + */ +ulong board_get_usable_ram_top(ulong total_size) +{ + struct memory_info *info = &gd->arch.meminfo; + uintptr_t dest_addr = 0; + struct memory_area *largest = NULL; + int i; + + /* Find largest area of memory below 4GB */ + + for (i = 0; i < info->num_areas; i++) { + struct memory_area *area = &info->area[i]; + + if (area->start >= 1ULL << 32) + continue; + if (!largest || area->size > largest->size) + largest = area; + } + + /* If no suitable area was found, return an error. */ + assert(largest); + if (!largest || largest->size < (2 << 20)) + panic("No available memory found for relocation"); + + dest_addr = largest->start + largest->size; + + return (ulong)dest_addr; +} + +void dram_init_banksize(void) +{ + struct memory_info *info = &gd->arch.meminfo; + int num_banks; + int i; + + for (i = 0, num_banks = 0; i < info->num_areas; i++) { + struct memory_area *area = &info->area[i]; + + if (area->start >= 1ULL << 32) + continue; + gd->bd->bi_dram[num_banks].start = area->start; + gd->bd->bi_dram[num_banks].size = area->size; + num_banks++; + } +} + +static const char *const ecc_decoder[] = { + "inactive", + "active on IO", + "disabled on IO", + "active" +}; + +/* + * Dump in the log memory controller configuration as read from the memory + * controller registers. + */ +static void report_memory_config(void) +{ + u32 addr_decoder_common, addr_decode_ch[2]; + int i; + + addr_decoder_common = readl(MCHBAR_REG(0x5000)); + addr_decode_ch[0] = readl(MCHBAR_REG(0x5004)); + addr_decode_ch[1] = readl(MCHBAR_REG(0x5008)); + + debug("memcfg DDR3 clock %d MHz\n", + (readl(MCHBAR_REG(0x5e04)) * 13333 * 2 + 50) / 100); + debug("memcfg channel assignment: A: %d, B % d, C % d\n", + addr_decoder_common & 3, + (addr_decoder_common >> 2) & 3, + (addr_decoder_common >> 4) & 3); + + for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) { + u32 ch_conf = addr_decode_ch[i]; + debug("memcfg channel[%d] config (%8.8x):\n", i, ch_conf); + debug(" ECC %s\n", ecc_decoder[(ch_conf >> 24) & 3]); + debug(" enhanced interleave mode %s\n", + ((ch_conf >> 22) & 1) ? "on" : "off"); + debug(" rank interleave %s\n", + ((ch_conf >> 21) & 1) ? "on" : "off"); + debug(" DIMMA %d MB width x%d %s rank%s\n", + ((ch_conf >> 0) & 0xff) * 256, + ((ch_conf >> 19) & 1) ? 16 : 8, + ((ch_conf >> 17) & 1) ? "dual" : "single", + ((ch_conf >> 16) & 1) ? "" : ", selected"); + debug(" DIMMB %d MB width x%d %s rank%s\n", + ((ch_conf >> 8) & 0xff) * 256, + ((ch_conf >> 20) & 1) ? 16 : 8, + ((ch_conf >> 18) & 1) ? "dual" : "single", + ((ch_conf >> 16) & 1) ? ", selected" : ""); + } +} + +static void post_system_agent_init(struct pei_data *pei_data) +{ + /* If PCIe init is skipped, set the PEG clock gating */ + if (!pei_data->pcie_init) + setbits_le32(MCHBAR_REG(0x7010), 1); +} + +static asmlinkage void console_tx_byte(unsigned char byte) +{ +#ifdef DEBUG + putc(byte); +#endif +} + +/** + * Find the PEI executable in the ROM and execute it. + * + * @param pei_data: configuration data for UEFI PEI reference code + */ +int sdram_initialise(struct pei_data *pei_data) +{ + unsigned version; + const char *data; + uint16_t done; + int ret; + + report_platform_info(); + + /* Wait for ME to be ready */ + ret = intel_early_me_init(); + if (ret) + return ret; + ret = intel_early_me_uma_size(); + if (ret < 0) + return ret; + + debug("Starting UEFI PEI System Agent\n"); + + /* If MRC data is not found we cannot continue S3 resume. */ + if (pei_data->boot_mode == PEI_BOOT_RESUME && !pei_data->mrc_input) { + debug("Giving up in sdram_initialize: No MRC data\n"); + outb(0x6, PORT_RESET); + cpu_hlt(); + } + + /* Pass console handler in pei_data */ + pei_data->tx_byte = console_tx_byte; + + debug("PEI data at %p, size %x:\n", pei_data, sizeof(*pei_data)); + + data = (char *)CONFIG_X86_MRC_START; + if (data) { + int rv; + int (*func)(struct pei_data *); + + debug("Calling MRC at %p\n", data); + post_code(POST_PRE_MRC); + func = (int (*)(struct pei_data *))data; + rv = func(pei_data); + post_code(POST_MRC); + if (rv) { + switch (rv) { + case -1: + printf("PEI version mismatch.\n"); + break; + case -2: + printf("Invalid memory frequency.\n"); + break; + default: + printf("MRC returned %x.\n", rv); + } + printf("Nonzero MRC return value.\n"); + return -EFAULT; + } + } else { + printf("UEFI PEI System Agent not found.\n"); + return -ENOSYS; + } + +#if CONFIG_USBDEBUG + /* mrc.bin reconfigures USB, so reinit it to have debug */ + early_usbdebug_init(); +#endif + + version = readl(MCHBAR_REG(0x5034)); + debug("System Agent Version %d.%d.%d Build %d\n", + version >> 24 , (version >> 16) & 0xff, + (version >> 8) & 0xff, version & 0xff); + + /* + * Send ME init done for SandyBridge here. This is done inside the + * SystemAgent binary on IvyBridge + */ + done = pci_read_config32(PCH_DEV, PCI_DEVICE_ID); + done &= BASE_REV_MASK; + if (BASE_REV_SNB == done) + intel_early_me_init_done(ME_INIT_STATUS_SUCCESS); + else + intel_early_me_status(); + + post_system_agent_init(pei_data); + report_memory_config(); + + return 0; +} + +static int copy_spd(struct pei_data *peid) +{ + const int gpio_vector[] = {41, 42, 43, 10, -1}; + int spd_index; + const void *blob = gd->fdt_blob; + int node, spd_node; + int ret, i; + + for (i = 0; ; i++) { + if (gpio_vector[i] == -1) + break; + ret = gpio_requestf(gpio_vector[i], "spd_id%d", i); + if (ret) { + debug("%s: Could not request gpio %d\n", __func__, + gpio_vector[i]); + return ret; + } + } + spd_index = gpio_get_values_as_int(gpio_vector); + debug("spd index %d\n", spd_index); + node = fdtdec_next_compatible(blob, 0, COMPAT_MEMORY_SPD); + if (node < 0) { + printf("SPD data not found.\n"); + return -ENOENT; + } + + for (spd_node = fdt_first_subnode(blob, node); + spd_node > 0; + spd_node = fdt_next_subnode(blob, spd_node)) { + const char *data; + int len; + + if (fdtdec_get_int(blob, spd_node, "reg", -1) != spd_index) + continue; + data = fdt_getprop(blob, spd_node, "data", &len); + if (len < sizeof(peid->spd_data[0])) { + printf("Missing SPD data\n"); + return -EINVAL; + } + + debug("Using SDRAM SPD data for '%s'\n", + fdt_get_name(blob, spd_node, NULL)); + memcpy(peid->spd_data[0], data, sizeof(peid->spd_data[0])); + break; + } + + if (spd_node < 0) { + printf("No SPD data found for index %d\n", spd_index); + return -ENOENT; + } + + return 0; +} + +/** + * add_memory_area() - Add a new usable memory area to our list + * + * Note: @start and @end must not span the first 4GB boundary + * + * @info: Place to store memory info + * @start: Start of this memory area + * @end: End of this memory area + 1 + */ +static int add_memory_area(struct memory_info *info, + uint64_t start, uint64_t end) +{ + struct memory_area *ptr; + + if (info->num_areas == CONFIG_NR_DRAM_BANKS) + return -ENOSPC; + + ptr = &info->area[info->num_areas]; + ptr->start = start; + ptr->size = end - start; + info->total_memory += ptr->size; + if (ptr->start < (1ULL << 32)) + info->total_32bit_memory += ptr->size; + debug("%d: memory %llx size %llx, total now %llx / %llx\n", + info->num_areas, ptr->start, ptr->size, + info->total_32bit_memory, info->total_memory); + info->num_areas++; + + return 0; +} + +/** + * sdram_find() - Find available memory + * + * This is a bit complicated since on x86 there are system memory holes all + * over the place. We create a list of available memory blocks + */ +static int sdram_find(pci_dev_t dev) +{ + struct memory_info *info = &gd->arch.meminfo; + uint32_t tseg_base, uma_size, tolud; + uint64_t tom, me_base, touud; + uint64_t uma_memory_base = 0; + uint64_t uma_memory_size; + unsigned long long tomk; + uint16_t ggc; + + /* Total Memory 2GB example: + * + * 00000000 0000MB-1992MB 1992MB RAM (writeback) + * 7c800000 1992MB-2000MB 8MB TSEG (SMRR) + * 7d000000 2000MB-2002MB 2MB GFX GTT (uncached) + * 7d200000 2002MB-2034MB 32MB GFX UMA (uncached) + * 7f200000 2034MB TOLUD + * 7f800000 2040MB MEBASE + * 7f800000 2040MB-2048MB 8MB ME UMA (uncached) + * 80000000 2048MB TOM + * 100000000 4096MB-4102MB 6MB RAM (writeback) + * + * Total Memory 4GB example: + * + * 00000000 0000MB-2768MB 2768MB RAM (writeback) + * ad000000 2768MB-2776MB 8MB TSEG (SMRR) + * ad800000 2776MB-2778MB 2MB GFX GTT (uncached) + * ada00000 2778MB-2810MB 32MB GFX UMA (uncached) + * afa00000 2810MB TOLUD + * ff800000 4088MB MEBASE + * ff800000 4088MB-4096MB 8MB ME UMA (uncached) + * 100000000 4096MB TOM + * 100000000 4096MB-5374MB 1278MB RAM (writeback) + * 14fe00000 5368MB TOUUD + */ + + /* Top of Upper Usable DRAM, including remap */ + touud = pci_read_config32(dev, TOUUD+4); + touud <<= 32; + touud |= pci_read_config32(dev, TOUUD); + + /* Top of Lower Usable DRAM */ + tolud = pci_read_config32(dev, TOLUD); + + /* Top of Memory - does not account for any UMA */ + tom = pci_read_config32(dev, 0xa4); + tom <<= 32; + tom |= pci_read_config32(dev, 0xa0); + + debug("TOUUD %llx TOLUD %08x TOM %llx\n", touud, tolud, tom); + + /* ME UMA needs excluding if total memory <4GB */ + me_base = pci_read_config32(dev, 0x74); + me_base <<= 32; + me_base |= pci_read_config32(dev, 0x70); + + debug("MEBASE %llx\n", me_base); + + /* TODO: Get rid of all this shifting by 10 bits */ + tomk = tolud >> 10; + if (me_base == tolud) { + /* ME is from MEBASE-TOM */ + uma_size = (tom - me_base) >> 10; + /* Increment TOLUD to account for ME as RAM */ + tolud += uma_size << 10; + /* UMA starts at old TOLUD */ + uma_memory_base = tomk * 1024ULL; + uma_memory_size = uma_size * 1024ULL; + debug("ME UMA base %llx size %uM\n", me_base, uma_size >> 10); + } + + /* Graphics memory comes next */ + ggc = pci_read_config16(dev, GGC); + if (!(ggc & 2)) { + debug("IGD decoded, subtracting "); + + /* Graphics memory */ + uma_size = ((ggc >> 3) & 0x1f) * 32 * 1024ULL; + debug("%uM UMA", uma_size >> 10); + tomk -= uma_size; + uma_memory_base = tomk * 1024ULL; + uma_memory_size += uma_size * 1024ULL; + + /* GTT Graphics Stolen Memory Size (GGMS) */ + uma_size = ((ggc >> 8) & 0x3) * 1024ULL; + tomk -= uma_size; + uma_memory_base = tomk * 1024ULL; + uma_memory_size += uma_size * 1024ULL; + debug(" and %uM GTT\n", uma_size >> 10); + } + + /* Calculate TSEG size from its base which must be below GTT */ + tseg_base = pci_read_config32(dev, 0xb8); + uma_size = (uma_memory_base - tseg_base) >> 10; + tomk -= uma_size; + uma_memory_base = tomk * 1024ULL; + uma_memory_size += uma_size * 1024ULL; + debug("TSEG base 0x%08x size %uM\n", tseg_base, uma_size >> 10); + + debug("Available memory below 4GB: %lluM\n", tomk >> 10); + + /* Report the memory regions */ + add_memory_area(info, 1 << 20, 2 << 28); + add_memory_area(info, (2 << 28) + (2 << 20), 4 << 28); + add_memory_area(info, (4 << 28) + (2 << 20), tseg_base); + add_memory_area(info, 1ULL << 32, touud); + /* + * If >= 4GB installed then memory from TOLUD to 4GB + * is remapped above TOM, TOUUD will account for both + */ + if (touud > (1ULL << 32ULL)) { + debug("Available memory above 4GB: %lluM\n", + (touud >> 20) - 4096); + } + + return 0; +} + +static void rcba_config(void) +{ + /* + * GFX INTA -> PIRQA (MSI) + * D28IP_P3IP WLAN INTA -> PIRQB + * D29IP_E1P EHCI1 INTA -> PIRQD + * D26IP_E2P EHCI2 INTA -> PIRQF + * D31IP_SIP SATA INTA -> PIRQF (MSI) + * D31IP_SMIP SMBUS INTB -> PIRQH + * D31IP_TTIP THRT INTC -> PIRQA + * D27IP_ZIP HDA INTA -> PIRQA (MSI) + * + * TRACKPAD -> PIRQE (Edge Triggered) + * TOUCHSCREEN -> PIRQG (Edge Triggered) + */ + + /* Device interrupt pin register (board specific) */ + writel((INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | + (INTB << D31IP_SMIP) | (INTA << D31IP_SIP), RCB_REG(D31IP)); + writel(NOINT << D30IP_PIP, RCB_REG(D30IP)); + writel(INTA << D29IP_E1P, RCB_REG(D29IP)); + writel(INTA << D28IP_P3IP, RCB_REG(D28IP)); + writel(INTA << D27IP_ZIP, RCB_REG(D27IP)); + writel(INTA << D26IP_E2P, RCB_REG(D26IP)); + writel(NOINT << D25IP_LIP, RCB_REG(D25IP)); + writel(NOINT << D22IP_MEI1IP, RCB_REG(D22IP)); + + /* Device interrupt route registers */ + writel(DIR_ROUTE(PIRQB, PIRQH, PIRQA, PIRQC), RCB_REG(D31IR)); + writel(DIR_ROUTE(PIRQD, PIRQE, PIRQF, PIRQG), RCB_REG(D29IR)); + writel(DIR_ROUTE(PIRQB, PIRQC, PIRQD, PIRQE), RCB_REG(D28IR)); + writel(DIR_ROUTE(PIRQA, PIRQH, PIRQA, PIRQB), RCB_REG(D27IR)); + writel(DIR_ROUTE(PIRQF, PIRQE, PIRQG, PIRQH), RCB_REG(D26IR)); + writel(DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD), RCB_REG(D25IR)); + writel(DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD), RCB_REG(D22IR)); + + /* Enable IOAPIC (generic) */ + writew(0x0100, RCB_REG(OIC)); + /* PCH BWG says to read back the IOAPIC enable register */ + (void)readw(RCB_REG(OIC)); + + /* Disable unused devices (board specific) */ + setbits_le32(RCB_REG(FD), PCH_DISABLE_ALWAYS); +}

int dram_init(void) { - /* TODO: Set up DRAM */ + struct pei_data pei_data __aligned(8) = { + .pei_version = PEI_VERSION, + .mchbar = DEFAULT_MCHBAR, + .dmibar = DEFAULT_DMIBAR, + .epbar = DEFAULT_EPBAR, + .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, + .smbusbar = SMBUS_IO_BASE, + .wdbbar = 0x4000000, + .wdbsize = 0x1000, + .hpet_address = CONFIG_HPET_ADDRESS, + .rcba = DEFAULT_RCBABASE, + .pmbase = DEFAULT_PMBASE, + .gpiobase = DEFAULT_GPIOBASE, + .thermalbase = 0xfed08000, + .system_type = 0, /* 0 Mobile, 1 Desktop/Server */ + .tseg_size = CONFIG_SMM_TSEG_SIZE, + .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, + .ec_present = 1, + .ddr3lv_support = 1, + /* + * 0 = leave channel enabled + * 1 = disable dimm 0 on channel + * 2 = disable dimm 1 on channel + * 3 = disable dimm 0+1 on channel + */ + .dimm_channel0_disabled = 2, + .dimm_channel1_disabled = 2, + .max_ddr3_freq = 1600, + .usb_port_config = { + /* + * Empty and onboard Ports 0-7, set to un-used pin + * OC3 + */ + { 0, 3, 0x0000 }, /* P0= Empty */ + { 1, 0, 0x0040 }, /* P1= Left USB 1 (OC0) */ + { 1, 1, 0x0040 }, /* P2= Left USB 2 (OC1) */ + { 1, 3, 0x0040 }, /* P3= SDCARD (no OC) */ + { 0, 3, 0x0000 }, /* P4= Empty */ + { 1, 3, 0x0040 }, /* P5= WWAN (no OC) */ + { 0, 3, 0x0000 }, /* P6= Empty */ + { 0, 3, 0x0000 }, /* P7= Empty */ + /* + * Empty and onboard Ports 8-13, set to un-used pin + * OC4 + */ + { 1, 4, 0x0040 }, /* P8= Camera (no OC) */ + { 1, 4, 0x0040 }, /* P9= Bluetooth (no OC) */ + { 0, 4, 0x0000 }, /* P10= Empty */ + { 0, 4, 0x0000 }, /* P11= Empty */ + { 0, 4, 0x0000 }, /* P12= Empty */ + { 0, 4, 0x0000 }, /* P13= Empty */ + }, + }; + pci_dev_t dev = PCI_BDF(0, 0, 0); + int ret; + + debug("Boot mode %d\n", gd->arch.pei_boot_mode); + debug("mcr_input %p\n", pei_data.mrc_input); + pei_data.boot_mode = gd->arch.pei_boot_mode; + ret = copy_spd(&pei_data); + if (!ret) + ret = sdram_initialise(&pei_data); + if (ret) + return ret; + + rcba_config(); + quick_ram_check(); + + writew(0xCAFE, MCHBAR_REG(SSKPD)); + + post_code(POST_DRAM); + + ret = sdram_find(dev); + if (ret) + return ret; + + gd->ram_size = gd->arch.meminfo.total_32bit_memory;

return 0; } diff --git a/arch/x86/cpu/start.S b/arch/x86/cpu/start.S index 1b738f9..b0d0ac0 100644 --- a/arch/x86/cpu/start.S +++ b/arch/x86/cpu/start.S @@ -78,20 +78,22 @@ car_init_ret: * We now have CONFIG_SYS_CAR_SIZE bytes of Cache-As-RAM (or SRAM, * or fully initialised SDRAM - we really don't care which) * starting at CONFIG_SYS_CAR_ADDR to be used as a temporary stack - * and early malloc area. + * and early malloc area. The MRC requires some space at the top. * * Stack grows down from top of CAR. We have: * * top-> CONFIG_SYS_CAR_ADDR + CONFIG_SYS_CAR_SIZE + * MRC area * global_data * x86 global descriptor table * early malloc area * stack * bottom-> CONFIG_SYS_CAR_ADDR */ - - /* Stack grows down from top of CAR */ - movl $(CONFIG_SYS_CAR_ADDR + CONFIG_SYS_CAR_SIZE), %esp + movl $(CONFIG_SYS_CAR_ADDR + CONFIG_SYS_CAR_SIZE - 4), %esp +#ifdef CONFIG_DCACHE_RAM_MRC_VAR_SIZE + subl $CONFIG_DCACHE_RAM_MRC_VAR_SIZE, %esp +#endif

/* Reserve space on stack for global data */ subl $GENERATED_GBL_DATA_SIZE, %esp diff --git a/arch/x86/dts/link.dts b/arch/x86/dts/link.dts index 74b2198..9329916 100644 --- a/arch/x86/dts/link.dts +++ b/arch/x86/dts/link.dts @@ -41,6 +41,117 @@ chosen { }; memory { device_type = "memory"; reg = <0 0>; };

+ spd { + compatible = "memory-spd"; + #address-cells = <1>; + #size-cells = <0>; + elpida_4Gb_1600_x16 { + reg = <0>; + data = [92 10 0b 03 04 19 02 02 + 03 52 01 08 0a 00 fe 00 + 69 78 69 3c 69 11 18 81 + 20 08 3c 3c 01 40 83 81 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 0f 11 42 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 02 fe 00 + 11 52 00 00 00 07 7f 37 + 45 42 4a 32 30 55 47 36 + 45 42 55 30 2d 47 4e 2d + 46 20 30 20 02 fe 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00]; + }; + samsung_4Gb_1600_1.35v_x16 { + reg = <1>; + data = [92 11 0b 03 04 19 02 02 + 03 11 01 08 0a 00 fe 00 + 69 78 69 3c 69 11 18 81 + f0 0a 3c 3c 01 40 83 01 + 00 80 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 0f 11 02 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 80 ce 01 + 00 00 00 00 00 00 6a 04 + 4d 34 37 31 42 35 36 37 + 34 42 48 30 2d 59 4b 30 + 20 20 00 00 80 ce 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00]; + }; + micron_4Gb_1600_1.35v_x16 { + reg = <2>; + data = [92 11 0b 03 04 19 02 02 + 03 11 01 08 0a 00 fe 00 + 69 78 69 3c 69 11 18 81 + 20 08 3c 3c 01 40 83 05 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 0f 01 02 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 80 2c 00 + 00 00 00 00 00 00 ad 75 + 34 4b 54 46 32 35 36 36 + 34 48 5a 2d 31 47 36 45 + 31 20 45 31 80 2c 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + ff ff ff ff ff ff ff ff + ff ff ff ff ff ff ff ff + ff ff ff ff ff ff ff ff + ff ff ff ff ff ff ff ff + ff ff ff ff ff ff ff ff + ff ff ff ff ff ff ff ff + ff ff ff ff ff ff ff ff + ff ff ff ff ff ff ff ff + ff ff ff ff ff ff ff ff + ff ff ff ff ff ff ff ff]; + }; + }; + spi { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/x86/include/asm/arch-ivybridge/me.h b/arch/x86/include/asm/arch-ivybridge/me.h new file mode 100644 index 0000000..3a0809d --- /dev/null +++ b/arch/x86/include/asm/arch-ivybridge/me.h @@ -0,0 +1,356 @@ +/* + * From Coreboot src/southbridge/intel/bd82x6x/me.h + * + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _ASM_INTEL_ME_H +#define _ASM_INTEL_ME_H + +#include <linux/compiler.h> +#include <linux/types.h> + +#define ME_RETRY 100000 /* 1 second */ +#define ME_DELAY 10 /* 10 us */ + +/* + * Management Engine PCI registers + */ + +#define PCI_CPU_MEBASE_L 0x70 /* Set by MRC */ +#define PCI_CPU_MEBASE_H 0x74 /* Set by MRC */ + +#define PCI_ME_HFS 0x40 +#define ME_HFS_CWS_RESET 0 +#define ME_HFS_CWS_INIT 1 +#define ME_HFS_CWS_REC 2 +#define ME_HFS_CWS_NORMAL 5 +#define ME_HFS_CWS_WAIT 6 +#define ME_HFS_CWS_TRANS 7 +#define ME_HFS_CWS_INVALID 8 +#define ME_HFS_STATE_PREBOOT 0 +#define ME_HFS_STATE_M0_UMA 1 +#define ME_HFS_STATE_M3 4 +#define ME_HFS_STATE_M0 5 +#define ME_HFS_STATE_BRINGUP 6 +#define ME_HFS_STATE_ERROR 7 +#define ME_HFS_ERROR_NONE 0 +#define ME_HFS_ERROR_UNCAT 1 +#define ME_HFS_ERROR_IMAGE 3 +#define ME_HFS_ERROR_DEBUG 4 +#define ME_HFS_MODE_NORMAL 0 +#define ME_HFS_MODE_DEBUG 2 +#define ME_HFS_MODE_DIS 3 +#define ME_HFS_MODE_OVER_JMPR 4 +#define ME_HFS_MODE_OVER_MEI 5 +#define ME_HFS_BIOS_DRAM_ACK 1 +#define ME_HFS_ACK_NO_DID 0 +#define ME_HFS_ACK_RESET 1 +#define ME_HFS_ACK_PWR_CYCLE 2 +#define ME_HFS_ACK_S3 3 +#define ME_HFS_ACK_S4 4 +#define ME_HFS_ACK_S5 5 +#define ME_HFS_ACK_GBL_RESET 6 +#define ME_HFS_ACK_CONTINUE 7 + +struct me_hfs { + u32 working_state:4; + u32 mfg_mode:1; + u32 fpt_bad:1; + u32 operation_state:3; + u32 fw_init_complete:1; + u32 ft_bup_ld_flr:1; + u32 update_in_progress:1; + u32 error_code:4; + u32 operation_mode:4; + u32 reserved:4; + u32 boot_options_present:1; + u32 ack_data:3; + u32 bios_msg_ack:4; +} __packed; + +#define PCI_ME_UMA 0x44 + +struct me_uma { + u32 size:6; + u32 reserved_1:10; + u32 valid:1; + u32 reserved_0:14; + u32 set_to_one:1; +} __packed; + +#define PCI_ME_H_GS 0x4c +#define ME_INIT_DONE 1 +#define ME_INIT_STATUS_SUCCESS 0 +#define ME_INIT_STATUS_NOMEM 1 +#define ME_INIT_STATUS_ERROR 2 + +struct me_did { + u32 uma_base:16; + u32 reserved:8; + u32 status:4; + u32 init_done:4; +} __packed; + +#define PCI_ME_GMES 0x48 +#define ME_GMES_PHASE_ROM 0 +#define ME_GMES_PHASE_BUP 1 +#define ME_GMES_PHASE_UKERNEL 2 +#define ME_GMES_PHASE_POLICY 3 +#define ME_GMES_PHASE_MODULE 4 +#define ME_GMES_PHASE_UNKNOWN 5 +#define ME_GMES_PHASE_HOST 6 + +struct me_gmes { + u32 bist_in_prog:1; + u32 icc_prog_sts:2; + u32 invoke_mebx:1; + u32 cpu_replaced_sts:1; + u32 mbp_rdy:1; + u32 mfs_failure:1; + u32 warm_rst_req_for_df:1; + u32 cpu_replaced_valid:1; + u32 reserved_1:2; + u32 fw_upd_ipu:1; + u32 reserved_2:4; + u32 current_state:8; + u32 current_pmevent:4; + u32 progress_code:4; +} __packed; + +#define PCI_ME_HERES 0xbc +#define PCI_ME_EXT_SHA1 0x00 +#define PCI_ME_EXT_SHA256 0x02 +#define PCI_ME_HER(x) (0xc0+(4*(x))) + +struct me_heres { + u32 extend_reg_algorithm:4; + u32 reserved:26; + u32 extend_feature_present:1; + u32 extend_reg_valid:1; +} __packed; + +/* + * Management Engine MEI registers + */ + +#define MEI_H_CB_WW 0x00 +#define MEI_H_CSR 0x04 +#define MEI_ME_CB_RW 0x08 +#define MEI_ME_CSR_HA 0x0c + +struct mei_csr { + u32 interrupt_enable:1; + u32 interrupt_status:1; + u32 interrupt_generate:1; + u32 ready:1; + u32 reset:1; + u32 reserved:3; + u32 buffer_read_ptr:8; + u32 buffer_write_ptr:8; + u32 buffer_depth:8; +} __packed; + +#define MEI_ADDRESS_CORE 0x01 +#define MEI_ADDRESS_AMT 0x02 +#define MEI_ADDRESS_RESERVED 0x03 +#define MEI_ADDRESS_WDT 0x04 +#define MEI_ADDRESS_MKHI 0x07 +#define MEI_ADDRESS_ICC 0x08 +#define MEI_ADDRESS_THERMAL 0x09 + +#define MEI_HOST_ADDRESS 0 + +struct mei_header { + u32 client_address:8; + u32 host_address:8; + u32 length:9; + u32 reserved:6; + u32 is_complete:1; +} __packed; + +#define MKHI_GROUP_ID_CBM 0x00 +#define MKHI_GROUP_ID_FWCAPS 0x03 +#define MKHI_GROUP_ID_MDES 0x08 +#define MKHI_GROUP_ID_GEN 0xff + +#define MKHI_GLOBAL_RESET 0x0b + +#define MKHI_FWCAPS_GET_RULE 0x02 + +#define MKHI_MDES_ENABLE 0x09 + +#define MKHI_GET_FW_VERSION 0x02 +#define MKHI_END_OF_POST 0x0c +#define MKHI_FEATURE_OVERRIDE 0x14 + +struct mkhi_header { + u32 group_id:8; + u32 command:7; + u32 is_response:1; + u32 reserved:8; + u32 result:8; +} __packed; + +struct me_fw_version { + u16 code_minor; + u16 code_major; + u16 code_build_number; + u16 code_hot_fix; + u16 recovery_minor; + u16 recovery_major; + u16 recovery_build_number; + u16 recovery_hot_fix; +} __packed; + + +#define HECI_EOP_STATUS_SUCCESS 0x0 +#define HECI_EOP_PERFORM_GLOBAL_RESET 0x1 + +#define CBM_RR_GLOBAL_RESET 0x01 + +#define GLOBAL_RESET_BIOS_MRC 0x01 +#define GLOBAL_RESET_BIOS_POST 0x02 +#define GLOBAL_RESET_MEBX 0x03 + +struct me_global_reset { + u8 request_origin; + u8 reset_type; +} __packed; + +enum me_bios_path { + ME_NORMAL_BIOS_PATH, + ME_S3WAKE_BIOS_PATH, + ME_ERROR_BIOS_PATH, + ME_RECOVERY_BIOS_PATH, + ME_DISABLE_BIOS_PATH, + ME_FIRMWARE_UPDATE_BIOS_PATH, +}; + +struct __packed mbp_fw_version_name { + u32 major_version:16; + u32 minor_version:16; + u32 hotfix_version:16; + u32 build_version:16; +}; + +struct __packed mbp_icc_profile { + u8 num_icc_profiles; + u8 icc_profile_soft_strap; + u8 icc_profile_index; + u8 reserved; + u32 register_lock_mask[3]; +}; + +struct __packed mefwcaps_sku { + u32 full_net:1; + u32 std_net:1; + u32 manageability:1; + u32 small_business:1; + u32 l3manageability:1; + u32 intel_at:1; + u32 intel_cls:1; + u32 reserved:3; + u32 intel_mpc:1; + u32 icc_over_clocking:1; + u32 pavp:1; + u32 reserved_1:4; + u32 ipv6:1; + u32 kvm:1; + u32 och:1; + u32 vlan:1; + u32 tls:1; + u32 reserved_4:1; + u32 wlan:1; + u32 reserved_5:8; +}; + +struct __packed tdt_state_flag { + u16 lock_state:1; + u16 authenticate_module:1; + u16 s3authentication:1; + u16 flash_wear_out:1; + u16 flash_variable_security:1; + u16 wwan3gpresent:1; + u16 wwan3goob:1; + u16 reserved:9; +}; + +struct __packed tdt_state_info { + u8 state; + u8 last_theft_trigger; + struct tdt_state_flag flags; +}; + +struct __packed platform_type_rule_data { + u32 platform_target_usage_type:4; + u32 platform_target_market_type:2; + u32 super_sku:1; + u32 reserved:1; + u32 intel_me_fw_image_type:4; + u32 platform_brand:4; + u32 reserved_1:16; +}; + +struct __packed mbp_fw_caps { + struct mefwcaps_sku fw_capabilities; + u8 available; +}; + +struct __packed mbp_rom_bist_data { + u16 device_id; + u16 fuse_test_flags; + u32 umchid[4]; +}; + +struct __packed mbp_platform_key { + u32 key[8]; +}; + +struct __packed mbp_plat_type { + struct platform_type_rule_data rule_data; + u8 available; +}; + +struct __packed me_bios_payload { + struct mbp_fw_version_name fw_version_name; + struct mbp_fw_caps fw_caps_sku; + struct mbp_rom_bist_data rom_bist_data; + struct mbp_platform_key platform_key; + struct mbp_plat_type fw_plat_type; + struct mbp_icc_profile icc_profile; + struct tdt_state_info at_state; + u32 mfsintegrity; +}; + +struct __packed mbp_header { + u32 mbp_size:8; + u32 num_entries:8; + u32 rsvd:16; +}; + +struct __packed mbp_item_header { + u32 app_id:8; + u32 item_id:8; + u32 length:8; + u32 rsvd:8; +}; + +struct __packed me_fwcaps { + u32 id; + u8 length; + struct mefwcaps_sku caps_sku; + u8 reserved[3]; +}; + +/* Defined in me_status.c for both romstage and ramstage */ +void intel_me_status(struct me_hfs *hfs, struct me_gmes *gmes); + +void intel_early_me_status(void); +int intel_early_me_init(void); +int intel_early_me_uma_size(void); +int intel_early_me_init_done(u8 status); + +#endif diff --git a/arch/x86/include/asm/arch-ivybridge/pch.h b/arch/x86/include/asm/arch-ivybridge/pch.h index ae338e3..c6efdb8 100644 --- a/arch/x86/include/asm/arch-ivybridge/pch.h +++ b/arch/x86/include/asm/arch-ivybridge/pch.h @@ -31,6 +31,13 @@ /* PCI Configuration Space (D31:F0): LPC */ #define PCH_LPC_DEV PCI_BDF(0, 0x1f, 0)

+#define GEN_PMCON_1 0xa0 +#define GEN_PMCON_2 0xa2 +#define GEN_PMCON_3 0xa4 +#define ETR3 0xac +#define ETR3_CWORWRE (1 << 18) +#define ETR3_CF9GR (1 << 20) + #define PMBASE 0x40 #define ACPI_CNTL 0x44 #define BIOS_CNTL 0xDC @@ -126,12 +133,97 @@ #define RPC 0x0400 /* 32bit */ #define RPFN 0x0404 /* 32bit */

+#define TRSR 0x1e00 /* 8bit */ +#define TRCR 0x1e10 /* 64bit */ +#define TWDR 0x1e18 /* 64bit */ + +#define IOTR0 0x1e80 /* 64bit */ +#define IOTR1 0x1e88 /* 64bit */ +#define IOTR2 0x1e90 /* 64bit */ +#define IOTR3 0x1e98 /* 64bit */ + +#define TCTL 0x3000 /* 8bit */ + +#define NOINT 0 +#define INTA 1 +#define INTB 2 +#define INTC 3 +#define INTD 4 + +#define DIR_IDR 12 /* Interrupt D Pin Offset */ +#define DIR_ICR 8 /* Interrupt C Pin Offset */ +#define DIR_IBR 4 /* Interrupt B Pin Offset */ +#define DIR_IAR 0 /* Interrupt A Pin Offset */ + +#define PIRQA 0 +#define PIRQB 1 +#define PIRQC 2 +#define PIRQD 3 +#define PIRQE 4 +#define PIRQF 5 +#define PIRQG 6 +#define PIRQH 7 + +/* IO Buffer Programming */ +#define IOBPIRI 0x2330 +#define IOBPD 0x2334 +#define IOBPS 0x2338 +#define IOBPS_RW_BX ((1 << 9)|(1 << 10)) +#define IOBPS_WRITE_AX ((1 << 9)|(1 << 10)) +#define IOBPS_READ_AX ((1 << 8)|(1 << 9)|(1 << 10)) + +#define D31IP 0x3100 /* 32bit */ +#define D31IP_TTIP 24 /* Thermal Throttle Pin */ +#define D31IP_SIP2 20 /* SATA Pin 2 */ +#define D31IP_SMIP 12 /* SMBUS Pin */ +#define D31IP_SIP 8 /* SATA Pin */ +#define D30IP 0x3104 /* 32bit */ +#define D30IP_PIP 0 /* PCI Bridge Pin */ +#define D29IP 0x3108 /* 32bit */ +#define D29IP_E1P 0 /* EHCI #1 Pin */ +#define D28IP 0x310c /* 32bit */ +#define D28IP_P8IP 28 /* PCI Express Port 8 */ +#define D28IP_P7IP 24 /* PCI Express Port 7 */ +#define D28IP_P6IP 20 /* PCI Express Port 6 */ +#define D28IP_P5IP 16 /* PCI Express Port 5 */ +#define D28IP_P4IP 12 /* PCI Express Port 4 */ +#define D28IP_P3IP 8 /* PCI Express Port 3 */ +#define D28IP_P2IP 4 /* PCI Express Port 2 */ +#define D28IP_P1IP 0 /* PCI Express Port 1 */ +#define D27IP 0x3110 /* 32bit */ +#define D27IP_ZIP 0 /* HD Audio Pin */ +#define D26IP 0x3114 /* 32bit */ +#define D26IP_E2P 0 /* EHCI #2 Pin */ +#define D25IP 0x3118 /* 32bit */ +#define D25IP_LIP 0 /* GbE LAN Pin */ +#define D22IP 0x3124 /* 32bit */ +#define D22IP_KTIP 12 /* KT Pin */ +#define D22IP_IDERIP 8 /* IDE-R Pin */ +#define D22IP_MEI2IP 4 /* MEI #2 Pin */ +#define D22IP_MEI1IP 0 /* MEI #1 Pin */ +#define D20IP 0x3128 /* 32bit */ +#define D20IP_XHCIIP 0 +#define D31IR 0x3140 /* 16bit */ +#define D30IR 0x3142 /* 16bit */ +#define D29IR 0x3144 /* 16bit */ +#define D28IR 0x3146 /* 16bit */ +#define D27IR 0x3148 /* 16bit */ +#define D26IR 0x314c /* 16bit */ +#define D25IR 0x3150 /* 16bit */ +#define D22IR 0x315c /* 16bit */ +#define D20IR 0x3160 /* 16bit */ +#define OIC 0x31fe /* 16bit */ + #define SPI_FREQ_SWSEQ 0x3893 #define SPI_DESC_COMP0 0x38b0 #define SPI_FREQ_WR_ERA 0x38b4 #define SOFT_RESET_CTRL 0x38f4 #define SOFT_RESET_DATA 0x38f8

+#define DIR_ROUTE(a, b, c, d) \ + (((d) << DIR_IDR) | ((c) << DIR_ICR) | \ + ((b) << DIR_IBR) | ((a) << DIR_IAR)) + #define RC 0x3400 /* 32bit */ #define HPTC 0x3404 /* 32bit */ #define GCS 0x3410 /* 32bit */ @@ -142,6 +234,27 @@ #define FD2 0x3428 /* 32bit */ #define CG 0x341c /* 32bit */

+/* Function Disable 1 RCBA 0x3418 */ +#define PCH_DISABLE_ALWAYS ((1 << 0)|(1 << 26)) +#define PCH_DISABLE_P2P (1 << 1) +#define PCH_DISABLE_SATA1 (1 << 2) +#define PCH_DISABLE_SMBUS (1 << 3) +#define PCH_DISABLE_HD_AUDIO (1 << 4) +#define PCH_DISABLE_EHCI2 (1 << 13) +#define PCH_DISABLE_LPC (1 << 14) +#define PCH_DISABLE_EHCI1 (1 << 15) +#define PCH_DISABLE_PCIE(x) (1 << (16 + x)) +#define PCH_DISABLE_THERMAL (1 << 24) +#define PCH_DISABLE_SATA2 (1 << 25) +#define PCH_DISABLE_XHCI (1 << 27) + +/* Function Disable 2 RCBA 0x3428 */ +#define PCH_DISABLE_KT (1 << 4) +#define PCH_DISABLE_IDER (1 << 3) +#define PCH_DISABLE_MEI2 (1 << 2) +#define PCH_DISABLE_MEI1 (1 << 1) +#define PCH_ENABLE_DBDF (1 << 0) + /* ICH7 GPIOBASE */ #define GPIO_USE_SEL 0x00 #define GP_IO_SEL 0x04 diff --git a/arch/x86/include/asm/arch-ivybridge/pei_data.h b/arch/x86/include/asm/arch-ivybridge/pei_data.h new file mode 100644 index 0000000..5026c8b --- /dev/null +++ b/arch/x86/include/asm/arch-ivybridge/pei_data.h @@ -0,0 +1,121 @@ +/* + * Copyright (c) 2011, Google Inc. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef ASM_ARCH_PEI_DATA_H +#define ASM_ARCH_PEI_DATA_H + +struct pch_usb3_controller_settings { + /* 0: Disable, 1: Enable, 2: Auto, 3: Smart Auto */ + uint16_t mode; + /* 4 bit mask, 1: switchable, 0: not switchable */ + uint16_t hs_port_switch_mask; + /* 0: No xHCI preOS driver, 1: xHCI preOS driver */ + uint16_t preboot_support; + /* 0: Disable, 1: Enable */ + uint16_t xhci_streams; +}; + +typedef asmlinkage void (*tx_byte_func)(unsigned char byte); + +#define PEI_VERSION 6 + +struct __packed pei_data { + uint32_t pei_version; + uint32_t mchbar; + uint32_t dmibar; + uint32_t epbar; + uint32_t pciexbar; + uint16_t smbusbar; + uint32_t wdbbar; + uint32_t wdbsize; + uint32_t hpet_address; + uint32_t rcba; + uint32_t pmbase; + uint32_t gpiobase; + uint32_t thermalbase; + uint32_t system_type; /* 0 Mobile, 1 Desktop/Server */ + uint32_t tseg_size; + uint8_t spd_addresses[4]; + uint8_t ts_addresses[4]; + int boot_mode; + int ec_present; + int gbe_enable; + /* + * 0 = leave channel enabled + * 1 = disable dimm 0 on channel + * 2 = disable dimm 1 on channel + * 3 = disable dimm 0+1 on channel + */ + int dimm_channel0_disabled; + int dimm_channel1_disabled; + /* Seed values saved in CMOS */ + uint32_t scrambler_seed; + uint32_t scrambler_seed_s3; + /* Data read from flash and passed into MRC */ + unsigned char *mrc_input; + unsigned int mrc_input_len; + /* Data from MRC that should be saved to flash */ + unsigned char *mrc_output; + unsigned int mrc_output_len; + /* + * Max frequency DDR3 could be ran at. Could be one of four values: + * 800, 1067, 1333, 1600 + */ + uint32_t max_ddr3_freq; + /* + * USB Port Configuration: + * [0] = enable + * [1] = overcurrent pin + * [2] = length + * + * Ports 0-7 can be mapped to OC0-OC3 + * Ports 8-13 can be mapped to OC4-OC7 + * + * Port Length + * MOBILE: + * < 0x050 = Setting 1 (back panel, 1-5in, lowest tx amplitude) + * < 0x140 = Setting 2 (back panel, 5-14in, highest tx amplitude) + * DESKTOP: + * < 0x080 = Setting 1 (front/back panel, <8in, lowest tx amplitude) + * < 0x130 = Setting 2 (back panel, 8-13in, higher tx amplitude) + * < 0x150 = Setting 3 (back panel, 13-15in, higest tx amplitude) + */ + uint16_t usb_port_config[16][3]; + /* See the usb3 struct above for details */ + struct pch_usb3_controller_settings usb3; + /* + * SPD data array for onboard RAM. Specify address 0xf0, + * 0xf1, 0xf2, 0xf3 to index one of the 4 slots in + * spd_address for a given "DIMM". + */ + uint8_t spd_data[4][256]; + tx_byte_func tx_byte; + int ddr3lv_support; + /* + * pcie_init needs to be set to 1 to have the system agent initialise + * PCIe. Note: This should only be required if your system has Gen3 + * devices and it will increase your boot time by at least 100ms. + */ + int pcie_init; + /* + * N mode functionality. Leave this setting at 0. + * 0 Auto + * 1 1N + * 2 2N + */ + int nmode; + /* + * DDR refresh rate config. JEDEC Standard No.21-C Annex K allows + * for DIMM SPD data to specify whether double-rate is required for + * extended operating temperature range. + * 0 Enable double rate based upon temperature thresholds + * 1 Normal rate + * 2 Always enable double rate + */ + int ddr_refresh_rate_config; +}; + +#endif diff --git a/arch/x86/include/asm/arch-ivybridge/sandybridge.h b/arch/x86/include/asm/arch-ivybridge/sandybridge.h index a1072f2..114ee19 100644 --- a/arch/x86/include/asm/arch-ivybridge/sandybridge.h +++ b/arch/x86/include/asm/arch-ivybridge/sandybridge.h @@ -102,6 +102,8 @@ #define SSKPD 0x5d14 /* 16bit (scratchpad) */ #define BIOS_RESET_CPL 0x5da8 /* 8bit */

+void report_platform_info(void); + void sandybridge_early_init(int chipset_type);

#endif diff --git a/arch/x86/include/asm/config.h b/arch/x86/include/asm/config.h index ff15828..c97d988 100644 --- a/arch/x86/include/asm/config.h +++ b/arch/x86/include/asm/config.h @@ -10,5 +10,6 @@ #define CONFIG_SYS_GENERIC_BOARD #define CONFIG_LMB #define CONFIG_SYS_BOOT_RAMDISK_HIGH +#define asmlinkage __attribute__((regparm(0)))

#endif diff --git a/arch/x86/include/asm/global_data.h b/arch/x86/include/asm/global_data.h index 4ea46d7..48bbd1a 100644 --- a/arch/x86/include/asm/global_data.h +++ b/arch/x86/include/asm/global_data.h @@ -17,6 +17,18 @@ enum pei_boot_mode_t {

};

+struct memory_area { + uint64_t start; + uint64_t size; +}; + +struct memory_info { + int num_areas; + uint64_t total_memory; + uint64_t total_32bit_memory; + struct memory_area area[CONFIG_NR_DRAM_BANKS]; +}; + /* Architecture-specific global data */ struct arch_global_data { struct global_data *gd_addr; /* Location of Global Data */ @@ -34,6 +46,7 @@ struct arch_global_data { struct pci_controller *hose; /* PCI hose for early use */ enum pei_boot_mode_t pei_boot_mode; const struct pch_gpio_map *gpio_map; /* board GPIO map */ + struct memory_info meminfo; /* Memory information */ };

#endif diff --git a/arch/x86/include/asm/post.h b/arch/x86/include/asm/post.h index 61dcda1..ce68839 100644 --- a/arch/x86/include/asm/post.h +++ b/arch/x86/include/asm/post.h @@ -27,6 +27,11 @@ #define POST_CPU_INIT 0x2b #define POST_EARLY_INIT 0x2c #define POST_CPU_INFO 0x2d +#define POST_PRE_MRC 0x2e +#define POST_MRC 0x2f +#define POST_DRAM 0x2f + +#define POST_RAM_FAILURE 0xea

/* Output a post code using al - value must be 0 to 0xff */ #ifdef __ASSEMBLY__ diff --git a/arch/x86/include/asm/u-boot-x86.h b/arch/x86/include/asm/u-boot-x86.h index 8d5b438..f115500 100644 --- a/arch/x86/include/asm/u-boot-x86.h +++ b/arch/x86/include/asm/u-boot-x86.h @@ -69,4 +69,6 @@ static inline __attribute__((no_instrument_function)) uint64_t rdtsc(void) void timer_set_tsc_base(uint64_t new_base); uint64_t timer_get_tsc(void);

+void quick_ram_check(void); + #endif /* _U_BOOT_I386_H_ */ diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile index 25b672a..d0c7f30 100644 --- a/arch/x86/lib/Makefile +++ b/arch/x86/lib/Makefile @@ -15,6 +15,7 @@ obj-$(CONFIG_SYS_PCAT_TIMER) += pcat_timer.o obj-$(CONFIG_PCI) += pci_type1.o obj-y += relocate.o obj-y += physmem.o +obj-y += ramtest.o obj-y += string.o obj-$(CONFIG_SYS_X86_TSC_TIMER) += tsc_timer.o obj-$(CONFIG_VIDEO_VGA) += video.o diff --git a/arch/x86/lib/ramtest.c b/arch/x86/lib/ramtest.c new file mode 100644 index 0000000..c21be03 --- /dev/null +++ b/arch/x86/lib/ramtest.c @@ -0,0 +1,79 @@ +/* + * Copyright (c) 2014 Google, Inc + * + * From Coreboot src/lib/ramtest.c + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/post.h> + +static void write_phys(unsigned long addr, u32 value) +{ +#if CONFIG_SSE2 + asm volatile( + "movnti %1, (%0)" + : /* outputs */ + : "r" (addr), "r" (value) /* inputs */ + : /* clobbers */ + ); +#else + writel(value, addr); +#endif +} + +static u32 read_phys(unsigned long addr) +{ + return readl(addr); +} + +static void phys_memory_barrier(void) +{ +#if CONFIG_SSE2 + /* Needed for movnti */ + asm volatile( + "sfence" + : + : + : "memory" + ); +#else + asm volatile("" + : + : + : "memory"); +#endif +} + +void quick_ram_check(void) +{ + int fail = 0; + u32 backup; + + backup = read_phys(CONFIG_RAMBASE); + write_phys(CONFIG_RAMBASE, 0x55555555); + phys_memory_barrier(); + if (read_phys(CONFIG_RAMBASE) != 0x55555555) + fail = 1; + write_phys(CONFIG_RAMBASE, 0xaaaaaaaa); + phys_memory_barrier(); + if (read_phys(CONFIG_RAMBASE) != 0xaaaaaaaa) + fail = 1; + write_phys(CONFIG_RAMBASE, 0x00000000); + phys_memory_barrier(); + if (read_phys(CONFIG_RAMBASE) != 0x00000000) + fail = 1; + write_phys(CONFIG_RAMBASE, 0xffffffff); + phys_memory_barrier(); + if (read_phys(CONFIG_RAMBASE) != 0xffffffff) + fail = 1; + + write_phys(CONFIG_RAMBASE, backup); + if (fail) { + post_code(POST_RAM_FAILURE); + panic("RAM INIT FAILURE!\n"); + } + phys_memory_barrier(); +} diff --git a/include/configs/chromebook_link.h b/include/configs/chromebook_link.h index 3063bd9..8caeca6 100644 --- a/include/configs/chromebook_link.h +++ b/include/configs/chromebook_link.h @@ -18,12 +18,16 @@ #define CONFIG_SYS_CAR_ADDR 0xff7e0000 #define CONFIG_SYS_CAR_SIZE (128 * 1024) #define CONFIG_SYS_MONITOR_LEN (1 << 20) +#define CONFIG_DCACHE_RAM_MRC_VAR_SIZE 0x4000 #define CONFIG_SYS_X86_START16 0xfffff800 #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_BOARD_EARLY_INIT_R +#define CONFIG_DISPLAY_CPUINFO

#define CONFIG_X86_RESET_VECTOR #define CONFIG_NR_DRAM_BANKS 8 +#define CONFIG_X86_MRC_START 0xfffa0000 +#define CONFIG_CACHE_MRC_SIZE_KB 512

#define CONFIG_COREBOOT_SERIAL

diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h index 825e9f7..f16ae32 100644 --- a/include/configs/x86-common.h +++ b/include/configs/x86-common.h @@ -192,7 +192,7 @@ #define CONFIG_SYS_STACK_SIZE (32 * 1024) #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_MALLOC_LEN 0x200000 -#define CONFIG_SYS_MALLOC_F_LEN (1 << 10) +#define CONFIG_SYS_MALLOC_F_LEN (2 << 10)

/* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE diff --git a/include/fdtdec.h b/include/fdtdec.h index 3bd60b7..abfd678 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -119,6 +119,7 @@ enum fdt_compat_id { COMPAT_PARADE_PS8625, /* Parade PS8622 EDP->LVDS bridge */ COMPAT_INTEL_LPC, /* Intel Low Pin Count I/F */ COMPAT_INTEL_MICROCODE, /* Intel microcode update */ + COMPAT_MEMORY_SPD, /* Memory SPD information */

COMPAT_COUNT, }; diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 9a68f9c..aafc4f9 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -74,6 +74,7 @@ static const char * const compat_names[COMPAT_COUNT] = { COMPAT(PARADE_PS8625, "parade,ps8625"), COMPAT(COMPAT_INTEL_LPC, "intel,lpc"), COMPAT(INTEL_MICROCODE, "intel,microcode"), + COMPAT(MEMORY_SPD, "memory-spd"), };

const char *fdtdec_get_compatible(enum fdt_compat_id id)