[U-Boot] [PATCH 1/4] ARM: armv7: Make indirect vector addresses globl
Make indirect vectors addresses global, so they can be replaced by various code that needs to do so. For example the MX6 PCI express driver needs to temporarily replace data abort handler when reading the config space.
Signed-off-by: Marek Vasut marex@denx.de Cc: Albert Aribaud albert.u.boot@aribaud.net Cc: Eric Nelson eric.nelson@boundarydevices.com Cc: Fabio Estevam fabio.estevam@freescale.com Cc: Stefano Babic sbabic@denx.de --- arch/arm/cpu/armv7/start.S | 7 +++++++ 1 file changed, 7 insertions(+)
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 6c9b11a..5aac773 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -38,12 +38,19 @@ _irq: .word _irq _fiq: .word _fiq _pad: .word 0x12345678 /* now 16*4=64 */ #else +.globl _undefined_instruction _undefined_instruction: .word undefined_instruction +.globl _software_interrupt _software_interrupt: .word software_interrupt +.globl _prefetch_abort _prefetch_abort: .word prefetch_abort +.globl _data_abort _data_abort: .word data_abort +.globl _not_used _not_used: .word not_used +.globl _irq _irq: .word irq +.globl _fiq _fiq: .word fiq _pad: .word 0x12345678 /* now 16*4=64 */ #endif /* CONFIG_SPL_BUILD */
Split the SATA clock enabling function and add PCI express clock enabling function. The SATA clock enabling function starts up the 100MHz SATA reference PLL in ENET_PLL register, but the code can be re-used to enable the 125MHz PCIe reference in ENET_PLL, so pull this code into separate function. Moreover, add the PCIe clock enabling code.
Signed-off-by: Marek Vasut marex@denx.de Cc: Albert Aribaud albert.u.boot@aribaud.net Cc: Eric Nelson eric.nelson@boundarydevices.com Cc: Fabio Estevam fabio.estevam@freescale.com Cc: Stefano Babic sbabic@denx.de --- arch/arm/cpu/armv7/mx6/clock.c | 75 ++++++++++++++++++++++++++++++----- arch/arm/include/asm/arch-mx6/clock.h | 1 + 2 files changed, 66 insertions(+), 10 deletions(-)
V2: Drop the clock teardown function, it is not needed. Instead, fix a patch for the Linux kernel to handle running link.
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index 873d9d0..b25a954 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -404,17 +404,12 @@ u32 imx_get_fecclk(void) return decode_pll(PLL_ENET, MXC_HCLK); }
-int enable_sata_clock(void) +static int enable_enet_pll(uint32_t en) { - u32 reg = 0; - s32 timeout = 100000; struct mxc_ccm_reg *const imx_ccm = (struct mxc_ccm_reg *) CCM_BASE_ADDR; - - /* Enable sata clock */ - reg = readl(&imx_ccm->CCGR5); /* CCGR5 */ - reg |= MXC_CCM_CCGR5_SATA_MASK; - writel(reg, &imx_ccm->CCGR5); + s32 timeout = 100000; + u32 reg = 0;
/* Enable PLLs */ reg = readl(&imx_ccm->analog_pll_enet); @@ -429,10 +424,70 @@ int enable_sata_clock(void) return -EIO; reg &= ~BM_ANADIG_PLL_SYS_BYPASS; writel(reg, &imx_ccm->analog_pll_enet); - reg |= BM_ANADIG_PLL_ENET_ENABLE_SATA; + reg |= en; writel(reg, &imx_ccm->analog_pll_enet); + return 0; +}
- return 0 ; +static void ungate_sata_clock(void) +{ + struct mxc_ccm_reg *const imx_ccm = + (struct mxc_ccm_reg *) CCM_BASE_ADDR; + + /* Enable SATA clock. */ + setbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK); +} + +static void ungate_pcie_clock(void) +{ + struct mxc_ccm_reg *const imx_ccm = + (struct mxc_ccm_reg *) CCM_BASE_ADDR; + + /* Enable PCIe clock. */ + setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_PCIE_MASK); +} + +int enable_sata_clock(void) +{ + ungate_sata_clock(); + return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA); +} + +int enable_pcie_clock(void) +{ + struct anatop_regs *anatop_regs = + (struct anatop_regs *)ANATOP_BASE_ADDR; + struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + /* + * Here be dragons! + * + * The register ANATOP_MISC1 is not documented in the Freescale + * MX6RM. The register that is mapped in the ANATOP space and + * marked as ANATOP_MISC1 is actually documented in the PMU section + * of the datasheet as PMU_MISC1. + * + * Switch LVDS clock source to SATA (0xb), disable clock INPUT and + * enable clock OUTPUT. This is important for PCI express link that + * is clocked from the i.MX6. + */ +#define ANADIG_ANA_MISC1_LVDSCLK1_IBEN (1 << 12) +#define ANADIG_ANA_MISC1_LVDSCLK1_OBEN (1 << 10) +#define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK 0x0000001F + clrsetbits_le32(&anatop_regs->ana_misc1, + ANADIG_ANA_MISC1_LVDSCLK1_IBEN | + ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK, + ANADIG_ANA_MISC1_LVDSCLK1_OBEN | 0xb); + + /* PCIe reference clock sourced from AXI. */ + clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL); + + /* Party time! Ungate the clock to the PCIe. */ + ungate_sata_clock(); + ungate_pcie_clock(); + + return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA | + BM_ANADIG_PLL_ENET_ENABLE_PCIE); }
unsigned int mxc_get_clock(enum mxc_clock clk) diff --git a/arch/arm/include/asm/arch-mx6/clock.h b/arch/arm/include/asm/arch-mx6/clock.h index 93f29a7..95b1270 100644 --- a/arch/arm/include/asm/arch-mx6/clock.h +++ b/arch/arm/include/asm/arch-mx6/clock.h @@ -48,6 +48,7 @@ unsigned int mxc_get_clock(enum mxc_clock clk); void enable_ocotp_clk(unsigned char enable); void enable_usboh3_clk(unsigned char enable); int enable_sata_clock(void); +int enable_pcie_clock(void); int enable_i2c_clk(unsigned char enable, unsigned i2c_num); void enable_ipu_clock(void); int enable_fec_anatop_clock(void);
On Sat, Dec 14, 2013 at 10:25 AM, Marek Vasut marex@denx.de wrote:
Split the SATA clock enabling function and add PCI express clock enabling function. The SATA clock enabling function starts up the 100MHz SATA reference PLL in ENET_PLL register, but the code can be re-used to enable the 125MHz PCIe reference in ENET_PLL, so pull this code into separate function. Moreover, add the PCIe clock enabling code.
Signed-off-by: Marek Vasut marex@denx.de Cc: Albert Aribaud albert.u.boot@aribaud.net Cc: Eric Nelson eric.nelson@boundarydevices.com Cc: Fabio Estevam fabio.estevam@freescale.com Cc: Stefano Babic sbabic@denx.de
arch/arm/cpu/armv7/mx6/clock.c | 75 ++++++++++++++++++++++++++++++----- arch/arm/include/asm/arch-mx6/clock.h | 1 + 2 files changed, 66 insertions(+), 10 deletions(-)
V2: Drop the clock teardown function, it is not needed. Instead, fix a patch for the Linux kernel to handle running link.
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index 873d9d0..b25a954 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -404,17 +404,12 @@ u32 imx_get_fecclk(void) return decode_pll(PLL_ENET, MXC_HCLK); }
-int enable_sata_clock(void) +static int enable_enet_pll(uint32_t en) {
u32 reg = 0;s32 timeout = 100000; struct mxc_ccm_reg *const imx_ccm = (struct mxc_ccm_reg *) CCM_BASE_ADDR;/* Enable sata clock */reg = readl(&imx_ccm->CCGR5); /* CCGR5 */reg |= MXC_CCM_CCGR5_SATA_MASK;writel(reg, &imx_ccm->CCGR5);
s32 timeout = 100000;u32 reg = 0; /* Enable PLLs */ reg = readl(&imx_ccm->analog_pll_enet);@@ -429,10 +424,70 @@ int enable_sata_clock(void) return -EIO; reg &= ~BM_ANADIG_PLL_SYS_BYPASS; writel(reg, &imx_ccm->analog_pll_enet);
reg |= BM_ANADIG_PLL_ENET_ENABLE_SATA;
reg |= en; writel(reg, &imx_ccm->analog_pll_enet);return 0;+}
return 0 ;+static void ungate_sata_clock(void) +{
struct mxc_ccm_reg *const imx_ccm =(struct mxc_ccm_reg *) CCM_BASE_ADDR;
Try to delete the space after a cast
/* Enable SATA clock. */setbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);+}
+static void ungate_pcie_clock(void) +{
struct mxc_ccm_reg *const imx_ccm =(struct mxc_ccm_reg *) CCM_BASE_ADDR;
<< same >>
Split the SATA clock enabling function and add PCI express clock enabling function. The SATA clock enabling function starts up the 100MHz SATA reference PLL in ENET_PLL register, but the code can be re-used to enable the 125MHz PCIe reference in ENET_PLL, so pull this code into separate function. Moreover, add the PCIe clock enabling code.
Signed-off-by: Marek Vasut marex@denx.de Cc: Albert Aribaud albert.u.boot@aribaud.net Cc: Eric Nelson eric.nelson@boundarydevices.com Cc: Fabio Estevam fabio.estevam@freescale.com Cc: Stefano Babic sbabic@denx.de --- arch/arm/cpu/armv7/mx6/clock.c | 75 ++++++++++++++++++++++++++++++----- arch/arm/include/asm/arch-mx6/clock.h | 1 + 2 files changed, 66 insertions(+), 10 deletions(-)
V2: Drop the clock teardown function, it is not needed. Instead, fix a patch for the Linux kernel to handle running link. V3: Fix some legacy coding style
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index 873d9d0..b25a954 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -404,17 +404,12 @@ u32 imx_get_fecclk(void) return decode_pll(PLL_ENET, MXC_HCLK); }
-int enable_sata_clock(void) +static int enable_enet_pll(uint32_t en) { - u32 reg = 0; - s32 timeout = 100000; struct mxc_ccm_reg *const imx_ccm = (struct mxc_ccm_reg *) CCM_BASE_ADDR; - - /* Enable sata clock */ - reg = readl(&imx_ccm->CCGR5); /* CCGR5 */ - reg |= MXC_CCM_CCGR5_SATA_MASK; - writel(reg, &imx_ccm->CCGR5); + s32 timeout = 100000; + u32 reg = 0;
/* Enable PLLs */ reg = readl(&imx_ccm->analog_pll_enet); @@ -429,10 +424,70 @@ int enable_sata_clock(void) return -EIO; reg &= ~BM_ANADIG_PLL_SYS_BYPASS; writel(reg, &imx_ccm->analog_pll_enet); - reg |= BM_ANADIG_PLL_ENET_ENABLE_SATA; + reg |= en; writel(reg, &imx_ccm->analog_pll_enet); + return 0; +}
- return 0 ; +static void ungate_sata_clock(void) +{ + struct mxc_ccm_reg *const imx_ccm = + (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + /* Enable SATA clock. */ + setbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK); +} + +static void ungate_pcie_clock(void) +{ + struct mxc_ccm_reg *const imx_ccm = + (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + /* Enable PCIe clock. */ + setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_PCIE_MASK); +} + +int enable_sata_clock(void) +{ + ungate_sata_clock(); + return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA); +} + +int enable_pcie_clock(void) +{ + struct anatop_regs *anatop_regs = + (struct anatop_regs *)ANATOP_BASE_ADDR; + struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + /* + * Here be dragons! + * + * The register ANATOP_MISC1 is not documented in the Freescale + * MX6RM. The register that is mapped in the ANATOP space and + * marked as ANATOP_MISC1 is actually documented in the PMU section + * of the datasheet as PMU_MISC1. + * + * Switch LVDS clock source to SATA (0xb), disable clock INPUT and + * enable clock OUTPUT. This is important for PCI express link that + * is clocked from the i.MX6. + */ +#define ANADIG_ANA_MISC1_LVDSCLK1_IBEN (1 << 12) +#define ANADIG_ANA_MISC1_LVDSCLK1_OBEN (1 << 10) +#define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK 0x0000001F + clrsetbits_le32(&anatop_regs->ana_misc1, + ANADIG_ANA_MISC1_LVDSCLK1_IBEN | + ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK, + ANADIG_ANA_MISC1_LVDSCLK1_OBEN | 0xb); + + /* PCIe reference clock sourced from AXI. */ + clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL); + + /* Party time! Ungate the clock to the PCIe. */ + ungate_sata_clock(); + ungate_pcie_clock(); + + return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA | + BM_ANADIG_PLL_ENET_ENABLE_PCIE); }
unsigned int mxc_get_clock(enum mxc_clock clk) diff --git a/arch/arm/include/asm/arch-mx6/clock.h b/arch/arm/include/asm/arch-mx6/clock.h index 93f29a7..95b1270 100644 --- a/arch/arm/include/asm/arch-mx6/clock.h +++ b/arch/arm/include/asm/arch-mx6/clock.h @@ -48,6 +48,7 @@ unsigned int mxc_get_clock(enum mxc_clock clk); void enable_ocotp_clk(unsigned char enable); void enable_usboh3_clk(unsigned char enable); int enable_sata_clock(void); +int enable_pcie_clock(void); int enable_i2c_clk(unsigned char enable, unsigned i2c_num); void enable_ipu_clock(void); int enable_fec_anatop_clock(void);
On Sat, Dec 14, 2013 at 10:57 AM, Marek Vasut marex@denx.de wrote:
Split the SATA clock enabling function and add PCI express clock enabling function. The SATA clock enabling function starts up the 100MHz SATA reference PLL in ENET_PLL register, but the code can be re-used to enable the 125MHz PCIe reference in ENET_PLL, so pull this code into separate function. Moreover, add the PCIe clock enabling code.
Signed-off-by: Marek Vasut marex@denx.de Cc: Albert Aribaud albert.u.boot@aribaud.net Cc: Eric Nelson eric.nelson@boundarydevices.com Cc: Fabio Estevam fabio.estevam@freescale.com Cc: Stefano Babic sbabic@denx.de
arch/arm/cpu/armv7/mx6/clock.c | 75 ++++++++++++++++++++++++++++++----- arch/arm/include/asm/arch-mx6/clock.h | 1 + 2 files changed, 66 insertions(+), 10 deletions(-)
V2: Drop the clock teardown function, it is not needed. Instead, fix a patch for the Linux kernel to handle running link. V3: Fix some legacy coding style
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index 873d9d0..b25a954 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -404,17 +404,12 @@ u32 imx_get_fecclk(void) return decode_pll(PLL_ENET, MXC_HCLK); }
-int enable_sata_clock(void) +static int enable_enet_pll(uint32_t en) {
u32 reg = 0;s32 timeout = 100000; struct mxc_ccm_reg *const imx_ccm = (struct mxc_ccm_reg *) CCM_BASE_ADDR;/* Enable sata clock */reg = readl(&imx_ccm->CCGR5); /* CCGR5 */reg |= MXC_CCM_CCGR5_SATA_MASK;writel(reg, &imx_ccm->CCGR5);
s32 timeout = 100000;u32 reg = 0; /* Enable PLLs */ reg = readl(&imx_ccm->analog_pll_enet);@@ -429,10 +424,70 @@ int enable_sata_clock(void) return -EIO; reg &= ~BM_ANADIG_PLL_SYS_BYPASS; writel(reg, &imx_ccm->analog_pll_enet);
reg |= BM_ANADIG_PLL_ENET_ENABLE_SATA;
reg |= en; writel(reg, &imx_ccm->analog_pll_enet);return 0;+}
return 0 ;+static void ungate_sata_clock(void) +{
struct mxc_ccm_reg *const imx_ccm =(struct mxc_ccm_reg *)CCM_BASE_ADDR;/* Enable SATA clock. */setbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);+}
+static void ungate_pcie_clock(void) +{
struct mxc_ccm_reg *const imx_ccm =(struct mxc_ccm_reg *)CCM_BASE_ADDR;/* Enable PCIe clock. */setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_PCIE_MASK);+}
+int enable_sata_clock(void) +{
ungate_sata_clock();return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA);+}
+int enable_pcie_clock(void) +{
struct anatop_regs *anatop_regs =(struct anatop_regs *)ANATOP_BASE_ADDR;struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;/** Here be dragons!** The register ANATOP_MISC1 is not documented in the Freescale* MX6RM. The register that is mapped in the ANATOP space and* marked as ANATOP_MISC1 is actually documented in the PMU section* of the datasheet as PMU_MISC1.** Switch LVDS clock source to SATA (0xb), disable clock INPUT and* enable clock OUTPUT. This is important for PCI express link that* is clocked from the i.MX6.*/+#define ANADIG_ANA_MISC1_LVDSCLK1_IBEN (1 << 12) +#define ANADIG_ANA_MISC1_LVDSCLK1_OBEN (1 << 10) +#define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK 0x0000001F
clrsetbits_le32(&anatop_regs->ana_misc1,ANADIG_ANA_MISC1_LVDSCLK1_IBEN |ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK,ANADIG_ANA_MISC1_LVDSCLK1_OBEN | 0xb);/* PCIe reference clock sourced from AXI. */clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL);/* Party time! Ungate the clock to the PCIe. */ungate_sata_clock();ungate_pcie_clock();return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA |BM_ANADIG_PLL_ENET_ENABLE_PCIE);}
unsigned int mxc_get_clock(enum mxc_clock clk) diff --git a/arch/arm/include/asm/arch-mx6/clock.h b/arch/arm/include/asm/arch-mx6/clock.h index 93f29a7..95b1270 100644 --- a/arch/arm/include/asm/arch-mx6/clock.h +++ b/arch/arm/include/asm/arch-mx6/clock.h @@ -48,6 +48,7 @@ unsigned int mxc_get_clock(enum mxc_clock clk); void enable_ocotp_clk(unsigned char enable); void enable_usboh3_clk(unsigned char enable); int enable_sata_clock(void); +int enable_pcie_clock(void); int enable_i2c_clk(unsigned char enable, unsigned i2c_num); void enable_ipu_clock(void); int enable_fec_anatop_clock(void);
Acked-by: Jagannadha Sutradharudu Teki jagannadh.teki@gmail.com
Hi Marek,
On 14/12/2013 06:27, Marek Vasut wrote:
Split the SATA clock enabling function and add PCI express clock enabling function. The SATA clock enabling function starts up the 100MHz SATA reference PLL in ENET_PLL register, but the code can be re-used to enable the 125MHz PCIe reference in ENET_PLL, so pull this code into separate function. Moreover, add the PCIe clock enabling code.
Signed-off-by: Marek Vasut marex@denx.de Cc: Albert Aribaud albert.u.boot@aribaud.net Cc: Eric Nelson eric.nelson@boundarydevices.com Cc: Fabio Estevam fabio.estevam@freescale.com Cc: Stefano Babic sbabic@denx.de
Applied to u-boot-imx, thanks !
Best regards, Stefano Babic
Add PCIe driver for the Freescale i.MX6 SoC . This driver operates the PCIe block in RC mode only, the EP mode is NOT supported. The driver is tested with the Intel e1000 NIC driver.
Signed-off-by: Marek Vasut marex@denx.de Cc: Albert Aribaud albert.u.boot@aribaud.net Cc: Eric Nelson eric.nelson@boundarydevices.com Cc: Fabio Estevam fabio.estevam@freescale.com Cc: Stefano Babic sbabic@denx.de --- arch/arm/include/asm/arch-mx6/iomux.h | 27 ++ drivers/pci/Makefile | 1 + drivers/pci/pcie_imx.c | 565 ++++++++++++++++++++++++++++++++++ 3 files changed, 593 insertions(+) create mode 100644 drivers/pci/pcie_imx.c
V2: - Check for link_in_training bit while waiting for LTSSM to finish. - Replace udelay(30000) with mdelay(30) in the core reset end seq. - Check if the link-up failed and don't probe the bus in such case to prevent a hang. - Do not assert LTSSM while the DWC core is in reset (thanks for finding this, Richard Zhu)
diff --git a/arch/arm/include/asm/arch-mx6/iomux.h b/arch/arm/include/asm/arch-mx6/iomux.h index fe4675e..f9ee0d9 100644 --- a/arch/arm/include/asm/arch-mx6/iomux.h +++ b/arch/arm/include/asm/arch-mx6/iomux.h @@ -15,6 +15,33 @@ #define IOMUXC_GPR1_OTG_ID_ENET_RX_ERR (0<<13) #define IOMUXC_GPR1_OTG_ID_GPIO1 (1<<13) #define IOMUXC_GPR1_OTG_ID_MASK (1<<13) +#define IOMUXC_GPR1_REF_SSP_EN (1 << 16) +#define IOMUXC_GPR1_TEST_POWERDOWN (1 << 18) + +/* + * IOMUXC_GPR8 bit fields + */ +#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1_MASK (0x3f << 0) +#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1_OFFSET 0 +#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB_MASK (0x3f << 6) +#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB_OFFSET 6 +#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_6DB_MASK (0x3f << 12) +#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_6DB_OFFSET 12 +#define IOMUXC_GPR8_PCS_TX_SWING_FULL_MASK (0x7f << 18) +#define IOMUXC_GPR8_PCS_TX_SWING_FULL_OFFSET 18 +#define IOMUXC_GPR8_PCS_TX_SWING_LOW_MASK (0x7f << 25) +#define IOMUXC_GPR8_PCS_TX_SWING_LOW_OFFSET 25 + +/* + * IOMUXC_GPR12 bit fields + */ +#define IOMUXC_GPR12_LOS_LEVEL_9 (0x9 << 4) +#define IOMUXC_GPR12_LOS_LEVEL_MASK (0x1f << 4) +#define IOMUXC_GPR12_APPS_LTSSM_ENABLE (1 << 10) +#define IOMUXC_GPR12_DEVICE_TYPE_EP (0x0 << 12) +#define IOMUXC_GPR12_DEVICE_TYPE_RC (0x2 << 12) +#define IOMUXC_GPR12_DEVICE_TYPE_MASK (0xf << 12) + /* * IOMUXC_GPR13 bit fields */ diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile index 99d51a6..565ff37 100644 --- a/drivers/pci/Makefile +++ b/drivers/pci/Makefile @@ -9,6 +9,7 @@ obj-$(CONFIG_FSL_PCI_INIT) += fsl_pci_init.o obj-$(CONFIG_PCI) += pci.o pci_auto.o obj-$(CONFIG_PCI_INDIRECT_BRIDGE) += pci_indirect.o obj-$(CONFIG_PCI_GT64120) += pci_gt64120.o +obj-$(CONFIG_PCIE_IMX) += pcie_imx.o obj-$(CONFIG_FTPCI100) += pci_ftpci100.o obj-$(CONFIG_IXP_PCI) += pci_ixp.o obj-$(CONFIG_SH4_PCI) += pci_sh4.o diff --git a/drivers/pci/pcie_imx.c b/drivers/pci/pcie_imx.c new file mode 100644 index 0000000..0a74867 --- /dev/null +++ b/drivers/pci/pcie_imx.c @@ -0,0 +1,565 @@ +/* + * Freescale i.MX6 PCI Express Root-Complex driver + * + * Copyright (C) 2013 Marek Vasut marex@denx.de + * + * Based on upstream Linux kernel driver: + * pci-imx6.c: Sean Cross xobs@kosagi.com + * pcie-designware.c: Jingoo Han jg1.han@samsung.com + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <pci.h> +#include <asm/arch/clock.h> +#include <asm/arch/iomux.h> +#include <asm/arch/crm_regs.h> +#include <asm/io.h> +#include <asm/sizes.h> +#include <errno.h> + +#define PCI_ACCESS_READ 0 +#define PCI_ACCESS_WRITE 1 + +#define MX6_DBI_ADDR 0x01ffc000 +#define MX6_DBI_SIZE 0x4000 +#define MX6_IO_ADDR 0x01000000 +#define MX6_IO_SIZE 0x100000 +#define MX6_MEM_ADDR 0x01100000 +#define MX6_MEM_SIZE 0xe00000 +#define MX6_ROOT_ADDR 0x01f00000 +#define MX6_ROOT_SIZE 0xfc000 + +/* PCIe Port Logic registers (memory-mapped) */ +#define PL_OFFSET 0x700 +#define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28) +#define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c) +#define PCIE_PHY_DEBUG_R1_LINK_UP (1 << 4) +#define PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING (1 << 29) + +#define PCIE_PHY_CTRL (PL_OFFSET + 0x114) +#define PCIE_PHY_CTRL_DATA_LOC 0 +#define PCIE_PHY_CTRL_CAP_ADR_LOC 16 +#define PCIE_PHY_CTRL_CAP_DAT_LOC 17 +#define PCIE_PHY_CTRL_WR_LOC 18 +#define PCIE_PHY_CTRL_RD_LOC 19 + +#define PCIE_PHY_STAT (PL_OFFSET + 0x110) +#define PCIE_PHY_STAT_DATA_LOC 0 +#define PCIE_PHY_STAT_ACK_LOC 16 + +/* PHY registers (not memory-mapped) */ +#define PCIE_PHY_RX_ASIC_OUT 0x100D + +#define PHY_RX_OVRD_IN_LO 0x1005 +#define PHY_RX_OVRD_IN_LO_RX_DATA_EN (1 << 5) +#define PHY_RX_OVRD_IN_LO_RX_PLL_EN (1 << 3) + +/* iATU registers */ +#define PCIE_ATU_VIEWPORT 0x900 +#define PCIE_ATU_REGION_INBOUND (0x1 << 31) +#define PCIE_ATU_REGION_OUTBOUND (0x0 << 31) +#define PCIE_ATU_REGION_INDEX1 (0x1 << 0) +#define PCIE_ATU_REGION_INDEX0 (0x0 << 0) +#define PCIE_ATU_CR1 0x904 +#define PCIE_ATU_TYPE_MEM (0x0 << 0) +#define PCIE_ATU_TYPE_IO (0x2 << 0) +#define PCIE_ATU_TYPE_CFG0 (0x4 << 0) +#define PCIE_ATU_TYPE_CFG1 (0x5 << 0) +#define PCIE_ATU_CR2 0x908 +#define PCIE_ATU_ENABLE (0x1 << 31) +#define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30) +#define PCIE_ATU_LOWER_BASE 0x90C +#define PCIE_ATU_UPPER_BASE 0x910 +#define PCIE_ATU_LIMIT 0x914 +#define PCIE_ATU_LOWER_TARGET 0x918 +#define PCIE_ATU_BUS(x) (((x) & 0xff) << 24) +#define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19) +#define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16) +#define PCIE_ATU_UPPER_TARGET 0x91C + +/* + * PHY access functions + */ +static int pcie_phy_poll_ack(void __iomem *dbi_base, int exp_val) +{ + u32 val; + u32 max_iterations = 10; + u32 wait_counter = 0; + + do { + val = readl(dbi_base + PCIE_PHY_STAT); + val = (val >> PCIE_PHY_STAT_ACK_LOC) & 0x1; + wait_counter++; + + if (val == exp_val) + return 0; + + udelay(1); + } while (wait_counter < max_iterations); + + return -ETIMEDOUT; +} + +static int pcie_phy_wait_ack(void __iomem *dbi_base, int addr) +{ + u32 val; + int ret; + + val = addr << PCIE_PHY_CTRL_DATA_LOC; + writel(val, dbi_base + PCIE_PHY_CTRL); + + val |= (0x1 << PCIE_PHY_CTRL_CAP_ADR_LOC); + writel(val, dbi_base + PCIE_PHY_CTRL); + + ret = pcie_phy_poll_ack(dbi_base, 1); + if (ret) + return ret; + + val = addr << PCIE_PHY_CTRL_DATA_LOC; + writel(val, dbi_base + PCIE_PHY_CTRL); + + ret = pcie_phy_poll_ack(dbi_base, 0); + if (ret) + return ret; + + return 0; +} + +/* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */ +static int pcie_phy_read(void __iomem *dbi_base, int addr , int *data) +{ + u32 val, phy_ctl; + int ret; + + ret = pcie_phy_wait_ack(dbi_base, addr); + if (ret) + return ret; + + /* assert Read signal */ + phy_ctl = 0x1 << PCIE_PHY_CTRL_RD_LOC; + writel(phy_ctl, dbi_base + PCIE_PHY_CTRL); + + ret = pcie_phy_poll_ack(dbi_base, 1); + if (ret) + return ret; + + val = readl(dbi_base + PCIE_PHY_STAT); + *data = val & 0xffff; + + /* deassert Read signal */ + writel(0x00, dbi_base + PCIE_PHY_CTRL); + + ret = pcie_phy_poll_ack(dbi_base, 0); + if (ret) + return ret; + + return 0; +} + +static int pcie_phy_write(void __iomem *dbi_base, int addr, int data) +{ + u32 var; + int ret; + + /* write addr */ + /* cap addr */ + ret = pcie_phy_wait_ack(dbi_base, addr); + if (ret) + return ret; + + var = data << PCIE_PHY_CTRL_DATA_LOC; + writel(var, dbi_base + PCIE_PHY_CTRL); + + /* capture data */ + var |= (0x1 << PCIE_PHY_CTRL_CAP_DAT_LOC); + writel(var, dbi_base + PCIE_PHY_CTRL); + + ret = pcie_phy_poll_ack(dbi_base, 1); + if (ret) + return ret; + + /* deassert cap data */ + var = data << PCIE_PHY_CTRL_DATA_LOC; + writel(var, dbi_base + PCIE_PHY_CTRL); + + /* wait for ack de-assertion */ + ret = pcie_phy_poll_ack(dbi_base, 0); + if (ret) + return ret; + + /* assert wr signal */ + var = 0x1 << PCIE_PHY_CTRL_WR_LOC; + writel(var, dbi_base + PCIE_PHY_CTRL); + + /* wait for ack */ + ret = pcie_phy_poll_ack(dbi_base, 1); + if (ret) + return ret; + + /* deassert wr signal */ + var = data << PCIE_PHY_CTRL_DATA_LOC; + writel(var, dbi_base + PCIE_PHY_CTRL); + + /* wait for ack de-assertion */ + ret = pcie_phy_poll_ack(dbi_base, 0); + if (ret) + return ret; + + writel(0x0, dbi_base + PCIE_PHY_CTRL); + + return 0; +} + +static int imx6_pcie_link_up(void) +{ + u32 rc, ltssm; + int rx_valid, temp; + + /* link is debug bit 36, debug register 1 starts at bit 32 */ + rc = readl(MX6_DBI_ADDR + PCIE_PHY_DEBUG_R1); + if ((rc & PCIE_PHY_DEBUG_R1_LINK_UP) && + !(rc & PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING)) + return -EAGAIN; + + /* + * From L0, initiate MAC entry to gen2 if EP/RC supports gen2. + * Wait 2ms (LTSSM timeout is 24ms, PHY lock is ~5us in gen2). + * If (MAC/LTSSM.state == Recovery.RcvrLock) + * && (PHY/rx_valid==0) then pulse PHY/rx_reset. Transition + * to gen2 is stuck + */ + pcie_phy_read((void *)MX6_DBI_ADDR, PCIE_PHY_RX_ASIC_OUT, &rx_valid); + ltssm = readl(MX6_DBI_ADDR + PCIE_PHY_DEBUG_R0) & 0x3F; + + if (rx_valid & 0x01) + return 0; + + if (ltssm != 0x0d) + return 0; + + printf("transition to gen2 is stuck, reset PHY!\n"); + + pcie_phy_read((void *)MX6_DBI_ADDR, PHY_RX_OVRD_IN_LO, &temp); + temp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN | PHY_RX_OVRD_IN_LO_RX_PLL_EN); + pcie_phy_write((void *)MX6_DBI_ADDR, PHY_RX_OVRD_IN_LO, temp); + + udelay(3000); + + pcie_phy_read((void *)MX6_DBI_ADDR, PHY_RX_OVRD_IN_LO, &temp); + temp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN | PHY_RX_OVRD_IN_LO_RX_PLL_EN); + pcie_phy_write((void *)MX6_DBI_ADDR, PHY_RX_OVRD_IN_LO, temp); + + return 0; +} + +/* + * iATU region setup + */ +static int imx_pcie_regions_setup(void) +{ + /* + * i.MX6 defines 16MB in the AXI address map for PCIe. + * + * That address space excepted the pcie registers is + * split and defined into different regions by iATU, + * with sizes and offsets as follows: + * + * 0x0100_0000 --- 0x010F_FFFF 1MB IORESOURCE_IO + * 0x0110_0000 --- 0x01EF_FFFF 14MB IORESOURCE_MEM + * 0x01F0_0000 --- 0x01FF_FFFF 1MB Cfg + Registers + */ + + /* CMD reg:I/O space, MEM space, and Bus Master Enable */ + setbits_le32(MX6_DBI_ADDR | PCI_COMMAND, + PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); + + /* Set the CLASS_REV of RC CFG header to PCI_CLASS_BRIDGE_PCI */ + setbits_le32(MX6_DBI_ADDR + PCI_CLASS_REVISION, + PCI_CLASS_BRIDGE_PCI << 16); + + /* Region #0 is used for Outbound CFG space access. */ + writel(0, MX6_DBI_ADDR + PCIE_ATU_VIEWPORT); + + writel(MX6_ROOT_ADDR, MX6_DBI_ADDR + PCIE_ATU_LOWER_BASE); + writel(0, MX6_DBI_ADDR + PCIE_ATU_UPPER_BASE); + writel(MX6_ROOT_ADDR + MX6_ROOT_SIZE, MX6_DBI_ADDR + PCIE_ATU_LIMIT); + + writel(0, MX6_DBI_ADDR + PCIE_ATU_LOWER_TARGET); + writel(0, MX6_DBI_ADDR + PCIE_ATU_UPPER_TARGET); + writel(PCIE_ATU_TYPE_CFG0, MX6_DBI_ADDR + PCIE_ATU_CR1); + writel(PCIE_ATU_ENABLE, MX6_DBI_ADDR + PCIE_ATU_CR2); + + return 0; +} + +/* + * PCI Express accessors + */ +static uint32_t get_bus_address(pci_dev_t d, int where) +{ + uint32_t va_address; + + /* Reconfigure Region #0 */ + writel(0, MX6_DBI_ADDR + PCIE_ATU_VIEWPORT); + + if (PCI_BUS(d) < 2) + writel(PCIE_ATU_TYPE_CFG0, MX6_DBI_ADDR + PCIE_ATU_CR1); + else + writel(PCIE_ATU_TYPE_CFG1, MX6_DBI_ADDR + PCIE_ATU_CR1); + + if (PCI_BUS(d) == 0) { + va_address = MX6_DBI_ADDR; + } else { + writel(d << 8, MX6_DBI_ADDR + PCIE_ATU_LOWER_TARGET); + va_address = MX6_IO_ADDR + SZ_16M - SZ_1M; + } + + va_address += (where & ~0x3); + + return va_address; +} + +static int imx_pcie_addr_valid(pci_dev_t d) +{ + if ((PCI_BUS(d) == 0) && (PCI_DEV(d) > 1)) + return -EINVAL; + if ((PCI_BUS(d) == 1) && (PCI_DEV(d) > 0)) + return -EINVAL; + return 0; +} + +/* + * Replace the original ARM DABT handler with a simple jump-back one. + * + * The problem here is that if we have a PCIe bridge attached to this PCIe + * controller, but no PCIe device is connected to the bridges' downstream + * port, the attempt to read/write from/to the config space will produce + * a DABT. This is a behavior of the controller and can not be disabled + * unfortuatelly. + * + * To work around the problem, we backup the current DABT handler address + * and replace it with our own DABT handler, which only bounces right back + * into the code. + */ +static void imx_pcie_fix_dabt_handler(bool set) +{ + extern uint32_t *_data_abort; + uint32_t *data_abort_addr = (uint32_t *)&_data_abort; + + static const uint32_t data_abort_bounce_handler = 0xe25ef004; + uint32_t data_abort_bounce_addr = (uint32_t)&data_abort_bounce_handler; + + static uint32_t data_abort_backup; + + if (set) { + data_abort_backup = *data_abort_addr; + *data_abort_addr = data_abort_bounce_addr; + } else { + *data_abort_addr = data_abort_backup; + } +} + +static int imx_pcie_read_config(struct pci_controller *hose, pci_dev_t d, + int where, u32 *val) +{ + uint32_t va_address; + int ret; + + ret = imx_pcie_addr_valid(d); + if (ret) { + *val = 0xffffffff; + return ret; + } + + va_address = get_bus_address(d, where); + + /* + * Read the PCIe config space. We must replace the DABT handler + * here in case we got data abort from the PCIe controller, see + * imx_pcie_fix_dabt_handler() description. Note that writing the + * "val" with valid value is also imperative here as in case we + * did got DABT, the val would contain random value. + */ + imx_pcie_fix_dabt_handler(true); + writel(0xffffffff, val); + *val = readl(va_address); + imx_pcie_fix_dabt_handler(false); + + return 0; +} + +static int imx_pcie_write_config(struct pci_controller *hose, pci_dev_t d, + int where, u32 val) +{ + uint32_t va_address = 0; + int ret; + + ret = imx_pcie_addr_valid(d); + if (ret) + return ret; + + va_address = get_bus_address(d, where); + + /* + * Write the PCIe config space. We must replace the DABT handler + * here in case we got data abort from the PCIe controller, see + * imx_pcie_fix_dabt_handler() description. + */ + imx_pcie_fix_dabt_handler(true); + writel(val, va_address); + imx_pcie_fix_dabt_handler(false); + + return 0; +} + +/* + * Initial bus setup + */ +static int imx6_pcie_assert_core_reset(void) +{ + struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; + + setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_TEST_POWERDOWN); + clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_REF_SSP_EN); + + return 0; +} + +static int imx6_pcie_init_phy(void) +{ + struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; + + clrbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_APPS_LTSSM_ENABLE); + + clrsetbits_le32(&iomuxc_regs->gpr[12], + IOMUXC_GPR12_DEVICE_TYPE_MASK, + IOMUXC_GPR12_DEVICE_TYPE_RC); + clrsetbits_le32(&iomuxc_regs->gpr[12], + IOMUXC_GPR12_LOS_LEVEL_MASK, + IOMUXC_GPR12_LOS_LEVEL_9); + + writel((0x0 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1_OFFSET) | + (0x0 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB_OFFSET) | + (20 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_6DB_OFFSET) | + (127 << IOMUXC_GPR8_PCS_TX_SWING_FULL_OFFSET) | + (127 << IOMUXC_GPR8_PCS_TX_SWING_LOW_OFFSET), + &iomuxc_regs->gpr[8]); + + return 0; +} + +static int imx6_pcie_deassert_core_reset(void) +{ + struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; + + /* FIXME: Power-up GPIO goes here. */ + + /* Enable PCIe */ + clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_TEST_POWERDOWN); + setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_REF_SSP_EN); + + enable_pcie_clock(); + + /* + * Wait for the clock to settle a bit, when the clock are sourced + * from the CPU, we need about 30mS to settle. + */ + mdelay(30); + + /* FIXME: GPIO reset goes here */ + mdelay(100); + + return 0; +} + +static int imx_pcie_link_up(void) +{ + struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; + uint32_t tmp; + int count = 0; + + imx6_pcie_assert_core_reset(); + imx6_pcie_init_phy(); + imx6_pcie_deassert_core_reset(); + + imx_pcie_regions_setup(); + + /* + * FIXME: Force the PCIe RC to Gen1 operation + * The RC must be forced into Gen1 mode before bringing the link + * up, otherwise no downstream devices are detected. After the + * link is up, a managed Gen1->Gen2 transition can be initiated. + */ + tmp = readl(MX6_DBI_ADDR + 0x7c); + tmp &= ~0xf; + tmp |= 0x1; + writel(tmp, MX6_DBI_ADDR + 0x7c); + + /* LTSSM enable, starting link. */ + setbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_APPS_LTSSM_ENABLE); + + while (!imx6_pcie_link_up()) { + udelay(10); + count++; + if (count >= 2000) { + debug("phy link never came up\n"); + debug("DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n", + readl(MX6_DBI_ADDR + PCIE_PHY_DEBUG_R0), + readl(MX6_DBI_ADDR + PCIE_PHY_DEBUG_R1)); + return -EINVAL; + } + } + + return 0; +} + +void imx_pcie_init(void) +{ + /* Static instance of the controller. */ + static struct pci_controller pcc; + struct pci_controller *hose = &pcc; + int ret; + + memset(&pcc, 0, sizeof(pcc)); + + /* PCI I/O space */ + pci_set_region(&hose->regions[0], + MX6_IO_ADDR, MX6_IO_ADDR, + MX6_IO_SIZE, PCI_REGION_IO); + + /* PCI memory space */ + pci_set_region(&hose->regions[1], + MX6_MEM_ADDR, MX6_MEM_ADDR, + MX6_MEM_SIZE, PCI_REGION_MEM); + + /* System memory space */ + pci_set_region(&hose->regions[2], + MMDC0_ARB_BASE_ADDR, MMDC0_ARB_BASE_ADDR, + 0xefffffff, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); + + hose->region_count = 3; + + pci_set_ops(hose, + pci_hose_read_config_byte_via_dword, + pci_hose_read_config_word_via_dword, + imx_pcie_read_config, + pci_hose_write_config_byte_via_dword, + pci_hose_write_config_word_via_dword, + imx_pcie_write_config); + + /* Start the controller. */ + ret = imx_pcie_link_up(); + + if (!ret) { + pci_register_hose(hose); + hose->last_busno = pci_hose_scan(hose); + } +} + +/* Probe function. */ +void pci_init_board(void) +{ + imx_pcie_init(); +}
On Sat, Dec 14, 2013 at 10:25 AM, Marek Vasut marex@denx.de wrote:
Add PCIe driver for the Freescale i.MX6 SoC . This driver operates the PCIe block in RC mode only, the EP mode is NOT supported. The driver is tested with the Intel e1000 NIC driver.
Signed-off-by: Marek Vasut marex@denx.de Cc: Albert Aribaud albert.u.boot@aribaud.net Cc: Eric Nelson eric.nelson@boundarydevices.com Cc: Fabio Estevam fabio.estevam@freescale.com Cc: Stefano Babic sbabic@denx.de
arch/arm/include/asm/arch-mx6/iomux.h | 27 ++ drivers/pci/Makefile | 1 + drivers/pci/pcie_imx.c | 565 ++++++++++++++++++++++++++++++++++ 3 files changed, 593 insertions(+) create mode 100644 drivers/pci/pcie_imx.c
V2: - Check for link_in_training bit while waiting for LTSSM to finish. - Replace udelay(30000) with mdelay(30) in the core reset end seq. - Check if the link-up failed and don't probe the bus in such case to prevent a hang. - Do not assert LTSSM while the DWC core is in reset (thanks for finding this, Richard Zhu)
diff --git a/arch/arm/include/asm/arch-mx6/iomux.h b/arch/arm/include/asm/arch-mx6/iomux.h index fe4675e..f9ee0d9 100644 --- a/arch/arm/include/asm/arch-mx6/iomux.h +++ b/arch/arm/include/asm/arch-mx6/iomux.h @@ -15,6 +15,33 @@ #define IOMUXC_GPR1_OTG_ID_ENET_RX_ERR (0<<13) #define IOMUXC_GPR1_OTG_ID_GPIO1 (1<<13) #define IOMUXC_GPR1_OTG_ID_MASK (1<<13) +#define IOMUXC_GPR1_REF_SSP_EN (1 << 16) +#define IOMUXC_GPR1_TEST_POWERDOWN (1 << 18)
+/*
- IOMUXC_GPR8 bit fields
- */
+#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1_MASK (0x3f << 0) +#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1_OFFSET 0 +#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB_MASK (0x3f << 6) +#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB_OFFSET 6 +#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_6DB_MASK (0x3f << 12) +#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_6DB_OFFSET 12 +#define IOMUXC_GPR8_PCS_TX_SWING_FULL_MASK (0x7f << 18) +#define IOMUXC_GPR8_PCS_TX_SWING_FULL_OFFSET 18 +#define IOMUXC_GPR8_PCS_TX_SWING_LOW_MASK (0x7f << 25) +#define IOMUXC_GPR8_PCS_TX_SWING_LOW_OFFSET 25
+/*
- IOMUXC_GPR12 bit fields
- */
+#define IOMUXC_GPR12_LOS_LEVEL_9 (0x9 << 4) +#define IOMUXC_GPR12_LOS_LEVEL_MASK (0x1f << 4) +#define IOMUXC_GPR12_APPS_LTSSM_ENABLE (1 << 10) +#define IOMUXC_GPR12_DEVICE_TYPE_EP (0x0 << 12) +#define IOMUXC_GPR12_DEVICE_TYPE_RC (0x2 << 12) +#define IOMUXC_GPR12_DEVICE_TYPE_MASK (0xf << 12)
/*
- IOMUXC_GPR13 bit fields
*/ diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile index 99d51a6..565ff37 100644 --- a/drivers/pci/Makefile +++ b/drivers/pci/Makefile @@ -9,6 +9,7 @@ obj-$(CONFIG_FSL_PCI_INIT) += fsl_pci_init.o obj-$(CONFIG_PCI) += pci.o pci_auto.o obj-$(CONFIG_PCI_INDIRECT_BRIDGE) += pci_indirect.o obj-$(CONFIG_PCI_GT64120) += pci_gt64120.o +obj-$(CONFIG_PCIE_IMX) += pcie_imx.o obj-$(CONFIG_FTPCI100) += pci_ftpci100.o obj-$(CONFIG_IXP_PCI) += pci_ixp.o obj-$(CONFIG_SH4_PCI) += pci_sh4.o diff --git a/drivers/pci/pcie_imx.c b/drivers/pci/pcie_imx.c new file mode 100644 index 0000000..0a74867 --- /dev/null +++ b/drivers/pci/pcie_imx.c @@ -0,0 +1,565 @@ +/*
- Freescale i.MX6 PCI Express Root-Complex driver
- Copyright (C) 2013 Marek Vasut marex@denx.de
- Based on upstream Linux kernel driver:
- pci-imx6.c: Sean Cross xobs@kosagi.com
- pcie-designware.c: Jingoo Han jg1.han@samsung.com
- SPDX-License-Identifier: GPL-2.0
- */
+#include <common.h> +#include <pci.h> +#include <asm/arch/clock.h> +#include <asm/arch/iomux.h> +#include <asm/arch/crm_regs.h> +#include <asm/io.h> +#include <asm/sizes.h> +#include <errno.h>
+#define PCI_ACCESS_READ 0 +#define PCI_ACCESS_WRITE 1
+#define MX6_DBI_ADDR 0x01ffc000 +#define MX6_DBI_SIZE 0x4000 +#define MX6_IO_ADDR 0x01000000 +#define MX6_IO_SIZE 0x100000 +#define MX6_MEM_ADDR 0x01100000 +#define MX6_MEM_SIZE 0xe00000 +#define MX6_ROOT_ADDR 0x01f00000 +#define MX6_ROOT_SIZE 0xfc000
+/* PCIe Port Logic registers (memory-mapped) */ +#define PL_OFFSET 0x700 +#define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28) +#define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c) +#define PCIE_PHY_DEBUG_R1_LINK_UP (1 << 4) +#define PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING (1 << 29)
+#define PCIE_PHY_CTRL (PL_OFFSET + 0x114) +#define PCIE_PHY_CTRL_DATA_LOC 0 +#define PCIE_PHY_CTRL_CAP_ADR_LOC 16 +#define PCIE_PHY_CTRL_CAP_DAT_LOC 17 +#define PCIE_PHY_CTRL_WR_LOC 18 +#define PCIE_PHY_CTRL_RD_LOC 19
+#define PCIE_PHY_STAT (PL_OFFSET + 0x110) +#define PCIE_PHY_STAT_DATA_LOC 0 +#define PCIE_PHY_STAT_ACK_LOC 16
+/* PHY registers (not memory-mapped) */ +#define PCIE_PHY_RX_ASIC_OUT 0x100D
+#define PHY_RX_OVRD_IN_LO 0x1005 +#define PHY_RX_OVRD_IN_LO_RX_DATA_EN (1 << 5) +#define PHY_RX_OVRD_IN_LO_RX_PLL_EN (1 << 3)
+/* iATU registers */ +#define PCIE_ATU_VIEWPORT 0x900 +#define PCIE_ATU_REGION_INBOUND (0x1 << 31) +#define PCIE_ATU_REGION_OUTBOUND (0x0 << 31) +#define PCIE_ATU_REGION_INDEX1 (0x1 << 0) +#define PCIE_ATU_REGION_INDEX0 (0x0 << 0) +#define PCIE_ATU_CR1 0x904 +#define PCIE_ATU_TYPE_MEM (0x0 << 0) +#define PCIE_ATU_TYPE_IO (0x2 << 0) +#define PCIE_ATU_TYPE_CFG0 (0x4 << 0) +#define PCIE_ATU_TYPE_CFG1 (0x5 << 0) +#define PCIE_ATU_CR2 0x908 +#define PCIE_ATU_ENABLE (0x1 << 31) +#define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30) +#define PCIE_ATU_LOWER_BASE 0x90C +#define PCIE_ATU_UPPER_BASE 0x910 +#define PCIE_ATU_LIMIT 0x914 +#define PCIE_ATU_LOWER_TARGET 0x918 +#define PCIE_ATU_BUS(x) (((x) & 0xff) << 24) +#define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19) +#define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16) +#define PCIE_ATU_UPPER_TARGET 0x91C
+/*
- PHY access functions
- */
+static int pcie_phy_poll_ack(void __iomem *dbi_base, int exp_val) +{
u32 val;u32 max_iterations = 10;u32 wait_counter = 0;do {val = readl(dbi_base + PCIE_PHY_STAT);val = (val >> PCIE_PHY_STAT_ACK_LOC) & 0x1;wait_counter++;if (val == exp_val)return 0;udelay(1);} while (wait_counter < max_iterations);return -ETIMEDOUT;+}
+static int pcie_phy_wait_ack(void __iomem *dbi_base, int addr) +{
u32 val;int ret;val = addr << PCIE_PHY_CTRL_DATA_LOC;writel(val, dbi_base + PCIE_PHY_CTRL);val |= (0x1 << PCIE_PHY_CTRL_CAP_ADR_LOC);writel(val, dbi_base + PCIE_PHY_CTRL);ret = pcie_phy_poll_ack(dbi_base, 1);if (ret)return ret;val = addr << PCIE_PHY_CTRL_DATA_LOC;writel(val, dbi_base + PCIE_PHY_CTRL);ret = pcie_phy_poll_ack(dbi_base, 0);if (ret)return ret;return 0;+}
+/* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */ +static int pcie_phy_read(void __iomem *dbi_base, int addr , int *data) +{
u32 val, phy_ctl;int ret;ret = pcie_phy_wait_ack(dbi_base, addr);if (ret)return ret;/* assert Read signal */phy_ctl = 0x1 << PCIE_PHY_CTRL_RD_LOC;writel(phy_ctl, dbi_base + PCIE_PHY_CTRL);ret = pcie_phy_poll_ack(dbi_base, 1);if (ret)return ret;val = readl(dbi_base + PCIE_PHY_STAT);*data = val & 0xffff;/* deassert Read signal */writel(0x00, dbi_base + PCIE_PHY_CTRL);ret = pcie_phy_poll_ack(dbi_base, 0);if (ret)return ret;return 0;+}
+static int pcie_phy_write(void __iomem *dbi_base, int addr, int data) +{
u32 var;int ret;/* write addr *//* cap addr */ret = pcie_phy_wait_ack(dbi_base, addr);if (ret)return ret;var = data << PCIE_PHY_CTRL_DATA_LOC;writel(var, dbi_base + PCIE_PHY_CTRL);/* capture data */var |= (0x1 << PCIE_PHY_CTRL_CAP_DAT_LOC);writel(var, dbi_base + PCIE_PHY_CTRL);ret = pcie_phy_poll_ack(dbi_base, 1);if (ret)return ret;/* deassert cap data */var = data << PCIE_PHY_CTRL_DATA_LOC;writel(var, dbi_base + PCIE_PHY_CTRL);/* wait for ack de-assertion */ret = pcie_phy_poll_ack(dbi_base, 0);if (ret)return ret;/* assert wr signal */var = 0x1 << PCIE_PHY_CTRL_WR_LOC;writel(var, dbi_base + PCIE_PHY_CTRL);/* wait for ack */ret = pcie_phy_poll_ack(dbi_base, 1);if (ret)return ret;/* deassert wr signal */var = data << PCIE_PHY_CTRL_DATA_LOC;writel(var, dbi_base + PCIE_PHY_CTRL);/* wait for ack de-assertion */ret = pcie_phy_poll_ack(dbi_base, 0);if (ret)return ret;writel(0x0, dbi_base + PCIE_PHY_CTRL);return 0;+}
+static int imx6_pcie_link_up(void) +{
u32 rc, ltssm;int rx_valid, temp;/* link is debug bit 36, debug register 1 starts at bit 32 */rc = readl(MX6_DBI_ADDR + PCIE_PHY_DEBUG_R1);if ((rc & PCIE_PHY_DEBUG_R1_LINK_UP) &&!(rc & PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING))return -EAGAIN;/** From L0, initiate MAC entry to gen2 if EP/RC supports gen2.* Wait 2ms (LTSSM timeout is 24ms, PHY lock is ~5us in gen2).* If (MAC/LTSSM.state == Recovery.RcvrLock)* && (PHY/rx_valid==0) then pulse PHY/rx_reset. Transition* to gen2 is stuck*/pcie_phy_read((void *)MX6_DBI_ADDR, PCIE_PHY_RX_ASIC_OUT, &rx_valid);ltssm = readl(MX6_DBI_ADDR + PCIE_PHY_DEBUG_R0) & 0x3F;if (rx_valid & 0x01)return 0;if (ltssm != 0x0d)return 0;printf("transition to gen2 is stuck, reset PHY!\n");pcie_phy_read((void *)MX6_DBI_ADDR, PHY_RX_OVRD_IN_LO, &temp);temp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN | PHY_RX_OVRD_IN_LO_RX_PLL_EN);pcie_phy_write((void *)MX6_DBI_ADDR, PHY_RX_OVRD_IN_LO, temp);udelay(3000);pcie_phy_read((void *)MX6_DBI_ADDR, PHY_RX_OVRD_IN_LO, &temp);temp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN | PHY_RX_OVRD_IN_LO_RX_PLL_EN);pcie_phy_write((void *)MX6_DBI_ADDR, PHY_RX_OVRD_IN_LO, temp);return 0;+}
+/*
- iATU region setup
- */
+static int imx_pcie_regions_setup(void) +{
/** i.MX6 defines 16MB in the AXI address map for PCIe.** That address space excepted the pcie registers is* split and defined into different regions by iATU,* with sizes and offsets as follows:** 0x0100_0000 --- 0x010F_FFFF 1MB IORESOURCE_IO* 0x0110_0000 --- 0x01EF_FFFF 14MB IORESOURCE_MEM* 0x01F0_0000 --- 0x01FF_FFFF 1MB Cfg + Registers*//* CMD reg:I/O space, MEM space, and Bus Master Enable */setbits_le32(MX6_DBI_ADDR | PCI_COMMAND,PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);/* Set the CLASS_REV of RC CFG header to PCI_CLASS_BRIDGE_PCI */setbits_le32(MX6_DBI_ADDR + PCI_CLASS_REVISION,PCI_CLASS_BRIDGE_PCI << 16);/* Region #0 is used for Outbound CFG space access. */writel(0, MX6_DBI_ADDR + PCIE_ATU_VIEWPORT);writel(MX6_ROOT_ADDR, MX6_DBI_ADDR + PCIE_ATU_LOWER_BASE);writel(0, MX6_DBI_ADDR + PCIE_ATU_UPPER_BASE);writel(MX6_ROOT_ADDR + MX6_ROOT_SIZE, MX6_DBI_ADDR + PCIE_ATU_LIMIT);writel(0, MX6_DBI_ADDR + PCIE_ATU_LOWER_TARGET);writel(0, MX6_DBI_ADDR + PCIE_ATU_UPPER_TARGET);writel(PCIE_ATU_TYPE_CFG0, MX6_DBI_ADDR + PCIE_ATU_CR1);writel(PCIE_ATU_ENABLE, MX6_DBI_ADDR + PCIE_ATU_CR2);return 0;+}
+/*
- PCI Express accessors
- */
+static uint32_t get_bus_address(pci_dev_t d, int where) +{
uint32_t va_address;/* Reconfigure Region #0 */writel(0, MX6_DBI_ADDR + PCIE_ATU_VIEWPORT);if (PCI_BUS(d) < 2)writel(PCIE_ATU_TYPE_CFG0, MX6_DBI_ADDR + PCIE_ATU_CR1);elsewritel(PCIE_ATU_TYPE_CFG1, MX6_DBI_ADDR + PCIE_ATU_CR1);if (PCI_BUS(d) == 0) {va_address = MX6_DBI_ADDR;} else {writel(d << 8, MX6_DBI_ADDR + PCIE_ATU_LOWER_TARGET);va_address = MX6_IO_ADDR + SZ_16M - SZ_1M;}va_address += (where & ~0x3);return va_address;+}
+static int imx_pcie_addr_valid(pci_dev_t d) +{
if ((PCI_BUS(d) == 0) && (PCI_DEV(d) > 1))return -EINVAL;if ((PCI_BUS(d) == 1) && (PCI_DEV(d) > 0))return -EINVAL;return 0;+}
+/*
- Replace the original ARM DABT handler with a simple jump-back one.
- The problem here is that if we have a PCIe bridge attached to this PCIe
- controller, but no PCIe device is connected to the bridges' downstream
- port, the attempt to read/write from/to the config space will produce
- a DABT. This is a behavior of the controller and can not be disabled
- unfortuatelly.
- To work around the problem, we backup the current DABT handler address
- and replace it with our own DABT handler, which only bounces right back
- into the code.
- */
+static void imx_pcie_fix_dabt_handler(bool set) +{
extern uint32_t *_data_abort;
Not a good idea to use extern in .c - any comments?
On Saturday, December 14, 2013 at 06:23:30 AM, Jagan Teki wrote: [...]
+/*
- Replace the original ARM DABT handler with a simple jump-back one.
- The problem here is that if we have a PCIe bridge attached to this
PCIe + * controller, but no PCIe device is connected to the bridges' downstream + * port, the attempt to read/write from/to the config space will produce + * a DABT. This is a behavior of the controller and can not be disabled + * unfortuatelly.
- To work around the problem, we backup the current DABT handler
address + * and replace it with our own DABT handler, which only bounces right back + * into the code.
- */
+static void imx_pcie_fix_dabt_handler(bool set) +{
extern uint32_t *_data_abort;Not a good idea to use extern in .c - any comments?
Why is half of the CC dropped from this email? (restored by hand)
As for the extern, there is no better way to replace the DABT handler (see patch 0001) for this purpose . This will be changed later though, once Alberts' patches land , but that's a post-2014.01 matter.
Best regards, Marek Vasut
On Sat, Dec 14, 2013 at 11:03 AM, Marek Vasut marex@denx.de wrote:
On Saturday, December 14, 2013 at 06:23:30 AM, Jagan Teki wrote: [...]
+/*
- Replace the original ARM DABT handler with a simple jump-back one.
- The problem here is that if we have a PCIe bridge attached to this
PCIe + * controller, but no PCIe device is connected to the bridges' downstream + * port, the attempt to read/write from/to the config space will produce + * a DABT. This is a behavior of the controller and can not be disabled + * unfortuatelly.
- To work around the problem, we backup the current DABT handler
address + * and replace it with our own DABT handler, which only bounces right back + * into the code.
- */
+static void imx_pcie_fix_dabt_handler(bool set) +{
extern uint32_t *_data_abort;Not a good idea to use extern in .c - any comments?
Why is half of the CC dropped from this email? (restored by hand)
Sorry, some accident.
As for the extern, there is no better way to replace the DABT handler (see patch 0001) for this purpose . This will be changed later though, once Alberts' patches land , but that's a post-2014.01 matter.
OK.
And one more thing, where is the patch V2, 1/4 - I couldn't find it.
On Saturday, December 14, 2013 at 09:52:21 AM, Jagan Teki wrote:
On Sat, Dec 14, 2013 at 11:03 AM, Marek Vasut marex@denx.de wrote:
On Saturday, December 14, 2013 at 06:23:30 AM, Jagan Teki wrote: [...]
+/*
- Replace the original ARM DABT handler with a simple jump-back one.
- The problem here is that if we have a PCIe bridge attached to this
PCIe + * controller, but no PCIe device is connected to the bridges' downstream + * port, the attempt to read/write from/to the config space will produce + * a DABT. This is a behavior of the controller and can not be disabled + * unfortuatelly.
- To work around the problem, we backup the current DABT handler
address + * and replace it with our own DABT handler, which only bounces right back + * into the code.
- */
+static void imx_pcie_fix_dabt_handler(bool set) +{
extern uint32_t *_data_abort;Not a good idea to use extern in .c - any comments?
Why is half of the CC dropped from this email? (restored by hand)
Sorry, some accident.
As for the extern, there is no better way to replace the DABT handler (see patch 0001) for this purpose . This will be changed later though, once Alberts' patches land , but that's a post-2014.01 matter.
OK.
And one more thing, where is the patch V2, 1/4 - I couldn't find it.
Nowhere, 1/4 didn't change.
Best regards, Marek Vasut
Hi Marek,
On 14/12/2013 05:55, Marek Vasut wrote:
Add PCIe driver for the Freescale i.MX6 SoC . This driver operates the PCIe block in RC mode only, the EP mode is NOT supported. The driver is tested with the Intel e1000 NIC driver.
Signed-off-by: Marek Vasut marex@denx.de Cc: Albert Aribaud albert.u.boot@aribaud.net Cc: Eric Nelson eric.nelson@boundarydevices.com Cc: Fabio Estevam fabio.estevam@freescale.com Cc: Stefano Babic sbabic@denx.de
Applied to u-boot-imx, thanks !
Best regards, Stefano Babic
----- ===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de =====================================================================
Enable PCI express on MX6 Sabrelite.
Signed-off-by: Marek Vasut marex@denx.de Cc: Albert Aribaud albert.u.boot@aribaud.net Cc: Eric Nelson eric.nelson@boundarydevices.com Cc: Fabio Estevam fabio.estevam@freescale.com Cc: Stefano Babic sbabic@denx.de --- include/configs/nitrogen6x.h | 11 +++++++++++ 1 file changed, 11 insertions(+)
V2: Enable just the PCI express, nothing more.
diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h index 957dabe..71dfe39 100644 --- a/include/configs/nitrogen6x.h +++ b/include/configs/nitrogen6x.h @@ -351,4 +351,15 @@ #define CONFIG_SUPPORT_RAW_INITRD #define CONFIG_CMD_FS_GENERIC
+/* + * PCI express + */ +#define CONFIG_CMD_PCI +#ifdef CONFIG_CMD_PCI +#define CONFIG_PCI +#define CONFIG_PCI_PNP +#define CONFIG_PCI_SCAN_SHOW +#define CONFIG_PCIE_IMX +#endif + #endif /* __CONFIG_H */
Hi Marek,
On 14/12/2013 05:55, Marek Vasut wrote:
Enable PCI express on MX6 Sabrelite.
Signed-off-by: Marek Vasut marex@denx.de Cc: Albert Aribaud albert.u.boot@aribaud.net Cc: Eric Nelson eric.nelson@boundarydevices.com Cc: Fabio Estevam fabio.estevam@freescale.com Cc: Stefano Babic sbabic@denx.de
Applied to u-boot-imx, thanks !
Best regards, Stefano Babic
Hi Marek,
On 14/12/2013 05:55, Marek Vasut wrote:
Make indirect vectors addresses global, so they can be replaced by various code that needs to do so. For example the MX6 PCI express driver needs to temporarily replace data abort handler when reading the config space.
Signed-off-by: Marek Vasut marex@denx.de Cc: Albert Aribaud albert.u.boot@aribaud.net Cc: Eric Nelson eric.nelson@boundarydevices.com Cc: Fabio Estevam fabio.estevam@freescale.com Cc: Stefano Babic sbabic@denx.de
Applied (due to dependencies with the rest of pathset) to u-boot-imx, thanks !
Best regards, Stefano Babic
participants (3)
-
Jagan Teki -
Marek Vasut -
Stefano Babic