[U-Boot] [PATCH] Tegra210: add QSPI driver
From: Yen Lin yelin@nvidia.com
Tested on P2571 board with Winbond SPI ROM. sf probe 2:0 to see SPI chip. Flashed U-Boot image to SPI, rebooted, read back data to RAM with sf read, then verified crc against original binary file.
Author: Yen Lin yelin@nvidia.com Signed-off-by: Yen Lin yelin@nvidia.com Signed-off-by: Tom Warren twarren@nvidia.com --- board/nvidia/p2571/pinmux-config-p2571.h | 14 +- configs/p2571_defconfig | 1 + drivers/spi/Kconfig | 5 + drivers/spi/Makefile | 1 + drivers/spi/tegra210_qspi.c | 424 +++++++++++++++++++++++++++++++ 5 files changed, 439 insertions(+), 6 deletions(-) create mode 100644 drivers/spi/tegra210_qspi.c
diff --git a/board/nvidia/p2571/pinmux-config-p2571.h b/board/nvidia/p2571/pinmux-config-p2571.h index d323301..83b4b99 100644 --- a/board/nvidia/p2571/pinmux-config-p2571.h +++ b/board/nvidia/p2571/pinmux-config-p2571.h @@ -210,12 +210,14 @@ static const struct pmux_pingrp_config p2571_pingrps[] = { PINCFG(DP_HPD0_PCC6, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), PINCFG(PCC7, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, NORMAL), PINCFG(SPI2_CS1_PDD0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(QSPI_SCK_PEE0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(QSPI_CS_N_PEE1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(QSPI_IO0_PEE2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(QSPI_IO1_PEE3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(QSPI_IO2_PEE4, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(QSPI_IO3_PEE5, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + + PINCFG(QSPI_SCK_PEE0, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(QSPI_CS_N_PEE1, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(QSPI_IO0_PEE2, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(QSPI_IO1_PEE3, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(QSPI_IO2_PEE4, QSPI, UP, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(QSPI_IO3_PEE5, QSPI, UP, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(CORE_PWR_REQ, CORE, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), PINCFG(CPU_PWR_REQ, CPU, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), PINCFG(PWR_INT_N, PMI, UP, NORMAL, INPUT, DISABLE, DEFAULT), diff --git a/configs/p2571_defconfig b/configs/p2571_defconfig index 5a592e9..7c19428 100644 --- a/configs/p2571_defconfig +++ b/configs/p2571_defconfig @@ -12,5 +12,6 @@ CONFIG_SYS_PROMPT="Tegra210 (P2571) # " # CONFIG_CMD_NFS is not set CONFIG_SPI_FLASH=y CONFIG_TEGRA114_SPI=y +CONFIG_TEGRA210_QSPI=y CONFIG_USB=y CONFIG_DM_USB=y diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 8e04fce..168f31d 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -115,6 +115,11 @@ config TEGRA20_SLINK be used to access the SPI NOR flash on platforms embedding this nVidia Tegra20/Tegra30 IP cores.
+config TEGRA210_QSPI + bool "nVidia Tegra210 QSPI driver" + help + Enable the Tegra Quad-SPI (QSPI) driver for T210. + config XILINX_SPI bool "Xilinx SPI driver" help diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index de241be..209a41e 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -46,6 +46,7 @@ obj-$(CONFIG_SH_QSPI) += sh_qspi.o obj-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o obj-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o obj-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o +obj-$(CONFIG_TEGRA210_QSPI) += tegra210_qspi.o obj-$(CONFIG_TI_QSPI) += ti_qspi.o obj-$(CONFIG_XILINX_SPI) += xilinx_spi.o obj-$(CONFIG_ZYNQ_SPI) += zynq_spi.o diff --git a/drivers/spi/tegra210_qspi.c b/drivers/spi/tegra210_qspi.c new file mode 100644 index 0000000..d827667 --- /dev/null +++ b/drivers/spi/tegra210_qspi.c @@ -0,0 +1,424 @@ +/* + * NVIDIA Tegra QSPI controller (T210) + * + * Copyright (c) 2015 NVIDIA Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <dm.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch-tegra/clk_rst.h> +#include <spi.h> +#include <fdtdec.h> +#include "tegra_spi.h" + +DECLARE_GLOBAL_DATA_PTR; + +/* COMMAND1 */ +#define QSPI_CMD1_GO (1 << 31) +#define QSPI_CMD1_M_S (1 << 30) +#define QSPI_CMD1_MODE_MASK 0x3 +#define QSPI_CMD1_MODE_SHIFT 28 +#define QSPI_CMD1_CS_SEL_MASK 0x3 +#define QSPI_CMD1_CS_SEL_SHIFT 26 +#define QSPI_CMD1_CS_POL_INACTIVE0 (1 << 22) +#define QSPI_CMD1_CS_SW_HW (1 << 21) +#define QSPI_CMD1_CS_SW_VAL (1 << 20) +#define QSPI_CMD1_IDLE_SDA_MASK 0x3 +#define QSPI_CMD1_IDLE_SDA_SHIFT 18 +#define QSPI_CMD1_BIDIR (1 << 17) +#define QSPI_CMD1_LSBI_FE (1 << 16) +#define QSPI_CMD1_LSBY_FE (1 << 15) +#define QSPI_CMD1_BOTH_EN_BIT (1 << 14) +#define QSPI_CMD1_BOTH_EN_BYTE (1 << 13) +#define QSPI_CMD1_RX_EN (1 << 12) +#define QSPI_CMD1_TX_EN (1 << 11) +#define QSPI_CMD1_PACKED (1 << 5) +#define QSPI_CMD1_BITLEN_MASK 0x1F +#define QSPI_CMD1_BITLEN_SHIFT 0 + +/* COMMAND2 */ +#define QSPI_CMD2_TX_CLK_TAP_DELAY (1 << 6) +#define QSPI_CMD2_TX_CLK_TAP_DELAY_MASK (0x3F << 6) +#define QSPI_CMD2_RX_CLK_TAP_DELAY (1 << 0) +#define QSPI_CMD2_RX_CLK_TAP_DELAY_MASK (0x3F << 0) + +/* TRANSFER STATUS */ +#define QSPI_XFER_STS_RDY (1 << 30) + +/* FIFO STATUS */ +#define QSPI_FIFO_STS_CS_INACTIVE (1 << 31) +#define QSPI_FIFO_STS_FRAME_END (1 << 30) +#define QSPI_FIFO_STS_RX_FIFO_FLUSH (1 << 15) +#define QSPI_FIFO_STS_TX_FIFO_FLUSH (1 << 14) +#define QSPI_FIFO_STS_ERR (1 << 8) +#define QSPI_FIFO_STS_TX_FIFO_OVF (1 << 7) +#define QSPI_FIFO_STS_TX_FIFO_UNR (1 << 6) +#define QSPI_FIFO_STS_RX_FIFO_OVF (1 << 5) +#define QSPI_FIFO_STS_RX_FIFO_UNR (1 << 4) +#define QSPI_FIFO_STS_TX_FIFO_FULL (1 << 3) +#define QSPI_FIFO_STS_TX_FIFO_EMPTY (1 << 2) +#define QSPI_FIFO_STS_RX_FIFO_FULL (1 << 1) +#define QSPI_FIFO_STS_RX_FIFO_EMPTY (1 << 0) + +#define QSPI_TIMEOUT 1000 + +struct qspi_regs { + u32 command1; /* 000:QSPI_COMMAND1 register */ + u32 command2; /* 004:QSPI_COMMAND2 register */ + u32 timing1; /* 008:QSPI_CS_TIM1 register */ + u32 timing2; /* 00c:QSPI_CS_TIM2 register */ + u32 xfer_status;/* 010:QSPI_TRANS_STATUS register */ + u32 fifo_status;/* 014:QSPI_FIFO_STATUS register */ + u32 tx_data; /* 018:QSPI_TX_DATA register */ + u32 rx_data; /* 01c:QSPI_RX_DATA register */ + u32 dma_ctl; /* 020:QSPI_DMA_CTL register */ + u32 dma_blk; /* 024:QSPI_DMA_BLK register */ + u32 rsvd[56]; /* 028-107 reserved */ + u32 tx_fifo; /* 108:QSPI_FIFO1 register */ + u32 rsvd2[31]; /* 10c-187 reserved */ + u32 rx_fifo; /* 188:QSPI_FIFO2 register */ + u32 spare_ctl; /* 18c:QSPI_SPARE_CTRL register */ +}; + +struct tegra210_qspi_priv { + struct qspi_regs *regs; + unsigned int freq; + unsigned int mode; + int periph_id; + int valid; + int last_transaction_us; +}; + +static int tegra210_qspi_ofdata_to_platdata(struct udevice *bus) +{ + struct tegra_spi_platdata *plat = bus->platdata; + const void *blob = gd->fdt_blob; + int node = bus->of_offset; + + plat->base = fdtdec_get_addr(blob, node, "reg"); + plat->periph_id = clock_decode_periph_id(blob, node); + + if (plat->periph_id == PERIPH_ID_NONE) { + debug("%s: could not decode periph id %d\n", __func__, + plat->periph_id); + return -FDT_ERR_NOTFOUND; + } + + /* Use 500KHz as a suitable default */ + plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency", + 500000); + plat->deactivate_delay_us = fdtdec_get_int(blob, node, + "spi-deactivate-delay", 0); + debug("%s: base=%#08lx, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n", + __func__, plat->base, plat->periph_id, plat->frequency, + plat->deactivate_delay_us); + + return 0; +} + +static int tegra210_qspi_probe(struct udevice *bus) +{ + struct tegra_spi_platdata *plat = dev_get_platdata(bus); + struct tegra210_qspi_priv *priv = dev_get_priv(bus); + + priv->regs = (struct qspi_regs *)plat->base; + + priv->last_transaction_us = timer_get_us(); + priv->freq = plat->frequency; + priv->periph_id = plat->periph_id; + + return 0; +} + +static int tegra210_qspi_claim_bus(struct udevice *bus) +{ + struct tegra210_qspi_priv *priv = dev_get_priv(bus); + struct qspi_regs *regs = priv->regs; + + /* Change SPI clock to correct frequency, PLLP_OUT0 source */ + clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH, priv->freq); + + /* Clear stale status here */ + setbits_le32(®s->fifo_status, + QSPI_FIFO_STS_ERR | + QSPI_FIFO_STS_TX_FIFO_OVF | + QSPI_FIFO_STS_TX_FIFO_UNR | + QSPI_FIFO_STS_RX_FIFO_OVF | + QSPI_FIFO_STS_RX_FIFO_UNR | + QSPI_FIFO_STS_TX_FIFO_FULL | + QSPI_FIFO_STS_TX_FIFO_EMPTY | + QSPI_FIFO_STS_RX_FIFO_FULL | + QSPI_FIFO_STS_RX_FIFO_EMPTY); + debug("%s: FIFO STATUS = %08x\n", __func__, readl(®s->fifo_status)); + + /* Set master mode and sw controlled CS */ + setbits_le32(®s->command1, QSPI_CMD1_M_S | QSPI_CMD1_CS_SW_HW | + (priv->mode << QSPI_CMD1_MODE_SHIFT)); + debug("%s: COMMAND1 = %08x\n", __func__, readl(®s->command1)); + + return 0; +} + +/** + * Activate the CS by driving it LOW + * + * @param slave Pointer to spi_slave to which controller has to + * communicate with + */ +static void spi_cs_activate(struct udevice *dev) +{ + struct udevice *bus = dev->parent; + struct tegra_spi_platdata *pdata = dev_get_platdata(bus); + struct tegra210_qspi_priv *priv = dev_get_priv(bus); + + /* If it's too soon to do another transaction, wait */ + if (pdata->deactivate_delay_us && + priv->last_transaction_us) { + ulong delay_us; /* The delay completed so far */ + delay_us = timer_get_us() - priv->last_transaction_us; + if (delay_us < pdata->deactivate_delay_us) + udelay(pdata->deactivate_delay_us - delay_us); + } + + clrbits_le32(&priv->regs->command1, QSPI_CMD1_CS_SW_VAL); +} + +/** + * Deactivate the CS by driving it HIGH + * + * @param slave Pointer to spi_slave to which controller has to + * communicate with + */ +static void spi_cs_deactivate(struct udevice *dev) +{ + struct udevice *bus = dev->parent; + struct tegra_spi_platdata *pdata = dev_get_platdata(bus); + struct tegra210_qspi_priv *priv = dev_get_priv(bus); + + setbits_le32(&priv->regs->command1, QSPI_CMD1_CS_SW_VAL); + + /* Remember time of this transaction so we can honour the bus delay */ + if (pdata->deactivate_delay_us) + priv->last_transaction_us = timer_get_us(); + + debug("Deactivate CS, bus '%s'\n", bus->name); +} + +static int tegra210_qspi_xfer(struct udevice *dev, unsigned int bitlen, + const void *data_out, void *data_in, + unsigned long flags) +{ + struct udevice *bus = dev->parent; + struct tegra210_qspi_priv *priv = dev_get_priv(bus); + struct qspi_regs *regs = priv->regs; + u32 reg, tmpdout, tmpdin = 0; + const u8 *dout = data_out; + u8 *din = data_in; + int num_bytes; + int ret; + + debug("%s: slave %u:%u dout %p din %p bitlen %u\n", + __func__, bus->seq, spi_chip_select(dev), dout, din, bitlen); + if (bitlen % 8) + return -1; + num_bytes = bitlen / 8; + + ret = 0; + + /* clear all error status bits */ + reg = readl(®s->fifo_status); + writel(reg, ®s->fifo_status); + + /* flush RX/TX FIFOs */ + setbits_le32(®s->fifo_status, + (QSPI_FIFO_STS_RX_FIFO_FLUSH | QSPI_FIFO_STS_TX_FIFO_FLUSH)); + while ((readl(®s->fifo_status) & + (QSPI_FIFO_STS_RX_FIFO_FLUSH | QSPI_FIFO_STS_TX_FIFO_FLUSH))) + ; + + /* + * Notes: + * 1. don't set LSBY_FE, so no need to swap bytes from/to TX/RX FIFOs; + * 2. don't set RX_EN and TX_EN yet. + * (SW needs to make sure that while programming the blk_size, + * tx_en and rx_en bits must be zero) + * [TODO] I (Yen Lin) have problems when both RX/TX EN bits are set + * i.e., both dout and din are not NULL. + */ + clrsetbits_le32(®s->command1, + (QSPI_CMD1_LSBI_FE | QSPI_CMD1_LSBY_FE | + QSPI_CMD1_RX_EN | QSPI_CMD1_TX_EN), + (spi_chip_select(dev) << QSPI_CMD1_CS_SEL_SHIFT)); + + /* set xfer size to 1 block (32 bits) */ + writel(0, ®s->dma_blk); + + if (flags & SPI_XFER_BEGIN) + spi_cs_activate(dev); + + /* handle data in 32-bit chunks */ + while (num_bytes > 0) { + int bytes; + int tm; + + tmpdout = 0; + bytes = (num_bytes > 4) ? 4 : num_bytes; + + if (dout != NULL) { + memcpy((void *)&tmpdout, (void *)dout, bytes); + dout += bytes; + num_bytes -= bytes; + writel(tmpdout, ®s->tx_fifo); + setbits_le32(®s->command1, QSPI_CMD1_TX_EN); + } + + if (din != NULL) + setbits_le32(®s->command1, QSPI_CMD1_RX_EN); + + /* clear ready bit */ + setbits_le32(®s->xfer_status, QSPI_XFER_STS_RDY); + + clrsetbits_le32(®s->command1, + QSPI_CMD1_BITLEN_MASK << QSPI_CMD1_BITLEN_SHIFT, + (bytes * 8 - 1) << QSPI_CMD1_BITLEN_SHIFT); + /* Need to stabilize other reg bit before GO bit set */ + udelay(2); + setbits_le32(®s->command1, QSPI_CMD1_GO); + udelay(1); + + /* + * Wait for SPI transmit FIFO to empty, or to time out. + * The RX FIFO status will be read and cleared last + */ + for (tm = 0; tm < QSPI_TIMEOUT; ++tm) { + u32 fifo_status, xfer_status; + + xfer_status = readl(®s->xfer_status); + if (!(xfer_status & QSPI_XFER_STS_RDY)) + continue; + + fifo_status = readl(®s->fifo_status); + if (fifo_status & QSPI_FIFO_STS_ERR) { + debug("%s: got a fifo error: ", __func__); + if (fifo_status & QSPI_FIFO_STS_TX_FIFO_OVF) + debug("tx FIFO overflow "); + if (fifo_status & QSPI_FIFO_STS_TX_FIFO_UNR) + debug("tx FIFO underrun "); + if (fifo_status & QSPI_FIFO_STS_RX_FIFO_OVF) + debug("rx FIFO overflow "); + if (fifo_status & QSPI_FIFO_STS_RX_FIFO_UNR) + debug("rx FIFO underrun "); + if (fifo_status & QSPI_FIFO_STS_TX_FIFO_FULL) + debug("tx FIFO full "); + if (fifo_status & QSPI_FIFO_STS_TX_FIFO_EMPTY) + debug("tx FIFO empty "); + if (fifo_status & QSPI_FIFO_STS_RX_FIFO_FULL) + debug("rx FIFO full "); + if (fifo_status & QSPI_FIFO_STS_RX_FIFO_EMPTY) + debug("rx FIFO empty "); + debug("\n"); + break; + } + + if (!(fifo_status & QSPI_FIFO_STS_RX_FIFO_EMPTY)) { + tmpdin = readl(®s->rx_fifo); + if (din != NULL) { + memcpy(din, &tmpdin, bytes); + din += bytes; + num_bytes -= bytes; + } + } + break; + } + + if (tm >= QSPI_TIMEOUT) + ret = tm; + + /* clear ACK RDY, etc. bits */ + writel(readl(®s->fifo_status), ®s->fifo_status); + } + + if (flags & SPI_XFER_END) + spi_cs_deactivate(dev); + + debug("%s: transfer ended. Value=%08x, fifo_status = %08x\n", + __func__, tmpdin, readl(®s->fifo_status)); + + if (ret) { + printf("%s: timeout during SPI transfer, tm %d\n", + __func__, ret); + return -1; + } + + return ret; +} + +static int tegra210_qspi_set_speed(struct udevice *bus, uint speed) +{ + struct tegra_spi_platdata *plat = bus->platdata; + struct tegra210_qspi_priv *priv = dev_get_priv(bus); + + if (speed > plat->frequency) + speed = plat->frequency; + priv->freq = speed; + debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq); + + return 0; +} + +static int tegra210_qspi_set_mode(struct udevice *bus, uint mode) +{ + struct tegra210_qspi_priv *priv = dev_get_priv(bus); + + priv->mode = mode; + debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode); + + return 0; +} + +static const struct dm_spi_ops tegra210_qspi_ops = { + .claim_bus = tegra210_qspi_claim_bus, + .xfer = tegra210_qspi_xfer, + .set_speed = tegra210_qspi_set_speed, + .set_mode = tegra210_qspi_set_mode, + /* + * cs_info is not needed, since we require all chip selects to be + * in the device tree explicitly + */ +}; + +static const struct udevice_id tegra210_qspi_ids[] = { + { .compatible = "nvidia,tegra210-qspi" }, + { } +}; + +U_BOOT_DRIVER(tegra210_qspi) = { + .name = "tegra210-qspi", + .id = UCLASS_SPI, + .of_match = tegra210_qspi_ids, + .ops = &tegra210_qspi_ops, + .ofdata_to_platdata = tegra210_qspi_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct tegra_spi_platdata), + .priv_auto_alloc_size = sizeof(struct tegra210_qspi_priv), + .per_child_auto_alloc_size = sizeof(struct spi_slave), + .probe = tegra210_qspi_probe, +};
Forgot Jagan
-----Original Message----- From: Tom Warren Sent: Friday, October 09, 2015 11:16 AM To: u-boot@lists.denx.de Cc: Stephen Warren swarren@nvidia.com; tomcwarren3959@gmail.com; Yen Lin yelin@nvidia.com; Tom Warren TWarren@nvidia.com Subject: [PATCH] Tegra210: add QSPI driver
From: Yen Lin yelin@nvidia.com
Tested on P2571 board with Winbond SPI ROM. sf probe 2:0 to see SPI chip. Flashed U-Boot image to SPI, rebooted, read back data to RAM with sf read, then verified crc against original binary file.
Author: Yen Lin yelin@nvidia.com Signed-off-by: Yen Lin yelin@nvidia.com Signed-off-by: Tom Warren twarren@nvidia.com --- board/nvidia/p2571/pinmux-config-p2571.h | 14 +- configs/p2571_defconfig | 1 + drivers/spi/Kconfig | 5 + drivers/spi/Makefile | 1 + drivers/spi/tegra210_qspi.c | 424 +++++++++++++++++++++++++++++++ 5 files changed, 439 insertions(+), 6 deletions(-) create mode 100644 drivers/spi/tegra210_qspi.c
diff --git a/board/nvidia/p2571/pinmux-config-p2571.h b/board/nvidia/p2571/pinmux-config-p2571.h index d323301..83b4b99 100644 --- a/board/nvidia/p2571/pinmux-config-p2571.h +++ b/board/nvidia/p2571/pinmux-config-p2571.h @@ -210,12 +210,14 @@ static const struct pmux_pingrp_config p2571_pingrps[] = { PINCFG(DP_HPD0_PCC6, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), PINCFG(PCC7, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, NORMAL), PINCFG(SPI2_CS1_PDD0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(QSPI_SCK_PEE0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(QSPI_CS_N_PEE1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(QSPI_IO0_PEE2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(QSPI_IO1_PEE3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(QSPI_IO2_PEE4, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(QSPI_IO3_PEE5, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + + PINCFG(QSPI_SCK_PEE0, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(QSPI_CS_N_PEE1, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(QSPI_IO0_PEE2, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(QSPI_IO1_PEE3, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(QSPI_IO2_PEE4, QSPI, UP, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(QSPI_IO3_PEE5, QSPI, UP, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(CORE_PWR_REQ, CORE, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), PINCFG(CPU_PWR_REQ, CPU, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), PINCFG(PWR_INT_N, PMI, UP, NORMAL, INPUT, DISABLE, DEFAULT), diff --git a/configs/p2571_defconfig b/configs/p2571_defconfig index 5a592e9..7c19428 100644 --- a/configs/p2571_defconfig +++ b/configs/p2571_defconfig @@ -12,5 +12,6 @@ CONFIG_SYS_PROMPT="Tegra210 (P2571) # " # CONFIG_CMD_NFS is not set CONFIG_SPI_FLASH=y CONFIG_TEGRA114_SPI=y +CONFIG_TEGRA210_QSPI=y CONFIG_USB=y CONFIG_DM_USB=y diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 8e04fce..168f31d 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -115,6 +115,11 @@ config TEGRA20_SLINK be used to access the SPI NOR flash on platforms embedding this nVidia Tegra20/Tegra30 IP cores.
+config TEGRA210_QSPI + bool "nVidia Tegra210 QSPI driver" + help + Enable the Tegra Quad-SPI (QSPI) driver for T210. + config XILINX_SPI bool "Xilinx SPI driver" help diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index de241be..209a41e 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -46,6 +46,7 @@ obj-$(CONFIG_SH_QSPI) += sh_qspi.o obj-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o obj-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o obj-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o +obj-$(CONFIG_TEGRA210_QSPI) += tegra210_qspi.o obj-$(CONFIG_TI_QSPI) += ti_qspi.o obj-$(CONFIG_XILINX_SPI) += xilinx_spi.o obj-$(CONFIG_ZYNQ_SPI) += zynq_spi.o diff --git a/drivers/spi/tegra210_qspi.c b/drivers/spi/tegra210_qspi.c new file mode 100644 index 0000000..d827667 --- /dev/null +++ b/drivers/spi/tegra210_qspi.c @@ -0,0 +1,424 @@ +/* + * NVIDIA Tegra QSPI controller (T210) + * + * Copyright (c) 2015 NVIDIA Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <dm.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch-tegra/clk_rst.h> +#include <spi.h> +#include <fdtdec.h> +#include "tegra_spi.h" + +DECLARE_GLOBAL_DATA_PTR; + +/* COMMAND1 */ +#define QSPI_CMD1_GO (1 << 31) +#define QSPI_CMD1_M_S (1 << 30) +#define QSPI_CMD1_MODE_MASK 0x3 +#define QSPI_CMD1_MODE_SHIFT 28 +#define QSPI_CMD1_CS_SEL_MASK 0x3 +#define QSPI_CMD1_CS_SEL_SHIFT 26 +#define QSPI_CMD1_CS_POL_INACTIVE0 (1 << 22) +#define QSPI_CMD1_CS_SW_HW (1 << 21) +#define QSPI_CMD1_CS_SW_VAL (1 << 20) +#define QSPI_CMD1_IDLE_SDA_MASK 0x3 +#define QSPI_CMD1_IDLE_SDA_SHIFT 18 +#define QSPI_CMD1_BIDIR (1 << 17) +#define QSPI_CMD1_LSBI_FE (1 << 16) +#define QSPI_CMD1_LSBY_FE (1 << 15) +#define QSPI_CMD1_BOTH_EN_BIT (1 << 14) +#define QSPI_CMD1_BOTH_EN_BYTE (1 << 13) +#define QSPI_CMD1_RX_EN (1 << 12) +#define QSPI_CMD1_TX_EN (1 << 11) +#define QSPI_CMD1_PACKED (1 << 5) +#define QSPI_CMD1_BITLEN_MASK 0x1F +#define QSPI_CMD1_BITLEN_SHIFT 0 + +/* COMMAND2 */ +#define QSPI_CMD2_TX_CLK_TAP_DELAY (1 << 6) +#define QSPI_CMD2_TX_CLK_TAP_DELAY_MASK (0x3F << 6) +#define QSPI_CMD2_RX_CLK_TAP_DELAY (1 << 0) +#define QSPI_CMD2_RX_CLK_TAP_DELAY_MASK (0x3F << 0) + +/* TRANSFER STATUS */ +#define QSPI_XFER_STS_RDY (1 << 30) + +/* FIFO STATUS */ +#define QSPI_FIFO_STS_CS_INACTIVE (1 << 31) +#define QSPI_FIFO_STS_FRAME_END (1 << 30) +#define QSPI_FIFO_STS_RX_FIFO_FLUSH (1 << 15) +#define QSPI_FIFO_STS_TX_FIFO_FLUSH (1 << 14) +#define QSPI_FIFO_STS_ERR (1 << 8) +#define QSPI_FIFO_STS_TX_FIFO_OVF (1 << 7) +#define QSPI_FIFO_STS_TX_FIFO_UNR (1 << 6) +#define QSPI_FIFO_STS_RX_FIFO_OVF (1 << 5) +#define QSPI_FIFO_STS_RX_FIFO_UNR (1 << 4) +#define QSPI_FIFO_STS_TX_FIFO_FULL (1 << 3) +#define QSPI_FIFO_STS_TX_FIFO_EMPTY (1 << 2) +#define QSPI_FIFO_STS_RX_FIFO_FULL (1 << 1) +#define QSPI_FIFO_STS_RX_FIFO_EMPTY (1 << 0) + +#define QSPI_TIMEOUT 1000 + +struct qspi_regs { + u32 command1; /* 000:QSPI_COMMAND1 register */ + u32 command2; /* 004:QSPI_COMMAND2 register */ + u32 timing1; /* 008:QSPI_CS_TIM1 register */ + u32 timing2; /* 00c:QSPI_CS_TIM2 register */ + u32 xfer_status;/* 010:QSPI_TRANS_STATUS register */ + u32 fifo_status;/* 014:QSPI_FIFO_STATUS register */ + u32 tx_data; /* 018:QSPI_TX_DATA register */ + u32 rx_data; /* 01c:QSPI_RX_DATA register */ + u32 dma_ctl; /* 020:QSPI_DMA_CTL register */ + u32 dma_blk; /* 024:QSPI_DMA_BLK register */ + u32 rsvd[56]; /* 028-107 reserved */ + u32 tx_fifo; /* 108:QSPI_FIFO1 register */ + u32 rsvd2[31]; /* 10c-187 reserved */ + u32 rx_fifo; /* 188:QSPI_FIFO2 register */ + u32 spare_ctl; /* 18c:QSPI_SPARE_CTRL register */ +}; + +struct tegra210_qspi_priv { + struct qspi_regs *regs; + unsigned int freq; + unsigned int mode; + int periph_id; + int valid; + int last_transaction_us; +}; + +static int tegra210_qspi_ofdata_to_platdata(struct udevice *bus) { + struct tegra_spi_platdata *plat = bus->platdata; + const void *blob = gd->fdt_blob; + int node = bus->of_offset; + + plat->base = fdtdec_get_addr(blob, node, "reg"); + plat->periph_id = clock_decode_periph_id(blob, node); + + if (plat->periph_id == PERIPH_ID_NONE) { + debug("%s: could not decode periph id %d\n", __func__, + plat->periph_id); + return -FDT_ERR_NOTFOUND; + } + + /* Use 500KHz as a suitable default */ + plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency", + 500000); + plat->deactivate_delay_us = fdtdec_get_int(blob, node, + "spi-deactivate-delay", 0); + debug("%s: base=%#08lx, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n", + __func__, plat->base, plat->periph_id, plat->frequency, + plat->deactivate_delay_us); + + return 0; +} + +static int tegra210_qspi_probe(struct udevice *bus) { + struct tegra_spi_platdata *plat = dev_get_platdata(bus); + struct tegra210_qspi_priv *priv = dev_get_priv(bus); + + priv->regs = (struct qspi_regs *)plat->base; + + priv->last_transaction_us = timer_get_us(); + priv->freq = plat->frequency; + priv->periph_id = plat->periph_id; + + return 0; +} + +static int tegra210_qspi_claim_bus(struct udevice *bus) { + struct tegra210_qspi_priv *priv = dev_get_priv(bus); + struct qspi_regs *regs = priv->regs; + + /* Change SPI clock to correct frequency, PLLP_OUT0 source */ + clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH, priv->freq); + + /* Clear stale status here */ + setbits_le32(®s->fifo_status, + QSPI_FIFO_STS_ERR | + QSPI_FIFO_STS_TX_FIFO_OVF | + QSPI_FIFO_STS_TX_FIFO_UNR | + QSPI_FIFO_STS_RX_FIFO_OVF | + QSPI_FIFO_STS_RX_FIFO_UNR | + QSPI_FIFO_STS_TX_FIFO_FULL | + QSPI_FIFO_STS_TX_FIFO_EMPTY | + QSPI_FIFO_STS_RX_FIFO_FULL | + QSPI_FIFO_STS_RX_FIFO_EMPTY); + debug("%s: FIFO STATUS = %08x\n", __func__, +readl(®s->fifo_status)); + + /* Set master mode and sw controlled CS */ + setbits_le32(®s->command1, QSPI_CMD1_M_S | QSPI_CMD1_CS_SW_HW | + (priv->mode << QSPI_CMD1_MODE_SHIFT)); + debug("%s: COMMAND1 = %08x\n", __func__, readl(®s->command1)); + + return 0; +} + +/** + * Activate the CS by driving it LOW + * + * @param slave Pointer to spi_slave to which controller has to + * communicate with + */ +static void spi_cs_activate(struct udevice *dev) { + struct udevice *bus = dev->parent; + struct tegra_spi_platdata *pdata = dev_get_platdata(bus); + struct tegra210_qspi_priv *priv = dev_get_priv(bus); + + /* If it's too soon to do another transaction, wait */ + if (pdata->deactivate_delay_us && + priv->last_transaction_us) { + ulong delay_us; /* The delay completed so far */ + delay_us = timer_get_us() - priv->last_transaction_us; + if (delay_us < pdata->deactivate_delay_us) + udelay(pdata->deactivate_delay_us - delay_us); + } + + clrbits_le32(&priv->regs->command1, QSPI_CMD1_CS_SW_VAL); } + +/** + * Deactivate the CS by driving it HIGH + * + * @param slave Pointer to spi_slave to which controller has to + * communicate with + */ +static void spi_cs_deactivate(struct udevice *dev) { + struct udevice *bus = dev->parent; + struct tegra_spi_platdata *pdata = dev_get_platdata(bus); + struct tegra210_qspi_priv *priv = dev_get_priv(bus); + + setbits_le32(&priv->regs->command1, QSPI_CMD1_CS_SW_VAL); + + /* Remember time of this transaction so we can honour the bus delay */ + if (pdata->deactivate_delay_us) + priv->last_transaction_us = timer_get_us(); + + debug("Deactivate CS, bus '%s'\n", bus->name); } + +static int tegra210_qspi_xfer(struct udevice *dev, unsigned int bitlen, + const void *data_out, void *data_in, + unsigned long flags) +{ + struct udevice *bus = dev->parent; + struct tegra210_qspi_priv *priv = dev_get_priv(bus); + struct qspi_regs *regs = priv->regs; + u32 reg, tmpdout, tmpdin = 0; + const u8 *dout = data_out; + u8 *din = data_in; + int num_bytes; + int ret; + + debug("%s: slave %u:%u dout %p din %p bitlen %u\n", + __func__, bus->seq, spi_chip_select(dev), dout, din, bitlen); + if (bitlen % 8) + return -1; + num_bytes = bitlen / 8; + + ret = 0; + + /* clear all error status bits */ + reg = readl(®s->fifo_status); + writel(reg, ®s->fifo_status); + + /* flush RX/TX FIFOs */ + setbits_le32(®s->fifo_status, + (QSPI_FIFO_STS_RX_FIFO_FLUSH | QSPI_FIFO_STS_TX_FIFO_FLUSH)); + while ((readl(®s->fifo_status) & + (QSPI_FIFO_STS_RX_FIFO_FLUSH | QSPI_FIFO_STS_TX_FIFO_FLUSH))) + ; + + /* + * Notes: + * 1. don't set LSBY_FE, so no need to swap bytes from/to TX/RX FIFOs; + * 2. don't set RX_EN and TX_EN yet. + * (SW needs to make sure that while programming the blk_size, + * tx_en and rx_en bits must be zero) + * [TODO] I (Yen Lin) have problems when both RX/TX EN bits are set + * i.e., both dout and din are not NULL. + */ + clrsetbits_le32(®s->command1, + (QSPI_CMD1_LSBI_FE | QSPI_CMD1_LSBY_FE | + QSPI_CMD1_RX_EN | QSPI_CMD1_TX_EN), + (spi_chip_select(dev) << QSPI_CMD1_CS_SEL_SHIFT)); + + /* set xfer size to 1 block (32 bits) */ + writel(0, ®s->dma_blk); + + if (flags & SPI_XFER_BEGIN) + spi_cs_activate(dev); + + /* handle data in 32-bit chunks */ + while (num_bytes > 0) { + int bytes; + int tm; + + tmpdout = 0; + bytes = (num_bytes > 4) ? 4 : num_bytes; + + if (dout != NULL) { + memcpy((void *)&tmpdout, (void *)dout, bytes); + dout += bytes; + num_bytes -= bytes; + writel(tmpdout, ®s->tx_fifo); + setbits_le32(®s->command1, QSPI_CMD1_TX_EN); + } + + if (din != NULL) + setbits_le32(®s->command1, QSPI_CMD1_RX_EN); + + /* clear ready bit */ + setbits_le32(®s->xfer_status, QSPI_XFER_STS_RDY); + + clrsetbits_le32(®s->command1, + QSPI_CMD1_BITLEN_MASK << QSPI_CMD1_BITLEN_SHIFT, + (bytes * 8 - 1) << QSPI_CMD1_BITLEN_SHIFT); + /* Need to stabilize other reg bit before GO bit set */ + udelay(2); + setbits_le32(®s->command1, QSPI_CMD1_GO); + udelay(1); + + /* + * Wait for SPI transmit FIFO to empty, or to time out. + * The RX FIFO status will be read and cleared last + */ + for (tm = 0; tm < QSPI_TIMEOUT; ++tm) { + u32 fifo_status, xfer_status; + + xfer_status = readl(®s->xfer_status); + if (!(xfer_status & QSPI_XFER_STS_RDY)) + continue; + + fifo_status = readl(®s->fifo_status); + if (fifo_status & QSPI_FIFO_STS_ERR) { + debug("%s: got a fifo error: ", __func__); + if (fifo_status & QSPI_FIFO_STS_TX_FIFO_OVF) + debug("tx FIFO overflow "); + if (fifo_status & QSPI_FIFO_STS_TX_FIFO_UNR) + debug("tx FIFO underrun "); + if (fifo_status & QSPI_FIFO_STS_RX_FIFO_OVF) + debug("rx FIFO overflow "); + if (fifo_status & QSPI_FIFO_STS_RX_FIFO_UNR) + debug("rx FIFO underrun "); + if (fifo_status & QSPI_FIFO_STS_TX_FIFO_FULL) + debug("tx FIFO full "); + if (fifo_status & QSPI_FIFO_STS_TX_FIFO_EMPTY) + debug("tx FIFO empty "); + if (fifo_status & QSPI_FIFO_STS_RX_FIFO_FULL) + debug("rx FIFO full "); + if (fifo_status & QSPI_FIFO_STS_RX_FIFO_EMPTY) + debug("rx FIFO empty "); + debug("\n"); + break; + } + + if (!(fifo_status & QSPI_FIFO_STS_RX_FIFO_EMPTY)) { + tmpdin = readl(®s->rx_fifo); + if (din != NULL) { + memcpy(din, &tmpdin, bytes); + din += bytes; + num_bytes -= bytes; + } + } + break; + } + + if (tm >= QSPI_TIMEOUT) + ret = tm; + + /* clear ACK RDY, etc. bits */ + writel(readl(®s->fifo_status), ®s->fifo_status); + } + + if (flags & SPI_XFER_END) + spi_cs_deactivate(dev); + + debug("%s: transfer ended. Value=%08x, fifo_status = %08x\n", + __func__, tmpdin, readl(®s->fifo_status)); + + if (ret) { + printf("%s: timeout during SPI transfer, tm %d\n", + __func__, ret); + return -1; + } + + return ret; +} + +static int tegra210_qspi_set_speed(struct udevice *bus, uint speed) { + struct tegra_spi_platdata *plat = bus->platdata; + struct tegra210_qspi_priv *priv = dev_get_priv(bus); + + if (speed > plat->frequency) + speed = plat->frequency; + priv->freq = speed; + debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq); + + return 0; +} + +static int tegra210_qspi_set_mode(struct udevice *bus, uint mode) { + struct tegra210_qspi_priv *priv = dev_get_priv(bus); + + priv->mode = mode; + debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode); + + return 0; +} + +static const struct dm_spi_ops tegra210_qspi_ops = { + .claim_bus = tegra210_qspi_claim_bus, + .xfer = tegra210_qspi_xfer, + .set_speed = tegra210_qspi_set_speed, + .set_mode = tegra210_qspi_set_mode, + /* + * cs_info is not needed, since we require all chip selects to be + * in the device tree explicitly + */ +}; + +static const struct udevice_id tegra210_qspi_ids[] = { + { .compatible = "nvidia,tegra210-qspi" }, + { } +}; + +U_BOOT_DRIVER(tegra210_qspi) = { + .name = "tegra210-qspi", + .id = UCLASS_SPI, + .of_match = tegra210_qspi_ids, + .ops = &tegra210_qspi_ops, + .ofdata_to_platdata = tegra210_qspi_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct tegra_spi_platdata), + .priv_auto_alloc_size = sizeof(struct tegra210_qspi_priv), + .per_child_auto_alloc_size = sizeof(struct spi_slave), + .probe = tegra210_qspi_probe, +}; -- 1.8.2.1.610.g562af5b -- nvpublic
On 10/09/2015 12:20 PM, Tom Warren wrote:
From: Yen Lin yelin@nvidia.com
Tested on P2571 board with Winbond SPI ROM. sf probe 2:0 to see SPI chip. Flashed U-Boot image to SPI, rebooted, read back data to RAM with sf read, then verified crc against original binary file.
board/nvidia/p2571/pinmux-config-p2571.h | 14 +- configs/p2571_defconfig | 1 +
As a general comment, driver changes should be in separate patches to board changes to enable the driver. The two things are logically separate, and this also helps when cherry-picking patches between branches that might not have p2571 support.
diff --git a/board/nvidia/p2571/pinmux-config-p2571.h b/board/nvidia/p2571/pinmux-config-p2571.h
- PINCFG(QSPI_SCK_PEE0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(QSPI_CS_N_PEE1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(QSPI_IO0_PEE2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(QSPI_IO1_PEE3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(QSPI_IO2_PEE4, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(QSPI_IO3_PEE5, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(QSPI_SCK_PEE0, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(QSPI_CS_N_PEE1, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(QSPI_IO0_PEE2, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(QSPI_IO1_PEE3, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(QSPI_IO2_PEE4, QSPI, UP, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(QSPI_IO3_PEE5, QSPI, UP, TRISTATE, OUTPUT, DISABLE, DEFAULT),
The current pinmux matches the syseng-supplied spreadsheet. If the spreadsheet is wrong, please get syseng to update the spreadsheet first. The pinmux files must not be manually edited, so we ensure that the mandated pinmux is used.
diff --git a/drivers/spi/tegra210_qspi.c b/drivers/spi/tegra210_qspi.c new file mode 100644 index 0000000..d827667
+static int tegra210_qspi_ofdata_to_platdata(struct udevice *bus) {
- struct tegra_spi_platdata *plat = bus->platdata;
- const void *blob = gd->fdt_blob;
- int node = bus->of_offset;
- plat->base = fdtdec_get_addr(blob, node, "reg");
I think that should use dev_get_addr() now, since that does the correct thing w.r.t. #address-cells/#size-cells.
+static int tegra210_qspi_claim_bus(struct udevice *bus) {
- /* Clear stale status here */
- setbits_le32(®s->fifo_status,
QSPI_FIFO_STS_ERR |QSPI_FIFO_STS_TX_FIFO_OVF |QSPI_FIFO_STS_TX_FIFO_UNR |QSPI_FIFO_STS_RX_FIFO_OVF |QSPI_FIFO_STS_RX_FIFO_UNR |QSPI_FIFO_STS_TX_FIFO_FULL |QSPI_FIFO_STS_TX_FIFO_EMPTY |QSPI_FIFO_STS_RX_FIFO_FULL |QSPI_FIFO_STS_RX_FIFO_EMPTY);- debug("%s: FIFO STATUS = %08x\n", __func__,
+readl(®s->fifo_status));
Indentation issue.
I would expect at least that setbits_le32() to happen inside the transfer function so that every transfer is immune to stale status, not just the first transfer after the bus is cleared.
Actually, it looks like the transfer function already does this, so the above code can simply be dropped.
Perhaps the other HW-touching code might be moved to, but it's probably fine to leave it here.
Stephen,
-----Original Message----- From: Stephen Warren [mailto:swarren@wwwdotorg.org] Sent: Friday, October 09, 2015 11:51 AM To: Tom Warren TWarren@nvidia.com Cc: u-boot@lists.denx.de; Jagan Teki jteki@openedev.com; Stephen Warren swarren@nvidia.com; tomcwarren3959@gmail.com Subject: Re: [U-Boot] [PATCH] Tegra210: add QSPI driver
On 10/09/2015 12:20 PM, Tom Warren wrote:
From: Yen Lin yelin@nvidia.com
Tested on P2571 board with Winbond SPI ROM. sf probe 2:0 to see SPI chip. Flashed U-Boot image to SPI, rebooted, read back data to RAM with sf read, then verified crc against original binary file.
board/nvidia/p2571/pinmux-config-p2571.h | 14 +- configs/p2571_defconfig | 1 +
As a general comment, driver changes should be in separate patches to board changes to enable the driver. The two things are logically separate, and this also helps when cherry-picking patches between branches that might not have p2571 support.
True, my bad. I'll resubmit.
diff --git a/board/nvidia/p2571/pinmux-config-p2571.h b/board/nvidia/p2571/pinmux-config-p2571.h
- PINCFG(QSPI_SCK_PEE0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(QSPI_CS_N_PEE1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(QSPI_IO0_PEE2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(QSPI_IO1_PEE3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(QSPI_IO2_PEE4, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(QSPI_IO3_PEE5, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(QSPI_SCK_PEE0, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(QSPI_CS_N_PEE1, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(QSPI_IO0_PEE2, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(QSPI_IO1_PEE3, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(QSPI_IO2_PEE4, QSPI, UP, TRISTATE, OUTPUT, DISABLE, DEFAULT),
- PINCFG(QSPI_IO3_PEE5, QSPI, UP, TRISTATE, OUTPUT, DISABLE, DEFAULT),
The current pinmux matches the syseng-supplied spreadsheet. If the spreadsheet is wrong, please get syseng to update the spreadsheet first. The pinmux files must not be manually edited, so we ensure that the mandated pinmux is used.
Valid point, I'm still used to changing the pinmux as desired to get new devices up. I'll pull down the latest P2571 spreadsheet and have it changed if it hasn't already been. Once it's corrected, I assume you can generate a new pinmux header and post a patch that I can put in ahead of the QSPI patches.
diff --git a/drivers/spi/tegra210_qspi.c b/drivers/spi/tegra210_qspi.c new file mode 100644 index 0000000..d827667
+static int tegra210_qspi_ofdata_to_platdata(struct udevice *bus) {
- struct tegra_spi_platdata *plat = bus->platdata;
- const void *blob = gd->fdt_blob;
- int node = bus->of_offset;
- plat->base = fdtdec_get_addr(blob, node, "reg");
I think that should use dev_get_addr() now, since that does the correct thing w.r.t. #address-cells/#size-cells.
Ok, I'll take a look. Thanks.
+static int tegra210_qspi_claim_bus(struct udevice *bus) {
- /* Clear stale status here */
- setbits_le32(®s->fifo_status,
QSPI_FIFO_STS_ERR |QSPI_FIFO_STS_TX_FIFO_OVF |QSPI_FIFO_STS_TX_FIFO_UNR |QSPI_FIFO_STS_RX_FIFO_OVF |QSPI_FIFO_STS_RX_FIFO_UNR |QSPI_FIFO_STS_TX_FIFO_FULL |QSPI_FIFO_STS_TX_FIFO_EMPTY |QSPI_FIFO_STS_RX_FIFO_FULL |QSPI_FIFO_STS_RX_FIFO_EMPTY);- debug("%s: FIFO STATUS = %08x\n", __func__,
+readl(®s->fifo_status));
Indentation issue.
I would expect at least that setbits_le32() to happen inside the transfer function so that every transfer is immune to stale status, not just the first transfer after the bus is cleared.
Actually, it looks like the transfer function already does this, so the above code can simply be dropped.
Perhaps the other HW-touching code might be moved to, but it's probably fine to leave it here.
Yen wrote and debugged this driver awhile back - I don't know why he wasn't included by 'send-email', but I've added him to the CC list.
Thanks,
Tom -- nvpublic
participants (3)
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Stephen Warren -
Tom Warren -
Tom Warren