The LS2080ARDB is a evaluation platform that supports LS2080A family SoCs. This patch add sbasic support for the platform.

Signed-off-by: York Sun yorksun@freescale.com Signed-off-by: Prabhakar Kushwaha prabhakar@freescale.com Signed-off-by: Bhupesh Sharma bhupesh.sharma@freescale.com Signed-off-by: Scott Wood scottwood@freescale.com

---

Changes in v4: Fix board README for inconsistent SoC name Fix comments in board header file

Changes in v3: None Changes in v2: None

arch/arm/Kconfig | 11 +++ arch/arm/cpu/armv8/fsl-lsch3/README | 4 +- board/freescale/{ls2085aqds => ls2085ardb}/Kconfig | 6 +- board/freescale/ls2085ardb/MAINTAINERS | 7 ++ .../freescale/{ls2085aqds => ls2085ardb}/Makefile | 2 +- board/freescale/{ls2085aqds => ls2085ardb}/README | 48 ++++--------- board/freescale/{ls2085aqds => ls2085ardb}/ddr.c | 0 board/freescale/{ls2085aqds => ls2085ardb}/ddr.h | 6 +- .../ls2085aqds.c => ls2085ardb/ls2085ardb.c} | 54 +++----------- .../ls2085ardb_qixis.h} | 12 +--- ...qds_ddr4_nor_defconfig => ls2085ardb_defconfig} | 2 +- include/configs/{ls2085aqds.h => ls2085ardb.h} | 75 ++++++++------------ 12 files changed, 82 insertions(+), 145 deletions(-) copy board/freescale/{ls2085aqds => ls2085ardb}/Kconfig (66%) create mode 100644 board/freescale/ls2085ardb/MAINTAINERS copy board/freescale/{ls2085aqds => ls2085ardb}/Makefile (81%) copy board/freescale/{ls2085aqds => ls2085ardb}/README (73%) copy board/freescale/{ls2085aqds => ls2085ardb}/ddr.c (100%) copy board/freescale/{ls2085aqds => ls2085ardb}/ddr.h (93%) copy board/freescale/{ls2085aqds/ls2085aqds.c => ls2085ardb/ls2085ardb.c} (76%) copy board/freescale/{ls2085aqds/ls2085aqds_qixis.h => ls2085ardb/ls2085ardb_qixis.h} (61%) copy configs/{ls1021aqds_ddr4_nor_defconfig => ls2085ardb_defconfig} (66%) copy include/configs/{ls2085aqds.h => ls2085ardb.h} (79%)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index f4a7851..7478eb4 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -658,6 +658,16 @@ config TARGET_LS2085AQDS development platform that supports the QorIQ LS2085A Layerscape Architecture processor.

+config TARGET_LS2085ARDB + bool "Support ls2085ardb" + select ARM64 + select ARMV8_MULTIENTRY + help + Support for Freescale LS2085ARDB platform. + The LS2080A Reference design board (RDB) is a high-performance + development platform that supports the QorIQ LS2085A + LayerScape Architecture processor. + config TARGET_LS1021AQDS bool "Support ls1021aqds" select CPU_V7 @@ -804,6 +814,7 @@ source "board/embest/mx6boards/Kconfig" source "board/esg/ima3-mx53/Kconfig" source "board/freescale/ls2085a/Kconfig" source "board/freescale/ls2085aqds/Kconfig" +source "board/freescale/ls2085ardb/Kconfig" source "board/freescale/ls1021aqds/Kconfig" source "board/freescale/ls1021atwr/Kconfig" source "board/freescale/mx23evk/Kconfig" diff --git a/arch/arm/cpu/armv8/fsl-lsch3/README b/arch/arm/cpu/armv8/fsl-lsch3/README index 817ea1b..4f36e2a 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/README +++ b/arch/arm/cpu/armv8/fsl-lsch3/README @@ -38,7 +38,7 @@ Flash Layout 32-MB NOR flash layout for pre-silicon platforms (simulator and emulator)

(2) A typical layout of various images (including Linux and other firmware images) - is shown below considering a 128MB NOR flash device present on QDS + is shown below considering a 128MB NOR flash device present on QDS and RDB boards: ----------------------------------------- ----> 0x5_8800_0000 --- | .. Unused .. (7M) | | @@ -86,7 +86,7 @@ Flash Layout | RCW and PBI (1M) | | ----------------------------------------- ----> 0x5_8000_0000 ---

- 128-MB NOR flash layout for QDS board + 128-MB NOR flash layout for QDS and RDB boards

Environment Variables ===================== diff --git a/board/freescale/ls2085aqds/Kconfig b/board/freescale/ls2085ardb/Kconfig similarity index 66% copy from board/freescale/ls2085aqds/Kconfig copy to board/freescale/ls2085ardb/Kconfig index deb640d..85a3dcd 100644 --- a/board/freescale/ls2085aqds/Kconfig +++ b/board/freescale/ls2085ardb/Kconfig @@ -1,8 +1,8 @@

-if TARGET_LS2085AQDS +if TARGET_LS2085ARDB

config SYS_BOARD - default "ls2085aqds" + default "ls2085ardb"

config SYS_VENDOR default "freescale" @@ -11,6 +11,6 @@ config SYS_SOC default "fsl-lsch3"

config SYS_CONFIG_NAME - default "ls2085aqds" + default "ls2085ardb"

endif diff --git a/board/freescale/ls2085ardb/MAINTAINERS b/board/freescale/ls2085ardb/MAINTAINERS new file mode 100644 index 0000000..436039f --- /dev/null +++ b/board/freescale/ls2085ardb/MAINTAINERS @@ -0,0 +1,7 @@ +LS2085A BOARD +M: Prabhakar Kushwaha prabhakar@freescale.com +S: Maintained +F: board/freescale/ls2085ardb/ +F: board/freescale/ls2085a/ls2085ardb.c +F: include/configs/ls2085ardb.h +F: configs/ls2085ardb_defconfig diff --git a/board/freescale/ls2085aqds/Makefile b/board/freescale/ls2085ardb/Makefile similarity index 81% copy from board/freescale/ls2085aqds/Makefile copy to board/freescale/ls2085ardb/Makefile index f174f33..0bfe21c 100644 --- a/board/freescale/ls2085aqds/Makefile +++ b/board/freescale/ls2085ardb/Makefile @@ -4,5 +4,5 @@ # SPDX-License-Identifier: GPL-2.0+ #

-obj-y += ls2085aqds.o +obj-y += ls2085ardb.o obj-y += ddr.o diff --git a/board/freescale/ls2085aqds/README b/board/freescale/ls2085ardb/README similarity index 73% copy from board/freescale/ls2085aqds/README copy to board/freescale/ls2085ardb/README index a4d7b53..cfd5185 100644 --- a/board/freescale/ls2085aqds/README +++ b/board/freescale/ls2085ardb/README @@ -1,10 +1,8 @@ Overview -------- -The LS2080A Development System (QDS) is a high-performance computing, -evaluation, and development platform that supports the QorIQ LS2080A -LayerScape Architecture processor. The LS2080AQDS provides validation and -SW development platform for the Freescale LS2080A processor series, with -a complete debugging environment. +The LS2085A Reference Design (RDB) is a high-performance computing, +evaluation, and development platform that supports the QorIQ LS2085A +Layerscape Architecture processor.

LS2085A SoC Overview ------------------ @@ -50,14 +48,11 @@ The LS2085A SoC includes the following function and features: - Service processor (SP) provides pre-boot initialization and secure-boot capabilities

- LS2080AQDS board Overview + LS2085ARDB board Overview ----------------------- - SERDES Connections, 16 lanes supporting: - PCI Express - 3.0 - - SGMII, SGMII 2.5 - - QSGMII - SATA 3.0 - - XAUI - XFI - DDR Controller - Two ports of 72-bits (8-bits ECC) DDR4. Each port supports four @@ -66,31 +61,20 @@ The LS2085A SoC includes the following function and features: and two DIMM connectors. Support is up to 1600MT/s. -IFC/Local Bus - IFC rev. 2.0 implementation supporting Little Endian connection scheme. - - One in-socket 128 MB NOR flash 16-bit data bus - - One 512 MB NAND flash with ECC support - - IFC Test Port - - PromJet Port - - FPGA connection + - 128 MB NOR flash 16-bit data bus + - One 2 GB NAND flash with ECC support + - CPLD connection - USB 3.0 - Two high speed USB 3.0 ports - First USB 3.0 port configured as Host with Type-A connector - Second USB 3.0 port configured as OTG with micro-AB connector - - SDHC: PCIe x1 Right Angle connector for supporting following cards - - 1/4-/8-bit SD/MMC Legacy CARD supporting 3.3V devices only - - 1-/4-/8-bit SD/MMC Card supporting 1.8V devices only - - 4-bit eMMC Card Rev 4.4 (1.8V only) - - 8-bit eMMC Card Rev 4.5 (1.8V only) + - SDHC adapter - SD Card Rev 2.0 and Rev 3.0 - - DSPI: 3 high-speed flash Memory for storage - - 16 MB high-speed flash Memory for boot code and storage (up to 108MHz) - - 8 MB high-speed flash Memory (up to 104 MHz) - - 512 MB low-speed flash Memory (up to 40 MHz) - - QSPI: via NAND/QSPI Card + - DSPI + - 128 MB high-speed flash Memory for boot code and storage (up to 108MHz) - 4 I2C controllers - Two SATA onboard connectors - UART - - Two 4-pin (HW control) or four 2-pin (SW control) serial ports at up to 115.2 Kbit/s - - Two DB9 D-Type connectors supporting one Serial port each - ARM JTAG support

Memory map from core's view @@ -110,20 +94,16 @@ IFC region map from core's view ------------------------------- During boot i.e. IFC Region #1:- 0x30000000 - 0x37ffffff : 128MB : NOR flash - 0x38000000 - 0x3BFFFFFF : 64MB : Promjet - 0x3C000000 - 0x40000000 : 64MB : FPGA etc + 0x3C000000 - 0x40000000 : 64MB : CPLD

After relocate to DDR i.e. IFC Region #2:- 0x5_1000_0000..0x5_1fff_ffff Memory Hole - 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB) + 0x5_2000_0000..0x5_3fff_ffff IFC CSx (CPLD, NAND and others 512MB) 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet) 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet)

Booting Options --------------- -a) Promjet Boot -b) NOR boot -c) NAND boot -d) SD boot -e) QSPI boot +a) NOR boot +b) NAND boot diff --git a/board/freescale/ls2085aqds/ddr.c b/board/freescale/ls2085ardb/ddr.c similarity index 100% copy from board/freescale/ls2085aqds/ddr.c copy to board/freescale/ls2085ardb/ddr.c diff --git a/board/freescale/ls2085aqds/ddr.h b/board/freescale/ls2085ardb/ddr.h similarity index 93% copy from board/freescale/ls2085aqds/ddr.h copy to board/freescale/ls2085ardb/ddr.h index b76ea61..bda9d4a 100644 --- a/board/freescale/ls2085aqds/ddr.h +++ b/board/freescale/ls2085ardb/ddr.h @@ -29,9 +29,9 @@ static const struct board_specific_parameters udimm0[] = { * ranks| mhz| GB |adjst| start | ctl2 | ctl3 */ {2, 1350, 0, 4, 6, 0x0708090B, 0x0C0D0E09,}, - {2, 1666, 0, 4, 7, 0x08090A0C, 0x0D0F100B,}, - {2, 1900, 0, 4, 7, 0x09090B0D, 0x0E10120B,}, - {2, 2300, 0, 4, 8, 0x090A0C0F, 0x1012130C,}, + {2, 1666, 0, 4, 8, 0x08090B0D, 0x0E10100C,}, + {2, 1900, 0, 4, 8, 0x090A0C0E, 0x1012120D,}, + {2, 2300, 0, 4, 9, 0x0A0B0C10, 0x1114140E,}, {} };

diff --git a/board/freescale/ls2085aqds/ls2085aqds.c b/board/freescale/ls2085ardb/ls2085ardb.c similarity index 76% copy from board/freescale/ls2085aqds/ls2085aqds.c copy to board/freescale/ls2085ardb/ls2085ardb.c index f7ed5b9..d05f2bc 100644 --- a/board/freescale/ls2085aqds/ls2085aqds.c +++ b/board/freescale/ls2085ardb/ls2085ardb.c @@ -19,7 +19,7 @@ #include <asm/arch-fsl-lsch3/soc.h>

#include "../common/qixis.h" -#include "ls2085aqds_qixis.h" +#include "ls2085ardb_qixis.h"

DECLARE_GLOBAL_DATA_PTR;

@@ -43,11 +43,7 @@ unsigned long long get_qixis_addr(void)

int checkboard(void) { - char buf[64]; u8 sw; - static const char *const freq[] = {"100", "125", "156.25", - "100 separate SSCG"}; - int clock;

sw = QIXIS_READ(arch); printf("Board: %s, ", CONFIG_IDENT_STRING); @@ -59,41 +55,20 @@ int checkboard(void)

if (sw < 0x8) printf("vBank: %d\n", sw); - else if (sw == 0x8) - puts("PromJet\n"); else if (sw == 0x9) puts("NAND\n"); - else if (sw == 0x15) - printf("IFCCard\n"); else printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);

- printf("FPGA: v%d (%s), build %d", - (int)QIXIS_READ(scver), qixis_read_tag(buf), - (int)qixis_read_minor()); - /* the timestamp string contains "\n" at the end */ - printf(" on %s", qixis_read_time(buf)); + printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));

- /* - * Display the actual SERDES reference clocks as configured by the - * dip switches on the board. Note that the SWx registers could - * technically be set to force the reference clocks to match the - * values that the SERDES expects (or vice versa). For now, however, - * we just display both values and hope the user notices when they - * don't match. - */ puts("SERDES1 Reference : "); - sw = QIXIS_READ(brdcfg[2]); - clock = (sw >> 6) & 3; - printf("Clock1 = %sMHz ", freq[clock]); - clock = (sw >> 4) & 3; - printf("Clock2 = %sMHz", freq[clock]); + printf("Clock1 = 156.25MHz "); + printf("Clock2 = 156.25MHz");

puts("\nSERDES2 Reference : "); - clock = (sw >> 2) & 3; - printf("Clock1 = %sMHz ", freq[clock]); - clock = (sw >> 0) & 3; - printf("Clock2 = %sMHz\n", freq[clock]); + printf("Clock1 = 100MHz "); + printf("Clock2 = 100MHz\n");

return 0; } @@ -121,21 +96,6 @@ unsigned long get_board_sys_clk(void) return 66666666; }

-unsigned long get_board_ddr_clk(void) -{ - u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); - - switch ((ddrclk_conf & 0x30) >> 4) { - case QIXIS_DDRCLK_100: - return 100000000; - case QIXIS_DDRCLK_125: - return 125000000; - case QIXIS_DDRCLK_133: - return 133333333; - } - return 66666666; -} - int select_i2c_ch_pca9547(u8 ch) { int ret; @@ -158,6 +118,8 @@ int board_init(void) #endif select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);

+ QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN); + return 0; }

diff --git a/board/freescale/ls2085aqds/ls2085aqds_qixis.h b/board/freescale/ls2085ardb/ls2085ardb_qixis.h similarity index 61% copy from board/freescale/ls2085aqds/ls2085aqds_qixis.h copy to board/freescale/ls2085ardb/ls2085ardb_qixis.h index bb43e65..cb60c00 100644 --- a/board/freescale/ls2085aqds/ls2085aqds_qixis.h +++ b/board/freescale/ls2085ardb/ls2085ardb_qixis.h @@ -4,8 +4,8 @@ * SPDX-License-Identifier: GPL-2.0+ */

-#ifndef __LS2_QDS_QIXIS_H__ -#define __LS2_QDS_QIXIS_H__ +#ifndef __LS2_RDB_QIXIS_H__ +#define __LS2_RDB_QIXIS_H__

/* SYSCLK */ #define QIXIS_SYSCLK_66 0x0 @@ -17,10 +17,4 @@ #define QIXIS_SYSCLK_160 0x6 #define QIXIS_SYSCLK_166 0x7

-/* DDRCLK */ -#define QIXIS_DDRCLK_66 0x0 -#define QIXIS_DDRCLK_100 0x1 -#define QIXIS_DDRCLK_125 0x2 -#define QIXIS_DDRCLK_133 0x3 - -#endif /*__LS2_QDS_QIXIS_H__*/ +#endif /*__LS2_RDB_QIXIS_H__*/ diff --git a/configs/ls1021aqds_ddr4_nor_defconfig b/configs/ls2085ardb_defconfig similarity index 66% copy from configs/ls1021aqds_ddr4_nor_defconfig copy to configs/ls2085ardb_defconfig index 3c57481..6b64f71 100644 --- a/configs/ls1021aqds_ddr4_nor_defconfig +++ b/configs/ls2085ardb_defconfig @@ -1,3 +1,3 @@ CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4" CONFIG_ARM=y -CONFIG_TARGET_LS1021AQDS=y +CONFIG_TARGET_LS2085ARDB=y diff --git a/include/configs/ls2085aqds.h b/include/configs/ls2085ardb.h similarity index 79% copy from include/configs/ls2085aqds.h copy to include/configs/ls2085ardb.h index 70162e7..707d431 100644 --- a/include/configs/ls2085aqds.h +++ b/include/configs/ls2085ardb.h @@ -4,24 +4,26 @@ * SPDX-License-Identifier: GPL-2.0+ */

-#ifndef __LS2_QDS_H -#define __LS2_QDS_H +#ifndef __LS2_RDB_H +#define __LS2_RDB_H

#include "ls2085a_common.h" #include <config_cmd_default.h>

-#define CONFIG_IDENT_STRING " LS2085A-QDS" -#define CONFIG_BOOTP_VCI_STRING "U-boot.LS2085A-QDS" +#define CONFIG_IDENT_STRING " LS2085A-RDB" +#define CONFIG_BOOTP_VCI_STRING "U-boot.LS2085A-RDB" + +#undef CONFIG_CONS_INDEX +#define CONFIG_CONS_INDEX 2

#define CONFIG_DISPLAY_BOARDINFO

#ifndef __ASSEMBLY__ unsigned long get_board_sys_clk(void); -unsigned long get_board_ddr_clk(void); #endif

#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() -#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() +#define CONFIG_DDR_CLK_FREQ 133333333 #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4)

#define CONFIG_DDR_SPD @@ -30,8 +32,8 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #define SPD_EEPROM_ADDRESS1 0x51 #define SPD_EEPROM_ADDRESS2 0x52 -#define SPD_EEPROM_ADDRESS3 0x53 -#define SPD_EEPROM_ADDRESS4 0x54 +#define SPD_EEPROM_ADDRESS3 0x54 +#define SPD_EEPROM_ADDRESS4 0x53 /* Board error */ #define SPD_EEPROM_ADDRESS5 0x55 #define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */ #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 @@ -57,16 +59,6 @@ unsigned long get_board_ddr_clk(void); CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR1_CSPR \ - (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS) | \ - CSPR_PORT_SIZE_16 | \ - CSPR_MSEL_NOR | \ - CSPR_V) -#define CONFIG_SYS_NOR1_CSPR_EARLY \ - (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY) | \ - CSPR_PORT_SIZE_16 | \ - CSPR_MSEL_NOR | \ - CSPR_V) #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12) #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ FTIM0_NOR_TEADC(0x5) | \ @@ -88,7 +80,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_FLASH_QUIET_TEST #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */

-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ @@ -113,25 +105,25 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ - | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ - | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ - | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ - | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ + | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ + | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ + | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ + | CSOR_NAND_PB(128)) /*Pages Per Block = 128*/

#define CONFIG_SYS_NAND_ONFI_DETECTION

/* ONFI NAND Flash mode0 Timing Params */ -#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ - FTIM0_NAND_TWP(0x18) | \ - FTIM0_NAND_TWCHT(0x07) | \ - FTIM0_NAND_TWH(0x0a)) -#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ - FTIM1_NAND_TWBE(0x39) | \ - FTIM1_NAND_TRR(0x0e) | \ - FTIM1_NAND_TRP(0x18)) -#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ - FTIM2_NAND_TREH(0x0a) | \ - FTIM2_NAND_TWHRE(0x1e)) +#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x0e) | \ + FTIM0_NAND_TWP(0x30) | \ + FTIM0_NAND_TWCHT(0x0e) | \ + FTIM0_NAND_TWH(0x14)) +#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x64) | \ + FTIM1_NAND_TWBE(0xab) | \ + FTIM1_NAND_TRR(0x1c) | \ + FTIM1_NAND_TRP(0x30)) +#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x1e) | \ + FTIM2_NAND_TREH(0x14) | \ + FTIM2_NAND_TWHRE(0x3c)) #define CONFIG_SYS_NAND_FTIM3 0x0

#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } @@ -139,7 +131,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_MTD_NAND_VERIFY_WRITE #define CONFIG_CMD_NAND

-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) +#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)

#define CONFIG_FSL_QIXIS /* use common QIXIS code */ #define QIXIS_LBMAP_SWITCH 0x06 @@ -148,6 +140,7 @@ unsigned long get_board_ddr_clk(void); #define QIXIS_LBMAP_DFLTBANK 0x00 #define QIXIS_LBMAP_ALTBANK 0x04 #define QIXIS_RST_CTL_RESET 0x31 +#define QIXIS_RST_CTL_RESET_EN 0x30 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 @@ -185,16 +178,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY -#define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY -#define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK @@ -280,4 +263,4 @@ unsigned long get_board_ddr_clk(void); "kernel_load=0xa0000000\0" \ "kernel_size=0x1000000\0"

-#endif /* __LS2_QDS_H */ +#endif /* __LS2_RDB_H */