[U-Boot] [PATCH 1/5] arm: ls1021a: merge SoC specific code in a separate file
Create a soc.c file to put the code for soc special settings.
Signed-off-by: Yuan Yao yao.yuan@freescale.com --- arch/arm/cpu/armv7/ls102xa/Makefile | 1 + arch/arm/cpu/armv7/ls102xa/soc.c | 66 +++++++++++++++++++++++++ arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h | 12 +++++ board/freescale/ls1021aqds/ls1021aqds.c | 49 +----------------- board/freescale/ls1021atwr/ls1021atwr.c | 42 +--------------- 5 files changed, 83 insertions(+), 87 deletions(-) create mode 100644 arch/arm/cpu/armv7/ls102xa/soc.c create mode 100644 arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h
diff --git a/arch/arm/cpu/armv7/ls102xa/Makefile b/arch/arm/cpu/armv7/ls102xa/Makefile index 2d55782..24bbfba 100644 --- a/arch/arm/cpu/armv7/ls102xa/Makefile +++ b/arch/arm/cpu/armv7/ls102xa/Makefile @@ -8,6 +8,7 @@ obj-y += cpu.o obj-y += clock.o obj-y += timer.o obj-y += fsl_epu.o +obj-y += soc.o
obj-$(CONFIG_OF_LIBFDT) += fdt.o obj-$(CONFIG_SYS_HAS_SERDES) += fsl_ls1_serdes.o ls102xa_serdes.o diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c new file mode 100644 index 0000000..0fdd6d4 --- /dev/null +++ b/arch/arm/cpu/armv7/ls102xa/soc.c @@ -0,0 +1,66 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/arch/clock.h> +#include <asm/io.h> +#include <asm/arch/immap_ls102xa.h> +#include <asm/arch/ls102xa_soc.h> + +unsigned int get_soc_major_rev(void) +{ + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + unsigned int svr, major; + + svr = in_be32(&gur->svr); + major = SVR_MAJ(svr); + + return major; +} + +int arch_soc_init(void) +{ + struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; + struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; + unsigned int major; + +#ifdef CONFIG_FSL_QSPI + out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL); +#endif + +#ifdef CONFIG_FSL_DCU_FB + out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN); +#endif + + /* Configure Little endian for SAI, ASRC and SPDIF */ + out_be32(&scfg->endiancr, SCFG_ENDIANCR_LE); + + /* + * Enable snoop requests and DVM message requests for + * Slave insterface S4 (A7 core cluster) + */ + out_le32(&cci->slave[4].snoop_ctrl, + CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); + + major = get_soc_major_rev(); + if (major == SOC_MAJOR_VER_1_0) { + /* + * Set CCI-400 Slave interface S1, S2 Shareable Override + * Register All transactions are treated as non-shareable + */ + out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE); + out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE); + + /* Workaround for the issue that DDR could not respond to + * barrier transaction which is generated by executing DSB/ISB + * instruction. Set CCI-400 control override register to + * terminate the barrier transaction. After DDR is initialized, + * allow barrier transaction to DDR again */ + out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER); + } + + return 0; +} diff --git a/arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h b/arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h new file mode 100644 index 0000000..f10cb91 --- /dev/null +++ b/arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h @@ -0,0 +1,12 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __FSL_LS102XA_SOC_H +#define __FSL_LS102XA_SOC_H + +unsigned int get_soc_major_rev(void); +int arch_soc_init(void); +#endif /* __FSL_LS102XA_SOC_H */ diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c index 655fc64..fd20735 100644 --- a/board/freescale/ls1021aqds/ls1021aqds.c +++ b/board/freescale/ls1021aqds/ls1021aqds.c @@ -12,6 +12,7 @@ #include <asm/arch/clock.h> #include <asm/arch/fsl_serdes.h> #include <asm/arch/ls102xa_stream_id.h> +#include <asm/arch/ls102xa_soc.h> #include <asm/arch/ls102xa_devdis.h> #include <hwconfig.h> #include <mmc.h> @@ -225,17 +226,6 @@ unsigned long get_board_ddr_clk(void) return 66666666; }
-unsigned int get_soc_major_rev(void) -{ - struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); - unsigned int svr, major; - - svr = in_be32(&gur->svr); - major = SVR_MAJ(svr); - - return major; -} - int select_i2c_ch_pca9547(u8 ch) { int ret; @@ -278,8 +268,6 @@ int board_mmc_init(bd_t *bis) int board_early_init_f(void) { struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; - struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; - unsigned int major;
#ifdef CONFIG_TSEC_ENET /* clear BD & FR bits for BE BD's and frame data */ @@ -290,40 +278,7 @@ int board_early_init_f(void) init_early_memctl_regs(); #endif
-#ifdef CONFIG_FSL_QSPI - out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL); -#endif - -#ifdef CONFIG_FSL_DCU_FB - out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN); -#endif - - /* Configure Little endian for SAI, ASRC and SPDIF */ - out_be32(&scfg->endiancr, SCFG_ENDIANCR_LE); - - /* - * Enable snoop requests and DVM message requests for - * Slave insterface S4 (A7 core cluster) - */ - out_le32(&cci->slave[4].snoop_ctrl, - CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); - - major = get_soc_major_rev(); - if (major == SOC_MAJOR_VER_1_0) { - /* - * Set CCI-400 Slave interface S1, S2 Shareable Override - * Register All transactions are treated as non-shareable - */ - out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE); - out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE); - - /* Workaround for the issue that DDR could not respond to - * barrier transaction which is generated by executing DSB/ISB - * instruction. Set CCI-400 control override register to - * terminate the barrier transaction. After DDR is initialized, - * allow barrier transaction to DDR again */ - out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER); - } + arch_soc_init();
#if defined(CONFIG_DEEP_SLEEP) if (is_warm_boot()) diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c index 228dbf8..14ff575 100644 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -12,6 +12,7 @@ #include <asm/arch/clock.h> #include <asm/arch/fsl_serdes.h> #include <asm/arch/ls102xa_stream_id.h> +#include <asm/arch/ls102xa_soc.h> #include <asm/arch/ls102xa_devdis.h> #include <hwconfig.h> #include <mmc.h> @@ -223,17 +224,6 @@ int checkboard(void) return 0; }
-unsigned int get_soc_major_rev(void) -{ - struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); - unsigned int svr, major; - - svr = in_be32(&gur->svr); - major = SVR_MAJ(svr); - - return major; -} - void ddrmc_init(void) { struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR; @@ -479,8 +469,6 @@ conflict: int board_early_init_f(void) { struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; - struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; - unsigned int major;
#ifdef CONFIG_TSEC_ENET /* clear BD & FR bits for BE BD's and frame data */ @@ -492,33 +480,7 @@ int board_early_init_f(void) init_early_memctl_regs(); #endif
-#ifdef CONFIG_FSL_DCU_FB - out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN); -#endif - -#ifdef CONFIG_FSL_QSPI - out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL); -#endif - - /* Configure Little endian for SAI, ASRC and SPDIF */ - out_be32(&scfg->endiancr, SCFG_ENDIANCR_LE); - - /* - * Enable snoop requests and DVM message requests for - * Slave insterface S4 (A7 core cluster) - */ - out_le32(&cci->slave[4].snoop_ctrl, - CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); - - major = get_soc_major_rev(); - if (major == SOC_MAJOR_VER_1_0) { - /* - * Set CCI-400 Slave interface S1, S2 Shareable Override - * Register All transactions are treated as non-shareable - */ - out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE); - out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE); - } + arch_soc_init();
#if defined(CONFIG_DEEP_SLEEP) if (is_warm_boot())
Enable the IP feature's snoop signal to support hardware snoop for cache coherence.
SNPCNFGCR contains the bits to drive snoop signal for various masters.
Signed-off-by: Yuan Yao yao.yuan@freescale.com --- arch/arm/cpu/armv7/ls102xa/soc.c | 8 ++++++++ arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 6 ++++++ 2 files changed, 14 insertions(+)
diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c index 0fdd6d4..6036473 100644 --- a/arch/arm/cpu/armv7/ls102xa/soc.c +++ b/arch/arm/cpu/armv7/ls102xa/soc.c @@ -62,5 +62,13 @@ int arch_soc_init(void) out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER); }
+ /* Enable all the snoop signal for various masters */ + out_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SEC_RD_WR | + SCFG_SNPCNFGCR_DCU_RD_WR | + SCFG_SNPCNFGCR_SATA_RD_WR | + SCFG_SNPCNFGCR_USB3_RD_WR | + SCFG_SNPCNFGCR_DBG_RD_WR | + SCFG_SNPCNFGCR_EDMA_SNP); + return 0; } diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h index 60aa0d3..950347a 100644 --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h @@ -149,6 +149,12 @@ struct ccsr_gur { #define SCFG_ETSECCMCR_GE1_CLK125 0x08000000 #define SCFG_PIXCLKCR_PXCKEN 0x80000000 #define SCFG_QSPI_CLKSEL 0xc0100000 +#define SCFG_SNPCNFGCR_SEC_RD_WR 0xc0000000 +#define SCFG_SNPCNFGCR_DCU_RD_WR 0x03000000 +#define SCFG_SNPCNFGCR_SATA_RD_WR 0x00c00000 +#define SCFG_SNPCNFGCR_USB3_RD_WR 0x00300000 +#define SCFG_SNPCNFGCR_DBG_RD_WR 0x000c0000 +#define SCFG_SNPCNFGCR_EDMA_SNP 0x00020000 #define SCFG_ENDIANCR_LE 0x80000000
/* Supplemental Configuration Unit */
Signed-off-by: Yuan Yao yao.yuan@freescale.com --- arch/arm/cpu/armv7/ls102xa/soc.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c index 6036473..97ba6d5 100644 --- a/arch/arm/cpu/armv7/ls102xa/soc.c +++ b/arch/arm/cpu/armv7/ls102xa/soc.c @@ -40,8 +40,14 @@ int arch_soc_init(void)
/* * Enable snoop requests and DVM message requests for - * Slave insterface S4 (A7 core cluster) + * All the slave insterfaces. */ + out_le32(&cci->slave[0].snoop_ctrl, + CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); + out_le32(&cci->slave[1].snoop_ctrl, + CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); + out_le32(&cci->slave[2].snoop_ctrl, + CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); out_le32(&cci->slave[4].snoop_ctrl, CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
Affects: DDR Description: Memory controller performance is not optimal with default internal target queue register values. Impact: Memory controller performance is not optimal. Workaround: Write a value of 63b2_0002h to address: 157_020Ch.
Signed-off-by: Yuan Yao yao.yuan@freescale.com --- arch/arm/cpu/armv7/ls102xa/soc.c | 10 ++++++++++ arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 2 +- 2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c index 97ba6d5..b15cd60 100644 --- a/arch/arm/cpu/armv7/ls102xa/soc.c +++ b/arch/arm/cpu/armv7/ls102xa/soc.c @@ -76,5 +76,15 @@ int arch_soc_init(void) SCFG_SNPCNFGCR_DBG_RD_WR | SCFG_SNPCNFGCR_EDMA_SNP);
+ /* + * Memory controller require a register write before being enabled. + * Affects: DDR + * Register: EDDRTQCFG + * Description: Memory controller performance is not optimal with + * default internal target queue register values. + * Workaround: Write a value of 63b2_0002h to address: 157_020Ch. + */ + out_be32(&scfg->eddrtqcfg, 0x63b20002); + return 0; } diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h index 950347a..adb0e05 100644 --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h @@ -227,7 +227,7 @@ struct ccsr_scfg { u32 scfgrevcr; u32 coresrencr; u32 pex2pmrdsr; - u32 ddrc1cr; + u32 eddrtqcfg; u32 ddrc2cr; u32 ddrc3cr; u32 ddrc4cr;
On 10/21/2015 03:14 AM, Yuan Yao wrote:
Affects: DDR Description: Memory controller performance is not optimal with default internal target queue register values. Impact: Memory controller performance is not optimal. Workaround: Write a value of 63b2_0002h to address: 157_020Ch.
Please rewrite the commit message to explain why and what this patch does, not copy-n-paste from erratum document.
York
EDDRTQCFG Registers are Integration Strap values which controls performance parameters for DDR Controller.
The bit 25 is used to disable priorities within DDR since DDR are connected backwards on Rev2.0.
Signed-off-by: Yuan Yao yao.yuan@freescale.com --- arch/arm/cpu/armv7/ls102xa/soc.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c index b15cd60..98d4acd 100644 --- a/arch/arm/cpu/armv7/ls102xa/soc.c +++ b/arch/arm/cpu/armv7/ls102xa/soc.c @@ -25,7 +25,7 @@ int arch_soc_init(void) { struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; - unsigned int major; + unsigned int major, reg;
#ifdef CONFIG_FSL_QSPI out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL); @@ -86,5 +86,16 @@ int arch_soc_init(void) */ out_be32(&scfg->eddrtqcfg, 0x63b20002);
+ /* + * EDDRTQCFG Registers are Integration Strap values which controls + * performance parameters for DDR Controller. + * The bit 25 is used for disable priorities within DDR. + * This is a workaround because of the DDR are connected backwards + * on Rev2.0. + */ + reg = in_be32(&scfg->eddrtqcfg); + reg |= 1 << 6; + out_be32(&scfg->eddrtqcfg, reg); + return 0; }
On 10/21/2015 03:14 AM, Yuan Yao wrote:
EDDRTQCFG Registers are Integration Strap values which controls performance parameters for DDR Controller.
The bit 25 is used to disable priorities within DDR since DDR are connected backwards on Rev2.0.
Signed-off-by: Yuan Yao yao.yuan@freescale.com
arch/arm/cpu/armv7/ls102xa/soc.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c index b15cd60..98d4acd 100644 --- a/arch/arm/cpu/armv7/ls102xa/soc.c +++ b/arch/arm/cpu/armv7/ls102xa/soc.c @@ -25,7 +25,7 @@ int arch_soc_init(void) { struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
- unsigned int major;
- unsigned int major, reg;
#ifdef CONFIG_FSL_QSPI out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL); @@ -86,5 +86,16 @@ int arch_soc_init(void) */ out_be32(&scfg->eddrtqcfg, 0x63b20002);
- /*
* EDDRTQCFG Registers are Integration Strap values which controls* performance parameters for DDR Controller.* The bit 25 is used for disable priorities within DDR.* This is a workaround because of the DDR are connected backwards* on Rev2.0.*/
Is there an erratum number for this? If not, please be specific about rev 2.0. Is it SoC version, or something else?
York
Yes, it's an erratum. But I don't have the erratum number from the document. I will connect the hardware team to check whether there is an erratum number.
Thanks.
Best Regards, Yuan Yao
-----Original Message----- From: York Sun [mailto:yorksun@freescale.com] Sent: Thursday, November 05, 2015 2:49 AM To: Yuan Yao-B46683 yao.yuan@freescale.com; Wang Huan-B18965 alison.wang@freescale.com Cc: u-boot@lists.denx.de Subject: Re: [PATCH 5/5] LS102XA:workaround:disable priorities within DDR
On 10/21/2015 03:14 AM, Yuan Yao wrote:
EDDRTQCFG Registers are Integration Strap values which controls performance parameters for DDR Controller.
The bit 25 is used to disable priorities within DDR since DDR are connected backwards on Rev2.0.
Signed-off-by: Yuan Yao yao.yuan@freescale.com
arch/arm/cpu/armv7/ls102xa/soc.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c index b15cd60..98d4acd 100644 --- a/arch/arm/cpu/armv7/ls102xa/soc.c +++ b/arch/arm/cpu/armv7/ls102xa/soc.c @@ -25,7 +25,7 @@ int arch_soc_init(void) { struct ccsr_scfg *scfg = (struct ccsr_scfg
*)CONFIG_SYS_FSL_SCFG_ADDR;
struct ccsr_cci400 *cci = (struct ccsr_cci400
*)CONFIG_SYS_CCI400_ADDR;
- unsigned int major;
- unsigned int major, reg;
#ifdef CONFIG_FSL_QSPI out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL); @@ -86,5 +86,16 @@
int
arch_soc_init(void) */ out_be32(&scfg->eddrtqcfg, 0x63b20002);
- /*
* EDDRTQCFG Registers are Integration Strap values which controls* performance parameters for DDR Controller.* The bit 25 is used for disable priorities within DDR.* This is a workaround because of the DDR are connected backwards* on Rev2.0.*/Is there an erratum number for this? If not, please be specific about rev 2.0. Is it SoC version, or something else?
York
Reviewed-by: Alison Wang alison.wang@freescale.com
Best Regards, Alison Wang
-----Original Message----- From: Yuan Yao [mailto:yao.yuan@freescale.com] Sent: Wednesday, October 21, 2015 6:15 PM To: Sun York-R58495; Wang Huan-B18965 Cc: u-boot@lists.denx.de Subject: [PATCH 1/5] arm: ls1021a: merge SoC specific code in a separate file
Create a soc.c file to put the code for soc special settings.
Signed-off-by: Yuan Yao yao.yuan@freescale.com
arch/arm/cpu/armv7/ls102xa/Makefile | 1 + arch/arm/cpu/armv7/ls102xa/soc.c | 66 +++++++++++++++++++++++++ arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h | 12 +++++ board/freescale/ls1021aqds/ls1021aqds.c | 49 +----------------- board/freescale/ls1021atwr/ls1021atwr.c | 42 +--------------- 5 files changed, 83 insertions(+), 87 deletions(-) create mode 100644 arch/arm/cpu/armv7/ls102xa/soc.c create mode 100644 arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h
diff --git a/arch/arm/cpu/armv7/ls102xa/Makefile b/arch/arm/cpu/armv7/ls102xa/Makefile index 2d55782..24bbfba 100644 --- a/arch/arm/cpu/armv7/ls102xa/Makefile +++ b/arch/arm/cpu/armv7/ls102xa/Makefile @@ -8,6 +8,7 @@ obj-y += cpu.o obj-y += clock.o obj-y += timer.o obj-y += fsl_epu.o +obj-y += soc.o
obj-$(CONFIG_OF_LIBFDT) += fdt.o obj-$(CONFIG_SYS_HAS_SERDES) += fsl_ls1_serdes.o ls102xa_serdes.o diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c new file mode 100644 index 0000000..0fdd6d4 --- /dev/null +++ b/arch/arm/cpu/armv7/ls102xa/soc.c @@ -0,0 +1,66 @@ +/*
- Copyright 2015 Freescale Semiconductor, Inc.
- SPDX-License-Identifier: GPL-2.0+
- */
+#include <common.h> +#include <asm/arch/clock.h> +#include <asm/io.h> +#include <asm/arch/immap_ls102xa.h> +#include <asm/arch/ls102xa_soc.h>
+unsigned int get_soc_major_rev(void) +{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
- unsigned int svr, major;
- svr = in_be32(&gur->svr);
- major = SVR_MAJ(svr);
- return major;
+}
+int arch_soc_init(void) +{
- struct ccsr_scfg *scfg = (struct ccsr_scfg
*)CONFIG_SYS_FSL_SCFG_ADDR;
- struct ccsr_cci400 *cci = (struct ccsr_cci400
*)CONFIG_SYS_CCI400_ADDR;
- unsigned int major;
+#ifdef CONFIG_FSL_QSPI
- out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL); #endif
+#ifdef CONFIG_FSL_DCU_FB
- out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN); #endif
- /* Configure Little endian for SAI, ASRC and SPDIF */
- out_be32(&scfg->endiancr, SCFG_ENDIANCR_LE);
- /*
* Enable snoop requests and DVM message requests for* Slave insterface S4 (A7 core cluster)*/- out_le32(&cci->slave[4].snoop_ctrl,
CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);- major = get_soc_major_rev();
- if (major == SOC_MAJOR_VER_1_0) {
/** Set CCI-400 Slave interface S1, S2 Shareable Override* Register All transactions are treated as non-shareable*/out_le32(&cci->slave[1].sha_ord,CCI400_SHAORD_NON_SHAREABLE);
out_le32(&cci->slave[2].sha_ord,CCI400_SHAORD_NON_SHAREABLE);
/* Workaround for the issue that DDR could not respond to* barrier transaction which is generated by executingDSB/ISB
* instruction. Set CCI-400 control override register to* terminate the barrier transaction. After DDR isinitialized,
* allow barrier transaction to DDR again */out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);- }
- return 0;
+} diff --git a/arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h b/arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h new file mode 100644 index 0000000..f10cb91 --- /dev/null +++ b/arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h @@ -0,0 +1,12 @@ +/*
- Copyright 2015 Freescale Semiconductor, Inc.
- SPDX-License-Identifier: GPL-2.0+
- */
+#ifndef __FSL_LS102XA_SOC_H +#define __FSL_LS102XA_SOC_H
+unsigned int get_soc_major_rev(void); +int arch_soc_init(void); +#endif /* __FSL_LS102XA_SOC_H */ diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c index 655fc64..fd20735 100644 --- a/board/freescale/ls1021aqds/ls1021aqds.c +++ b/board/freescale/ls1021aqds/ls1021aqds.c @@ -12,6 +12,7 @@ #include <asm/arch/clock.h> #include <asm/arch/fsl_serdes.h> #include <asm/arch/ls102xa_stream_id.h> +#include <asm/arch/ls102xa_soc.h> #include <asm/arch/ls102xa_devdis.h> #include <hwconfig.h> #include <mmc.h> @@ -225,17 +226,6 @@ unsigned long get_board_ddr_clk(void) return 66666666; }
-unsigned int get_soc_major_rev(void) -{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
- unsigned int svr, major;
- svr = in_be32(&gur->svr);
- major = SVR_MAJ(svr);
- return major;
-}
int select_i2c_ch_pca9547(u8 ch) { int ret; @@ -278,8 +268,6 @@ int board_mmc_init(bd_t *bis) int board_early_init_f(void) { struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
- struct ccsr_cci400 *cci = (struct ccsr_cci400
*)CONFIG_SYS_CCI400_ADDR;
- unsigned int major;
#ifdef CONFIG_TSEC_ENET /* clear BD & FR bits for BE BD's and frame data */ @@ -290,40 +278,7 @@ int board_early_init_f(void) init_early_memctl_regs(); #endif
-#ifdef CONFIG_FSL_QSPI
- out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
-#endif
-#ifdef CONFIG_FSL_DCU_FB
- out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN);
-#endif
- /* Configure Little endian for SAI, ASRC and SPDIF */
- out_be32(&scfg->endiancr, SCFG_ENDIANCR_LE);
- /*
* Enable snoop requests and DVM message requests for* Slave insterface S4 (A7 core cluster)*/- out_le32(&cci->slave[4].snoop_ctrl,
CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);- major = get_soc_major_rev();
- if (major == SOC_MAJOR_VER_1_0) {
/** Set CCI-400 Slave interface S1, S2 Shareable Override* Register All transactions are treated as non-shareable*/out_le32(&cci->slave[1].sha_ord,CCI400_SHAORD_NON_SHAREABLE);
out_le32(&cci->slave[2].sha_ord,CCI400_SHAORD_NON_SHAREABLE);
/* Workaround for the issue that DDR could not respond to* barrier transaction which is generated by executingDSB/ISB
* instruction. Set CCI-400 control override register to* terminate the barrier transaction. After DDR isinitialized,
* allow barrier transaction to DDR again */out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);- }
- arch_soc_init();
#if defined(CONFIG_DEEP_SLEEP) if (is_warm_boot()) diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c index 228dbf8..14ff575 100644 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -12,6 +12,7 @@ #include <asm/arch/clock.h> #include <asm/arch/fsl_serdes.h> #include <asm/arch/ls102xa_stream_id.h> +#include <asm/arch/ls102xa_soc.h> #include <asm/arch/ls102xa_devdis.h> #include <hwconfig.h> #include <mmc.h> @@ -223,17 +224,6 @@ int checkboard(void) return 0; }
-unsigned int get_soc_major_rev(void) -{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
- unsigned int svr, major;
- svr = in_be32(&gur->svr);
- major = SVR_MAJ(svr);
- return major;
-}
void ddrmc_init(void) { struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR; @@ -479,8 +469,6 @@ conflict: int board_early_init_f(void) { struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
- struct ccsr_cci400 *cci = (struct ccsr_cci400
*)CONFIG_SYS_CCI400_ADDR;
- unsigned int major;
#ifdef CONFIG_TSEC_ENET /* clear BD & FR bits for BE BD's and frame data */ @@ -492,33 +480,7 @@ int board_early_init_f(void) init_early_memctl_regs(); #endif
-#ifdef CONFIG_FSL_DCU_FB
- out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN);
-#endif
-#ifdef CONFIG_FSL_QSPI
- out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
-#endif
- /* Configure Little endian for SAI, ASRC and SPDIF */
- out_be32(&scfg->endiancr, SCFG_ENDIANCR_LE);
- /*
* Enable snoop requests and DVM message requests for* Slave insterface S4 (A7 core cluster)*/- out_le32(&cci->slave[4].snoop_ctrl,
CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);- major = get_soc_major_rev();
- if (major == SOC_MAJOR_VER_1_0) {
/** Set CCI-400 Slave interface S1, S2 Shareable Override* Register All transactions are treated as non-shareable*/out_le32(&cci->slave[1].sha_ord,CCI400_SHAORD_NON_SHAREABLE);
out_le32(&cci->slave[2].sha_ord,CCI400_SHAORD_NON_SHAREABLE);
- }
- arch_soc_init();
#if defined(CONFIG_DEEP_SLEEP) if (is_warm_boot()) -- 2.1.0.27.g96db324
participants (4)
-
Huan Wang -
Yao Yuan -
York Sun -
Yuan Yao