[U-Boot] [Patch v2 0/7] Add support for TQMa6 modules
From: Markus Niebel Markus.Niebel@tq-group.com
This series add support for the TQMa6 boards from TQ Systems. The first Patch adds basic support for the modiules and the starterkit baseboard while the other patches add additional features
Markus Niebel (7): Add TQ Systems TQMa6 board support TQMa6: mba6: add RGMII enet TQMa6: add SPI support TQMa6: add SPI NOR boot support TQMa6: MBa6: add usb support TQMa6: add I2C support TQMa6: add pmic support
board/tqc/tqma6/Makefile | 9 + board/tqc/tqma6/README | 35 ++++ board/tqc/tqma6/clocks.cfg | 24 +++ board/tqc/tqma6/tqma6.c | 258 +++++++++++++++++++++++ board/tqc/tqma6/tqma6_bb.h | 30 +++ board/tqc/tqma6/tqma6_mba6.c | 358 +++++++++++++++++++++++++++++++ board/tqc/tqma6/tqma6q.cfg | 125 +++++++++++ board/tqc/tqma6/tqma6s.cfg | 125 +++++++++++ boards.cfg | 4 + include/configs/tqma6.h | 477 ++++++++++++++++++++++++++++++++++++++++++ 10 files changed, 1445 insertions(+) create mode 100644 board/tqc/tqma6/Makefile create mode 100644 board/tqc/tqma6/README create mode 100644 board/tqc/tqma6/clocks.cfg create mode 100644 board/tqc/tqma6/tqma6.c create mode 100644 board/tqc/tqma6/tqma6_bb.h create mode 100644 board/tqc/tqma6/tqma6_mba6.c create mode 100644 board/tqc/tqma6/tqma6q.cfg create mode 100644 board/tqc/tqma6/tqma6s.cfg create mode 100644 include/configs/tqma6.h
From: Markus Niebel Markus.Niebel@tq-group.com
This patch adds the changes to boards.cfg and the board directory under board/tqc.
TQMa6 is a family of modules based on Freescale i.MX6. It consists of TQMa6Q (i.MX6 Quad), TQMa6D (i.MX6 Dual) featuring eMMC, and 1 GiB DDR3 TQMa6S (i.MX6 Solo) featuring eMMC and 512 MiB DDR3 The modules can be boot from SD (on USDHC2) and eMMC (on USDHC3).
Additional features will be added later: - Ethernet - SPI - I2C - USB
The modules needs a baseboard. Initially the MBa6x starterkit mainboard is supported. To easy support for other mainboards the functionality is splitted in one file for the module (tqma6.c) and one file for the baseboard (tqma6_ mba6)
Signed-off-by: Markus Niebel Markus.Niebel@tq-group.com --- - changes for v2: - fix long line warning as suggested by W. Denk - remove baudrate from CONFIG_EXTRA_ENV_SETTINGS - remove unused define CONFIG_TQMA6X_BASEBOARD_NAME - add missing mmcblkdev definition to mmcboot logic in CONFIG_EXTRA_ENV_SETTINGS
board/tqc/tqma6/Makefile | 9 ++ board/tqc/tqma6/README | 31 ++++++ board/tqc/tqma6/clocks.cfg | 24 +++++ board/tqc/tqma6/tqma6.c | 186 ++++++++++++++++++++++++++++++++++ board/tqc/tqma6/tqma6_bb.h | 30 ++++++ board/tqc/tqma6/tqma6_mba6.c | 148 +++++++++++++++++++++++++++ board/tqc/tqma6/tqma6q.cfg | 125 +++++++++++++++++++++++ board/tqc/tqma6/tqma6s.cfg | 125 +++++++++++++++++++++++ boards.cfg | 2 + include/configs/tqma6.h | 225 ++++++++++++++++++++++++++++++++++++++++++ 10 files changed, 905 insertions(+) create mode 100644 board/tqc/tqma6/Makefile create mode 100644 board/tqc/tqma6/README create mode 100644 board/tqc/tqma6/clocks.cfg create mode 100644 board/tqc/tqma6/tqma6.c create mode 100644 board/tqc/tqma6/tqma6_bb.h create mode 100644 board/tqc/tqma6/tqma6_mba6.c create mode 100644 board/tqc/tqma6/tqma6q.cfg create mode 100644 board/tqc/tqma6/tqma6s.cfg create mode 100644 include/configs/tqma6.h
diff --git a/board/tqc/tqma6/Makefile b/board/tqc/tqma6/Makefile new file mode 100644 index 0000000..9ee6920 --- /dev/null +++ b/board/tqc/tqma6/Makefile @@ -0,0 +1,9 @@ +# +# Copyright (C) 2014, Markus Niebel Markus.Niebel@tq-group.com +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := tqma6.o + +obj-$(CONFIG_MBA6) += tqma6_mba6.o diff --git a/board/tqc/tqma6/README b/board/tqc/tqma6/README new file mode 100644 index 0000000..096cd17 --- /dev/null +++ b/board/tqc/tqma6/README @@ -0,0 +1,31 @@ +U-Boot for the TQ Systems TQMa6 modules + +This file contains information for the port of +U-Boot to the TQ Systems TQMa6 modules. + +1. Boot source +-------------- + +The following boot source is supported: + +- SD/eMMC + +2. Building +------------ + +To build U-Boot for the TQ Systems TQMa6 modules: + + make tqma6<x>_<baseboard>_<boot>_config + make + +x is a placeholder for the CPU variant +q - means i.MX6Q/D: TQMa6Q (i.MX6Q) and TQMa6D (i.MX6D) +s - means i.MX6S: TQMa6S (i.MX6S) + +baseboard is a placeholder for the boot device +mmc - means eMMC + +This gives the following configurations: + +tqma6q_mba6_mmc_config +tqma6s_mba6_mmc_config diff --git a/board/tqc/tqma6/clocks.cfg b/board/tqc/tqma6/clocks.cfg new file mode 100644 index 0000000..d9dd273 --- /dev/null +++ b/board/tqc/tqma6/clocks.cfg @@ -0,0 +1,24 @@ +/* + * Copyright (C) 2013 Boundary Devices + * Copyright (C) 2013, 2014 Markus Niebel Markus.Niebel@tq-group.com + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer doc/README.imximage for more details about how-to configure + * and create imximage boot image + */ + +/* set the default clock gate to save power */ +DATA 4, CCM_CCGR0, 0x00C03F3F +DATA 4, CCM_CCGR1, 0x0030FC03 +DATA 4, CCM_CCGR2, 0x0FFFC000 +DATA 4, CCM_CCGR3, 0x3FF00000 +DATA 4, CCM_CCGR4, 0x00FFF300 +DATA 4, CCM_CCGR5, 0x0F0000C3 +DATA 4, CCM_CCGR6, 0x000003FF + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +DATA 4, MX6_IOMUXC_GPR6, 0x007F007F +DATA 4, MX6_IOMUXC_GPR7, 0x007F007F diff --git a/board/tqc/tqma6/tqma6.c b/board/tqc/tqma6/tqma6.c new file mode 100644 index 0000000..66fbc06 --- /dev/null +++ b/board/tqc/tqma6/tqma6.c @@ -0,0 +1,186 @@ +/* + * Copyright (C) 2012 Freescale Semiconductor, Inc. + * Author: Fabio Estevam fabio.estevam@freescale.com + * + * Copyright (C) 2013, 2014 TQ Systems (ported SabreSD to TQMa6x) + * Author: Markus Niebel markus.niebel@tq-group.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/arch/clock.h> +#include <asm/arch/mx6-pins.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/iomux.h> +#include <asm/arch/sys_proto.h> +#include <asm/errno.h> +#include <asm/gpio.h> +#include <asm/io.h> +#include <common.h> +#include <fsl_esdhc.h> +#include <libfdt.h> +#include <mmc.h> + +#include "tqma6_bb.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define USDHC_CLK_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define GPIO_OUT_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define GPIO_IN_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); + + return 0; +} + +static const uint16_t tqma6_emmc_dsr = 0x0100; + +/* eMMC on USDHCI3 always present */ +static iomux_v3_cfg_t const tqma6_usdhc3_pads[] = { + NEW_PAD_CTRL(MX6_PAD_SD3_CLK__SD3_CLK, USDHC_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_SD3_CMD__SD3_CMD, USDHC_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_SD3_DAT0__SD3_DATA0, USDHC_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_SD3_DAT1__SD3_DATA1, USDHC_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_SD3_DAT2__SD3_DATA2, USDHC_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_SD3_DAT3__SD3_DATA3, USDHC_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_SD3_DAT4__SD3_DATA4, USDHC_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_SD3_DAT5__SD3_DATA5, USDHC_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_SD3_DAT6__SD3_DATA6, USDHC_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_SD3_DAT7__SD3_DATA7, USDHC_PAD_CTRL), + /* eMMC reset */ + NEW_PAD_CTRL(MX6_PAD_SD3_RST__SD3_RESET, GPIO_OUT_PAD_CTRL), +}; + +/* + * According to the board_mmc_init() the following map is done: + * (U-boot device node) (Physical Port) + * mmc0 eMMC (SD3) + * mmc1 SD2 + */ +struct fsl_esdhc_cfg tqma6_usdhc_cfg = { + .esdhc_base = USDHC3_BASE_ADDR +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + if (cfg->esdhc_base == USDHC3_BASE_ADDR) + /* eMMC/uSDHC3 is always present */ + ret = 1; + else + ret = tqma6_bb_board_mmc_getcd(mmc); + + return ret; +} + +int board_mmc_getwp(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + if (cfg->esdhc_base == USDHC3_BASE_ADDR) + /* eMMC/uSDHC3 is always present */ + ret = 0; + else + ret = tqma6_bb_board_mmc_getwp(mmc); + + return ret; +} + +int board_mmc_init(bd_t *bis) +{ + imx_iomux_v3_setup_multiple_pads(tqma6_usdhc3_pads, + ARRAY_SIZE(tqma6_usdhc3_pads)); + tqma6_usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + if (fsl_esdhc_initialize(bis, &tqma6_usdhc_cfg)) { + printf("Warning: failed to initialize eMMC dev\n"); + } else { + struct mmc *mmc = find_mmc_device(0); + if (mmc) + mmc_set_dsr(mmc, tqma6_emmc_dsr); + } + + tqma6_bb_board_mmc_init(bis); + + return 0; +} + +int board_early_init_f(void) +{ + return tqma6_bb_board_early_init_f(); +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + tqma6_bb_board_init(); + + return 0; +} + +static const char *tqma6_get_boardname(void) +{ + u32 cpurev = get_cpu_rev(); + + switch ((cpurev & 0xFF000) >> 12) { + case MXC_CPU_MX6SOLO: + return "TQMa6S"; + break; + case MXC_CPU_MX6DL: + return "TQMa6DL"; + break; + case MXC_CPU_MX6D: + return "TQMa6D"; + break; + case MXC_CPU_MX6Q: + return "TQMa6Q"; + break; + default: + return "??"; + }; +} + +int board_late_init(void) +{ + setenv("board", tqma6_get_boardname()); + + tqma6_bb_board_late_init(); + + return 0; +} + +int checkboard(void) +{ + printf("Board: %s on a %s\n", tqma6_get_boardname(), + tqma6_bb_get_boardname()); + return 0; +} + +/* ++ * Device Tree Support ++ */ +#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) +void ft_board_setup(void *blob, bd_t *bd) +{ + /* bring in eMMC dsr settings */ + do_fixup_by_path_u32(blob, + "/soc/aips-bus@02100000/usdhc@02198000", + "tq,dsr", tqma6_emmc_dsr, 2); + tqma6_bb_ft_board_setup(blob, bd); +} +#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */ diff --git a/board/tqc/tqma6/tqma6_bb.h b/board/tqc/tqma6/tqma6_bb.h new file mode 100644 index 0000000..9d072d2 --- /dev/null +++ b/board/tqc/tqma6/tqma6_bb.h @@ -0,0 +1,30 @@ +/* + * Copyright (C) 2013, 2014 TQ Systems + * Author: Markus Niebel markus.niebel@tq-group.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __TQMA6_BB__ +#define __TQMA6_BB + +#include <common.h> + +int tqma6_bb_board_mmc_getwp(struct mmc *mmc); +int tqma6_bb_board_mmc_getcd(struct mmc *mmc); +int tqma6_bb_board_mmc_init(bd_t *bis); + +int tqma6_bb_board_early_init_f(void); +int tqma6_bb_board_init(void); +int tqma6_bb_board_late_init(void); +int tqma6_bb_checkboard(void); + +const char *tqma6_bb_get_boardname(void); +/* + * Device Tree Support + */ +#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) +void tqma6_bb_ft_board_setup(void *blob, bd_t *bd); +#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */ + +#endif diff --git a/board/tqc/tqma6/tqma6_mba6.c b/board/tqc/tqma6/tqma6_mba6.c new file mode 100644 index 0000000..8679db8 --- /dev/null +++ b/board/tqc/tqma6/tqma6_mba6.c @@ -0,0 +1,148 @@ +/* + * Copyright (C) 2012 Freescale Semiconductor, Inc. + * Author: Fabio Estevam fabio.estevam@freescale.com + * + * Copyright (C) 2013, 2014 TQ Systems (ported SabreSD to TQMa6x) + * Author: Markus Niebel markus.niebel@tq-group.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/mx6-pins.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/iomux.h> +#include <asm/arch/sys_proto.h> +#include <asm/errno.h> +#include <asm/gpio.h> + +#include <common.h> +#include <fsl_esdhc.h> +#include <libfdt.h> +#include <mmc.h> + +#include "tqma6_bb.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_CLK_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define GPIO_OUT_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define GPIO_IN_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +static iomux_v3_cfg_t const mba6_uart2_pads[] = { + NEW_PAD_CTRL(MX6_PAD_SD4_DAT4__UART2_RX_DATA, UART_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_SD4_DAT7__UART2_TX_DATA, UART_PAD_CTRL), +}; + +static void mba6_setup_iomuxc_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(mba6_uart2_pads, + ARRAY_SIZE(mba6_uart2_pads)); +} + +#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4) +#define USDHC2_WP_GPIO IMX_GPIO_NR(1, 2) + +/* + * According to the board_mmc_init() the following map is done: + * (U-boot device node) (Physical Port) + * mmc0 eMMC (SD3) + * mmc1 SD2 + */ + +int tqma6_bb_board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + if (cfg->esdhc_base == USDHC2_BASE_ADDR) + ret = !gpio_get_value(USDHC2_CD_GPIO); + + return ret; +} + +int tqma6_bb_board_mmc_getwp(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + if (cfg->esdhc_base == USDHC2_BASE_ADDR) + ret = !gpio_get_value(USDHC2_WP_GPIO); + + return ret; +} + +static struct fsl_esdhc_cfg mba6_usdhc_cfg = { + .esdhc_base = USDHC3_BASE_ADDR +}; + +static iomux_v3_cfg_t const mba6_usdhc2_pads[] = { + NEW_PAD_CTRL(MX6_PAD_SD2_CLK__SD2_CLK, USDHC_CLK_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_SD2_CMD__SD2_CMD, USDHC_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_SD2_DAT0__SD2_DATA0, USDHC_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_SD2_DAT1__SD2_DATA1, USDHC_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_SD2_DAT2__SD2_DATA2, USDHC_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_SD2_DAT3__SD2_DATA3, USDHC_PAD_CTRL), + /* CD */ + NEW_PAD_CTRL(MX6_PAD_GPIO_4__GPIO1_IO04, GPIO_IN_PAD_CTRL), + /* WP */ + NEW_PAD_CTRL(MX6_PAD_GPIO_2__GPIO1_IO02, GPIO_IN_PAD_CTRL), +}; + +int tqma6_bb_board_mmc_init(bd_t *bis) +{ + imx_iomux_v3_setup_multiple_pads(mba6_usdhc2_pads, + ARRAY_SIZE(mba6_usdhc2_pads)); + gpio_direction_input(USDHC2_CD_GPIO); + gpio_direction_input(USDHC2_WP_GPIO); + + mba6_usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + if (fsl_esdhc_initialize(bis, &mba6_usdhc_cfg)) + printf("Warning: failed to initialize SD\n"); + + return 0; +} + +int tqma6_bb_board_early_init_f(void) +{ + mba6_setup_iomuxc_uart(); + + return 0; +} + +int tqma6_bb_board_init(void) +{ + return 0; +} + +int tqma6_bb_board_late_init(void) +{ + return 0; +} + +const char *tqma6_bb_get_boardname(void) +{ + return "MBa6x"; +} + +/* + * Device Tree Support + */ +#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) +void tqma6_bb_ft_board_setup(void *blob, bd_t *bd) +{ + /* TBD */ +} +#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */ diff --git a/board/tqc/tqma6/tqma6q.cfg b/board/tqc/tqma6/tqma6q.cfg new file mode 100644 index 0000000..f54dff7 --- /dev/null +++ b/board/tqc/tqma6/tqma6q.cfg @@ -0,0 +1,125 @@ +/* + * Copyright (C) 2013, 2014 Markus Niebel Markus.Niebel@tq-group.com + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer doc/README.imximage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +/* image version */ +IMAGE_VERSION 2 + +#define __ASSEMBLY__ +#include <config.h> + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ +#if defined(CONFIG_TQMA6X_MMC_BOOT) +BOOT_FROM sd +#elif defined(CONFIG_TQMA6X_SPI_BOOT) +BOOT_FROM spi +#endif + +#include "asm/arch/mx6-ddr.h" +#include "asm/arch/iomux.h" +#include "asm/arch/crm_regs.h" + +/* TQMa6Q/D DDR config Rev. 0100B */ +/* IOMUX configuration */ +DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000 +DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000 +DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00008030 +DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00008030 +DATA 4, MX6_IOM_DRAM_CAS, 0x00008030 +DATA 4, MX6_IOM_DRAM_RAS, 0x00008030 +DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030 +DATA 4, MX6_IOM_DRAM_RESET, 0x000C3030 +DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000 +DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00000000 +DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000 +DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030 +DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030 +DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030 +DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000 +DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030 +DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000 +DATA 4, MX6_IOM_GRP_B0DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B1DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B2DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B3DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B4DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B5DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B6DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B7DS, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM0, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM1, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM2, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM3, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM4, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM5, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM6, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM7, 0x00000030 + +/* memory interface calibration values */ +DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003 +DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003 +DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001B0013 +DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x0018001B +DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x001B0016 +DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x0012001C +DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x43400350 +DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x023E032C +DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x43400348 +DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x03300304 +DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x3C323436 +DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x38383242 +DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x3E3C4440 +DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x4236483E +DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 + +/* configure memory interface */ +DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036 +DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040 +DATA 4, MX6_MMDC_P0_MDCFG0, 0x545A79B4 +DATA 4, MX6_MMDC_P0_MDCFG1, 0xDB538F64 +DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB +DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 +DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2 +DATA 4, MX6_MMDC_P0_MDOR, 0x005A1023 +DATA 4, MX6_MMDC_P0_MDASP, 0x00000027 +DATA 4, MX6_MMDC_P0_MDCTL, 0x831A0000 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00088032 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031 +DATA 4, MX6_MMDC_P0_MDSCR, 0x09308030 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 +DATA 4, MX6_MMDC_P0_MDREF, 0x00005800 +DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022222 +DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022222 +DATA 4, MX6_MMDC_P0_MDPDC, 0x00025536 +DATA 4, MX6_MMDC_P0_MAPSR, 0x00001006 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 + +#include "clocks.cfg" diff --git a/board/tqc/tqma6/tqma6s.cfg b/board/tqc/tqma6/tqma6s.cfg new file mode 100644 index 0000000..24d4e2f --- /dev/null +++ b/board/tqc/tqma6/tqma6s.cfg @@ -0,0 +1,125 @@ +/* + * Copyright (C) 2013, 2014 Markus Niebel Markus.Niebel@tq-group.com + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer doc/README.imximage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +/* image version */ +IMAGE_VERSION 2 + +#define __ASSEMBLY__ +#include <config.h> + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ +#if defined(CONFIG_TQMA6X_MMC_BOOT) +BOOT_FROM sd +#elif defined(CONFIG_TQMA6X_SPI_BOOT) +BOOT_FROM spi +#endif + +#include "asm/arch/mx6-ddr.h" +#include "asm/arch/iomux.h" +#include "asm/arch/crm_regs.h" + +/* TQMa6S DDR config Rev. 0100B */ +/* IOMUX configuration */ +DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000 +DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000 +DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00008000 +DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00008030 +DATA 4, MX6_IOM_DRAM_CAS, 0x00008030 +DATA 4, MX6_IOM_DRAM_RAS, 0x00008030 +DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030 +DATA 4, MX6_IOM_DRAM_RESET, 0x000C3030 +DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000 +DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00000000 +DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000 +DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030 +DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030 +DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030 +DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000 +DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000000 +DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000000 +DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000000 +DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000000 +DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000 +DATA 4, MX6_IOM_GRP_B0DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B1DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B2DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B3DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B4DS, 0x00000000 +DATA 4, MX6_IOM_GRP_B5DS, 0x00000000 +DATA 4, MX6_IOM_GRP_B6DS, 0x00000000 +DATA 4, MX6_IOM_GRP_B7DS, 0x00000000 +DATA 4, MX6_IOM_DRAM_DQM0, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM1, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM2, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM3, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM4, 0x00000000 +DATA 4, MX6_IOM_DRAM_DQM5, 0x00000000 +DATA 4, MX6_IOM_DRAM_DQM6, 0x00000000 +DATA 4, MX6_IOM_DRAM_DQM7, 0x00000000 + +/* memory interface calibration values */ +DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003 +DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1380000 +DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x0014000E +DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x00120014 +DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00000000 +DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x00000000 +DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x0240023C +DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x0228022C +DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x00000000 +DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x00000000 +DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4A4A4E4A +DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x00000000 +DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x36362A32 +DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x00000000 +DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x00000000 +DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x00000000 +DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x00000000 +DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x00000000 +DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000000 + +/* configure memory interface */ +DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002D +DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030 +DATA 4, MX6_MMDC_P0_MDCFG0, 0x3F435333 +DATA 4, MX6_MMDC_P0_MDCFG1, 0xB68E8B63 +DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB +DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 +DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2 +DATA 4, MX6_MMDC_P0_MDOR, 0x00431023 +DATA 4, MX6_MMDC_P0_MDASP, 0x00000017 +DATA 4, MX6_MMDC_P0_MDCTL, 0x83190000 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008032 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031 +DATA 4, MX6_MMDC_P0_MDSCR, 0x05208030 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 +DATA 4, MX6_MMDC_P0_MDREF, 0x00005800 +DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022222 +DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00000000 +DATA 4, MX6_MMDC_P0_MDPDC, 0x0002552D +DATA 4, MX6_MMDC_P0_MAPSR, 0x00001006 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 + +#include "clocks.cfg" diff --git a/boards.cfg b/boards.cfg index fd4324d..4868ed9 100644 --- a/boards.cfg +++ b/boards.cfg @@ -330,6 +330,8 @@ Active arm armv7 mx6 freescale mx6sabresd Active arm armv7 mx6 freescale mx6slevk mx6slevk mx6slevk:IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL Fabio Estevam fabio.estevam@freescale.com Active arm armv7 mx6 gateworks gw_ventana gwventana gw_ventana:IMX_CONFIG=board/gateworks/gw_ventana/gw_ventana.cfg,MX6QDL,SPL Tim Harvey tharvey@gateworks.com Active arm armv7 mx6 solidrun hummingboard hummingboard_solo hummingboard:IMX_CONFIG=board/solidrun/hummingboard/solo.cfg,MX6S,DDR_MB=512 Jon Nettleton jon.nettleton@gmail.com +Active arm armv7 mx6 tqc tqma6 tqma6q_mba6_mmc tqma6:IMX_CONFIG=board/tqc/tqma6/tqma6q.cfg,MX6Q,MBA6,TQMA6X_MMC_BOOT Markus Niebel Markus.Niebel@tq-group.com +Active arm armv7 mx6 tqc tqma6 tqma6s_mba6_mmc tqma6:IMX_CONFIG=board/tqc/tqma6/tqma6s.cfg,MX6S,MBA6,TQMA6X_MMC_BOOT Markus Niebel Markus.Niebel@tq-group.com Active arm armv7 omap3 - overo omap3_overo - Steve Sakoman sakoman@gmail.com Active arm armv7 omap3 - pandora omap3_pandora - Grazvydas Ignotas notasas@gmail.com Active arm armv7 omap3 8dtech eco5pk eco5pk - Raphael Assenat raph@8d.com diff --git a/include/configs/tqma6.h b/include/configs/tqma6.h new file mode 100644 index 0000000..4a2eaa2 --- /dev/null +++ b/include/configs/tqma6.h @@ -0,0 +1,225 @@ +/* + * Copyright (C) 2013, 2014 Markus Niebel Markus.Niebel@tq-group.com + * + * Configuration settings for the TQ Systems TQMa6<Q,S> module. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include "mx6_common.h" +#include <asm/arch/imx-regs.h> +#include <asm/imx-common/gpio.h> +#include <linux/sizes.h> + +#define CONFIG_MX6 + +#if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S) +#define PHYS_SDRAM_SIZE (512u * SZ_1M) +#elif defined(CONFIG_MX6Q) +#define PHYS_SDRAM_SIZE (1024u * SZ_1M) +#endif + +#if defined(CONFIG_MBA6) + +#if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S) +#define CONFIG_DEFAULT_FDT_FILE "imx6dl-mba6x.dtb" +#elif defined(CONFIG_MX6Q) +#define CONFIG_DEFAULT_FDT_FILE "imx6q-mba6x.dtb" +#endif + +#endif + +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_SYS_GENERIC_BOARD + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_LATE_INIT + +#define CONFIG_MXC_GPIO +#define CONFIG_MXC_UART + +/* MMC Configs */ +#define CONFIG_FSL_ESDHC +#define CONFIG_FSL_USDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 + +#define CONFIG_MMC +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_BOUNCE_BUFFER + +/* Fuses */ +#define CONFIG_MXC_OCOTP +#define CONFIG_CMD_FUSE + +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION + +#if defined(CONFIG_MBA6) + +#define CONFIG_MXC_UART_BASE UART2_BASE +#define CONFIG_CONSOLE_DEV "ttymxc1" + +#else + +#error "define baseboard specific things (uart, number of SD-card slots)" + +#endif + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 + +/* Command definition */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_BMODE +#define CONFIG_CMD_BOOTZ +#define CONFIG_CMD_ITEST +#define CONFIG_CMD_SETEXPR +#undef CONFIG_CMD_IMLS + +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_LOADADDR 0x12000000 +#define CONFIG_SYS_TEXT_BASE 0x17800000 + +#define CONFIG_ENV_SIZE (SZ_8K) +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * SZ_1M) + +#if defined(CONFIG_TQMA6X_MMC_BOOT) + +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_UBOOT_OFFSET SZ_1K +#define CONFIG_UBOOT_SECTOR_START 0x2 +#define CONFIG_UBOOT_SECTOR_COUNT 0x7fe + +#define CONFIG_ENV_OFFSET SZ_1M +#define CONFIG_SYS_MMC_ENV_DEV 0 + +#define CONFIG_FDT_OFFSET (2 * SZ_1M) +#define CONFIG_FDT_SECTOR_START 0x1000 +#define CONFIG_FDT_SECTOR_COUNT 0x800 + +#define CONFIG_KERNEL_SECTOR_START 0x2000 +#define CONFIG_KERNEL_SECTOR_COUNT 0x2000 + +#define CONFIG_EXTRA_BOOTDEV_ENV_SETTINGS \ + "uboot_start="__stringify(CONFIG_UBOOT_SECTOR_START)"\0" \ + "uboot_size="__stringify(CONFIG_UBOOT_SECTOR_COUNT)"\0" \ + "fdt_start="__stringify(CONFIG_FDT_SECTOR_START)"\0" \ + "fdt_size="__stringify(CONFIG_FDT_SECTOR_COUNT)"\0" \ + "kernel_start="__stringify(CONFIG_KERNEL_SECTOR_START)"\0" \ + "kernel_size="__stringify(CONFIG_KERNEL_SECTOR_COUNT)"\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "loadimage=mmc dev ${mmcdev}; " \ + "mmc read ${loadaddr} ${kernel_start} ${kernel_size};\0" \ + "loadfdt=mmc dev ${mmcdev}; " \ + "mmc read ${fdt_addr} ${fdt_start} ${fdt_size};\0" \ + +#define CONFIG_BOOTCOMMAND \ + "run mmcboot; run panicboot" + +#else + +#error "need to define boot source" + +#endif + +#define CONFIG_FDT_ADDRESS 0x11000000 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "board=tqma6\0" \ + "uimage=uImage\0" \ + "zimage=zImage\0" \ + "boot_type=bootz\0" \ + "kernel_name=if test "${boot_type}" != bootz; then " \ + "setenv kernel ${uimage}; " \ + "else setenv kernel ${zimage}; fi\0" \ + "uboot=u-boot.imx\0" \ + "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "fdt_addr="__stringify(CONFIG_FDT_ADDRESS)"\0" \ + "console=" CONFIG_CONSOLE_DEV "\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "addtty=setenv bootargs ${bootargs} console=${console},${baudrate}\0" \ + "addfb=setenv bootargs ${bootargs} " \ + "imx-fbdev.legacyfb_depth=32 consoleblank=0\0" \ + "mmcpart=2\0" \ + "mmcargs=run addmmc addtty addfb\0" \ + "addmmc=setenv bootargs ${bootargs} " \ + "root=/dev/mmcblk${mmcblkdev}p${mmcpart} rw " \ + "rootfstype=${rootfstype} rootwait\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "setenv bootargs; " \ + "setenv mmcblkdev 0; " \ + "run mmcargs; " \ + "run loadimage; " \ + "if run loadfdt; then " \ + "echo boot device tree kernel ...; " \ + "${boot_type} ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "${boot_type}; " \ + "fi;\0" \ + "setenv bootargs \0" \ + "panicboot=echo No boot device !!! reset\0" \ + CONFIG_EXTRA_BOOTDEV_ENV_SETTINGS \ + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_CBSIZE 512 + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_CMDLINE_EDITING +#define CONFIG_STACKSIZE (128u * SZ_1K) + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* FLASH and environment organization */ +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP +#define CONFIG_FIT +#define CONFIG_FIT_VERBOSE + +#ifndef CONFIG_SYS_DCACHE_OFF +#define CONFIG_CMD_CACHE +#endif + +#endif /* __CONFIG_H */
From: Markus Niebel Markus.Niebel@tq-group.com
Add RGMII ethernet using micrel KSZ9031 phy to mba6 mainboard for TQMa6<x> module. The phy needs special configurateions for the pad skew registers to adjust for the signal routing.
Also support for standard ethernet commands and uppdate via tftp is supported.
Signed-off-by: Markus Niebel Markus.Niebel@tq-group.com --- - changes for v2: - add missing stuff for tftp and nfs in CONFIG_EXTRA_ENV_SETTINGS - fix fdt_file in env (was partially fdt)
board/tqc/tqma6/tqma6_mba6.c | 158 ++++++++++++++++++++++++++++++++++++++++++ include/configs/tqma6.h | 94 ++++++++++++++++++++++++- 2 files changed, 251 insertions(+), 1 deletion(-)
diff --git a/board/tqc/tqma6/tqma6_mba6.c b/board/tqc/tqma6/tqma6_mba6.c index 8679db8..c30f379 100644 --- a/board/tqc/tqma6/tqma6_mba6.c +++ b/board/tqc/tqma6/tqma6_mba6.c @@ -20,7 +20,11 @@ #include <common.h> #include <fsl_esdhc.h> #include <libfdt.h> +#include <malloc.h> +#include <micrel.h> +#include <miiphy.h> #include <mmc.h> +#include <netdev.h>
#include "tqma6_bb.h"
@@ -41,6 +45,87 @@ DECLARE_GLOBAL_DATA_PTR; #define GPIO_IN_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \ PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+#if defined(CONFIG_MX6Q) + +#define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII 0x02e0790 +#define IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM 0x02e07ac + +#elif defined(CONFIG_MX6S) + +#define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII 0x02e0768 +#define IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM 0x02e0788 + +#else + +#error "need to define target CPU" + +#endif + +#define ENET_RX_PAD_CTRL (PAD_CTL_DSE_34ohm) +#define ENET_TX_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_34ohm) +#define ENET_CLK_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH | \ + PAD_CTL_DSE_34ohm) +#define ENET_MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_60ohm) + +/* disable on die termination for RGMII */ +#define IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM_DISABLE 0x00000000 +/* optimised drive strength for 1.0 .. 1.3 V signal on RGMII */ +#define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII_1P2V 0x00080000 +/* optimised drive strength for 1.3 .. 2.5 V signal on RGMII */ +#define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII_1P5V 0x000C0000 + +#define ENET_PHY_RESET_GPIO IMX_GPIO_NR(1, 25) + +static iomux_v3_cfg_t const mba6_enet_pads[] = { + NEW_PAD_CTRL(MX6_PAD_ENET_MDIO__ENET_MDIO, ENET_MDIO_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_ENET_MDC__ENET_MDC, ENET_MDIO_PAD_CTRL), + + NEW_PAD_CTRL(MX6_PAD_RGMII_TXC__RGMII_TXC, ENET_TX_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_RGMII_TD0__RGMII_TD0, ENET_TX_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_RGMII_TD1__RGMII_TD1, ENET_TX_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_RGMII_TD2__RGMII_TD2, ENET_TX_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_RGMII_TD3__RGMII_TD3, ENET_TX_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL, ENET_TX_PAD_CTRL), + + NEW_PAD_CTRL(MX6_PAD_ENET_REF_CLK__ENET_TX_CLK, ENET_CLK_PAD_CTRL), + /* + * these pins are also used for config strapping by phy + */ + NEW_PAD_CTRL(MX6_PAD_RGMII_RD0__RGMII_RD0, ENET_RX_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_RGMII_RD1__RGMII_RD1, ENET_RX_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_RGMII_RD2__RGMII_RD2, ENET_RX_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_RGMII_RD3__RGMII_RD3, ENET_RX_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_RGMII_RXC__RGMII_RXC, ENET_RX_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL, ENET_RX_PAD_CTRL), + /* KSZ9031 PHY Reset */ + NEW_PAD_CTRL(MX6_PAD_ENET_CRS_DV__GPIO1_IO25, GPIO_OUT_PAD_CTRL), +}; + +static void mba6_setup_iomuxc_enet(void) +{ + __raw_writel(IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM_DISABLE, + (void *)IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM); + __raw_writel(IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII_1P5V, + (void *)IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII); + + imx_iomux_v3_setup_multiple_pads(mba6_enet_pads, + ARRAY_SIZE(mba6_enet_pads)); + + /* Reset PHY */ + gpio_direction_output(ENET_PHY_RESET_GPIO , 0); + /* Need delay 10ms after power on according to KSZ9031 spec */ + udelay(1000 * 10); + gpio_set_value(ENET_PHY_RESET_GPIO, 1); + /* + * KSZ9031 manual: 100 usec wait time after reset before communication + * over MDIO + * BUGBUG: hardware has an RC const that needs > 10 msec from 0->1 on + * reset before the phy sees a high level + */ + udelay(200); +} + static iomux_v3_cfg_t const mba6_uart2_pads[] = { NEW_PAD_CTRL(MX6_PAD_SD4_DAT4__UART2_RX_DATA, UART_PAD_CTRL), NEW_PAD_CTRL(MX6_PAD_SD4_DAT7__UART2_TX_DATA, UART_PAD_CTRL), @@ -115,6 +200,76 @@ int tqma6_bb_board_mmc_init(bd_t *bis) return 0; }
+int board_phy_config(struct phy_device *phydev) +{ +#if defined(CONFIG_MX6Q) +#define MBA6X_KSZ9031_CTRL_SKEW 0x0032 +#define MBA6X_KSZ9031_CLK_SKEW 0x03ff +#define MBA6X_KSZ9031_RX_SKEW 0x3333 +#define MBA6X_KSZ9031_TX_SKEW 0x2036 +#elif defined(CONFIG_MX6S) +#define MBA6X_KSZ9031_CTRL_SKEW 0x0030 +#define MBA6X_KSZ9031_CLK_SKEW 0x03ff +#define MBA6X_KSZ9031_RX_SKEW 0x3333 +#define MBA6X_KSZ9031_TX_SKEW 0x2052 +#else +#error +#endif + /* min rx/tx ctrl delay */ + ksz9031_phy_extended_write(phydev, 2, + MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW, + MII_KSZ9031_MOD_DATA_NO_POST_INC, + MBA6X_KSZ9031_CTRL_SKEW); + /* min rx delay */ + ksz9031_phy_extended_write(phydev, 2, + MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW, + MII_KSZ9031_MOD_DATA_NO_POST_INC, + MBA6X_KSZ9031_RX_SKEW); + /* max tx delay */ + ksz9031_phy_extended_write(phydev, 2, + MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW, + MII_KSZ9031_MOD_DATA_NO_POST_INC, + MBA6X_KSZ9031_TX_SKEW); + /* rx/tx clk skew */ + ksz9031_phy_extended_write(phydev, 2, + MII_KSZ9031_EXT_RGMII_CLOCK_SKEW, + MII_KSZ9031_MOD_DATA_NO_POST_INC, + MBA6X_KSZ9031_CLK_SKEW); + + phydev->drv->config(phydev); + + return 0; +} + +int board_eth_init(bd_t *bis) +{ + uint32_t base = IMX_FEC_BASE; + struct mii_dev *bus = NULL; + struct phy_device *phydev = NULL; + int ret; + + bus = fec_get_miibus(base, -1); + if (!bus) + return 0; + /* scan phy */ + phydev = phy_find_by_mask(bus, (0xf << CONFIG_FEC_MXC_PHYADDR), + PHY_INTERFACE_MODE_RGMII); + + if (!phydev) { + free(bus); + printf("No phy found\n"); + return 0; + } + ret = fec_probe(bis, -1, base, bus, phydev); + if (ret) { + printf("FEC MXC: %s:failed\n", __func__); + free(phydev); + free(bus); + } + + return 0; +} + int tqma6_bb_board_early_init_f(void) { mba6_setup_iomuxc_uart(); @@ -124,6 +279,9 @@ int tqma6_bb_board_early_init_f(void)
int tqma6_bb_board_init(void) { + /* do it here - to have reset completed */ + mba6_setup_iomuxc_enet(); + return 0; }
diff --git a/include/configs/tqma6.h b/include/configs/tqma6.h index 4a2eaa2..055675e 100644 --- a/include/configs/tqma6.h +++ b/include/configs/tqma6.h @@ -65,6 +65,37 @@ #define CONFIG_CMD_FAT #define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET + +#define CONFIG_FEC_MXC +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_PHYLIB +#define CONFIG_MII + +#if defined(CONFIG_MBA6) + +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_ETHPRIME "FEC" + +#define CONFIG_FEC_MXC_PHYADDR 0x03 +#define CONFIG_PHY_MICREL +#define CONFIG_PHY_KSZ9031 + +#else + +#error "define PHY to use for your baseboard" + +#endif + +#define CONFIG_ARP_TIMEOUT 200UL +/* Network config - Allow larger/faster download for TFTP/NFS */ +#define CONFIG_IP_DEFRAG +#define CONFIG_TFTP_BLOCKSIZE 4096 +#define CONFIG_NFS_READ_SIZE 4096 + #if defined(CONFIG_MBA6)
#define CONFIG_MXC_UART_BASE UART2_BASE @@ -128,9 +159,43 @@ "mmc read ${loadaddr} ${kernel_start} ${kernel_size};\0" \ "loadfdt=mmc dev ${mmcdev}; " \ "mmc read ${fdt_addr} ${fdt_start} ${fdt_size};\0" \ + "update_uboot=if tftp ${uboot}; then " \ + "if itest ${filesize} > 0; then " \ + "mmc dev ${mmcdev}; mmc rescan; " \ + "setexpr blkc ${filesize} / 0x200; " \ + "setexpr blkc ${blkc} + 1; " \ + "if itest ${blkc} <= ${uboot_size}; then " \ + "mmc write ${loadaddr} ${uboot_start} " \ + "${blkc}; " \ + "fi; " \ + "fi; fi; " \ + "setenv filesize; setenv blkc \0" \ + "update_kernel=run kernel_name; " \ + "if tftp ${kernel}; then " \ + "if itest ${filesize} > 0; then " \ + "mmc dev ${mmcdev}; mmc rescan; " \ + "setexpr blkc ${filesize} / 0x200; " \ + "setexpr blkc ${blkc} + 1; " \ + "if itest ${blkc} <= ${kernel_size}; then " \ + "mmc write ${loadaddr} " \ + "${kernel_start} ${blkc}; " \ + "fi; " \ + "fi; " \ + "fi; " \ + "setenv filesize; setenv blkc \0" \ + "update_fdt=if tftp ${fdt_file}; then " \ + "if itest ${filesize} > 0; then " \ + "mmc dev ${mmcdev}; mmc rescan; " \ + "setexpr blkc ${filesize} / 0x200; " \ + "setexpr blkc ${blkc} + 1; " \ + "if itest ${blkc} <= ${fdt_size}; then " \ + "mmc write ${loadaddr} ${fdt_start} ${blkc}; " \ + "fi; " \ + "fi; fi; " \ + "setenv filesize; setenv blkc \0" \
#define CONFIG_BOOTCOMMAND \ - "run mmcboot; run panicboot" + "run mmcboot; run netboot; run panicboot"
#else
@@ -174,6 +239,33 @@ "${boot_type}; " \ "fi;\0" \ "setenv bootargs \0" \ + "netdev=eth0\0" \ + "nfsroot=/srv/nfs/tqma6\0" \ + "ipmode=static\0" \ + "netargs=run addnfs addip addtty addfb\0" \ + "addnfs=setenv bootargs ${bootargs} " \ + "root=/dev/nfs rw " \ + "nfsroot=${serverip}:${nfsroot},v3,tcp;\0" \ + "addip_static=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:" \ + "${hostname}:${netdev}:off\0" \ + "addip_dynamic=setenv bootargs ${bootargs} ip=dhcp\0" \ + "addip=if test "${ipmode}" != static; then " \ + "run addip_dynamic; else run addip_static; fi\0" \ + "set_getcmd=if test "${ipmode}" != static; then " \ + "setenv getcmd dhcp; setenv autoload yes; " \ + "else setenv getcmd tftp; setenv autoload no; fi\0" \ + "netboot=echo Booting from net ...; " \ + "run kernel_name; " \ + "run set_getcmd; " \ + "setenv bootargs; " \ + "run netargs; " \ + "if ${getcmd} ${kernel}; then " \ + "if ${getcmd} ${fdt_addr} ${fdt_file}; then " \ + "${boot_type} ${loadaddr} - ${fdt_addr}; " \ + "fi; " \ + "fi; " \ + "echo ... failed\0" \ "panicboot=echo No boot device !!! reset\0" \ CONFIG_EXTRA_BOOTDEV_ENV_SETTINGS \
From: Markus Niebel Markus.Niebel@tqs.de
This patch adds the support for SPI, the serial flash on TQMa6<x> and the two additional CS on MBa6
Signed-off-by: Markus Niebel Markus.Niebel@tq-group.com --- board/tqc/tqma6/tqma6.c | 27 +++++++++++++++++++++++++++ board/tqc/tqma6/tqma6_mba6.c | 24 ++++++++++++++++++++++++ include/configs/tqma6.h | 14 ++++++++++++++ 3 files changed, 65 insertions(+)
diff --git a/board/tqc/tqma6/tqma6.c b/board/tqc/tqma6/tqma6.c index 66fbc06..7c737d1 100644 --- a/board/tqc/tqma6/tqma6.c +++ b/board/tqc/tqma6/tqma6.c @@ -37,6 +37,9 @@ DECLARE_GLOBAL_DATA_PTR; #define GPIO_IN_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \ PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+#define SPI_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + int dram_init(void) { gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); @@ -118,6 +121,28 @@ int board_mmc_init(bd_t *bis) return 0; }
+static iomux_v3_cfg_t const tqma6_ecspi1_pads[] = { + /* SS1 */ + NEW_PAD_CTRL(MX6_PAD_EIM_D19__GPIO3_IO19, SPI_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_EIM_D16__ECSPI1_SCLK, SPI_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_EIM_D17__ECSPI1_MISO, SPI_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_EIM_D18__ECSPI1_MOSI, SPI_PAD_CTRL), +}; + +static unsigned const tqma6_ecspi1_cs[] = { + IMX_GPIO_NR(3, 19), +}; + +static void tqma6_iomuxc_spi(void) +{ + unsigned i; + + for (i = 0; i < ARRAY_SIZE(tqma6_ecspi1_cs); ++i) + gpio_direction_output(tqma6_ecspi1_cs[i], 1); + imx_iomux_v3_setup_multiple_pads(tqma6_ecspi1_pads, + ARRAY_SIZE(tqma6_ecspi1_pads)); +} + int board_early_init_f(void) { return tqma6_bb_board_early_init_f(); @@ -128,6 +153,8 @@ int board_init(void) /* address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+ tqma6_iomuxc_spi(); + tqma6_bb_board_init();
return 0; diff --git a/board/tqc/tqma6/tqma6_mba6.c b/board/tqc/tqma6/tqma6_mba6.c index c30f379..94df68f 100644 --- a/board/tqc/tqma6/tqma6_mba6.c +++ b/board/tqc/tqma6/tqma6_mba6.c @@ -45,6 +45,9 @@ DECLARE_GLOBAL_DATA_PTR; #define GPIO_IN_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \ PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+#define SPI_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + #if defined(CONFIG_MX6Q)
#define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII 0x02e0790 @@ -200,6 +203,26 @@ int tqma6_bb_board_mmc_init(bd_t *bis) return 0; }
+static iomux_v3_cfg_t const mba6_ecspi1_pads[] = { + NEW_PAD_CTRL(MX6_PAD_EIM_D24__GPIO3_IO24, SPI_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_EIM_D25__GPIO3_IO25, SPI_PAD_CTRL), +}; + +static unsigned const mba6_ecspi1_cs[] = { + IMX_GPIO_NR(3, 24), + IMX_GPIO_NR(3, 25), +}; + +static void mba6_setup_iomuxc_spi(void) +{ + unsigned i; + + for (i = 0; i < ARRAY_SIZE(mba6_ecspi1_cs); ++i) + gpio_direction_output(mba6_ecspi1_cs[i], 1); + imx_iomux_v3_setup_multiple_pads(mba6_ecspi1_pads, + ARRAY_SIZE(mba6_ecspi1_pads)); +} + int board_phy_config(struct phy_device *phydev) { #if defined(CONFIG_MX6Q) @@ -279,6 +302,7 @@ int tqma6_bb_board_early_init_f(void)
int tqma6_bb_board_init(void) { + mba6_setup_iomuxc_spi(); /* do it here - to have reset completed */ mba6_setup_iomuxc_enet();
diff --git a/include/configs/tqma6.h b/include/configs/tqma6.h index 055675e..2c5016d 100644 --- a/include/configs/tqma6.h +++ b/include/configs/tqma6.h @@ -47,6 +47,20 @@ #define CONFIG_MXC_GPIO #define CONFIG_MXC_UART
+/* SPI */ +#define CONFIG_CMD_SPI +#define CONFIG_MXC_SPI + +/* SPI Flash */ +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_STMICRO + +#define CONFIG_CMD_SF +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_CS (0 | (IMX_GPIO_NR(3, 19) << 8)) +#define CONFIG_SF_DEFAULT_SPEED 50000000 +#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) + /* MMC Configs */ #define CONFIG_FSL_ESDHC #define CONFIG_FSL_USDHC
From: Markus Niebel Markus.Niebel@tqs.de
This patch adds support for booting from SPI NOR flash and having the environment also in SPI NOR. Also all environment settings to allow update of bootloader and kernel are added.
Signed-off-by: Markus Niebel Markus.Niebel@tq-group.com --- board/tqc/tqma6/README | 4 ++ boards.cfg | 2 + include/configs/tqma6.h | 103 +++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 109 insertions(+)
diff --git a/board/tqc/tqma6/README b/board/tqc/tqma6/README index 096cd17..2c012e7 100644 --- a/board/tqc/tqma6/README +++ b/board/tqc/tqma6/README @@ -9,6 +9,7 @@ U-Boot to the TQ Systems TQMa6 modules. The following boot source is supported:
- SD/eMMC +- SPI NOR
2. Building ------------ @@ -24,8 +25,11 @@ s - means i.MX6S: TQMa6S (i.MX6S)
baseboard is a placeholder for the boot device mmc - means eMMC +spi - mean SPI NOR
This gives the following configurations:
tqma6q_mba6_mmc_config +tqma6q_mba6_spi_config tqma6s_mba6_mmc_config +tqma6s_mba6_spi_config diff --git a/boards.cfg b/boards.cfg index 4868ed9..d41288a 100644 --- a/boards.cfg +++ b/boards.cfg @@ -331,7 +331,9 @@ Active arm armv7 mx6 freescale mx6slevk Active arm armv7 mx6 gateworks gw_ventana gwventana gw_ventana:IMX_CONFIG=board/gateworks/gw_ventana/gw_ventana.cfg,MX6QDL,SPL Tim Harvey tharvey@gateworks.com Active arm armv7 mx6 solidrun hummingboard hummingboard_solo hummingboard:IMX_CONFIG=board/solidrun/hummingboard/solo.cfg,MX6S,DDR_MB=512 Jon Nettleton jon.nettleton@gmail.com Active arm armv7 mx6 tqc tqma6 tqma6q_mba6_mmc tqma6:IMX_CONFIG=board/tqc/tqma6/tqma6q.cfg,MX6Q,MBA6,TQMA6X_MMC_BOOT Markus Niebel Markus.Niebel@tq-group.com +Active arm armv7 mx6 tqc tqma6 tqma6q_mba6_spi tqma6:IMX_CONFIG=board/tqc/tqma6/tqma6q.cfg,MX6Q,MBA6,TQMA6X_SPI_BOOT Markus Niebel Markus.Niebel@tq-group.com Active arm armv7 mx6 tqc tqma6 tqma6s_mba6_mmc tqma6:IMX_CONFIG=board/tqc/tqma6/tqma6s.cfg,MX6S,MBA6,TQMA6X_MMC_BOOT Markus Niebel Markus.Niebel@tq-group.com +Active arm armv7 mx6 tqc tqma6 tqma6s_mba6_spi tqma6:IMX_CONFIG=board/tqc/tqma6/tqma6s.cfg,MX6S,MBA6,TQMA6X_SPI_BOOT Markus Niebel Markus.Niebel@tq-group.com Active arm armv7 omap3 - overo omap3_overo - Steve Sakoman sakoman@gmail.com Active arm armv7 omap3 - pandora omap3_pandora - Grazvydas Ignotas notasas@gmail.com Active arm armv7 omap3 8dtech eco5pk eco5pk - Raphael Assenat raph@8d.com diff --git a/include/configs/tqma6.h b/include/configs/tqma6.h index 2c5016d..d2b12c3 100644 --- a/include/configs/tqma6.h +++ b/include/configs/tqma6.h @@ -211,6 +211,109 @@ #define CONFIG_BOOTCOMMAND \ "run mmcboot; run netboot; run panicboot"
+#elif defined(CONFIG_TQMA6X_SPI_BOOT) + +#define CONFIG_FLASH_SECTOR_SIZE 0x10000 + +#define CONFIG_UBOOT_OFFSET 0x400 +#define CONFIG_UBOOT_SECTOR_START 0x0 +/* max u-boot size: 512k */ +#define CONFIG_UBOOT_SECTOR_SIZE CONFIG_FLASH_SECTOR_SIZE +#define CONFIG_UBOOT_SECTOR_COUNT 0x8 +#define CONFIG_UBOOT_SIZE (CONFIG_UBOOT_SECTOR_SIZE * \ + CONFIG_UBOOT_SECTOR_COUNT) + +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT +#define CONFIG_ENV_OFFSET (CONFIG_UBOOT_SIZE) +#define CONFIG_ENV_SECT_SIZE CONFIG_FLASH_SECTOR_SIZE +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ + CONFIG_ENV_SECT_SIZE) + +#define CONFIG_ENV_SPI_BUS (CONFIG_SF_DEFAULT_BUS) +#define CONFIG_ENV_SPI_CS (CONFIG_SF_DEFAULT_CS) +#define CONFIG_ENV_SPI_MAX_HZ (CONFIG_SF_DEFAULT_SPEED) +#define CONFIG_ENV_SPI_MODE (CONFIG_SF_DEFAULT_MODE) + +#define CONFIG_FDT_OFFSET (CONFIG_ENV_OFFSET_REDUND + \ + CONFIG_ENV_SECT_SIZE) +#define CONFIG_FDT_SECT_SIZE (CONFIG_FLASH_SECTOR_SIZE) + +#define CONFIG_FDT_SECTOR_START 0x0a /* 8 Sector u-boot, 2 Sector env */ +#define CONFIG_FDT_SECTOR_COUNT 0x01 + +#define CONFIG_KERNEL_SECTOR_START 0x10 +#define CONFIG_KERNEL_SECTOR_COUNT 0x60 + +#define CONFIG_EXTRA_BOOTDEV_ENV_SETTINGS \ + "mmcblkdev=0\0" \ + "uboot_offset="__stringify(CONFIG_UBOOT_OFFSET)"\0" \ + "uboot_sectors="__stringify(CONFIG_UBOOT_SECTOR_COUNT)"\0" \ + "fdt_start="__stringify(CONFIG_FDT_SECTOR_START)"\0" \ + "fdt_sectors="__stringify(CONFIG_FDT_SECTOR_COUNT)"\0" \ + "kernel_start="__stringify(CONFIG_KERNEL_SECTOR_START)"\0" \ + "kernel_sectors="__stringify(CONFIG_KERNEL_SECTOR_COUNT)"\0" \ + "update_uboot=if tftp ${uboot}; then " \ + "if itest ${filesize} > 0; then " \ + "setexpr blkc ${filesize} + " \ + __stringify(CONFIG_UBOOT_OFFSET) "; " \ + "setexpr size ${uboot_sectors} * " \ + __stringify(CONFIG_FLASH_SECTOR_SIZE)"; " \ + "if itest ${blkc} <= ${size}; then " \ + "sf probe; " \ + "sf erase 0 ${size}; " \ + "sf write ${loadaddr} ${uboot_offset} " \ + "${filesize}; " \ + "fi; " \ + "fi; fi; " \ + "setenv filesize 0; setenv blkc; setenv size \0" \ + "update_kernel=run kernel_name; if tftp ${kernel}; then " \ + "if itest ${filesize} > 0; then " \ + "setexpr size ${kernel_sectors} * " \ + __stringify(CONFIG_FLASH_SECTOR_SIZE)"; " \ + "setexpr offset ${kernel_start} * " \ + __stringify(CONFIG_FLASH_SECTOR_SIZE)"; " \ + "if itest ${filesize} <= ${size}; then " \ + "sf probe; " \ + "sf erase ${offset} ${size}; " \ + "sf write ${loadaddr} ${offset} " \ + "${filesize}; " \ + "fi; " \ + "fi; fi; " \ + "setenv filesize 0; setenv size ; setenv offset\0" \ + "update_fdt=if tftp ${fdt_file}; then " \ + "if itest ${filesize} > 0; then " \ + "setexpr size ${fdt_sectors} * " \ + __stringify(CONFIG_FLASH_SECTOR_SIZE)"; " \ + "setexpr offset ${fdt_start} * " \ + __stringify(CONFIG_FLASH_SECTOR_SIZE)"; " \ + "if itest ${filesize} <= ${size}; then " \ + "sf probe; " \ + "sf erase ${offset} ${size}; " \ + "sf write ${loadaddr} ${offset} " \ + "${filesize}; " \ + "fi; " \ + "fi; fi; " \ + "setenv filesize 0; setenv size ; setenv offset\0" \ + "loadimage=sf probe; " \ + "setexpr size ${kernel_sectors} * " \ + __stringify(CONFIG_FLASH_SECTOR_SIZE)"; " \ + "setexpr offset ${kernel_start} * " \ + __stringify(CONFIG_FLASH_SECTOR_SIZE)"; " \ + "sf read ${loadaddr} ${offset} ${size}; " \ + "setenv size ; setenv offset\0" \ + "loadfdt=sf probe; " \ + "setexpr size ${fdt_sectors} * " \ + __stringify(CONFIG_FLASH_SECTOR_SIZE)"; " \ + "setexpr offset ${fdt_start} * " \ + __stringify(CONFIG_FLASH_SECTOR_SIZE)"; " \ + "sf read ${${fdt_addr}} ${offset} ${size}; " \ + "setenv size ; setenv offset\0" \ + + +#define CONFIG_BOOTCOMMAND \ + "sf probe; run mmcboot; run netboot; run panicboot" \ + #else
#error "need to define boot source"
From: Markus Niebel Markus.Niebel@tqs.de
add support for USB and USB storage on the USB ports on the MBA6 baseboard for TQMa6 moduels
Signed-off-by: Markus Niebel Markus.Niebel@tq-group.com --- board/tqc/tqma6/tqma6_mba6.c | 7 +++++++ include/configs/tqma6.h | 11 +++++++++++ 2 files changed, 18 insertions(+)
diff --git a/board/tqc/tqma6/tqma6_mba6.c b/board/tqc/tqma6/tqma6_mba6.c index 94df68f..4082e05 100644 --- a/board/tqc/tqma6/tqma6_mba6.c +++ b/board/tqc/tqma6/tqma6_mba6.c @@ -293,6 +293,13 @@ int board_eth_init(bd_t *bis) return 0; }
+#ifdef CONFIG_USB_EHCI_MX6 +int board_ehci_hcd_init(int port) +{ + return 0; +} +#endif + int tqma6_bb_board_early_init_f(void) { mba6_setup_iomuxc_uart(); diff --git a/include/configs/tqma6.h b/include/configs/tqma6.h index d2b12c3..115f45a 100644 --- a/include/configs/tqma6.h +++ b/include/configs/tqma6.h @@ -71,6 +71,17 @@ #define CONFIG_GENERIC_MMC #define CONFIG_BOUNCE_BUFFER
+/* USB Configs */ +#define CONFIG_CMD_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_MX6 +#define CONFIG_USB_STORAGE +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_SMSC95XX +#define CONFIG_MXC_USB_PORT 1 +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 + /* Fuses */ #define CONFIG_MXC_OCOTP #define CONFIG_CMD_FUSE
From: Markus Niebel Markus.Niebel@tqs.de
This patch adds support for the I2C busses and devices on the TQMa6 modules and MBa6 baseboards. Support for the PMIC will be added later on.
Signed-off-by: Markus Niebel Markus.Niebel@tq-group.com --- board/tqc/tqma6/tqma6.c | 27 +++++++++++++++++++++++++++ board/tqc/tqma6/tqma6_mba6.c | 35 ++++++++++++++++++++++++++++------- include/configs/tqma6.h | 27 +++++++++++++++++++++++++++ 3 files changed, 82 insertions(+), 7 deletions(-)
diff --git a/board/tqc/tqma6/tqma6.c b/board/tqc/tqma6/tqma6.c index 7c737d1..556a70d 100644 --- a/board/tqc/tqma6/tqma6.c +++ b/board/tqc/tqma6/tqma6.c @@ -16,9 +16,11 @@ #include <asm/errno.h> #include <asm/gpio.h> #include <asm/io.h> +#include <asm/imx-common/mxc_i2c.h> #include <common.h> #include <fsl_esdhc.h> #include <libfdt.h> +#include <i2c.h> #include <mmc.h>
#include "tqma6_bb.h" @@ -40,6 +42,10 @@ DECLARE_GLOBAL_DATA_PTR; #define SPI_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE | PAD_CTL_SRE_FAST) + int dram_init(void) { gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); @@ -143,6 +149,26 @@ static void tqma6_iomuxc_spi(void) ARRAY_SIZE(tqma6_ecspi1_pads)); }
+static struct i2c_pads_info tqma6_i2c3_pads = { + /* I2C3: on board LM75, M24C64, */ + .scl = { + .i2c_mode = NEW_PAD_CTRL(MX6_PAD_GPIO_5__I2C3_SCL, I2C_PAD_CTRL), + .gpio_mode = NEW_PAD_CTRL(MX6_PAD_GPIO_5__GPIO1_IO05, I2C_PAD_CTRL), + .gp = IMX_GPIO_NR(1, 5) + }, + .sda = { + .i2c_mode = NEW_PAD_CTRL(MX6_PAD_GPIO_6__I2C3_SDA, I2C_PAD_CTRL), + .gpio_mode = NEW_PAD_CTRL(MX6_PAD_GPIO_6__GPIO1_IO06, I2C_PAD_CTRL), + .gp = IMX_GPIO_NR(1, 6) + } +}; + +static void tqma6_setup_i2c(void) +{ + /* use logical index for bus, e.g. I2C1 -> 0 */ + setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &tqma6_i2c3_pads); +} + int board_early_init_f(void) { return tqma6_bb_board_early_init_f(); @@ -154,6 +180,7 @@ int board_init(void) gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
tqma6_iomuxc_spi(); + tqma6_setup_i2c();
tqma6_bb_board_init();
diff --git a/board/tqc/tqma6/tqma6_mba6.c b/board/tqc/tqma6/tqma6_mba6.c index 4082e05..276ffe5 100644 --- a/board/tqc/tqma6/tqma6_mba6.c +++ b/board/tqc/tqma6/tqma6_mba6.c @@ -16,11 +16,13 @@ #include <asm/arch/sys_proto.h> #include <asm/errno.h> #include <asm/gpio.h> +#include <asm/imx-common/mxc_i2c.h>
#include <common.h> #include <fsl_esdhc.h> #include <libfdt.h> #include <malloc.h> +#include <i2c.h> #include <micrel.h> #include <miiphy.h> #include <mmc.h> @@ -48,6 +50,10 @@ DECLARE_GLOBAL_DATA_PTR; #define SPI_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE | PAD_CTL_SRE_FAST) + #if defined(CONFIG_MX6Q)
#define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII 0x02e0790 @@ -203,6 +209,27 @@ int tqma6_bb_board_mmc_init(bd_t *bis) return 0; }
+static struct i2c_pads_info mba6_i2c1_pads = { +/* I2C1: MBa6x */ + .scl = { + .i2c_mode = NEW_PAD_CTRL(MX6_PAD_CSI0_DAT9__I2C1_SCL, I2C_PAD_CTRL), + .gpio_mode = NEW_PAD_CTRL(MX6_PAD_CSI0_DAT9__GPIO5_IO27, I2C_PAD_CTRL), + .gp = IMX_GPIO_NR(5, 27) + }, + .sda = { + .i2c_mode = NEW_PAD_CTRL(MX6_PAD_CSI0_DAT8__I2C1_SDA, I2C_PAD_CTRL), + .gpio_mode = NEW_PAD_CTRL(MX6_PAD_CSI0_DAT8__GPIO5_IO26, I2C_PAD_CTRL), + .gp = IMX_GPIO_NR(5, 26) + } +}; + +static void mba6_setup_i2c(void) +{ + /* use logical index for bus, e.g. I2C1 -> 0 */ + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mba6_i2c1_pads); +} + + static iomux_v3_cfg_t const mba6_ecspi1_pads[] = { NEW_PAD_CTRL(MX6_PAD_EIM_D24__GPIO3_IO24, SPI_PAD_CTRL), NEW_PAD_CTRL(MX6_PAD_EIM_D25__GPIO3_IO25, SPI_PAD_CTRL), @@ -293,13 +320,6 @@ int board_eth_init(bd_t *bis) return 0; }
-#ifdef CONFIG_USB_EHCI_MX6 -int board_ehci_hcd_init(int port) -{ - return 0; -} -#endif - int tqma6_bb_board_early_init_f(void) { mba6_setup_iomuxc_uart(); @@ -309,6 +329,7 @@ int tqma6_bb_board_early_init_f(void)
int tqma6_bb_board_init(void) { + mba6_setup_i2c(); mba6_setup_iomuxc_spi(); /* do it here - to have reset completed */ mba6_setup_iomuxc_enet(); diff --git a/include/configs/tqma6.h b/include/configs/tqma6.h index 115f45a..df7395d 100644 --- a/include/configs/tqma6.h +++ b/include/configs/tqma6.h @@ -61,6 +61,33 @@ #define CONFIG_SF_DEFAULT_SPEED 50000000 #define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
+/* I2C Configs */ +#define CONFIG_CMD_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_I2C_MULTI_BUS +/* #define CONFIG_I2C_MXC */ +#define CONFIG_SYS_I2C_SPEED 100000 + +/* I2C SYSMON (LM75) */ +#define CONFIG_DTT_LM75 +#if defined(CONFIG_MBA6) +#define CONFIG_DTT_SENSORS { 0, 1 } +#else +#define CONFIG_DTT_SENSORS { 0 } +#endif +#define CONFIG_DTT_MAX_TEMP 70 +#define CONFIG_DTT_MIN_TEMP -30 +#define CONFIG_DTT_HYSTERESIS 3 +#define CONFIG_CMD_DTT + +/* I2C EEPROM (M24C64) */ +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 +#define CONFIG_SYS_I2C_EEPROM_PAGE_WRITE_BITS 5 /* 32 Bytes */ +#define CONFIG_SYS_I2C_EEPROM_PAGE_WRITE_DELAY_MS 20 +#define CONFIG_CMD_EEPROM + /* MMC Configs */ #define CONFIG_FSL_ESDHC #define CONFIG_FSL_USDHC
From: Markus Niebel Markus.Niebel@tq-group.com
Support for the PMIC on the TQMa6 modules is added.
Signed-off-by: Markus Niebel Markus.Niebel@tq-group.com --- - changes for v2: - add missing int power_init_board(void) to tqma6.c board/tqc/tqma6/tqma6.c | 18 ++++++++++++++++++ include/configs/tqma6.h | 5 +++++ 2 files changed, 23 insertions(+)
diff --git a/board/tqc/tqma6/tqma6.c b/board/tqc/tqma6/tqma6.c index 556a70d..ba8ff07 100644 --- a/board/tqc/tqma6/tqma6.c +++ b/board/tqc/tqma6/tqma6.c @@ -22,6 +22,8 @@ #include <libfdt.h> #include <i2c.h> #include <mmc.h> +#include <power/pfuze100_pmic.h> +#include <power/pmic.h>
#include "tqma6_bb.h"
@@ -169,6 +171,22 @@ static void tqma6_setup_i2c(void) setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &tqma6_i2c3_pads); }
+/* setup board specific PMIC */ +int power_init_board(void) +{ + struct pmic *p; + u32 reg; + + /* configure PFUZE100 PMIC */ + power_pfuze100_init(2); + p = pmic_get("PFUZE100_PMIC"); + if (p && !pmic_probe(p)) { + pmic_reg_read(p, PFUZE100_DEVICEID, ®); + printf("PMIC: PFUZE100 ID=0x%02x\n", reg); + } + return 0; +} + int board_early_init_f(void) { return tqma6_bb_board_early_init_f(); diff --git a/include/configs/tqma6.h b/include/configs/tqma6.h index df7395d..b33a9fb 100644 --- a/include/configs/tqma6.h +++ b/include/configs/tqma6.h @@ -88,6 +88,11 @@ #define CONFIG_SYS_I2C_EEPROM_PAGE_WRITE_DELAY_MS 20 #define CONFIG_CMD_EEPROM
+#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_PFUZE100 +#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 + /* MMC Configs */ #define CONFIG_FSL_ESDHC #define CONFIG_FSL_USDHC
Hi Markus,
On 16/06/2014 18:51, Markus Niebel wrote:
From: Markus Niebel Markus.Niebel@tq-group.com
This series add support for the TQMa6 boards from TQ Systems. The first Patch adds basic support for the modiules and the starterkit baseboard while the other patches add additional features
Markus Niebel (7): Add TQ Systems TQMa6 board support TQMa6: mba6: add RGMII enet TQMa6: add SPI support TQMa6: add SPI NOR boot support TQMa6: MBa6: add usb support TQMa6: add I2C support TQMa6: add pmic support
board/tqc/tqma6/Makefile | 9 + board/tqc/tqma6/README | 35 ++++ board/tqc/tqma6/clocks.cfg | 24 +++ board/tqc/tqma6/tqma6.c | 258 +++++++++++++++++++++++ board/tqc/tqma6/tqma6_bb.h | 30 +++ board/tqc/tqma6/tqma6_mba6.c | 358 +++++++++++++++++++++++++++++++ board/tqc/tqma6/tqma6q.cfg | 125 +++++++++++ board/tqc/tqma6/tqma6s.cfg | 125 +++++++++++ boards.cfg | 4 + include/configs/tqma6.h | 477 ++++++++++++++++++++++++++++++++++++++++++
I understand that your patchset follow your internal development. However, it is very uncommon that patches introducing new files are followed by patches changing the same files again.
I think you should squash your patches. This makes easy to review them.
Do you take a look at the last patches to have a single image running on different variations of i.MX6 ? Dual and Quad are supported. Some work for the Solo is required.
Is it not an attractive alternative for you ? Instead of having several entries in boards.cfg for each variation of your board, you could have maybe only one or a couple.
Best regards, Stefano Babic
Am 17.06.2014 17:55, wrote Stefano Babic:
Hi Markus,
On 16/06/2014 18:51, Markus Niebel wrote:
From: Markus Niebel Markus.Niebel@tq-group.com
This series add support for the TQMa6 boards from TQ Systems. The first Patch adds basic support for the modiules and the starterkit baseboard while the other patches add additional features
Markus Niebel (7): Add TQ Systems TQMa6 board support TQMa6: mba6: add RGMII enet TQMa6: add SPI support TQMa6: add SPI NOR boot support TQMa6: MBa6: add usb support TQMa6: add I2C support TQMa6: add pmic support
board/tqc/tqma6/Makefile | 9 + board/tqc/tqma6/README | 35 ++++ board/tqc/tqma6/clocks.cfg | 24 +++ board/tqc/tqma6/tqma6.c | 258 +++++++++++++++++++++++ board/tqc/tqma6/tqma6_bb.h | 30 +++ board/tqc/tqma6/tqma6_mba6.c | 358 +++++++++++++++++++++++++++++++ board/tqc/tqma6/tqma6q.cfg | 125 +++++++++++ board/tqc/tqma6/tqma6s.cfg | 125 +++++++++++ boards.cfg | 4 + include/configs/tqma6.h | 477 ++++++++++++++++++++++++++++++++++++++++++
I understand that your patchset follow your internal development. However, it is very uncommon that patches introducing new files are followed by patches changing the same files again.
I think you should squash your patches. This makes easy to review them.
I thought to have at first a simple and restricted config / board support would be easier to read, but no problem - will squash it.
Do you take a look at the last patches to have a single image running on different variations of i.MX6 ? Dual and Quad are supported. Some work for the Solo is required.
Is it not an attractive alternative for you ? Instead of having several entries in boards.cfg for each variation of your board, you could have maybe only one or a couple.
Sure it is - main difference will be boot devices. The env on different boot media in one image is AFAIK not possible - so at the moment four configs are needed: SP vs MMC and i.MX6Q/D vs i.MX6S (But this is slightly OT)
Best regards, Stefano Babic
Best regards, Markus Niebel
Hi Markus,
On 17/06/2014 19:40, Markus Niebel wrote:
Is it not an attractive alternative for you ? Instead of having several entries in boards.cfg for each variation of your board, you could have maybe only one or a couple.
Sure it is - main difference will be boot devices.
Right - I am expecting then an entry in boards.cfg for each media, that is able to run on all SOCs.
The env on different boot media in one image is AFAIK not possible - so at the moment four configs are needed: SP vs MMC and i.MX6Q/D vs i.MX6S (But this is slightly OT)
Well, SP vs MMC is right. But having an entry for all SOCs without having to select one of it at compile time, it is really a plus ;-)
Best regards, Stefano Babic
Hello Stefano,
Am 17.06.2014 19:58, schrieb Stefano Babic:
Hi Markus,
On 17/06/2014 19:40, Markus Niebel wrote:
Is it not an attractive alternative for you ? Instead of having several entries in boards.cfg for each variation of your board, you could have maybe only one or a couple.
Sure it is - main difference will be boot devices.
Right - I am expecting then an entry in boards.cfg for each media, that is able to run on all SOCs.
Do you mean, accepting the board needs the switch to SPL / single image support? Or will the current solution - one entry for TQMa6 with MX6Q/D and one for TQMa6 with i.MX6S - be accepted?
The env on different boot media in one image is AFAIK not possible - so at the moment four configs are needed: SP vs MMC and i.MX6Q/D vs i.MX6S (But this is slightly OT)
Well, SP vs MMC is right. But having an entry for all SOCs without having to select one of it at compile time, it is really a plus ;-)
Best regards, Stefano Babic
Best Regards
Markus
Hi Markus,
On 23/06/2014 11:52, Markus Niebel wrote:
Hello Stefano,
Am 17.06.2014 19:58, schrieb Stefano Babic:
Hi Markus,
On 17/06/2014 19:40, Markus Niebel wrote:
Is it not an attractive alternative for you ? Instead of having several entries in boards.cfg for each variation of your board, you could have maybe only one or a couple.
Sure it is - main difference will be boot devices.
Right - I am expecting then an entry in boards.cfg for each media, that is able to run on all SOCs.
Do you mean, accepting the board needs the switch to SPL / single image support?
No, there is no block about it. My suggestion is to evaluate the advantages of such solution.
Or will the current solution - one entry for TQMa6 with MX6Q/D and one for TQMa6 with i.MX6S - be accepted?
As I said, no blocking point. It can still be accepted.
Best regards, Stefano Babic
participants (3)
-
Markus Niebel -
Markus Niebel -
Stefano Babic