Re: [U-Boot] Falcon mode boot support

On Wed, Dec 17, 2014 at 04:27:37PM -0000, Andy Pont wrote:
Hi Tom,
Following the experiment that yielded the following results:
U-Boot> time sf read ${loadaddr} 0x200000 ${loadsize}
I get the following back:
SF: 2541352 bytes @ 0x200000 Read: OK time: 2.447 seconds
I have done some reading and poking around and have added the OMAP3_MCSPI_CHCONF_TURBO flag to the SPI channel enablement in the omap3_spi_read() function within omap3_spi.c and now the same command takes 1.279 seconds to execute.
I have also added a couple of printf() statements around the call to read the flash device that loads the kernel image in spi_load_image_os() and the timestamps on the output to the serial console consistently show that it is taking around 3.5 seconds to load the same kernel image.
I haven't fully looked into what is going on as I haven't yet found the full call path from spi_flash_read() in spi_flash.h to when it eventually results in the call to omap3_spi_read() and so it may be doing more and I'm not actually comparing apples with apples.
Could you (or maybe Jagannadha as SPI custodian) point me in the right direction?
I suspect that this might be related to the general problem on these part families where SPL isn't as fast as we expect it to be, perhaps cache related.

Hi Tom,
I suspect that this might be related to the general problem on these part families where SPL isn't as fast as we expect it to be, perhaps cache related.
I did a bit of digging around following this line of thought and found an old discussion on the mailing list (http://lists.denx.de/pipermail/u-boot/2013-June/156949.html) regarding someone who had a very similar problem with SPL/Falcon and NAND flash.
I have emailed Bas van den Berg to see if he is willing to share his final implementation as adding the code that adds the SRAM to the MMU and enables the caches to the end of am33xx_spl_board_init() hangs within the enable_caches() function.
Unfortunately this getting well out of my comfort zone with the ARM cores and so I'm not sure where to go next and how to debug it further.
Regards,
Andy.
participants (2)
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Andy Pont
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Tom Rini