The MPIC initialization code for Freescale e500 CPUs was not using I/O accessors, and it was not issuing a read-back to the MPIC after setting mixed mode. This may be the cause of a spurious interrupt on some systems.

Signed-off-by: Timur Tabi timur@freescale.com --- cpu/mpc85xx/interrupts.c | 12 +++++++----- 1 files changed, 7 insertions(+), 5 deletions(-)

diff --git a/cpu/mpc85xx/interrupts.c b/cpu/mpc85xx/interrupts.c index 4ef8395..409367d 100644 --- a/cpu/mpc85xx/interrupts.c +++ b/cpu/mpc85xx/interrupts.c @@ -31,15 +31,17 @@ #include <watchdog.h> #include <command.h> #include <asm/processor.h> +#include <asm/io.h>

-int interrupt_init_cpu(unsigned long *decrementer_count) +int interrupt_init_cpu(unsigned int *decrementer_count) { - volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR); + ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC85xx_PIC_ADDR;

- pic->gcr = MPC85xx_PICGCR_RST; - while (pic->gcr & MPC85xx_PICGCR_RST) + out_be32(&pic->gcr, MPC85xx_PICGCR_RST); + while (in_be32(&pic->gcr) & MPC85xx_PICGCR_RST) ; - pic->gcr = MPC85xx_PICGCR_M; + out_be32(&pic->gcr, MPC85xx_PICGCR_M); + in_be32(&pic->gcr);

*decrementer_count = get_tbclk() / CONFIG_SYS_HZ;