[U-Boot] [PATCH V2 0/9] ARM: OMAP3-DRA7: CP15 erratum workarounds and improvements
Hi,
uggh.. realized that u-boot mailing list does not like too many recipients.. So, just tom and list this time.. Sorry for the spam
V1: http://comments.gmane.org/gmane.comp.boot-loaders.u-boot/212174
V2 of this series is a culmination of a) bunch of refactoring to ensure common code in generic logic - cpuid mostly b) split the arm generic patch (patch #4 out.. to allow independent review) c) Saw a chance to incorporate OMAP3 into the same framework, and in fact can exactly allow exynos also do the job: https://patchwork.ozlabs.org/patch/440852/A https://patchwork.ozlabs.org/patch/442646/ https://patchwork.ozlabs.org/patch/442297/ (obviously the code has changed since the original omap3 implementation)
Carrying on the blurb as posted previously :)
Triggered by a user report, it was seen that recommended errata workaround and performance trade-offs as recommended by TI architects for ARM configuration was not being followed in OMAP5+ ARM A15 platforms in u-boot configuration. Note OMAP5, DRA7 all share the same cortex A15 revision (ID=0x412fc0f2) and the workarounds and improvement configurations apply equally.
Certain errata workaround done in this series obviously have the controversy potential considering that each of the SoCs implement workaround based on secure monitor calls, but both the service requested and the parameters of secure monitor calls can be widely variant. Examples: OMAP family of processors have quite the family of SMC calls: https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/arch/ar... meanwhile Exynos has a much simpler invocation: https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/arch/ar...
To maintain some resemblance of symmetry the following series introduces a arch/machine dependent errata macro which must be enabled prior to any of such workarounds can be implemented.
I am open to better ways of doing this which might benefit others in ARM community with similar needs. Lets discuss.
These patches are based on: v2015.04-rc1 but also apply on latest master.
Note:(OMAP3 is just build tested.. as I stated previously) ./MAKEALL -s omap3 v2015.04-rc1: http://pastebin.ubuntu.com/10397352/ v2015.04-rc1+ this series: http://pastebin.ubuntu.com/10397267/ (same sets of failures of build - no regressions introduced that I could see).
Angela Stegmaier (1): configs: ti_omap5_common: Enable workaround for ARM errata 798870
Nishanth Menon (7): ARM: OMAP: Change set_pl310_ctrl_reg to be generic ARM: OMAP3: Rename omap3.h to omap.h to be generic as all SoCs ARM: OMAP3: Get rid of omap3_gp_romcode_call and replace with omap_smc1 ARM: Provide a mechanism to invoke SoC specific errata WA for CP15 ARM: OMAP3: Introduce OMAP3 Cortex-A8 revision specific errata configs: ti_omap3_common: Enable workaround for ARM errata 454179, 430973, 621766 ARM: OMAP5 / DRA7: Setup L2 Aux Control Register with recommended configuration
Praveen Rao (1): ARM: DRA7 / OMAP5: Add workaround for ARM errata 798870
README | 9 ++++ arch/arm/cpu/armv7/omap-common/Makefile | 2 +- arch/arm/cpu/armv7/omap-common/lowlevel_init.S | 15 ++++-- arch/arm/cpu/armv7/omap3/board.c | 24 ++-------- arch/arm/cpu/armv7/omap3/lowlevel_init.S | 48 +++++++++++++++----- arch/arm/cpu/armv7/omap4/hwinit.c | 4 +- arch/arm/cpu/armv7/omap5/Makefile | 1 + arch/arm/cpu/armv7/omap5/hwinit.c | 16 +++++++ arch/arm/cpu/armv7/omap5/lowlevel_init.S | 46 +++++++++++++++++++ arch/arm/cpu/armv7/start.S | 14 ++++++ .../arm/include/asm/arch-omap3/{omap3.h => omap.h} | 0 arch/arm/include/asm/arch-omap3/sys_proto.h | 3 +- arch/arm/include/asm/arch-omap4/sys_proto.h | 5 +- arch/arm/include/asm/arch-omap5/sys_proto.h | 4 ++ include/configs/am3517_crane.h | 2 +- include/configs/am3517_evm.h | 2 +- include/configs/cm_t35.h | 2 +- include/configs/cm_t3517.h | 2 +- include/configs/dig297.h | 2 +- include/configs/mcx.h | 2 +- include/configs/nokia_rx51.h | 2 +- include/configs/omap3_evm.h | 2 +- include/configs/omap3_evm_quick_mmc.h | 2 +- include/configs/omap3_evm_quick_nand.h | 2 +- include/configs/omap3_logic.h | 2 +- include/configs/omap3_mvblx.h | 2 +- include/configs/omap3_pandora.h | 2 +- include/configs/omap3_sdp3430.h | 2 +- include/configs/omap3_zoom1.h | 2 +- include/configs/tam3517-common.h | 2 +- include/configs/tao3530.h | 2 +- include/configs/ti_omap3_common.h | 8 +++- include/configs/ti_omap5_common.h | 4 ++ include/configs/tricorder.h | 2 +- 34 files changed, 178 insertions(+), 61 deletions(-) create mode 100644 arch/arm/cpu/armv7/omap5/lowlevel_init.S rename arch/arm/include/asm/arch-omap3/{omap3.h => omap.h} (100%)
Regards, Nishanth Menon
set_pl310_ctrl_reg does use the Secure Monitor Call (SMC) to setup PL310 control register, however, that is something that is generic enough to be used for OMAP5 generation of processors as well. The only difference being the service being invoked for the function.
So, convert the service to a macro and use a generic name (same as that used in Linux for some consistency). While at that, also add a data barrier which is necessary as per recommendation.
Signed-off-by: Nishanth Menon nm@ti.com --- arch/arm/cpu/armv7/omap-common/lowlevel_init.S | 13 ++++++++----- arch/arm/cpu/armv7/omap4/hwinit.c | 4 ++-- arch/arm/include/asm/arch-omap4/sys_proto.h | 5 ++++- 3 files changed, 14 insertions(+), 8 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S index 86c0e4217478..9b24369e4dc1 100644 --- a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S +++ b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S @@ -22,11 +22,14 @@ ENTRY(save_boot_params) bx lr ENDPROC(save_boot_params)
-ENTRY(set_pl310_ctrl_reg) - PUSH {r4-r11, lr} @ save registers - ROM code may pollute +ENTRY(omap_smc1) + PUSH {r4-r12, lr} @ save registers - ROM code may pollute @ our registers - LDR r12, =0x102 @ Set PL310 control register - value in R0 + MOV r12, r0 @ Service + MOV r0, r1 @ Argument + DSB + DMB .word 0xe1600070 @ SMC #0 - hand assembled because -march=armv5 @ call ROM Code API to set control register - POP {r4-r11, pc} -ENDPROC(set_pl310_ctrl_reg) + POP {r4-r12, pc} +ENDPROC(omap_smc1) diff --git a/arch/arm/cpu/armv7/omap4/hwinit.c b/arch/arm/cpu/armv7/omap4/hwinit.c index db16548fac49..9792761d40a0 100644 --- a/arch/arm/cpu/armv7/omap4/hwinit.c +++ b/arch/arm/cpu/armv7/omap4/hwinit.c @@ -159,11 +159,11 @@ void init_omap_revision(void) #ifndef CONFIG_SYS_L2CACHE_OFF void v7_outer_cache_enable(void) { - set_pl310_ctrl_reg(1); + omap_smc1(OMAP4_SERVICE_PL310_CONTROL_REG_SET, 1); }
void v7_outer_cache_disable(void) { - set_pl310_ctrl_reg(0); + omap_smc1(OMAP4_SERVICE_PL310_CONTROL_REG_SET, 0); } #endif /* !CONFIG_SYS_L2CACHE_OFF */ diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h index e19975efaf50..f425e3af54f5 100644 --- a/arch/arm/include/asm/arch-omap4/sys_proto.h +++ b/arch/arm/include/asm/arch-omap4/sys_proto.h @@ -37,7 +37,7 @@ void do_set_mux(u32 base, struct pad_conf_entry const *array, int size); void set_muxconf_regs_essential(void); u32 wait_on_value(u32, u32, void *, u32); void sdelay(unsigned long); -void set_pl310_ctrl_reg(u32 val); +void omap_smc1(u32 service, u32 val); void setup_clocks_for_console(void); void prcm_init(void); void bypass_dpll(u32 const base); @@ -57,4 +57,7 @@ int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data); u32 warm_reset(void); void force_emif_self_refresh(void); void setup_warmreset_time(void); + +#define OMAP4_SERVICE_PL310_CONTROL_REG_SET 0x102 + #endif
This is in preperation of using generic cross OMAP code.
Signed-off-by: Nishanth Menon nm@ti.com --- .../arm/include/asm/arch-omap3/{omap3.h => omap.h} | 0 include/configs/am3517_crane.h | 2 +- include/configs/am3517_evm.h | 2 +- include/configs/cm_t35.h | 2 +- include/configs/cm_t3517.h | 2 +- include/configs/dig297.h | 2 +- include/configs/mcx.h | 2 +- include/configs/nokia_rx51.h | 2 +- include/configs/omap3_evm.h | 2 +- include/configs/omap3_evm_quick_mmc.h | 2 +- include/configs/omap3_evm_quick_nand.h | 2 +- include/configs/omap3_logic.h | 2 +- include/configs/omap3_mvblx.h | 2 +- include/configs/omap3_pandora.h | 2 +- include/configs/omap3_sdp3430.h | 2 +- include/configs/omap3_zoom1.h | 2 +- include/configs/tam3517-common.h | 2 +- include/configs/tao3530.h | 2 +- include/configs/ti_omap3_common.h | 2 +- include/configs/tricorder.h | 2 +- 20 files changed, 19 insertions(+), 19 deletions(-) rename arch/arm/include/asm/arch-omap3/{omap3.h => omap.h} (100%)
diff --git a/arch/arm/include/asm/arch-omap3/omap3.h b/arch/arm/include/asm/arch-omap3/omap.h similarity index 100% rename from arch/arm/include/asm/arch-omap3/omap3.h rename to arch/arm/include/asm/arch-omap3/omap.h diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h index 09ee10c0590b..a4128773ddb2 100644 --- a/include/configs/am3517_crane.h +++ b/include/configs/am3517_crane.h @@ -23,7 +23,7 @@ #define CONFIG_EMIF4 /* The chip has EMIF4 controller */
#include <asm/arch/cpu.h> /* get chip and board defs */ -#include <asm/arch/omap3.h> +#include <asm/arch/omap.h>
/* * Display CPU and Board information diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h index 190ef0e71bfb..94398c625eb0 100644 --- a/include/configs/am3517_evm.h +++ b/include/configs/am3517_evm.h @@ -23,7 +23,7 @@ #define CONFIG_EMIF4 /* The chip has EMIF4 controller */
#include <asm/arch/cpu.h> /* get chip and board defs */ -#include <asm/arch/omap3.h> +#include <asm/arch/omap.h>
/* * Display CPU and Board information diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h index 9767512a5cf0..56a5506f5c78 100644 --- a/include/configs/cm_t35.h +++ b/include/configs/cm_t35.h @@ -30,7 +30,7 @@ #define CONFIG_SDRC /* The chip has SDRC controller */
#include <asm/arch/cpu.h> /* get chip and board defs */ -#include <asm/arch/omap3.h> +#include <asm/arch/omap.h>
/* * Display CPU and Board information diff --git a/include/configs/cm_t3517.h b/include/configs/cm_t3517.h index 918032bd753a..ee1b7a0cb5a7 100644 --- a/include/configs/cm_t3517.h +++ b/include/configs/cm_t3517.h @@ -30,7 +30,7 @@ #define CONFIG_EMIF4 /* The chip has EMIF4 controller */
#include <asm/arch/cpu.h> /* get chip and board defs */ -#include <asm/arch/omap3.h> +#include <asm/arch/omap.h>
/* * Display CPU and Board information diff --git a/include/configs/dig297.h b/include/configs/dig297.h index c8739ed29490..8791199fc61d 100644 --- a/include/configs/dig297.h +++ b/include/configs/dig297.h @@ -36,7 +36,7 @@ #define CONFIG_SDRC /* The chip has SDRC controller */
#include <asm/arch/cpu.h> /* get chip and board defs */ -#include <asm/arch/omap3.h> +#include <asm/arch/omap.h>
/* * Display CPU and Board information diff --git a/include/configs/mcx.h b/include/configs/mcx.h index 26eb2203540f..2cf66c40d6fe 100644 --- a/include/configs/mcx.h +++ b/include/configs/mcx.h @@ -26,7 +26,7 @@ #define CONFIG_EMIF4 /* The chip has EMIF4 controller */
#include <asm/arch/cpu.h> /* get chip and board defs */ -#include <asm/arch/omap3.h> +#include <asm/arch/omap.h>
#define CONFIG_OF_LIBFDT #define CONFIG_FIT diff --git a/include/configs/nokia_rx51.h b/include/configs/nokia_rx51.h index 46fc91e5e197..442e16ae686b 100644 --- a/include/configs/nokia_rx51.h +++ b/include/configs/nokia_rx51.h @@ -42,7 +42,7 @@ #define CONFIG_SDRC /* The chip has SDRC controller */
#include <asm/arch/cpu.h> /* get chip and board defs */ -#include <asm/arch/omap3.h> +#include <asm/arch/omap.h> #include <asm/arch/mem.h> #include <linux/stringify.h>
diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h index 8bdc08f5864c..4e587e10ffd3 100644 --- a/include/configs/omap3_evm.h +++ b/include/configs/omap3_evm.h @@ -18,7 +18,7 @@ #define __OMAP3EVM_CONFIG_H
#include <asm/arch/cpu.h> -#include <asm/arch/omap3.h> +#include <asm/arch/omap.h>
/* ---------------------------------------------------------------------------- * Supported U-boot commands diff --git a/include/configs/omap3_evm_quick_mmc.h b/include/configs/omap3_evm_quick_mmc.h index 1185f425501f..a7acc1becbeb 100644 --- a/include/configs/omap3_evm_quick_mmc.h +++ b/include/configs/omap3_evm_quick_mmc.h @@ -13,7 +13,7 @@ #define __OMAP3_EVM_QUICK_MMC_H
#include <asm/arch/cpu.h> -#include <asm/arch/omap3.h> +#include <asm/arch/omap.h>
/* ---------------------------------------------------------------------------- * Supported U-boot commands diff --git a/include/configs/omap3_evm_quick_nand.h b/include/configs/omap3_evm_quick_nand.h index 4427e88b7e4b..c6cad9388961 100644 --- a/include/configs/omap3_evm_quick_nand.h +++ b/include/configs/omap3_evm_quick_nand.h @@ -13,7 +13,7 @@ #define __OMAP3_EVM_QUICK_NAND_H
#include <asm/arch/cpu.h> -#include <asm/arch/omap3.h> +#include <asm/arch/omap.h>
/* ---------------------------------------------------------------------------- * Supported U-boot commands diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h index aeb385f5ff6b..fcef46735835 100644 --- a/include/configs/omap3_logic.h +++ b/include/configs/omap3_logic.h @@ -24,7 +24,7 @@ #define CONFIG_SDRC /* The chip has SDRC controller */
#include <asm/arch/cpu.h> /* get chip and board defs */ -#include <asm/arch/omap3.h> +#include <asm/arch/omap.h>
/* * Display CPU and Board information diff --git a/include/configs/omap3_mvblx.h b/include/configs/omap3_mvblx.h index bf1d34dedb4d..20ec3ad15439 100644 --- a/include/configs/omap3_mvblx.h +++ b/include/configs/omap3_mvblx.h @@ -27,7 +27,7 @@ #define CONFIG_SDRC /* The chip has SDRC controller */
#include <asm/arch/cpu.h> /* get chip and board defs */ -#include <asm/arch/omap3.h> +#include <asm/arch/omap.h>
/* * Display CPU and Board information diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h index 45feeb577320..b92d67abccf9 100644 --- a/include/configs/omap3_pandora.h +++ b/include/configs/omap3_pandora.h @@ -21,7 +21,7 @@ #define CONFIG_SDRC /* The chip has SDRC controller */
#include <asm/arch/cpu.h> /* get chip and board defs */ -#include <asm/arch/omap3.h> +#include <asm/arch/omap.h>
/* * Display CPU and Board information diff --git a/include/configs/omap3_sdp3430.h b/include/configs/omap3_sdp3430.h index ac307eb45629..bf5c7a8faf77 100644 --- a/include/configs/omap3_sdp3430.h +++ b/include/configs/omap3_sdp3430.h @@ -27,7 +27,7 @@ #define CONFIG_SDRC /* The chip has SDRC controller */
#include <asm/arch/cpu.h> /* get chip and board defs */ -#include <asm/arch/omap3.h> +#include <asm/arch/omap.h>
/* * NOTE: these #defines presume standard SDP jumper settings. diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h index c5d742c2bd80..611cd5e1a350 100644 --- a/include/configs/omap3_zoom1.h +++ b/include/configs/omap3_zoom1.h @@ -22,7 +22,7 @@ #define CONFIG_NAND #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ #include <asm/arch/cpu.h> /* get chip and board defs */ -#include <asm/arch/omap3.h> +#include <asm/arch/omap.h> #include <configs/ti_omap3_common.h>
/* Remove SPL boot option - we do not support that on LDP yet */ diff --git a/include/configs/tam3517-common.h b/include/configs/tam3517-common.h index 9fbe68a8a2f2..bff9687b3c9c 100644 --- a/include/configs/tam3517-common.h +++ b/include/configs/tam3517-common.h @@ -25,7 +25,7 @@ #define CONFIG_EMIF4 /* The chip has EMIF4 controller */
#include <asm/arch/cpu.h> /* get chip and board defs */ -#include <asm/arch/omap3.h> +#include <asm/arch/omap.h>
/* * Display CPU and Board information diff --git a/include/configs/tao3530.h b/include/configs/tao3530.h index 7d2c0d2fa75c..4dfd5cb9fbb7 100644 --- a/include/configs/tao3530.h +++ b/include/configs/tao3530.h @@ -27,7 +27,7 @@ #define CONFIG_SDRC /* Has an SDRC controller */
#include <asm/arch/cpu.h> /* get chip and board defs */ -#include <asm/arch/omap3.h> +#include <asm/arch/omap.h>
/* * Display CPU and Board information diff --git a/include/configs/ti_omap3_common.h b/include/configs/ti_omap3_common.h index 3c634ee680d0..f909f6b94a18 100644 --- a/include/configs/ti_omap3_common.h +++ b/include/configs/ti_omap3_common.h @@ -16,7 +16,7 @@
#include <asm/arch/cpu.h> -#include <asm/arch/omap3.h> +#include <asm/arch/omap.h>
#ifndef CONFIG_SPL_BUILD # define CONFIG_DM diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h index 36621a553cdf..f27cd1b9b061 100644 --- a/include/configs/tricorder.h +++ b/include/configs/tricorder.h @@ -32,7 +32,7 @@ #define CONFIG_SDRC /* The chip has SDRC controller */
#include <asm/arch/cpu.h> /* get chip and board defs */ -#include <asm/arch/omap3.h> +#include <asm/arch/omap.h>
#define CONFIG_SYS_GENERIC_BOARD
Le mardi 24 février 2015 à 16:57 -0600, Nishanth Menon a écrit :
This is in preperation of using generic cross OMAP code.
I found it a bit confusing at first, since as far as I could see, this series does not introduce any cross-omap header (omap_smc1's prototype is being defined and duplicated in each arch-omap[345]/sys_proto.h, so there could be a need for one).
However, since this is the naming scheme using in arch-omap[45], I'm fine with the renaming just for the sake of consistency.
Do I get to add a Reviewed-By field?
Signed-off-by: Nishanth Menon nm@ti.com
.../arm/include/asm/arch-omap3/{omap3.h => omap.h} | 0 include/configs/am3517_crane.h | 2 +- include/configs/am3517_evm.h | 2 +- include/configs/cm_t35.h | 2 +- include/configs/cm_t3517.h | 2 +- include/configs/dig297.h | 2 +- include/configs/mcx.h | 2 +- include/configs/nokia_rx51.h | 2 +- include/configs/omap3_evm.h | 2 +- include/configs/omap3_evm_quick_mmc.h | 2 +- include/configs/omap3_evm_quick_nand.h | 2 +- include/configs/omap3_logic.h | 2 +- include/configs/omap3_mvblx.h | 2 +- include/configs/omap3_pandora.h | 2 +- include/configs/omap3_sdp3430.h | 2 +- include/configs/omap3_zoom1.h | 2 +- include/configs/tam3517-common.h | 2 +- include/configs/tao3530.h | 2 +- include/configs/ti_omap3_common.h | 2 +- include/configs/tricorder.h | 2 +- 20 files changed, 19 insertions(+), 19 deletions(-) rename arch/arm/include/asm/arch-omap3/{omap3.h => omap.h} (100%)
diff --git a/arch/arm/include/asm/arch-omap3/omap3.h b/arch/arm/include/asm/arch-omap3/omap.h similarity index 100% rename from arch/arm/include/asm/arch-omap3/omap3.h rename to arch/arm/include/asm/arch-omap3/omap.h diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h index 09ee10c0590b..a4128773ddb2 100644 --- a/include/configs/am3517_crane.h +++ b/include/configs/am3517_crane.h @@ -23,7 +23,7 @@ #define CONFIG_EMIF4 /* The chip has EMIF4 controller */
#include <asm/arch/cpu.h> /* get chip and board defs */ -#include <asm/arch/omap3.h> +#include <asm/arch/omap.h>
/*
- Display CPU and Board information
diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h index 190ef0e71bfb..94398c625eb0 100644 --- a/include/configs/am3517_evm.h +++ b/include/configs/am3517_evm.h @@ -23,7 +23,7 @@ #define CONFIG_EMIF4 /* The chip has EMIF4 controller */
#include <asm/arch/cpu.h> /* get chip and board defs */ -#include <asm/arch/omap3.h> +#include <asm/arch/omap.h>
/*
- Display CPU and Board information
diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h index 9767512a5cf0..56a5506f5c78 100644 --- a/include/configs/cm_t35.h +++ b/include/configs/cm_t35.h @@ -30,7 +30,7 @@ #define CONFIG_SDRC /* The chip has SDRC controller */
#include <asm/arch/cpu.h> /* get chip and board defs */ -#include <asm/arch/omap3.h> +#include <asm/arch/omap.h>
/*
- Display CPU and Board information
diff --git a/include/configs/cm_t3517.h b/include/configs/cm_t3517.h index 918032bd753a..ee1b7a0cb5a7 100644 --- a/include/configs/cm_t3517.h +++ b/include/configs/cm_t3517.h @@ -30,7 +30,7 @@ #define CONFIG_EMIF4 /* The chip has EMIF4 controller */
#include <asm/arch/cpu.h> /* get chip and board defs */ -#include <asm/arch/omap3.h> +#include <asm/arch/omap.h>
/*
- Display CPU and Board information
diff --git a/include/configs/dig297.h b/include/configs/dig297.h index c8739ed29490..8791199fc61d 100644 --- a/include/configs/dig297.h +++ b/include/configs/dig297.h @@ -36,7 +36,7 @@ #define CONFIG_SDRC /* The chip has SDRC controller */
#include <asm/arch/cpu.h> /* get chip and board defs */ -#include <asm/arch/omap3.h> +#include <asm/arch/omap.h>
/*
- Display CPU and Board information
diff --git a/include/configs/mcx.h b/include/configs/mcx.h index 26eb2203540f..2cf66c40d6fe 100644 --- a/include/configs/mcx.h +++ b/include/configs/mcx.h @@ -26,7 +26,7 @@ #define CONFIG_EMIF4 /* The chip has EMIF4 controller */
#include <asm/arch/cpu.h> /* get chip and board defs */ -#include <asm/arch/omap3.h> +#include <asm/arch/omap.h>
#define CONFIG_OF_LIBFDT #define CONFIG_FIT diff --git a/include/configs/nokia_rx51.h b/include/configs/nokia_rx51.h index 46fc91e5e197..442e16ae686b 100644 --- a/include/configs/nokia_rx51.h +++ b/include/configs/nokia_rx51.h @@ -42,7 +42,7 @@ #define CONFIG_SDRC /* The chip has SDRC controller */
#include <asm/arch/cpu.h> /* get chip and board defs */ -#include <asm/arch/omap3.h> +#include <asm/arch/omap.h> #include <asm/arch/mem.h> #include <linux/stringify.h>
diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h index 8bdc08f5864c..4e587e10ffd3 100644 --- a/include/configs/omap3_evm.h +++ b/include/configs/omap3_evm.h @@ -18,7 +18,7 @@ #define __OMAP3EVM_CONFIG_H
#include <asm/arch/cpu.h> -#include <asm/arch/omap3.h> +#include <asm/arch/omap.h>
/* ----------------------------------------------------------------------------
- Supported U-boot commands
diff --git a/include/configs/omap3_evm_quick_mmc.h b/include/configs/omap3_evm_quick_mmc.h index 1185f425501f..a7acc1becbeb 100644 --- a/include/configs/omap3_evm_quick_mmc.h +++ b/include/configs/omap3_evm_quick_mmc.h @@ -13,7 +13,7 @@ #define __OMAP3_EVM_QUICK_MMC_H
#include <asm/arch/cpu.h> -#include <asm/arch/omap3.h> +#include <asm/arch/omap.h>
/* ----------------------------------------------------------------------------
- Supported U-boot commands
diff --git a/include/configs/omap3_evm_quick_nand.h b/include/configs/omap3_evm_quick_nand.h index 4427e88b7e4b..c6cad9388961 100644 --- a/include/configs/omap3_evm_quick_nand.h +++ b/include/configs/omap3_evm_quick_nand.h @@ -13,7 +13,7 @@ #define __OMAP3_EVM_QUICK_NAND_H
#include <asm/arch/cpu.h> -#include <asm/arch/omap3.h> +#include <asm/arch/omap.h>
/* ----------------------------------------------------------------------------
- Supported U-boot commands
diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h index aeb385f5ff6b..fcef46735835 100644 --- a/include/configs/omap3_logic.h +++ b/include/configs/omap3_logic.h @@ -24,7 +24,7 @@ #define CONFIG_SDRC /* The chip has SDRC controller */
#include <asm/arch/cpu.h> /* get chip and board defs */ -#include <asm/arch/omap3.h> +#include <asm/arch/omap.h>
/*
- Display CPU and Board information
diff --git a/include/configs/omap3_mvblx.h b/include/configs/omap3_mvblx.h index bf1d34dedb4d..20ec3ad15439 100644 --- a/include/configs/omap3_mvblx.h +++ b/include/configs/omap3_mvblx.h @@ -27,7 +27,7 @@ #define CONFIG_SDRC /* The chip has SDRC controller */
#include <asm/arch/cpu.h> /* get chip and board defs */ -#include <asm/arch/omap3.h> +#include <asm/arch/omap.h>
/*
- Display CPU and Board information
diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h index 45feeb577320..b92d67abccf9 100644 --- a/include/configs/omap3_pandora.h +++ b/include/configs/omap3_pandora.h @@ -21,7 +21,7 @@ #define CONFIG_SDRC /* The chip has SDRC controller */
#include <asm/arch/cpu.h> /* get chip and board defs */ -#include <asm/arch/omap3.h> +#include <asm/arch/omap.h>
/*
- Display CPU and Board information
diff --git a/include/configs/omap3_sdp3430.h b/include/configs/omap3_sdp3430.h index ac307eb45629..bf5c7a8faf77 100644 --- a/include/configs/omap3_sdp3430.h +++ b/include/configs/omap3_sdp3430.h @@ -27,7 +27,7 @@ #define CONFIG_SDRC /* The chip has SDRC controller */
#include <asm/arch/cpu.h> /* get chip and board defs */ -#include <asm/arch/omap3.h> +#include <asm/arch/omap.h>
/*
- NOTE: these #defines presume standard SDP jumper settings.
diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h index c5d742c2bd80..611cd5e1a350 100644 --- a/include/configs/omap3_zoom1.h +++ b/include/configs/omap3_zoom1.h @@ -22,7 +22,7 @@ #define CONFIG_NAND #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ #include <asm/arch/cpu.h> /* get chip and board defs */ -#include <asm/arch/omap3.h> +#include <asm/arch/omap.h> #include <configs/ti_omap3_common.h>
/* Remove SPL boot option - we do not support that on LDP yet */ diff --git a/include/configs/tam3517-common.h b/include/configs/tam3517-common.h index 9fbe68a8a2f2..bff9687b3c9c 100644 --- a/include/configs/tam3517-common.h +++ b/include/configs/tam3517-common.h @@ -25,7 +25,7 @@ #define CONFIG_EMIF4 /* The chip has EMIF4 controller */
#include <asm/arch/cpu.h> /* get chip and board defs */ -#include <asm/arch/omap3.h> +#include <asm/arch/omap.h>
/*
- Display CPU and Board information
diff --git a/include/configs/tao3530.h b/include/configs/tao3530.h index 7d2c0d2fa75c..4dfd5cb9fbb7 100644 --- a/include/configs/tao3530.h +++ b/include/configs/tao3530.h @@ -27,7 +27,7 @@ #define CONFIG_SDRC /* Has an SDRC controller */
#include <asm/arch/cpu.h> /* get chip and board defs */ -#include <asm/arch/omap3.h> +#include <asm/arch/omap.h>
/*
- Display CPU and Board information
diff --git a/include/configs/ti_omap3_common.h b/include/configs/ti_omap3_common.h index 3c634ee680d0..f909f6b94a18 100644 --- a/include/configs/ti_omap3_common.h +++ b/include/configs/ti_omap3_common.h @@ -16,7 +16,7 @@
#include <asm/arch/cpu.h> -#include <asm/arch/omap3.h> +#include <asm/arch/omap.h>
#ifndef CONFIG_SPL_BUILD # define CONFIG_DM diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h index 36621a553cdf..f27cd1b9b061 100644 --- a/include/configs/tricorder.h +++ b/include/configs/tricorder.h @@ -32,7 +32,7 @@ #define CONFIG_SDRC /* The chip has SDRC controller */
#include <asm/arch/cpu.h> /* get chip and board defs */ -#include <asm/arch/omap3.h> +#include <asm/arch/omap.h>
#define CONFIG_SYS_GENERIC_BOARD
On Wed, Feb 25, 2015 at 5:02 AM, Paul Kocialkowski contact@paulk.fr wrote:
Le mardi 24 février 2015 à 16:57 -0600, Nishanth Menon a écrit :
This is in preperation of using generic cross OMAP code.
I found it a bit confusing at first, since as far as I could see, this series does not introduce any cross-omap header (omap_smc1's prototype is being defined and duplicated in each arch-omap[345]/sys_proto.h, so there could be a need for one).
However, since this is the naming scheme using in arch-omap[45], I'm fine with the renaming just for the sake of consistency.
The consolidation path is a long way, I think.. lets do that in next stage?
Do I get to add a Reviewed-By field?
Lets get the discussions completed, then we can.. I think.
-- Regards, Nishanth Menon
omap_smc1 is now generic enough to remove duplicate omap3_gp_romcode_call logic that omap3 introduced.
As part of this change, move to using the generic lowlevel_init.S for omap3 as well.
Signed-off-by: Nishanth Menon nm@ti.com --- arch/arm/cpu/armv7/omap-common/Makefile | 2 +- arch/arm/cpu/armv7/omap-common/lowlevel_init.S | 2 ++ arch/arm/cpu/armv7/omap3/board.c | 6 ++---- arch/arm/cpu/armv7/omap3/lowlevel_init.S | 11 ----------- arch/arm/include/asm/arch-omap3/sys_proto.h | 2 +- 5 files changed, 6 insertions(+), 17 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap-common/Makefile b/arch/arm/cpu/armv7/omap-common/Makefile index 7695e16d36f5..f3725b267c99 100644 --- a/arch/arm/cpu/armv7/omap-common/Makefile +++ b/arch/arm/cpu/armv7/omap-common/Makefile @@ -28,7 +28,7 @@ endif
ifeq ($(CONFIG_OMAP34XX),) obj-y += boot-common.o -obj-y += lowlevel_init.o endif +obj-y += lowlevel_init.o
obj-y += mem-common.o diff --git a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S index 9b24369e4dc1..7d0f09496d85 100644 --- a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S +++ b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S @@ -16,11 +16,13 @@ #include <asm/arch/spl.h> #include <linux/linkage.h>
+#ifndef CONFIG_OMAP34XX ENTRY(save_boot_params) ldr r1, =OMAP_SRAM_SCRATCH_BOOT_PARAMS str r0, [r1] bx lr ENDPROC(save_boot_params) +#endif
ENTRY(omap_smc1) PUSH {r4-r12, lr} @ save registers - ROM code may pollute diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c index 90d6ae7bb5f5..51abc4b09e36 100644 --- a/arch/arm/cpu/armv7/omap3/board.c +++ b/arch/arm/cpu/armv7/omap3/board.c @@ -418,8 +418,7 @@ static void omap3_update_aux_cr_secure(u32 set_bits, u32 clear_bits) acr |= set_bits;
if (get_device_type() == GP_DEVICE) { - omap3_gp_romcode_call(OMAP3_GP_ROMCODE_API_WRITE_ACR, - acr); + omap_smc1(OMAP3_GP_ROMCODE_API_WRITE_ACR, acr); } else { struct emu_hal_params emu_romcode_params; emu_romcode_params.num_params = 1; @@ -459,8 +458,7 @@ static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits) static void omap3_invalidate_l2_cache_secure(void) { if (get_device_type() == GP_DEVICE) { - omap3_gp_romcode_call(OMAP3_GP_ROMCODE_API_L2_INVAL, - 0); + omap_smc1(OMAP3_GP_ROMCODE_API_L2_INVAL, 0); } else { struct emu_hal_params emu_romcode_params; emu_romcode_params.num_params = 1; diff --git a/arch/arm/cpu/armv7/omap3/lowlevel_init.S b/arch/arm/cpu/armv7/omap3/lowlevel_init.S index 78577b1d1c75..84591b8b5bab 100644 --- a/arch/arm/cpu/armv7/omap3/lowlevel_init.S +++ b/arch/arm/cpu/armv7/omap3/lowlevel_init.S @@ -27,17 +27,6 @@ ENTRY(save_boot_params) ENDPROC(save_boot_params) #endif
-ENTRY(omap3_gp_romcode_call) - PUSH {r4-r12, lr} @ Save all registers from ROM code! - MOV r12, r0 @ Copy the Service ID in R12 - MOV r0, r1 @ Copy parameter to R0 - mcr p15, 0, r0, c7, c10, 4 @ DSB - mcr p15, 0, r0, c7, c10, 5 @ DMB - .word 0xe1600070 @ SMC #0 to enter monitor - hand assembled - @ because we use -march=armv5 - POP {r4-r12, pc} -ENDPROC(omap3_gp_romcode_call) - /* * Funtion for making PPA HAL API calls in secure devices * Input: diff --git a/arch/arm/include/asm/arch-omap3/sys_proto.h b/arch/arm/include/asm/arch-omap3/sys_proto.h index bcf92fbe658b..c06605d533d3 100644 --- a/arch/arm/include/asm/arch-omap3/sys_proto.h +++ b/arch/arm/include/asm/arch-omap3/sys_proto.h @@ -73,6 +73,6 @@ void power_init_r(void); void dieid_num_r(void); void get_dieid(u32 *id); void do_omap3_emu_romcode_call(u32 service_id, u32 parameters); -void omap3_gp_romcode_call(u32 service_id, u32 parameter); +void omap_smc1(u32 service, u32 val); u32 warm_reset(void); #endif
Le mardi 24 février 2015 à 16:57 -0600, Nishanth Menon a écrit :
omap_smc1 is now generic enough to remove duplicate omap3_gp_romcode_call logic that omap3 introduced.
As far as I could see, this did not introduce any regression on my omap3630 device (omap_smc1 is used from omap3_invalidate_l2_cache_secure in my case). Looks good to me.
As part of this change, move to using the generic lowlevel_init.S for omap3 as well.
Signed-off-by: Nishanth Menon nm@ti.com
arch/arm/cpu/armv7/omap-common/Makefile | 2 +- arch/arm/cpu/armv7/omap-common/lowlevel_init.S | 2 ++ arch/arm/cpu/armv7/omap3/board.c | 6 ++---- arch/arm/cpu/armv7/omap3/lowlevel_init.S | 11 ----------- arch/arm/include/asm/arch-omap3/sys_proto.h | 2 +- 5 files changed, 6 insertions(+), 17 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap-common/Makefile b/arch/arm/cpu/armv7/omap-common/Makefile index 7695e16d36f5..f3725b267c99 100644 --- a/arch/arm/cpu/armv7/omap-common/Makefile +++ b/arch/arm/cpu/armv7/omap-common/Makefile @@ -28,7 +28,7 @@ endif
ifeq ($(CONFIG_OMAP34XX),) obj-y += boot-common.o -obj-y += lowlevel_init.o endif +obj-y += lowlevel_init.o
obj-y += mem-common.o diff --git a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S index 9b24369e4dc1..7d0f09496d85 100644 --- a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S +++ b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S @@ -16,11 +16,13 @@ #include <asm/arch/spl.h> #include <linux/linkage.h>
+#ifndef CONFIG_OMAP34XX ENTRY(save_boot_params) ldr r1, =OMAP_SRAM_SCRATCH_BOOT_PARAMS str r0, [r1] bx lr ENDPROC(save_boot_params) +#endif
ENTRY(omap_smc1) PUSH {r4-r12, lr} @ save registers - ROM code may pollute diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c index 90d6ae7bb5f5..51abc4b09e36 100644 --- a/arch/arm/cpu/armv7/omap3/board.c +++ b/arch/arm/cpu/armv7/omap3/board.c @@ -418,8 +418,7 @@ static void omap3_update_aux_cr_secure(u32 set_bits, u32 clear_bits) acr |= set_bits;
if (get_device_type() == GP_DEVICE) {
omap3_gp_romcode_call(OMAP3_GP_ROMCODE_API_WRITE_ACR,acr);
omap_smc1(OMAP3_GP_ROMCODE_API_WRITE_ACR, acr);@@ -459,8 +458,7 @@ static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits) static void omap3_invalidate_l2_cache_secure(void) { if (get_device_type() == GP_DEVICE) {
omap3_gp_romcode_call(OMAP3_GP_ROMCODE_API_L2_INVAL,0);
omap_smc1(OMAP3_GP_ROMCODE_API_L2_INVAL, 0);diff --git a/arch/arm/cpu/armv7/omap3/lowlevel_init.S b/arch/arm/cpu/armv7/omap3/lowlevel_init.S index 78577b1d1c75..84591b8b5bab 100644 --- a/arch/arm/cpu/armv7/omap3/lowlevel_init.S +++ b/arch/arm/cpu/armv7/omap3/lowlevel_init.S @@ -27,17 +27,6 @@ ENTRY(save_boot_params) ENDPROC(save_boot_params) #endif
-ENTRY(omap3_gp_romcode_call)
- PUSH {r4-r12, lr} @ Save all registers from ROM code!
- MOV r12, r0 @ Copy the Service ID in R12
- MOV r0, r1 @ Copy parameter to R0
- mcr p15, 0, r0, c7, c10, 4 @ DSB
- mcr p15, 0, r0, c7, c10, 5 @ DMB
- .word 0xe1600070 @ SMC #0 to enter monitor - hand assembled
@ because we use -march=armv5- POP {r4-r12, pc}
-ENDPROC(omap3_gp_romcode_call)
/*
- Funtion for making PPA HAL API calls in secure devices
- Input:
diff --git a/arch/arm/include/asm/arch-omap3/sys_proto.h b/arch/arm/include/asm/arch-omap3/sys_proto.h index bcf92fbe658b..c06605d533d3 100644 --- a/arch/arm/include/asm/arch-omap3/sys_proto.h +++ b/arch/arm/include/asm/arch-omap3/sys_proto.h @@ -73,6 +73,6 @@ void power_init_r(void); void dieid_num_r(void); void get_dieid(u32 *id); void do_omap3_emu_romcode_call(u32 service_id, u32 parameters); -void omap3_gp_romcode_call(u32 service_id, u32 parameter); +void omap_smc1(u32 service, u32 val); u32 warm_reset(void); #endif
Every SoC has slightly different manner of setting up access to L2ACLR and similar registers since the Secure Monitor handling of Secure Monitor Call(smc) is diverse. Hence an ARCH specific macro is introduced to implement SoC specific errata workaround implementations.
Signed-off-by: Nishanth Menon nm@ti.com --- README | 5 +++++ arch/arm/cpu/armv7/start.S | 14 ++++++++++++++ 2 files changed, 19 insertions(+)
diff --git a/README b/README index a28ff133ee05..2e53e0c5757d 100644 --- a/README +++ b/README @@ -621,6 +621,11 @@ The following options need to be configured: exists, unlike the similar options in the Linux kernel. Do not set these options unless they apply!
+ NOTE: The following are machine specific errata that are enabled + with CONFIG_ARM_ARCH_CP15_ERRATA define. These need to have an + SoC specific implementation of the erratum workaround to + function. + - Driver Model Driver model is a new framework for devices in U-Boot introduced in early 2014. U-Boot is being progressively diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 70048c10aee6..3b814d8f42d3 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -163,6 +163,20 @@ ENTRY(cpu_init_cp15) mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register #endif
+#ifdef CONFIG_ARM_ARCH_CP15_ERRATA + mrc p15, 0, r0, c0, c0, 0 @ r0 has Read Main ID Register (MIDR) + mov r1, r0, lsr #20 @ get variant field + and r1, r1, #0xf @ r1 has CPU variant + and r2, r0, #0xf @ r2 has CPU revision + mov r3, r1, lsl #4 @ shift variant field for combined value + orr r3, r2, r3 @ r3 has combined CPU variant + revision + /* C Prototype: + * void arch_cp15_errata_workaround(u32 midr, u32 variant, + * u32 rev, u32 comb); + */ + b arch_cp15_errata_workaround @ Do Machine specific errata WAs +#endif + mov pc, lr @ back to my caller ENDPROC(cpu_init_cp15)
From: Praveen Rao prao@ti.com
This patch adds workaround for ARM errata 798870 which says "If back-to-back speculative cache line fills (fill A and fill B) are issued from the L1 data cache of a CPU to the L2 cache, the second request (fill B) is then cancelled, and the second request would have detected a hazard against a recent write or eviction (write B) to the same cache line as fill B then the L2 logic might deadlock."
An implementation for OMAP5 and DRA7 is introduced here as well. Obviously, implementations for other SoC families such as Exynos etc will be widely different.
Signed-off-by: Praveen Rao prao@ti.com Signed-off-by: Angela Stegmaier angelabaker@ti.com Signed-off-by: Nishanth Menon nm@ti.com --- README | 1 + arch/arm/cpu/armv7/omap5/Makefile | 1 + arch/arm/cpu/armv7/omap5/lowlevel_init.S | 46 +++++++++++++++++++++++++++ arch/arm/include/asm/arch-omap5/sys_proto.h | 1 + 4 files changed, 49 insertions(+) create mode 100644 arch/arm/cpu/armv7/omap5/lowlevel_init.S
diff --git a/README b/README index 2e53e0c5757d..d76cdc68d406 100644 --- a/README +++ b/README @@ -625,6 +625,7 @@ The following options need to be configured: with CONFIG_ARM_ARCH_CP15_ERRATA define. These need to have an SoC specific implementation of the erratum workaround to function. + CONFIG_ARM_ERRATA_798870
- Driver Model Driver model is a new framework for devices in U-Boot diff --git a/arch/arm/cpu/armv7/omap5/Makefile b/arch/arm/cpu/armv7/omap5/Makefile index 64c68791f18e..b645dd4f58b7 100644 --- a/arch/arm/cpu/armv7/omap5/Makefile +++ b/arch/arm/cpu/armv7/omap5/Makefile @@ -11,3 +11,4 @@ obj-y += sdram.o obj-y += prcm-regs.o obj-y += hw_data.o obj-y += abb.o +obj-y += lowlevel_init.o diff --git a/arch/arm/cpu/armv7/omap5/lowlevel_init.S b/arch/arm/cpu/armv7/omap5/lowlevel_init.S new file mode 100644 index 000000000000..974e3a59fb08 --- /dev/null +++ b/arch/arm/cpu/armv7/omap5/lowlevel_init.S @@ -0,0 +1,46 @@ +/* + * Board specific misc setup + * + * (C) Copyright 2015 + * Texas Instruments, <www.ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <config.h> +#include <asm/arch/omap.h> +#include <asm/omap_common.h> +#include <asm/arch/spl.h> +#include <linux/linkage.h> + +#define OMAP5_SERVICE_L2ACTLR_SET 0x104 + +#ifdef CONFIG_ARM_ARCH_CP15_ERRATA + .globl arch_cp15_errata_workaround +/* + * R0 has MIDR + * R1 has CPU Variant (bits 20-23) + * R2 has CPU Revision (bits 0-3) + * R3 is compbined CPU variant << 4 + CPU revision + */ +ENTRY(arch_cp15_errata_workaround) + push {r4-r11, lr} @ save registers - ROM code may pollute + +#ifdef CONFIG_ARM_ERRATA_798870 + /* We are r2p2, but anyways for completeness.. */ + cmp r3, #0x30 @ Applies to lower than R3p0 + bge skip_errata_798870 @ skip if not affected rev + cmp r3, #0x20 @ Applies to including and above R2p0 + blt skip_errata_798870 @ skip if not affected rev + + mrc p15, 1, r1, c15, c0, 0 @ read l2 aux ctrl reg + orr r1, r1, #1 << 7 @ set bit #7 + ldr r0, =OMAP5_SERVICE_L2ACTLR_SET @ Set L2 Cache Auxiliary control register - value in R0 + b omap_smc1 + +skip_errata_798870: +#endif + pop {r4-r11, pc} +ENDPROC(arch_cp15_errata_workaround) + +#endif diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h b/arch/arm/include/asm/arch-omap5/sys_proto.h index 103830319a41..0a7a52d138df 100644 --- a/arch/arm/include/asm/arch-omap5/sys_proto.h +++ b/arch/arm/include/asm/arch-omap5/sys_proto.h @@ -56,6 +56,7 @@ void force_emif_self_refresh(void); void get_ioregs(const struct ctrl_ioregs **regs); void srcomp_enable(void); void setup_warmreset_time(void); +void omap_smc1(u32 service, u32 val);
static inline u32 div_round_up(u32 num, u32 den) {
From: Angela Stegmaier angelabaker@ti.com
Enable the workaround for ARM errata 798870 for OMAP5 and DRA7xx since they are Coretx-A15 r2.
Signed-off-by: Angela Stegmaier angelabaker@ti.com Signed-off-by: Nishanth Menon nm@ti.com --- include/configs/ti_omap5_common.h | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h index 925cb42dd38d..bce9a505cbb3 100644 --- a/include/configs/ti_omap5_common.h +++ b/include/configs/ti_omap5_common.h @@ -21,6 +21,10 @@ #define CONFIG_DISPLAY_BOARDINFO #define CONFIG_ARCH_CPU_INIT
+/* Common ARM Erratas */ +#define CONFIG_ARM_ARCH_CP15_ERRATA +#define CONFIG_ARM_ERRATA_798870 + #define CONFIG_SYS_CACHELINE_SIZE 64
/* Use General purpose timer 1 */
430973: Stale prediction on replaced inter working branch causes Cortex-A8 to execute in the wrong ARM/Thumb state Impacts: Everything lower than r2p1 Work around: Set IBE to 1
454179: Stale prediction may inhibit target address misprediction on next predicted taken branch Impacts: Everything lower than r2p1 Work around: Set IBE and disable branch size mispredict to 1
621766: Under a specific set of conditions, executing a sequence of NEON or vfp load instructions can cause processor deadlock Impacts: Everything lower than r2p1 Work around: Set L1NEON to 1
Since the OMAP3 generation of processors have a wide variety of CPU revisions, it is more logical to enforce an implementation using revision checks.
Signed-off-by: Nishanth Menon nm@ti.com --- README | 3 +++ arch/arm/cpu/armv7/omap3/board.c | 2 +- arch/arm/cpu/armv7/omap3/lowlevel_init.S | 37 +++++++++++++++++++++++++++ arch/arm/include/asm/arch-omap3/sys_proto.h | 1 + 4 files changed, 42 insertions(+), 1 deletion(-)
diff --git a/README b/README index d76cdc68d406..f309e27bbd02 100644 --- a/README +++ b/README @@ -625,6 +625,9 @@ The following options need to be configured: with CONFIG_ARM_ARCH_CP15_ERRATA define. These need to have an SoC specific implementation of the erratum workaround to function. + CONFIG_ARM_ERRATA_430973 + CONFIG_ARM_ERRATA_454179 + CONFIG_ARM_ERRATA_621766 CONFIG_ARM_ERRATA_798870
- Driver Model diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c index 51abc4b09e36..7ce30949a6c6 100644 --- a/arch/arm/cpu/armv7/omap3/board.c +++ b/arch/arm/cpu/armv7/omap3/board.c @@ -408,7 +408,7 @@ static void omap3_emu_romcode_call(u32 service_id, u32 *parameters) do_omap3_emu_romcode_call(service_id, OMAP3_PUBLIC_SRAM_SCRATCH_AREA); }
-static void omap3_update_aux_cr_secure(u32 set_bits, u32 clear_bits) +void omap3_update_aux_cr_secure(u32 set_bits, u32 clear_bits) { u32 acr;
diff --git a/arch/arm/cpu/armv7/omap3/lowlevel_init.S b/arch/arm/cpu/armv7/omap3/lowlevel_init.S index 84591b8b5bab..b8e6ebccd4e7 100644 --- a/arch/arm/cpu/armv7/omap3/lowlevel_init.S +++ b/arch/arm/cpu/armv7/omap3/lowlevel_init.S @@ -48,6 +48,43 @@ ENTRY(do_omap3_emu_romcode_call) POP {r4-r12, pc} ENDPROC(do_omap3_emu_romcode_call)
+#ifdef CONFIG_ARM_ARCH_CP15_ERRATA + .globl arch_cp15_errata_workaround +/* + * R0 has MIDR + * R1 has CPU Variant (bits 20-23) + * R2 has CPU Revision (bits 0-3) + * R3 is compbined CPU variant << 4 + CPU revision + */ +ENTRY(arch_cp15_errata_workaround) + push {r4-r12, lr} @ save registers - ROM code may pollute + + mov r0, #0 @ Nothing to set in ACR + mov r1, #0 @ Nothing to clear in ACR + +#ifdef CONFIG_ARM_ERRATA_454179 + cmp r3, #0x21 @ Only on < r2p1 + orrlt r0, r0, #(0x3 << 6) @ Set DBSM(BIT7) and IBE(BIT6) bits +#endif + +#ifdef CONFIG_ARM_ERRATA_430973 + cmp r3, #0x21 @ Only on < r2p1 + orrlt r0, r0, #(0x1 << 6) @ Set IBE bit +#endif + +#ifdef CONFIG_ARM_ERRATA_621766 + cmp r3, #0x21 @ Only on < r2p1 + orrlt r0, r0, #(0x1 << 5) @ Set L1NEON bit +#endif + + add r2, r1, r0 + teq r2, #0 @ See if nothing to set or clear + bne omap3_update_aux_cr_secure @update as per ROM code configuration needs + + pop {r4-r12, pc} @restore the registers back. +ENDPROC(arch_cp15_errata_workaround) +#endif + #if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_NAND_BOOT) /************************************************************************** * cpy_clk_code: relocates clock code into SRAM where its safer to execute diff --git a/arch/arm/include/asm/arch-omap3/sys_proto.h b/arch/arm/include/asm/arch-omap3/sys_proto.h index c06605d533d3..56126fe8e863 100644 --- a/arch/arm/include/asm/arch-omap3/sys_proto.h +++ b/arch/arm/include/asm/arch-omap3/sys_proto.h @@ -74,5 +74,6 @@ void dieid_num_r(void); void get_dieid(u32 *id); void do_omap3_emu_romcode_call(u32 service_id, u32 parameters); void omap_smc1(u32 service, u32 val); +void omap3_update_aux_cr_secure(u32 set_bits, u32 clear_bits); u32 warm_reset(void); #endif
Le mardi 24 février 2015 à 16:57 -0600, Nishanth Menon a écrit :
430973: Stale prediction on replaced inter working branch causes Cortex-A8 to execute in the wrong ARM/Thumb state Impacts: Everything lower than r2p1 Work around: Set IBE to 1
According to the Linux kernel source, this should only affect r1p* (hence, not r2p0): https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/arch/ar...
454179: Stale prediction may inhibit target address misprediction on next predicted taken branch Impacts: Everything lower than r2p1 Work around: Set IBE and disable branch size mispredict to 1
621766: Under a specific set of conditions, executing a sequence of NEON or vfp load instructions can cause processor deadlock Impacts: Everything lower than r2p1 Work around: Set L1NEON to 1
Erratum 458693 also sets L1NEON bit and is said to only affect r2p0 according to the Linux kernel source: https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/arch/ar...
I'm not sure this is relevant (different erratum but similar workaround), but it seems odd to me.
Since the OMAP3 generation of processors have a wide variety of CPU revisions, it is more logical to enforce an implementation using revision checks.
Anyways, this worked just fine on my omap3630 device (> r2p1) and didn't trigger the errata workarounds. I reckon someone would have to test on a device that does require those workarounds (e.g. omap35xx).
Signed-off-by: Nishanth Menon nm@ti.com
README | 3 +++ arch/arm/cpu/armv7/omap3/board.c | 2 +- arch/arm/cpu/armv7/omap3/lowlevel_init.S | 37 +++++++++++++++++++++++++++ arch/arm/include/asm/arch-omap3/sys_proto.h | 1 + 4 files changed, 42 insertions(+), 1 deletion(-)
diff --git a/README b/README index d76cdc68d406..f309e27bbd02 100644 --- a/README +++ b/README @@ -625,6 +625,9 @@ The following options need to be configured: with CONFIG_ARM_ARCH_CP15_ERRATA define. These need to have an SoC specific implementation of the erratum workaround to function.
CONFIG_ARM_ERRATA_430973CONFIG_ARM_ERRATA_454179CONFIG_ARM_ERRATA_621766
- Driver Model
diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c index 51abc4b09e36..7ce30949a6c6 100644 --- a/arch/arm/cpu/armv7/omap3/board.c +++ b/arch/arm/cpu/armv7/omap3/board.c @@ -408,7 +408,7 @@ static void omap3_emu_romcode_call(u32 service_id, u32 *parameters) do_omap3_emu_romcode_call(service_id, OMAP3_PUBLIC_SRAM_SCRATCH_AREA); }
-static void omap3_update_aux_cr_secure(u32 set_bits, u32 clear_bits) +void omap3_update_aux_cr_secure(u32 set_bits, u32 clear_bits) { u32 acr;
diff --git a/arch/arm/cpu/armv7/omap3/lowlevel_init.S b/arch/arm/cpu/armv7/omap3/lowlevel_init.S index 84591b8b5bab..b8e6ebccd4e7 100644 --- a/arch/arm/cpu/armv7/omap3/lowlevel_init.S +++ b/arch/arm/cpu/armv7/omap3/lowlevel_init.S @@ -48,6 +48,43 @@ ENTRY(do_omap3_emu_romcode_call) POP {r4-r12, pc} ENDPROC(do_omap3_emu_romcode_call)
+#ifdef CONFIG_ARM_ARCH_CP15_ERRATA
- .globl arch_cp15_errata_workaround
+/*
- R0 has MIDR
- R1 has CPU Variant (bits 20-23)
- R2 has CPU Revision (bits 0-3)
- R3 is compbined CPU variant << 4 + CPU revision
- */
+ENTRY(arch_cp15_errata_workaround)
- push {r4-r12, lr} @ save registers - ROM code may pollute
- mov r0, #0 @ Nothing to set in ACR
- mov r1, #0 @ Nothing to clear in ACR
+#ifdef CONFIG_ARM_ERRATA_454179
- cmp r3, #0x21 @ Only on < r2p1
- orrlt r0, r0, #(0x3 << 6) @ Set DBSM(BIT7) and IBE(BIT6) bits
+#endif
+#ifdef CONFIG_ARM_ERRATA_430973
- cmp r3, #0x21 @ Only on < r2p1
- orrlt r0, r0, #(0x1 << 6) @ Set IBE bit
+#endif
+#ifdef CONFIG_ARM_ERRATA_621766
- cmp r3, #0x21 @ Only on < r2p1
- orrlt r0, r0, #(0x1 << 5) @ Set L1NEON bit
+#endif
- add r2, r1, r0
- teq r2, #0 @ See if nothing to set or clear
- bne omap3_update_aux_cr_secure @update as per ROM code configuration needs
- pop {r4-r12, pc} @restore the registers back.
+ENDPROC(arch_cp15_errata_workaround) +#endif
#if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_NAND_BOOT) /**************************************************************************
- cpy_clk_code: relocates clock code into SRAM where its safer to execute
diff --git a/arch/arm/include/asm/arch-omap3/sys_proto.h b/arch/arm/include/asm/arch-omap3/sys_proto.h index c06605d533d3..56126fe8e863 100644 --- a/arch/arm/include/asm/arch-omap3/sys_proto.h +++ b/arch/arm/include/asm/arch-omap3/sys_proto.h @@ -74,5 +74,6 @@ void dieid_num_r(void); void get_dieid(u32 *id); void do_omap3_emu_romcode_call(u32 service_id, u32 parameters); void omap_smc1(u32 service, u32 val); +void omap3_update_aux_cr_secure(u32 set_bits, u32 clear_bits); u32 warm_reset(void); #endif
On 02/25/2015 05:15 AM, Paul Kocialkowski wrote:
Le mardi 24 février 2015 à 16:57 -0600, Nishanth Menon a écrit :
430973: Stale prediction on replaced inter working branch causes Cortex-A8 to execute in the wrong ARM/Thumb state Impacts: Everything lower than r2p1 Work around: Set IBE to 1
According to the Linux kernel source, this should only affect r1p* (hence, not r2p0): https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/arch/ar...
I did look at the official Cortex-A8 errata doc (I think this is under NDA at least under TI).. Doc revision 20.0
This has a "Errata Summary Table" where "X" indicates the revision impacted. As per that, I see: r1p1, r1p2, r1p3, r1p7 impacted. the first not impacted is r2p1.
Hence the cmp r3, #0x21 (and orrlt).
Can someone from ARM ltd comment if there could be a better implementation? I will post a V3 based on latest documentation on my hand.
454179: Stale prediction may inhibit target address misprediction on next predicted taken branch Impacts: Everything lower than r2p1 Work around: Set IBE and disable branch size mispredict to 1
621766: Under a specific set of conditions, executing a sequence of NEON or vfp load instructions can cause processor deadlock Impacts: Everything lower than r2p1 Work around: Set L1NEON to 1
Erratum 458693 also sets L1NEON bit and is said to only affect r2p0 according to the Linux kernel source: https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/arch/ar...
I'm not sure this is relevant (different erratum but similar workaround), but it seems odd to me.
Since the OMAP3 generation of processors have a wide variety of CPU revisions, it is more logical to enforce an implementation using revision checks.
Anyways, this worked just fine on my omap3630 device (> r2p1) and didn't trigger the errata workarounds. I reckon someone would have to test on a device that does require those workarounds (e.g. omap35xx).
Signed-off-by: Nishanth Menon nm@ti.com
README | 3 +++ arch/arm/cpu/armv7/omap3/board.c | 2 +- arch/arm/cpu/armv7/omap3/lowlevel_init.S | 37 +++++++++++++++++++++++++++ arch/arm/include/asm/arch-omap3/sys_proto.h | 1 + 4 files changed, 42 insertions(+), 1 deletion(-)
diff --git a/README b/README index d76cdc68d406..f309e27bbd02 100644 --- a/README +++ b/README @@ -625,6 +625,9 @@ The following options need to be configured: with CONFIG_ARM_ARCH_CP15_ERRATA define. These need to have an SoC specific implementation of the erratum workaround to function.
CONFIG_ARM_ERRATA_430973CONFIG_ARM_ERRATA_454179CONFIG_ARM_ERRATA_621766
- Driver Model
diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c index 51abc4b09e36..7ce30949a6c6 100644 --- a/arch/arm/cpu/armv7/omap3/board.c +++ b/arch/arm/cpu/armv7/omap3/board.c @@ -408,7 +408,7 @@ static void omap3_emu_romcode_call(u32 service_id, u32 *parameters) do_omap3_emu_romcode_call(service_id, OMAP3_PUBLIC_SRAM_SCRATCH_AREA); }
-static void omap3_update_aux_cr_secure(u32 set_bits, u32 clear_bits) +void omap3_update_aux_cr_secure(u32 set_bits, u32 clear_bits) { u32 acr;
diff --git a/arch/arm/cpu/armv7/omap3/lowlevel_init.S b/arch/arm/cpu/armv7/omap3/lowlevel_init.S index 84591b8b5bab..b8e6ebccd4e7 100644 --- a/arch/arm/cpu/armv7/omap3/lowlevel_init.S +++ b/arch/arm/cpu/armv7/omap3/lowlevel_init.S @@ -48,6 +48,43 @@ ENTRY(do_omap3_emu_romcode_call) POP {r4-r12, pc} ENDPROC(do_omap3_emu_romcode_call)
+#ifdef CONFIG_ARM_ARCH_CP15_ERRATA
- .globl arch_cp15_errata_workaround
+/*
- R0 has MIDR
- R1 has CPU Variant (bits 20-23)
- R2 has CPU Revision (bits 0-3)
- R3 is compbined CPU variant << 4 + CPU revision
- */
+ENTRY(arch_cp15_errata_workaround)
- push {r4-r12, lr} @ save registers - ROM code may pollute
- mov r0, #0 @ Nothing to set in ACR
- mov r1, #0 @ Nothing to clear in ACR
+#ifdef CONFIG_ARM_ERRATA_454179
- cmp r3, #0x21 @ Only on < r2p1
- orrlt r0, r0, #(0x3 << 6) @ Set DBSM(BIT7) and IBE(BIT6) bits
+#endif
+#ifdef CONFIG_ARM_ERRATA_430973
- cmp r3, #0x21 @ Only on < r2p1
- orrlt r0, r0, #(0x1 << 6) @ Set IBE bit
+#endif
+#ifdef CONFIG_ARM_ERRATA_621766
- cmp r3, #0x21 @ Only on < r2p1
- orrlt r0, r0, #(0x1 << 5) @ Set L1NEON bit
+#endif
- add r2, r1, r0
- teq r2, #0 @ See if nothing to set or clear
- bne omap3_update_aux_cr_secure @update as per ROM code configuration needs
- pop {r4-r12, pc} @restore the registers back.
+ENDPROC(arch_cp15_errata_workaround) +#endif
#if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_NAND_BOOT) /**************************************************************************
- cpy_clk_code: relocates clock code into SRAM where its safer to execute
diff --git a/arch/arm/include/asm/arch-omap3/sys_proto.h b/arch/arm/include/asm/arch-omap3/sys_proto.h index c06605d533d3..56126fe8e863 100644 --- a/arch/arm/include/asm/arch-omap3/sys_proto.h +++ b/arch/arm/include/asm/arch-omap3/sys_proto.h @@ -74,5 +74,6 @@ void dieid_num_r(void); void get_dieid(u32 *id); void do_omap3_emu_romcode_call(u32 service_id, u32 parameters); void omap_smc1(u32 service, u32 val); +void omap3_update_aux_cr_secure(u32 set_bits, u32 clear_bits); u32 warm_reset(void); #endif
On Wed, 25 Feb 2015 13:49:52 -0600 Nishanth Menon nm@ti.com wrote:
On 02/25/2015 05:15 AM, Paul Kocialkowski wrote:
Le mardi 24 février 2015 à 16:57 -0600, Nishanth Menon a écrit :
430973: Stale prediction on replaced inter working branch causes Cortex-A8 to execute in the wrong ARM/Thumb state Impacts: Everything lower than r2p1 Work around: Set IBE to 1
According to the Linux kernel source, this should only affect r1p* (hence, not r2p0): https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/arch/ar...
I did look at the official Cortex-A8 errata doc (I think this is under NDA at least under TI).. Doc revision 20.0
The errata list is not that much secret. But more like all the documents that you get from your employer are just under NDA by default. Even though they might be also available from the other sources.
I had the same problem. And specifically requested and obtained my own personal copy of the Cortex-A8 errata list from ARM as a private individual (to my gmail address, and clearly stating that I wanted it for the purposes *not* related to my corporate job) :-)
I'm not allowed to share my copy with the other people though, so everyone has to get it directly from ARM. I believe that that this only requires filling in the registration form on the ARM website and agreeing with the conditions.
There are also PDF documents from Freescale in public access, which contain some Cortex-A8 errata information too:
http://cache.freescale.com/files/32bit/doc/errata/IMX50CE.pdf http://www.freescale.com/docs/pcn_attachments/15760_IMX53CE_Rev4.pdf
Enable the OMAP3 specific errata code for 454179, 430973, 621766 and while at it, remove legacy non-revision checked errata logic.
Signed-off-by: Nishanth Menon nm@ti.com --- arch/arm/cpu/armv7/omap3/board.c | 16 ---------------- include/configs/ti_omap3_common.h | 6 ++++++ 2 files changed, 6 insertions(+), 16 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c index 7ce30949a6c6..cc3a43341335 100644 --- a/arch/arm/cpu/armv7/omap3/board.c +++ b/arch/arm/cpu/armv7/omap3/board.c @@ -35,7 +35,6 @@ DECLARE_GLOBAL_DATA_PTR;
/* Declarations */ extern omap3_sysinfo sysinfo; -static void omap3_setup_aux_cr(void); #ifndef CONFIG_SYS_L2CACHE_OFF static void omap3_invalidate_l2_cache_secure(void); #endif @@ -246,9 +245,6 @@ void s_init(void)
try_unlock_memory();
- /* Errata workarounds */ - omap3_setup_aux_cr(); - #ifndef CONFIG_SYS_L2CACHE_OFF /* Invalidate L2-cache from secure mode */ omap3_invalidate_l2_cache_secure(); @@ -428,18 +424,6 @@ void omap3_update_aux_cr_secure(u32 set_bits, u32 clear_bits) } }
-static void omap3_setup_aux_cr(void) -{ - /* Workaround for Cortex-A8 errata: #454179 #430973 - * Set "IBE" bit - * Set "Disable Branch Size Mispredicts" bit - * Workaround for erratum #621766 - * Enable L1NEON bit - * ACR |= (IBE | DBSM | L1NEON) => ACR |= 0xE0 - */ - omap3_update_aux_cr_secure(0xE0, 0); -} - #ifndef CONFIG_SYS_L2CACHE_OFF static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits) { diff --git a/include/configs/ti_omap3_common.h b/include/configs/ti_omap3_common.h index f909f6b94a18..db15c12ddf53 100644 --- a/include/configs/ti_omap3_common.h +++ b/include/configs/ti_omap3_common.h @@ -27,6 +27,12 @@ # define CONFIG_SYS_MALLOC_F_LEN (1 << 10) #endif
+/* Common ARM Erratas */ +#define CONFIG_ARM_ARCH_CP15_ERRATA +#define CONFIG_ARM_ERRATA_454179 +#define CONFIG_ARM_ERRATA_430973 +#define CONFIG_ARM_ERRATA_621766 + /* The chip has SDRC controller */ #define CONFIG_SDRC
Le mardi 24 février 2015 à 16:57 -0600, Nishanth Menon a écrit :
Enable the OMAP3 specific errata code for 454179, 430973, 621766 and while at it, remove legacy non-revision checked errata logic.
Signed-off-by: Nishanth Menon nm@ti.com
arch/arm/cpu/armv7/omap3/board.c | 16 ---------------- include/configs/ti_omap3_common.h | 6 ++++++ 2 files changed, 6 insertions(+), 16 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c index 7ce30949a6c6..cc3a43341335 100644 --- a/arch/arm/cpu/armv7/omap3/board.c +++ b/arch/arm/cpu/armv7/omap3/board.c @@ -35,7 +35,6 @@ DECLARE_GLOBAL_DATA_PTR;
/* Declarations */ extern omap3_sysinfo sysinfo; -static void omap3_setup_aux_cr(void); #ifndef CONFIG_SYS_L2CACHE_OFF static void omap3_invalidate_l2_cache_secure(void); #endif @@ -246,9 +245,6 @@ void s_init(void)
try_unlock_memory();
- /* Errata workarounds */
- omap3_setup_aux_cr();
#ifndef CONFIG_SYS_L2CACHE_OFF /* Invalidate L2-cache from secure mode */ omap3_invalidate_l2_cache_secure(); @@ -428,18 +424,6 @@ void omap3_update_aux_cr_secure(u32 set_bits, u32 clear_bits) } }
-static void omap3_setup_aux_cr(void) -{
- /* Workaround for Cortex-A8 errata: #454179 #430973
* Set "IBE" bit* Set "Disable Branch Size Mispredicts" bit* Workaround for erratum #621766* Enable L1NEON bit* ACR |= (IBE | DBSM | L1NEON) => ACR |= 0xE0*/- omap3_update_aux_cr_secure(0xE0, 0);
-}
#ifndef CONFIG_SYS_L2CACHE_OFF static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits) { diff --git a/include/configs/ti_omap3_common.h b/include/configs/ti_omap3_common.h index f909f6b94a18..db15c12ddf53 100644 --- a/include/configs/ti_omap3_common.h +++ b/include/configs/ti_omap3_common.h
Only a couple of OMAP3 boards in U-Boot include ti_omap3_common.h. You can find a complete list of all the configs that need those options enabled from my first patch on that topic: http://lists.denx.de/pipermail/u-boot/2015-February/205809.html
I guess it's better to enable those on all the currently-supported omap3 platforms: that's the way it was so far and it won't hurt in cases it's not needed thanks to the revision detection.
@@ -27,6 +27,12 @@ # define CONFIG_SYS_MALLOC_F_LEN (1 << 10) #endif
+/* Common ARM Erratas */ +#define CONFIG_ARM_ARCH_CP15_ERRATA +#define CONFIG_ARM_ERRATA_454179 +#define CONFIG_ARM_ERRATA_430973 +#define CONFIG_ARM_ERRATA_621766
/* The chip has SDRC controller */ #define CONFIG_SDRC
-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1
On 02/25/15 13:19, Paul Kocialkowski wrote:
Le mardi 24 février 2015 à 16:57 -0600, Nishanth Menon a écrit :
Enable the OMAP3 specific errata code for 454179, 430973, 621766 and while at it, remove legacy non-revision checked errata logic.
Signed-off-by: Nishanth Menon nm@ti.com
arch/arm/cpu/armv7/omap3/board.c | 16 ---------------- include/configs/ti_omap3_common.h | 6 ++++++ 2 files changed, 6 insertions(+), 16 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c index 7ce30949a6c6..cc3a43341335 100644 --- a/arch/arm/cpu/armv7/omap3/board.c +++ b/arch/arm/cpu/armv7/omap3/board.c @@ -35,7 +35,6 @@ DECLARE_GLOBAL_DATA_PTR;
/* Declarations */ extern omap3_sysinfo sysinfo; -static void omap3_setup_aux_cr(void); #ifndef CONFIG_SYS_L2CACHE_OFF static void omap3_invalidate_l2_cache_secure(void); #endif @@ -246,9 +245,6 @@ void s_init(void)
try_unlock_memory();
- /* Errata workarounds */
- omap3_setup_aux_cr();
#ifndef CONFIG_SYS_L2CACHE_OFF /* Invalidate L2-cache from secure mode */ omap3_invalidate_l2_cache_secure(); @@ -428,18 +424,6 @@ void omap3_update_aux_cr_secure(u32 set_bits, u32 clear_bits) } }
-static void omap3_setup_aux_cr(void) -{
- /* Workaround for Cortex-A8 errata: #454179 #430973
* Set "IBE" bit* Set "Disable Branch Size Mispredicts" bit* Workaround for erratum #621766* Enable L1NEON bit* ACR |= (IBE | DBSM | L1NEON) => ACR |= 0xE0*/- omap3_update_aux_cr_secure(0xE0, 0);
-}
#ifndef CONFIG_SYS_L2CACHE_OFF static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits) { diff --git a/include/configs/ti_omap3_common.h b/include/configs/ti_omap3_common.h index f909f6b94a18..db15c12ddf53 100644 --- a/include/configs/ti_omap3_common.h +++ b/include/configs/ti_omap3_common.h
Only a couple of OMAP3 boards in U-Boot include ti_omap3_common.h. You can find a complete list of all the configs that need those options enabled from my first patch on that topic: http://lists.denx.de/pipermail/u-boot/2015-February/205809.html
I guess it's better to enable those on all the currently-supported omap3 platforms: that's the way it was so far and it won't hurt in cases it's not needed thanks to the revision detection.
Or... I think this patch might be a good enough argument to request people switch to include ti_omap3_common.h instead of duplicating it in private configs...
Don't you think?
@@ -27,6 +27,12 @@ # define CONFIG_SYS_MALLOC_F_LEN (1 << 10) #endif
+/* Common ARM Erratas */ +#define CONFIG_ARM_ARCH_CP15_ERRATA +#define CONFIG_ARM_ERRATA_454179 +#define CONFIG_ARM_ERRATA_430973 +#define CONFIG_ARM_ERRATA_621766
/* The chip has SDRC controller */ #define CONFIG_SDRC
U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
- -- Regards, Igor.
Le mercredi 25 février 2015 à 13:31 +0200, Igor Grinberg a écrit :
On 02/25/15 13:19, Paul Kocialkowski wrote:
Le mardi 24 février 2015 à 16:57 -0600, Nishanth Menon a écrit :
Enable the OMAP3 specific errata code for 454179, 430973, 621766 and while at it, remove legacy non-revision checked errata logic.
Signed-off-by: Nishanth Menon nm@ti.com
arch/arm/cpu/armv7/omap3/board.c | 16 ---------------- include/configs/ti_omap3_common.h | 6 ++++++ 2 files changed, 6 insertions(+), 16 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c index 7ce30949a6c6..cc3a43341335 100644 --- a/arch/arm/cpu/armv7/omap3/board.c +++ b/arch/arm/cpu/armv7/omap3/board.c @@ -35,7 +35,6 @@ DECLARE_GLOBAL_DATA_PTR;
/* Declarations */ extern omap3_sysinfo sysinfo; -static void omap3_setup_aux_cr(void); #ifndef CONFIG_SYS_L2CACHE_OFF static void omap3_invalidate_l2_cache_secure(void); #endif @@ -246,9 +245,6 @@ void s_init(void)
try_unlock_memory();
- /* Errata workarounds */
- omap3_setup_aux_cr();
#ifndef CONFIG_SYS_L2CACHE_OFF /* Invalidate L2-cache from secure mode */ omap3_invalidate_l2_cache_secure(); @@ -428,18 +424,6 @@ void omap3_update_aux_cr_secure(u32 set_bits, u32 clear_bits) } }
-static void omap3_setup_aux_cr(void) -{
- /* Workaround for Cortex-A8 errata: #454179 #430973
* Set "IBE" bit* Set "Disable Branch Size Mispredicts" bit* Workaround for erratum #621766* Enable L1NEON bit* ACR |= (IBE | DBSM | L1NEON) => ACR |= 0xE0*/- omap3_update_aux_cr_secure(0xE0, 0);
-}
#ifndef CONFIG_SYS_L2CACHE_OFF static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits) { diff --git a/include/configs/ti_omap3_common.h b/include/configs/ti_omap3_common.h index f909f6b94a18..db15c12ddf53 100644 --- a/include/configs/ti_omap3_common.h +++ b/include/configs/ti_omap3_common.h
Only a couple of OMAP3 boards in U-Boot include ti_omap3_common.h. You can find a complete list of all the configs that need those options enabled from my first patch on that topic: http://lists.denx.de/pipermail/u-boot/2015-February/205809.html
I guess it's better to enable those on all the currently-supported omap3 platforms: that's the way it was so far and it won't hurt in cases it's not needed thanks to the revision detection.
Or... I think this patch might be a good enough argument to request people switch to include ti_omap3_common.h instead of duplicating it in private configs...
Don't you think?
The way I see it, ti_omap3_common.h is common for OMAP3 boards made by TI. A few things there are not generic to omap3 in general (e.g. not every board uses the U-Boot SPL, or UART3 for console).
However, I agree it would be beneficial to have an omap3_common.h config with the options that are expected to be shared accross every possible omap3 device (and with a few clever ifdef so that the minimum has to be set in the including board configs).
I could try to come up with such a config if you wish, but I'm afraid I'm not the most qualified person to do this (I only have a single omap3 device).
@@ -27,6 +27,12 @@ # define CONFIG_SYS_MALLOC_F_LEN (1 << 10) #endif
+/* Common ARM Erratas */ +#define CONFIG_ARM_ARCH_CP15_ERRATA +#define CONFIG_ARM_ERRATA_454179 +#define CONFIG_ARM_ERRATA_430973 +#define CONFIG_ARM_ERRATA_621766
/* The chip has SDRC controller */ #define CONFIG_SDRC
U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
On Wed, Feb 25, 2015 at 6:27 AM, Paul Kocialkowski contact@paulk.fr wrote:
Le mercredi 25 février 2015 à 13:31 +0200, Igor Grinberg a écrit :
On 02/25/15 13:19, Paul Kocialkowski wrote:
Le mardi 24 février 2015 à 16:57 -0600, Nishanth Menon a écrit :
Enable the OMAP3 specific errata code for 454179, 430973, 621766 and while at it, remove legacy non-revision checked errata logic.
Signed-off-by: Nishanth Menon nm@ti.com
arch/arm/cpu/armv7/omap3/board.c | 16 ---------------- include/configs/ti_omap3_common.h | 6 ++++++ 2 files changed, 6 insertions(+), 16 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c index 7ce30949a6c6..cc3a43341335 100644 --- a/arch/arm/cpu/armv7/omap3/board.c +++ b/arch/arm/cpu/armv7/omap3/board.c @@ -35,7 +35,6 @@ DECLARE_GLOBAL_DATA_PTR;
/* Declarations */ extern omap3_sysinfo sysinfo; -static void omap3_setup_aux_cr(void); #ifndef CONFIG_SYS_L2CACHE_OFF static void omap3_invalidate_l2_cache_secure(void); #endif @@ -246,9 +245,6 @@ void s_init(void)
try_unlock_memory();
- /* Errata workarounds */
- omap3_setup_aux_cr();
#ifndef CONFIG_SYS_L2CACHE_OFF /* Invalidate L2-cache from secure mode */ omap3_invalidate_l2_cache_secure(); @@ -428,18 +424,6 @@ void omap3_update_aux_cr_secure(u32 set_bits, u32 clear_bits) } }
-static void omap3_setup_aux_cr(void) -{
- /* Workaround for Cortex-A8 errata: #454179 #430973
Set "IBE" bit
Set "Disable Branch Size Mispredicts" bit
- Workaround for erratum #621766
Enable L1NEON bit
- ACR |= (IBE | DBSM | L1NEON) => ACR |= 0xE0
- */
- omap3_update_aux_cr_secure(0xE0, 0);
-}
#ifndef CONFIG_SYS_L2CACHE_OFF static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits) { diff --git a/include/configs/ti_omap3_common.h b/include/configs/ti_omap3_common.h index f909f6b94a18..db15c12ddf53 100644 --- a/include/configs/ti_omap3_common.h +++ b/include/configs/ti_omap3_common.h
Only a couple of OMAP3 boards in U-Boot include ti_omap3_common.h. You can find a complete list of all the configs that need those options enabled from my first patch on that topic: http://lists.denx.de/pipermail/u-boot/2015-February/205809.html
I guess it's better to enable those on all the currently-supported omap3 platforms: that's the way it was so far and it won't hurt in cases it's not needed thanks to the revision detection.
Or... I think this patch might be a good enough argument to request people switch to include ti_omap3_common.h instead of duplicating it in private configs...
Don't you think?
The way I see it, ti_omap3_common.h is common for OMAP3 boards made by TI. A few things there are not generic to omap3 in general (e.g. not every board uses the U-Boot SPL, or UART3 for console).
However, I agree it would be beneficial to have an omap3_common.h config with the options that are expected to be shared accross every possible omap3 device (and with a few clever ifdef so that the minimum has to be set in the including board configs).
I could try to come up with such a config if you wish, but I'm afraid I'm not the most qualified person to do this (I only have a single omap3 device).
I am planning on a V3 based on trying to converge exynos and TI platforms into a common code base. I will stick with ti_*_common.h headers for now, we will keep all the other headers updated for the moment. I do stand with the opinion that we should all be using the same ti_omap3_common header for all platforms using the same SoC... but that could be done as follow on patches.
That said, Paul, if you could contribute patches to the effect of integrating all these platforms to ti_*_common.h, that'd be great.
-- Regards, Nishanth Menon
Le mercredi 25 février 2015 à 08:32 -0600, menon.nishanth@gmail.com a écrit :
On Wed, Feb 25, 2015 at 6:27 AM, Paul Kocialkowski contact@paulk.fr wrote:
Le mercredi 25 février 2015 à 13:31 +0200, Igor Grinberg a écrit :
On 02/25/15 13:19, Paul Kocialkowski wrote:
Le mardi 24 février 2015 à 16:57 -0600, Nishanth Menon a écrit :
Enable the OMAP3 specific errata code for 454179, 430973, 621766 and while at it, remove legacy non-revision checked errata logic.
Signed-off-by: Nishanth Menon nm@ti.com
arch/arm/cpu/armv7/omap3/board.c | 16 ---------------- include/configs/ti_omap3_common.h | 6 ++++++ 2 files changed, 6 insertions(+), 16 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c index 7ce30949a6c6..cc3a43341335 100644 --- a/arch/arm/cpu/armv7/omap3/board.c +++ b/arch/arm/cpu/armv7/omap3/board.c @@ -35,7 +35,6 @@ DECLARE_GLOBAL_DATA_PTR;
/* Declarations */ extern omap3_sysinfo sysinfo; -static void omap3_setup_aux_cr(void); #ifndef CONFIG_SYS_L2CACHE_OFF static void omap3_invalidate_l2_cache_secure(void); #endif @@ -246,9 +245,6 @@ void s_init(void)
try_unlock_memory();
- /* Errata workarounds */
- omap3_setup_aux_cr();
#ifndef CONFIG_SYS_L2CACHE_OFF /* Invalidate L2-cache from secure mode */ omap3_invalidate_l2_cache_secure(); @@ -428,18 +424,6 @@ void omap3_update_aux_cr_secure(u32 set_bits, u32 clear_bits) } }
-static void omap3_setup_aux_cr(void) -{
- /* Workaround for Cortex-A8 errata: #454179 #430973
Set "IBE" bit
Set "Disable Branch Size Mispredicts" bit
- Workaround for erratum #621766
Enable L1NEON bit
- ACR |= (IBE | DBSM | L1NEON) => ACR |= 0xE0
- */
- omap3_update_aux_cr_secure(0xE0, 0);
-}
#ifndef CONFIG_SYS_L2CACHE_OFF static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits) { diff --git a/include/configs/ti_omap3_common.h b/include/configs/ti_omap3_common.h index f909f6b94a18..db15c12ddf53 100644 --- a/include/configs/ti_omap3_common.h +++ b/include/configs/ti_omap3_common.h
Only a couple of OMAP3 boards in U-Boot include ti_omap3_common.h. You can find a complete list of all the configs that need those options enabled from my first patch on that topic: http://lists.denx.de/pipermail/u-boot/2015-February/205809.html
I guess it's better to enable those on all the currently-supported omap3 platforms: that's the way it was so far and it won't hurt in cases it's not needed thanks to the revision detection.
Or... I think this patch might be a good enough argument to request people switch to include ti_omap3_common.h instead of duplicating it in private configs...
Don't you think?
The way I see it, ti_omap3_common.h is common for OMAP3 boards made by TI. A few things there are not generic to omap3 in general (e.g. not every board uses the U-Boot SPL, or UART3 for console).
However, I agree it would be beneficial to have an omap3_common.h config with the options that are expected to be shared accross every possible omap3 device (and with a few clever ifdef so that the minimum has to be set in the including board configs).
I could try to come up with such a config if you wish, but I'm afraid I'm not the most qualified person to do this (I only have a single omap3 device).
I am planning on a V3 based on trying to converge exynos and TI platforms into a common code base. I will stick with ti_*_common.h headers for now, we will keep all the other headers updated for the moment. I do stand with the opinion that we should all be using the same ti_omap3_common header for all platforms using the same SoC... but that could be done as follow on patches.
That said, Paul, if you could contribute patches to the effect of integrating all these platforms to ti_*_common.h, that'd be great.
I will try to come up with a common configuration for omap3 (and possibly omap4 and omap5 too). Do you mind if I drop the ti_ prefix? I don't feel it's relevant to mention the chip manufacturer there, especially when it's not used anywhere else in the tree (except for the boards that are actually procuced by TI such as the evms, etc).
On 02/25/2015 03:23 PM, Paul Kocialkowski wrote:
Le mercredi 25 février 2015 à 08:32 -0600, menon.nishanth@gmail.com a
[...]
That said, Paul, if you could contribute patches to the effect of integrating all these platforms to ti_*_common.h, that'd be great.
I will try to come up with a common configuration for omap3 (and possibly omap4 and omap5 too). Do you mind if I drop the ti_ prefix? I don't feel it's relevant to mention the chip manufacturer there, especially when it's not used anywhere else in the tree (except for the boards that are actually procuced by TI such as the evms, etc).
I think we have maintained ti_ prefix for omap3,4,5 etc.. might make sense to retain that.. but then, I am no decision maker in that regards, I suggest posting a proposal and seeing feedback folks have w.r.t.
-- Regards, Nishanth Menon
Le mercredi 25 février 2015 à 23:11 -0600, Nishanth Menon a écrit :
On 02/25/2015 03:23 PM, Paul Kocialkowski wrote:
Le mercredi 25 février 2015 à 08:32 -0600, menon.nishanth@gmail.com a
[...]
That said, Paul, if you could contribute patches to the effect of integrating all these platforms to ti_*_common.h, that'd be great.
I will try to come up with a common configuration for omap3 (and possibly omap4 and omap5 too). Do you mind if I drop the ti_ prefix? I don't feel it's relevant to mention the chip manufacturer there, especially when it's not used anywhere else in the tree (except for the boards that are actually procuced by TI such as the evms, etc).
I think we have maintained ti_ prefix for omap3,4,5 etc.. might make sense to retain that.. but then, I am no decision maker in that regards, I suggest posting a proposal and seeing feedback folks have w.r.t.
I have started looking at the situation for am33xx, omap3, omap4 and omap5 and I'll post a RFC at some point in the near future. I'm a bit busy right now and this is not high priority since your latest series includes all the configs for the affected omap3 boards.
Update to existing recommendation for L2ACTLR configuration to prevent system instability and optimize performance.
These apply to both OMAP5 and DRA7.
Reported-by: Vivek Chengalvala vchengalvala@ti.com Signed-off-by: Nishanth Menon nm@ti.com --- arch/arm/cpu/armv7/omap5/hwinit.c | 16 ++++++++++++++++ arch/arm/include/asm/arch-omap5/sys_proto.h | 3 +++ 2 files changed, 19 insertions(+)
diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c index a8a474a88be9..632df4f0bfae 100644 --- a/arch/arm/cpu/armv7/omap5/hwinit.c +++ b/arch/arm/cpu/armv7/omap5/hwinit.c @@ -304,6 +304,21 @@ void config_data_eye_leveling_samples(u32 emif_base) (*ctrl)->control_emif2_sdram_config_ext); }
+void init_cpu_configuration(void) +{ + u32 l2actlr; + + asm volatile("mrc p15, 1, %0, c15, c0, 0" : "=r"(l2actlr)); + /* + * L2ACTLR: Ensure to enable the following: + * 3: Disable clean/evict push to external + * 4: Disable WriteUnique and WriteLineUnique transactions from master + * 8: Disable DVM/CMO message broadcast + */ + l2actlr |= 0x118; + omap_smc1(OMAP5_SERVICE_L2ACTLR_SET, l2actlr); +} + void init_omap_revision(void) { /* @@ -342,6 +357,7 @@ void init_omap_revision(void) default: *omap_si_rev = OMAP5430_SILICON_ID_INVALID; } + init_cpu_configuration(); }
void reset_cpu(ulong ignored) diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h b/arch/arm/include/asm/arch-omap5/sys_proto.h index 0a7a52d138df..e2e186859373 100644 --- a/arch/arm/include/asm/arch-omap5/sys_proto.h +++ b/arch/arm/include/asm/arch-omap5/sys_proto.h @@ -67,4 +67,7 @@ static inline u32 usec_to_32k(u32 usec) { return div_round_up(32768 * usec, 1000000); } + +#define OMAP5_SERVICE_L2ACTLR_SET 0x104 + #endif
participants (5)
-
Igor Grinberg -
menon.nishanth＠gmail.com -
Nishanth Menon -
Paul Kocialkowski -
Siarhei Siamashka