[U-Boot] [PATCH v2 0/3] ARM: UniPhier: fix SocGlue header

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[U-Boot] [PATCH] ARM: UniPhier:...

Masahiro Yamada

21 Jan 2015 21 Jan '15

7:27 a.m.

Masahiro Yamada (3): ARM: UniPhier: use <linux/sizes.h> for readability ARM: UniPhier: rename SG_MEMCONF_* macros for readability ARM: UniPhier: add SG_MEMCONF macros for DDR channel 2

arch/arm/include/asm/arch-uniphier/sg-regs.h | 109 +++++++++++++++++++-------- 1 file changed, 77 insertions(+), 32 deletions(-)

-- 1.9.1

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Masahiro Yamada

21 Jan 21 Jan

7:27 a.m.

New subject: [U-Boot] [PATCH v2 1/3] ARM: UniPhier: use <linux/sizes.h> for readability

Signed-off-by: Masahiro Yamada yamada.m@jp.panasonic.com ---

Changes in v2: - Split into two patches

arch/arm/include/asm/arch-uniphier/sg-regs.h | 25 +++++++++++++------------ 1 file changed, 13 insertions(+), 12 deletions(-)

diff --git a/arch/arm/include/asm/arch-uniphier/sg-regs.h b/arch/arm/include/asm/arch-uniphier/sg-regs.h index fa5e6ae..7bf45c5 100644 --- a/arch/arm/include/asm/arch-uniphier/sg-regs.h +++ b/arch/arm/include/asm/arch-uniphier/sg-regs.h @@ -101,6 +101,7 @@ #else

#include <linux/types.h> +#include <linux/sizes.h> #include <asm/io.h>

static inline void sg_set_pinsel(int n, int value) @@ -111,23 +112,23 @@ static inline void sg_set_pinsel(int n, int value)

static inline u32 sg_memconf_val_ch0(unsigned long size, int num) { - int size_mb = (size >> 20) / num; + int size_mb = size / num; u32 ret;

switch (size_mb) { - case 64: + case SZ_64M: ret = SG_MEMCONF_CH0_SIZE_64MB; break; - case 128: + case SZ_128M: ret = SG_MEMCONF_CH0_SIZE_128MB; break; - case 256: + case SZ_256M: ret = SG_MEMCONF_CH0_SIZE_256MB; break; - case 512: + case SZ_512M: ret = SG_MEMCONF_CH0_SIZE_512MB; break; - case 1024: + case SZ_1G: ret = SG_MEMCONF_CH0_SIZE_1024MB; break; default: @@ -151,23 +152,23 @@ static inline u32 sg_memconf_val_ch0(unsigned long size, int num)

static inline u32 sg_memconf_val_ch1(unsigned long size, int num) { - int size_mb = (size >> 20) / num; + int size_mb = size / num; u32 ret;

switch (size_mb) { - case 64: + case SZ_64M: ret = SG_MEMCONF_CH1_SIZE_64MB; break; - case 128: + case SZ_128M: ret = SG_MEMCONF_CH1_SIZE_128MB; break; - case 256: + case SZ_256M: ret = SG_MEMCONF_CH1_SIZE_256MB; break; - case 512: + case SZ_512M: ret = SG_MEMCONF_CH1_SIZE_512MB; break; - case 1024: + case SZ_1G: ret = SG_MEMCONF_CH1_SIZE_1024MB; break; default:

-- 1.9.1

Masahiro Yamada

7:27 a.m.

New subject: [U-Boot] [PATCH v2 2/3] ARM: UniPhier: rename SG_MEMCONF_* macros for readability

Match the suffixes of SG_MEMCONF_* macros with SZ_* macros defined by <linux/sizes.h> for readability.

Signed-off-by: Masahiro Yamada yamada.m@jp.panasonic.com ---

Changes in v2: - Split into two patches

arch/arm/include/asm/arch-uniphier/sg-regs.h | 40 ++++++++++++++-------------- 1 file changed, 20 insertions(+), 20 deletions(-)

diff --git a/arch/arm/include/asm/arch-uniphier/sg-regs.h b/arch/arm/include/asm/arch-uniphier/sg-regs.h index 7bf45c5..9b468d4 100644 --- a/arch/arm/include/asm/arch-uniphier/sg-regs.h +++ b/arch/arm/include/asm/arch-uniphier/sg-regs.h @@ -25,19 +25,19 @@ /* Memory Configuration */ #define SG_MEMCONF (SG_CTRL_BASE | 0x0400)

-#define SG_MEMCONF_CH0_SIZE_64MB ((0x0 << 10) | (0x01 << 0)) -#define SG_MEMCONF_CH0_SIZE_128MB ((0x0 << 10) | (0x02 << 0)) -#define SG_MEMCONF_CH0_SIZE_256MB ((0x0 << 10) | (0x03 << 0)) -#define SG_MEMCONF_CH0_SIZE_512MB ((0x1 << 10) | (0x00 << 0)) -#define SG_MEMCONF_CH0_SIZE_1024MB ((0x1 << 10) | (0x01 << 0)) +#define SG_MEMCONF_CH0_SZ_64M ((0x0 << 10) | (0x01 << 0)) +#define SG_MEMCONF_CH0_SZ_128M ((0x0 << 10) | (0x02 << 0)) +#define SG_MEMCONF_CH0_SZ_256M ((0x0 << 10) | (0x03 << 0)) +#define SG_MEMCONF_CH0_SZ_512M ((0x1 << 10) | (0x00 << 0)) +#define SG_MEMCONF_CH0_SZ_1G ((0x1 << 10) | (0x01 << 0)) #define SG_MEMCONF_CH0_NUM_1 (0x1 << 8) #define SG_MEMCONF_CH0_NUM_2 (0x0 << 8)

-#define SG_MEMCONF_CH1_SIZE_64MB ((0x0 << 11) | (0x01 << 2)) -#define SG_MEMCONF_CH1_SIZE_128MB ((0x0 << 11) | (0x02 << 2)) -#define SG_MEMCONF_CH1_SIZE_256MB ((0x0 << 11) | (0x03 << 2)) -#define SG_MEMCONF_CH1_SIZE_512MB ((0x1 << 11) | (0x00 << 2)) -#define SG_MEMCONF_CH1_SIZE_1024MB ((0x1 << 11) | (0x01 << 2)) +#define SG_MEMCONF_CH1_SZ_64M ((0x0 << 11) | (0x01 << 2)) +#define SG_MEMCONF_CH1_SZ_128M ((0x0 << 11) | (0x02 << 2)) +#define SG_MEMCONF_CH1_SZ_256M ((0x0 << 11) | (0x03 << 2)) +#define SG_MEMCONF_CH1_SZ_512M ((0x1 << 11) | (0x00 << 2)) +#define SG_MEMCONF_CH1_SZ_1G ((0x1 << 11) | (0x01 << 2)) #define SG_MEMCONF_CH1_NUM_1 (0x1 << 9) #define SG_MEMCONF_CH1_NUM_2 (0x0 << 9)

@@ -117,19 +117,19 @@ static inline u32 sg_memconf_val_ch0(unsigned long size, int num)

switch (size_mb) { case SZ_64M: - ret = SG_MEMCONF_CH0_SIZE_64MB; + ret = SG_MEMCONF_CH0_SZ_64M; break; case SZ_128M: - ret = SG_MEMCONF_CH0_SIZE_128MB; + ret = SG_MEMCONF_CH0_SZ_128M; break; case SZ_256M: - ret = SG_MEMCONF_CH0_SIZE_256MB; + ret = SG_MEMCONF_CH0_SZ_256M; break; case SZ_512M: - ret = SG_MEMCONF_CH0_SIZE_512MB; + ret = SG_MEMCONF_CH0_SZ_512M; break; case SZ_1G: - ret = SG_MEMCONF_CH0_SIZE_1024MB; + ret = SG_MEMCONF_CH0_SZ_1G; break; default: BUG(); @@ -157,19 +157,19 @@ static inline u32 sg_memconf_val_ch1(unsigned long size, int num)

switch (size_mb) { case SZ_64M: - ret = SG_MEMCONF_CH1_SIZE_64MB; + ret = SG_MEMCONF_CH1_SZ_64M; break; case SZ_128M: - ret = SG_MEMCONF_CH1_SIZE_128MB; + ret = SG_MEMCONF_CH1_SZ_128M; break; case SZ_256M: - ret = SG_MEMCONF_CH1_SIZE_256MB; + ret = SG_MEMCONF_CH1_SZ_256M; break; case SZ_512M: - ret = SG_MEMCONF_CH1_SIZE_512MB; + ret = SG_MEMCONF_CH1_SZ_512M; break; case SZ_1G: - ret = SG_MEMCONF_CH1_SIZE_1024MB; + ret = SG_MEMCONF_CH1_SZ_1G; break; default: BUG();

-- 1.9.1

Masahiro Yamada

7:27 a.m.

New subject: [U-Boot] [PATCH v2 3/3] ARM: UniPhier: add SG_MEMCONF macros for DDR channel 2

PH1-sLD3, PH1-LD6b have DDR channel 2.

Signed-off-by: Masahiro Yamada yamada.m@jp.panasonic.com ---

Changes in v2: None

arch/arm/include/asm/arch-uniphier/sg-regs.h | 44 ++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+)

diff --git a/arch/arm/include/asm/arch-uniphier/sg-regs.h b/arch/arm/include/asm/arch-uniphier/sg-regs.h index 9b468d4..4ae67c8 100644 --- a/arch/arm/include/asm/arch-uniphier/sg-regs.h +++ b/arch/arm/include/asm/arch-uniphier/sg-regs.h @@ -41,6 +41,13 @@ #define SG_MEMCONF_CH1_NUM_1 (0x1 << 9) #define SG_MEMCONF_CH1_NUM_2 (0x0 << 9)

+#define SG_MEMCONF_CH2_SZ_64M ((0x0 << 26) | (0x01 << 16)) +#define SG_MEMCONF_CH2_SZ_128M ((0x0 << 26) | (0x02 << 16)) +#define SG_MEMCONF_CH2_SZ_256M ((0x0 << 26) | (0x03 << 16)) +#define SG_MEMCONF_CH2_SZ_512M ((0x1 << 26) | (0x00 << 16)) +#define SG_MEMCONF_CH2_NUM_1 (0x1 << 24) +#define SG_MEMCONF_CH2_NUM_2 (0x0 << 24) + #define SG_MEMCONF_SPARSEMEM (0x1 << 4)

/* Pin Control */ @@ -189,6 +196,43 @@ static inline u32 sg_memconf_val_ch1(unsigned long size, int num) } return ret; } + +static inline u32 sg_memconf_val_ch2(unsigned long size, int num) +{ + int size_mb = size / num; + u32 ret; + + switch (size_mb) { + case SZ_64M: + ret = SG_MEMCONF_CH2_SZ_64M; + break; + case SZ_128M: + ret = SG_MEMCONF_CH2_SZ_128M; + break; + case SZ_256M: + ret = SG_MEMCONF_CH2_SZ_256M; + break; + case SZ_512M: + ret = SG_MEMCONF_CH2_SZ_512M; + break; + default: + BUG(); + break; + } + + switch (num) { + case 1: + ret |= SG_MEMCONF_CH2_NUM_1; + break; + case 2: + ret |= SG_MEMCONF_CH2_NUM_2; + break; + default: + BUG(); + break; + } + return ret; +} #endif /* __ASSEMBLY__ */

#endif /* ARCH_SG_REGS_H */

-- 1.9.1

Masahiro YAMADA

22 Jan 22 Jan

5:11 p.m.

2015-01-21 15:27 GMT+09:00 Masahiro Yamada yamada.m@jp.panasonic.com:

...

Masahiro Yamada (3): ARM: UniPhier: use <linux/sizes.h> for readability ARM: UniPhier: rename SG_MEMCONF_* macros for readability ARM: UniPhier: add SG_MEMCONF macros for DDR channel 2

arch/arm/include/asm/arch-uniphier/sg-regs.h | 109 +++++++++++++++++++-------- 1 file changed, 77 insertions(+), 32 deletions(-)

Series, Applied to u-boot-uniphier/master

-- Best Regards Masahiro Yamada

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