All RK3308 boards has now been synced to Linux kernel v6.8 DTs and can migrate to use OF_UPSTREAM.

Migrate all RK3308 boards to use OF_UPSTREAM.

Signed-off-by: Jonas Karlman jonas@kwiboo.se --- arch/arm/dts/Makefile | 5 ----- arch/arm/mach-rockchip/Kconfig | 1 + configs/evb-rk3308_defconfig | 2 +- configs/roc-cc-rk3308_defconfig | 2 +- configs/rock-pi-s-rk3308_defconfig | 2 +- 5 files changed, 4 insertions(+), 8 deletions(-)

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index c9f1b25ad647..319ec23a4fee 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -92,11 +92,6 @@ dtb-$(CONFIG_ROCKCHIP_RK3288) += \ rk3288-veyron-speedy.dtb \ rk3288-vyasa.dtb

-dtb-$(CONFIG_ROCKCHIP_RK3308) += \ - rk3308-evb.dtb \ - rk3308-roc-cc.dtb \ - rk3308-rock-pi-s.dtb - dtb-$(CONFIG_ROCKCHIP_RK3328) += \ rk3328-evb.dtb \ rk3328-nanopi-r2c.dtb \ diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 262cb7cba3ea..f1caf4f3738b 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -166,6 +166,7 @@ config ROCKCHIP_RK3308 imply LEGACY_IMAGE_FORMAT imply MISC imply MISC_INIT_R + imply OF_UPSTREAM imply RNG_ROCKCHIP imply ROCKCHIP_COMMON_BOARD imply ROCKCHIP_OTP diff --git a/configs/evb-rk3308_defconfig b/configs/evb-rk3308_defconfig index 04a94e13a68a..f4c2ea12adaa 100644 --- a/configs/evb-rk3308_defconfig +++ b/configs/evb-rk3308_defconfig @@ -2,7 +2,7 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_DEFAULT_DEVICE_TREE="rk3308-evb" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3308-evb" CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3308=y diff --git a/configs/roc-cc-rk3308_defconfig b/configs/roc-cc-rk3308_defconfig index ef58bd657532..862ea4301f25 100644 --- a/configs/roc-cc-rk3308_defconfig +++ b/configs/roc-cc-rk3308_defconfig @@ -3,7 +3,7 @@ CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y CONFIG_SPL_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="rk3308-roc-cc" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3308-roc-cc" CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3308=y diff --git a/configs/rock-pi-s-rk3308_defconfig b/configs/rock-pi-s-rk3308_defconfig index 37a124eae181..c15ba3d8a451 100644 --- a/configs/rock-pi-s-rk3308_defconfig +++ b/configs/rock-pi-s-rk3308_defconfig @@ -2,7 +2,7 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_DEFAULT_DEVICE_TREE="rk3308-rock-pi-s" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3308-rock-pi-s" CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3308=y

Remove redundant device tree files now that RK3308 boards have been migrated to use OF_UPSTREAM.

Signed-off-by: Jonas Karlman jonas@kwiboo.se --- arch/arm/dts/rk3308-evb.dts | 230 --- arch/arm/dts/rk3308-roc-cc.dts | 190 --- arch/arm/dts/rk3308-rock-pi-s.dts | 314 ---- arch/arm/dts/rk3308.dtsi | 1888 ------------------------ include/dt-bindings/clock/rk3308-cru.h | 387 ----- 5 files changed, 3009 deletions(-) delete mode 100644 arch/arm/dts/rk3308-evb.dts delete mode 100644 arch/arm/dts/rk3308-roc-cc.dts delete mode 100644 arch/arm/dts/rk3308-rock-pi-s.dts delete mode 100644 arch/arm/dts/rk3308.dtsi delete mode 100644 include/dt-bindings/clock/rk3308-cru.h

diff --git a/arch/arm/dts/rk3308-evb.dts b/arch/arm/dts/rk3308-evb.dts deleted file mode 100644 index 184b84fdde07..000000000000 --- a/arch/arm/dts/rk3308-evb.dts +++ /dev/null @@ -1,230 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd - * - */ - -/dts-v1/; -#include <dt-bindings/input/input.h> -#include "rk3308.dtsi" - -/ { - model = "Rockchip RK3308 EVB"; - compatible = "rockchip,rk3308-evb", "rockchip,rk3308"; - - chosen { - stdout-path = "serial4:1500000n8"; - }; - - adc-keys0 { - compatible = "adc-keys"; - io-channels = <&saradc 0>; - io-channel-names = "buttons"; - poll-interval = <100>; - keyup-threshold-microvolt = <1800000>; - - button-func { - linux,code = <KEY_FN>; - label = "function"; - press-threshold-microvolt = <18000>; - }; - }; - - adc-keys1 { - compatible = "adc-keys"; - io-channels = <&saradc 1>; - io-channel-names = "buttons"; - poll-interval = <100>; - keyup-threshold-microvolt = <1800000>; - - button-esc { - linux,code = <KEY_MICMUTE>; - label = "micmute"; - press-threshold-microvolt = <1130000>; - }; - - button-home { - linux,code = <KEY_MODE>; - label = "mode"; - press-threshold-microvolt = <901000>; - }; - - button-menu { - linux,code = <KEY_PLAY>; - label = "play"; - press-threshold-microvolt = <624000>; - }; - - button-down { - linux,code = <KEY_VOLUMEDOWN>; - label = "volume down"; - press-threshold-microvolt = <300000>; - }; - - button-up { - linux,code = <KEY_VOLUMEUP>; - label = "volume up"; - press-threshold-microvolt = <18000>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - - pinctrl-names = "default"; - pinctrl-0 = <&pwr_key>; - - key-power { - gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>; - linux,code = <KEY_POWER>; - label = "GPIO Key Power"; - debounce-interval = <100>; - wakeup-source; - }; - }; - - vcc12v_dcin: vcc12v-dcin { - compatible = "regulator-fixed"; - regulator-name = "vcc12v_dcin"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-always-on; - regulator-boot-on; - }; - - vcc5v0_sys: vcc5v0-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc12v_dcin>; - }; - - vccio_sdio: vcc_1v8: vcc-1v8 { - compatible = "regulator-fixed"; - regulator-name = "vcc_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_io>; - }; - - vcc_ddr: vcc-ddr { - compatible = "regulator-fixed"; - regulator-name = "vcc_ddr"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc5v0_sys>; - }; - - vcc_io: vcc-io { - compatible = "regulator-fixed"; - regulator-name = "vcc_io"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc5v0_sys>; - }; - - vccio_flash: vccio-flash { - compatible = "regulator-fixed"; - regulator-name = "vccio_flash"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_io>; - }; - - vcc5v0_host: vcc5v0-host { - compatible = "regulator-fixed"; - gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; - enable-active-high; - pinctrl-names = "default"; - pinctrl-0 = <&usb_drv>; - regulator-name = "vbus_host"; - vin-supply = <&vcc5v0_sys>; - }; - - vdd_core: vdd-core { - compatible = "pwm-regulator"; - pwms = <&pwm0 0 5000 1>; - regulator-name = "vdd_core"; - regulator-min-microvolt = <827000>; - regulator-max-microvolt = <1340000>; - regulator-always-on; - regulator-boot-on; - regulator-settling-time-up-us = <250>; - pwm-supply = <&vcc5v0_sys>; - }; - - vdd_log: vdd-log { - compatible = "regulator-fixed"; - regulator-name = "vdd_log"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc5v0_sys>; - }; - - vdd_1v0: vdd-1v0 { - compatible = "regulator-fixed"; - regulator-name = "vdd_1v0"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc5v0_sys>; - }; -}; - -&cpu0 { - cpu-supply = <&vdd_core>; -}; - -&saradc { - status = "okay"; - vref-supply = <&vcc_1v8>; -}; - -&pinctrl { - pinctrl-names = "default"; - pinctrl-0 = <&rtc_32k>; - - buttons { - pwr_key: pwr-key { - rockchip,pins = <0 RK_PA6 0 &pcfg_pull_up>; - }; - }; - - usb { - usb_drv: usb-drv { - rockchip,pins = <0 RK_PC5 0 &pcfg_pull_none>; - }; - }; - - sdio-pwrseq { - wifi_enable_h: wifi-enable-h { - rockchip,pins = <0 RK_PA2 0 &pcfg_pull_none>; - }; - }; -}; - -&pwm0 { - status = "okay"; - pinctrl-0 = <&pwm0_pin_pull_down>; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&uart4_xfer>; - status = "okay"; -}; diff --git a/arch/arm/dts/rk3308-roc-cc.dts b/arch/arm/dts/rk3308-roc-cc.dts deleted file mode 100644 index 9232357f4fec..000000000000 --- a/arch/arm/dts/rk3308-roc-cc.dts +++ /dev/null @@ -1,190 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd - */ - -/dts-v1/; -#include "rk3308.dtsi" - -/ { - model = "Firefly ROC-RK3308-CC board"; - compatible = "firefly,roc-rk3308-cc", "rockchip,rk3308"; - - aliases { - mmc0 = &sdmmc; - mmc1 = &emmc; - }; - - chosen { - stdout-path = "serial2:1500000n8"; - }; - - ir-receiver { - compatible = "gpio-ir-receiver"; - gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&ir_recv_pin>; - }; - - ir_tx { - compatible = "pwm-ir-tx"; - pwms = <&pwm5 0 25000 0>; - }; - - leds { - compatible = "gpio-leds"; - - power_led: led-0 { - label = "firefly:red:power"; - linux,default-trigger = "ir-power-click"; - default-state = "on"; - gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; - }; - - user_led: led-1 { - label = "firefly:blue:user"; - linux,default-trigger = "ir-user-click"; - default-state = "off"; - gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_HIGH>; - }; - }; - - typec_vcc5v: typec-vcc5v { - compatible = "regulator-fixed"; - regulator-name = "typec_vcc5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - vcc5v0_sys: vcc5v0-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&typec_vcc5v>; - }; - - vcc_io: vcc-io { - compatible = "regulator-fixed"; - regulator-name = "vcc_io"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc5v0_sys>; - }; - - vcc_sdmmc: vcc-sdmmc { - compatible = "regulator-gpio"; - regulator-name = "vcc_sdmmc"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_HIGH>; - states = <1800000 0x0>, - <3300000 0x1>; - vin-supply = <&vcc5v0_sys>; - }; - - vcc_sd: vcc-sd { - compatible = "regulator-fixed"; - gpio = <&gpio4 RK_PD6 GPIO_ACTIVE_LOW>; - regulator-name = "vcc_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_io>; - }; - - vdd_core: vdd-core { - compatible = "pwm-regulator"; - pwms = <&pwm0 0 5000 1>; - regulator-name = "vdd_core"; - regulator-min-microvolt = <827000>; - regulator-max-microvolt = <1340000>; - regulator-settling-time-up-us = <250>; - regulator-always-on; - regulator-boot-on; - pwm-supply = <&vcc5v0_sys>; - }; - - vdd_log: vdd-log { - compatible = "regulator-fixed"; - regulator-name = "vdd_log"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc5v0_sys>; - }; -}; - -&cpu0 { - cpu-supply = <&vdd_core>; -}; - -&emmc { - cap-mmc-highspeed; - mmc-hs200-1_8v; - non-removable; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <400000>; - status = "okay"; - - rtc: rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - #clock-cells = <0>; - }; -}; - -&pwm5 { - status = "okay"; - pinctrl-names = "active"; - pinctrl-0 = <&pwm5_pin_pull_down>; -}; - -&pinctrl { - pinctrl-names = "default"; - pinctrl-0 = <&rtc_32k>; - - ir-receiver { - ir_recv_pin: ir-recv-pin { - rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - buttons { - pwr_key: pwr-key { - rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; -}; - -&pwm0 { - status = "okay"; - pinctrl-0 = <&pwm0_pin_pull_down>; -}; - -&sdmmc { - cap-mmc-highspeed; - cap-sd-highspeed; - card-detect-delay = <300>; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-sdr104; - vmmc-supply = <&vcc_sd>; - vqmmc-supply = <&vcc_sdmmc>; - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; diff --git a/arch/arm/dts/rk3308-rock-pi-s.dts b/arch/arm/dts/rk3308-rock-pi-s.dts deleted file mode 100644 index b47fe02c33fb..000000000000 --- a/arch/arm/dts/rk3308-rock-pi-s.dts +++ /dev/null @@ -1,314 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 Akash Gajjar akash@openedev.com - * Copyright (c) 2019 Jagan Teki jagan@openedev.com - */ - -/dts-v1/; -#include "rk3308.dtsi" - -/ { - model = "Radxa ROCK Pi S"; - compatible = "radxa,rockpis", "rockchip,rk3308"; - - aliases { - ethernet0 = &gmac; - mmc0 = &emmc; - mmc1 = &sdmmc; - }; - - chosen { - stdout-path = "serial0:1500000n8"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&green_led_gio>, <&heartbeat_led_gpio>; - - green-led { - default-state = "on"; - gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; - label = "rockpis:green:power"; - linux,default-trigger = "default-on"; - }; - - blue-led { - default-state = "on"; - gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; - label = "rockpis:blue:user"; - linux,default-trigger = "heartbeat"; - }; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - pinctrl-0 = <&wifi_enable_h>; - pinctrl-names = "default"; - reset-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; - }; - - vcc_1v8: vcc-1v8 { - compatible = "regulator-fixed"; - regulator-name = "vcc_1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_io>; - }; - - vcc_io: vcc-io { - compatible = "regulator-fixed"; - regulator-name = "vcc_io"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc5v0_sys>; - }; - - vcc_ddr: vcc-ddr { - compatible = "regulator-fixed"; - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - vin-supply = <&vcc5v0_sys>; - }; - - vcc5v0_otg: vcc5v0-otg { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&otg_vbus_drv>; - regulator-name = "vcc5v0_otg"; - regulator-always-on; - vin-supply = <&vcc5v0_sys>; - }; - - vcc5v0_sys: vcc5v0-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - vdd_core: vdd-core { - compatible = "pwm-regulator"; - pwms = <&pwm0 0 5000 1>; - pwm-supply = <&vcc5v0_sys>; - regulator-name = "vdd_core"; - regulator-min-microvolt = <827000>; - regulator-max-microvolt = <1340000>; - regulator-settling-time-up-us = <250>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_log: vdd-log { - compatible = "regulator-fixed"; - regulator-name = "vdd_log"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - vin-supply = <&vcc5v0_sys>; - }; -}; - -&cpu0 { - cpu-supply = <&vdd_core>; -}; - -&emmc { - bus-width = <4>; - cap-mmc-highspeed; - mmc-hs200-1_8v; - non-removable; - vmmc-supply = <&vcc_io>; - status = "okay"; -}; - -&gmac { - clock_in_out = "output"; - phy-supply = <&vcc_io>; - snps,reset-gpio = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 50000 50000>; - status = "okay"; -}; - -&gpio0 { - gpio-line-names = - /* GPIO0_A0 - A7 */ - "", "", "", "", "", "", "", "", - /* GPIO0_B0 - B7 */ - "", "", "", "header1-pin3 [GPIO0_B3]", - "header1-pin5 [GPIO0_B4]", "", "", - "header1-pin11 [GPIO0_B7]", - /* GPIO0_C0 - C7 */ - "header1-pin13 [GPIO0_C0]", - "header1-pin15 [GPIO0_C1]", "", "", "", - "", "", "", - /* GPIO0_D0 - D7 */ - "", "", "", "", "", "", "", ""; -}; - -&gpio1 { - gpio-line-names = - /* GPIO1_A0 - A7 */ - "", "", "", "", "", "", "", "", - /* GPIO1_B0 - B7 */ - "", "", "", "", "", "", "", "", - /* GPIO1_C0 - C7 */ - "", "", "", "", "", "", "header1-pin21 [GPIO1_C6]", - "header1-pin19 [GPIO1_C7]", - /* GPIO1_D0 - D7 */ - "header1-pin23 [GPIO1_D0]", "header1-pin24 [GPIO1_D1]", - "", "", "", "", "", ""; -}; - -&gpio2 { - gpio-line-names = - /* GPIO2_A0 - A7 */ - "header1-pin10 [GPIO2_A0]", "header1-pin8 [GPIO2_A1]", - "", "", - "header1-pin7 [GPIO2_A4]", "header1-pin12 [GPIO2_A5]", - "header2-pin46 [GPIO2_A6]", "header1-pin22 [GPIO1_A7]", - /* GPIO2_B0 - B7 */ - "header2-pin45 [GPIO2_B0]", "header1-pin18 [GPIO2_B1]", - "header1-pin16 [GPIO2_B2]", "header2-pin44 [GPIO2_B3]", - "header2-pin43 [GPIO2_B4]", "header2-pin28 [GPIO2_B5]", - "header2-pin30 [GPIO2_B6]", "header2-pin32 [GPIO2_B7]", - /* GPIO2_C0 - C7 */ - "header2-pin34 [GPIO2_C0]", "", "", "", "", "", "", "", - /* GPIO2_D0 - D7 */ - "", "", "", "", "", "", "", ""; -}; - -&gpio3 { - gpio-line-names = - /* GPIO3_A0 - A7 */ - "", "", "", "", "", "", "", "", - /* GPIO3_B0 - B7 */ - "", "", "header2-pin42 [GPIO3_B2]", - "header2-pin41 [GPIO3_B3]", "header2-pin40 [GPIO3_B4]", - "header2-pin39 [GPIO3_B5]", "", "", - /* GPIO3_C0 - C7 */ - "", "", "", "", "", "", "", "", - /* GPIO3_D0 - D7 */ - "", "", "", "", "", "", "", ""; -}; - -&i2c1 { - status = "okay"; -}; - -&pinctrl { - pinctrl-names = "default"; - pinctrl-0 = <&rtc_32k>; - - leds { - green_led_gio: green-led-gpio { - rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - heartbeat_led_gpio: heartbeat-led-gpio { - rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb { - otg_vbus_drv: otg-vbus-drv { - rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - sdio-pwrseq { - wifi_enable_h: wifi-enable-h { - rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - wifi_host_wake: wifi-host-wake { - rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; -}; - -&pwm0 { - status = "okay"; - pinctrl-0 = <&pwm0_pin_pull_down>; -}; - -&saradc { - vref-supply = <&vcc_1v8>; - status = "okay"; -}; - -&sdio { - #address-cells = <1>; - #size-cells = <0>; - cap-sd-highspeed; - cap-sdio-irq; - keep-power-in-suspend; - max-frequency = <1000000>; - mmc-pwrseq = <&sdio_pwrseq>; - non-removable; - sd-uhs-sdr104; - status = "okay"; -}; - -&sdmmc { - cap-sd-highspeed; - status = "okay"; -}; - -&u2phy { - status = "okay"; - - u2phy_host: host-port { - phy-supply = <&vcc5v0_otg>; - status = "okay"; - }; - - u2phy_otg: otg-port { - phy-supply = <&vcc5v0_otg>; - status = "okay"; - }; -}; - -&uart0 { - status = "okay"; -}; - -&uart4 { - status = "okay"; - - bluetooth { - compatible = "realtek,rtl8723bs-bt"; - device-wake-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>; - host-wake-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; - }; -}; - -&usb_host_ehci { - status = "okay"; -}; - -&usb_host_ohci { - status = "okay"; -}; - -&usb20_otg { - dr_mode = "peripheral"; - status = "okay"; -}; - -&wdt { - status = "okay"; -}; diff --git a/arch/arm/dts/rk3308.dtsi b/arch/arm/dts/rk3308.dtsi deleted file mode 100644 index cfc0a87b5195..000000000000 --- a/arch/arm/dts/rk3308.dtsi +++ /dev/null @@ -1,1888 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd - * - */ - -#include <dt-bindings/clock/rk3308-cru.h> -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/pinctrl/rockchip.h> -#include <dt-bindings/soc/rockchip,boot-mode.h> -#include <dt-bindings/thermal/thermal.h> - -/ { - compatible = "rockchip,rk3308"; - - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - gpio0 = &gpio0; - gpio1 = &gpio1; - gpio2 = &gpio2; - gpio3 = &gpio3; - gpio4 = &gpio4; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - serial4 = &uart4; - spi0 = &spi0; - spi1 = &spi1; - spi2 = &spi2; - }; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a35"; - reg = <0x0 0x0>; - enable-method = "psci"; - clocks = <&cru ARMCLK>; - #cooling-cells = <2>; - dynamic-power-coefficient = <90>; - operating-points-v2 = <&cpu0_opp_table>; - cpu-idle-states = <&CPU_SLEEP>; - next-level-cache = <&l2>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a35"; - reg = <0x0 0x1>; - enable-method = "psci"; - operating-points-v2 = <&cpu0_opp_table>; - cpu-idle-states = <&CPU_SLEEP>; - next-level-cache = <&l2>; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a35"; - reg = <0x0 0x2>; - enable-method = "psci"; - operating-points-v2 = <&cpu0_opp_table>; - cpu-idle-states = <&CPU_SLEEP>; - next-level-cache = <&l2>; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a35"; - reg = <0x0 0x3>; - enable-method = "psci"; - operating-points-v2 = <&cpu0_opp_table>; - cpu-idle-states = <&CPU_SLEEP>; - next-level-cache = <&l2>; - }; - - idle-states { - entry-method = "psci"; - - CPU_SLEEP: cpu-sleep { - compatible = "arm,idle-state"; - local-timer-stop; - arm,psci-suspend-param = <0x0010000>; - entry-latency-us = <120>; - exit-latency-us = <250>; - min-residency-us = <900>; - }; - }; - - l2: l2-cache { - compatible = "cache"; - cache-level = <2>; - cache-unified; - }; - }; - - cpu0_opp_table: opp-table-0 { - compatible = "operating-points-v2"; - opp-shared; - - opp-408000000 { - opp-hz = /bits/ 64 <408000000>; - opp-microvolt = <950000 950000 1340000>; - clock-latency-ns = <40000>; - opp-suspend; - }; - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <950000 950000 1340000>; - clock-latency-ns = <40000>; - }; - opp-816000000 { - opp-hz = /bits/ 64 <816000000>; - opp-microvolt = <1025000 1025000 1340000>; - clock-latency-ns = <40000>; - }; - opp-1008000000 { - opp-hz = /bits/ 64 <1008000000>; - opp-microvolt = <1125000 1125000 1340000>; - clock-latency-ns = <40000>; - }; - }; - - arm-pmu { - compatible = "arm,cortex-a35-pmu"; - interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; - }; - - mac_clkin: external-mac-clock { - compatible = "fixed-clock"; - clock-frequency = <50000000>; - clock-output-names = "mac_clkin"; - #clock-cells = <0>; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, - <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, - <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, - <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; - }; - - xin24m: xin24m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "xin24m"; - }; - - grf: grf@ff000000 { - compatible = "rockchip,rk3308-grf", "syscon", "simple-mfd"; - reg = <0x0 0xff000000 0x0 0x08000>; - - reboot-mode { - compatible = "syscon-reboot-mode"; - offset = <0x500>; - mode-bootloader = <BOOT_BL_DOWNLOAD>; - mode-loader = <BOOT_BL_DOWNLOAD>; - mode-normal = <BOOT_NORMAL>; - mode-recovery = <BOOT_RECOVERY>; - mode-fastboot = <BOOT_FASTBOOT>; - }; - }; - - usb2phy_grf: syscon@ff008000 { - compatible = "rockchip,rk3308-usb2phy-grf", "syscon", "simple-mfd"; - reg = <0x0 0xff008000 0x0 0x4000>; - #address-cells = <1>; - #size-cells = <1>; - - u2phy: usb2phy@100 { - compatible = "rockchip,rk3308-usb2phy"; - reg = <0x100 0x10>; - assigned-clocks = <&cru USB480M>; - assigned-clock-parents = <&u2phy>; - clocks = <&cru SCLK_USBPHY_REF>; - clock-names = "phyclk"; - clock-output-names = "usb480m_phy"; - #clock-cells = <0>; - status = "disabled"; - - u2phy_otg: otg-port { - interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "otg-bvalid", "otg-id", - "linestate"; - #phy-cells = <0>; - status = "disabled"; - }; - - u2phy_host: host-port { - interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "linestate"; - #phy-cells = <0>; - status = "disabled"; - }; - }; - }; - - detect_grf: syscon@ff00b000 { - compatible = "rockchip,rk3308-detect-grf", "syscon", "simple-mfd"; - reg = <0x0 0xff00b000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - }; - - core_grf: syscon@ff00c000 { - compatible = "rockchip,rk3308-core-grf", "syscon", "simple-mfd"; - reg = <0x0 0xff00c000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - }; - - i2c0: i2c@ff040000 { - compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xff040000 0x0 0x1000>; - clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>; - clock-names = "i2c", "pclk"; - interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_xfer>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c1: i2c@ff050000 { - compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xff050000 0x0 0x1000>; - clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; - clock-names = "i2c", "pclk"; - interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_xfer>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@ff060000 { - compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xff060000 0x0 0x1000>; - clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; - clock-names = "i2c", "pclk"; - interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_xfer>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c3: i2c@ff070000 { - compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xff070000 0x0 0x1000>; - clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; - clock-names = "i2c", "pclk"; - interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3m0_xfer>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - wdt: watchdog@ff080000 { - compatible = "rockchip,rk3308-wdt", "snps,dw-wdt"; - reg = <0x0 0xff080000 0x0 0x100>; - clocks = <&cru PCLK_WDT>; - interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - uart0: serial@ff0a0000 { - compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; - reg = <0x0 0xff0a0000 0x0 0x100>; - interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; - clock-names = "baudclk", "apb_pclk"; - reg-shift = <2>; - reg-io-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; - status = "disabled"; - }; - - uart1: serial@ff0b0000 { - compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; - reg = <0x0 0xff0b0000 0x0 0x100>; - interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; - clock-names = "baudclk", "apb_pclk"; - reg-shift = <2>; - reg-io-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>; - status = "disabled"; - }; - - uart2: serial@ff0c0000 { - compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; - reg = <0x0 0xff0c0000 0x0 0x100>; - interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; - clock-names = "baudclk", "apb_pclk"; - reg-shift = <2>; - reg-io-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&uart2m0_xfer>; - status = "disabled"; - }; - - uart3: serial@ff0d0000 { - compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; - reg = <0x0 0xff0d0000 0x0 0x100>; - interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; - clock-names = "baudclk", "apb_pclk"; - reg-shift = <2>; - reg-io-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&uart3_xfer>; - status = "disabled"; - }; - - uart4: serial@ff0e0000 { - compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; - reg = <0x0 0xff0e0000 0x0 0x100>; - interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; - clock-names = "baudclk", "apb_pclk"; - reg-shift = <2>; - reg-io-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>; - status = "disabled"; - }; - - spi0: spi@ff120000 { - compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi"; - reg = <0x0 0xff120000 0x0 0x1000>; - interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; - clock-names = "spiclk", "apb_pclk"; - dmas = <&dmac0 0>, <&dmac0 1>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_clk &spi0_csn0 &spi0_miso &spi0_mosi>; - status = "disabled"; - }; - - spi1: spi@ff130000 { - compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi"; - reg = <0x0 0xff130000 0x0 0x1000>; - interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; - clock-names = "spiclk", "apb_pclk"; - dmas = <&dmac0 2>, <&dmac0 3>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_miso &spi1_mosi>; - status = "disabled"; - }; - - spi2: spi@ff140000 { - compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi"; - reg = <0x0 0xff140000 0x0 0x1000>; - interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; - clock-names = "spiclk", "apb_pclk"; - dmas = <&dmac1 16>, <&dmac1 17>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&spi2_clk &spi2_csn0 &spi2_miso &spi2_mosi>; - status = "disabled"; - }; - - pwm8: pwm@ff160000 { - compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xff160000 0x0 0x10>; - clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; - clock-names = "pwm", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm8_pin>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm9: pwm@ff160010 { - compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xff160010 0x0 0x10>; - clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; - clock-names = "pwm", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm9_pin>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm10: pwm@ff160020 { - compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xff160020 0x0 0x10>; - clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; - clock-names = "pwm", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm10_pin>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm11: pwm@ff160030 { - compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xff160030 0x0 0x10>; - clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; - clock-names = "pwm", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm11_pin>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm4: pwm@ff170000 { - compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xff170000 0x0 0x10>; - clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; - clock-names = "pwm", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm4_pin>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm5: pwm@ff170010 { - compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xff170010 0x0 0x10>; - clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; - clock-names = "pwm", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm5_pin>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm6: pwm@ff170020 { - compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xff170020 0x0 0x10>; - clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; - clock-names = "pwm", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm6_pin>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm7: pwm@ff170030 { - compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xff170030 0x0 0x10>; - clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; - clock-names = "pwm", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm7_pin>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm0: pwm@ff180000 { - compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xff180000 0x0 0x10>; - clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; - clock-names = "pwm", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pin>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm1: pwm@ff180010 { - compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xff180010 0x0 0x10>; - clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; - clock-names = "pwm", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm1_pin>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm2: pwm@ff180020 { - compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xff180020 0x0 0x10>; - clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; - clock-names = "pwm", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm2_pin>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm3: pwm@ff180030 { - compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xff180030 0x0 0x10>; - clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; - clock-names = "pwm", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm3_pin>; - #pwm-cells = <3>; - status = "disabled"; - }; - - rktimer: rktimer@ff1a0000 { - compatible = "rockchip,rk3288-timer"; - reg = <0x0 0xff1a0000 0x0 0x20>; - interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>; - clock-names = "pclk", "timer"; - }; - - saradc: saradc@ff1e0000 { - compatible = "rockchip,rk3308-saradc", "rockchip,rk3399-saradc"; - reg = <0x0 0xff1e0000 0x0 0x100>; - interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; - clock-names = "saradc", "apb_pclk"; - #io-channel-cells = <1>; - resets = <&cru SRST_SARADC_P>; - reset-names = "saradc-apb"; - status = "disabled"; - }; - - dmac0: dma-controller@ff2c0000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x0 0xff2c0000 0x0 0x4000>; - interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; - arm,pl330-periph-burst; - clocks = <&cru ACLK_DMAC0>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - }; - - dmac1: dma-controller@ff2d0000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x0 0xff2d0000 0x0 0x4000>; - interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; - arm,pl330-periph-burst; - clocks = <&cru ACLK_DMAC1>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - }; - - i2s_2ch_0: i2s@ff350000 { - compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s"; - reg = <0x0 0xff350000 0x0 0x1000>; - interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru SCLK_I2S0_2CH>, <&cru HCLK_I2S0_2CH>; - clock-names = "i2s_clk", "i2s_hclk"; - dmas = <&dmac1 8>, <&dmac1 9>; - dma-names = "tx", "rx"; - resets = <&cru SRST_I2S0_2CH_M>, <&cru SRST_I2S0_2CH_H>; - reset-names = "reset-m", "reset-h"; - pinctrl-names = "default"; - pinctrl-0 = <&i2s_2ch_0_sclk - &i2s_2ch_0_lrck - &i2s_2ch_0_sdi - &i2s_2ch_0_sdo>; - status = "disabled"; - }; - - i2s_2ch_1: i2s@ff360000 { - compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s"; - reg = <0x0 0xff360000 0x0 0x1000>; - interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru SCLK_I2S1_2CH>, <&cru HCLK_I2S1_2CH>; - clock-names = "i2s_clk", "i2s_hclk"; - dmas = <&dmac1 11>; - dma-names = "rx"; - resets = <&cru SRST_I2S1_2CH_M>, <&cru SRST_I2S1_2CH_H>; - reset-names = "reset-m", "reset-h"; - status = "disabled"; - }; - - spdif_tx: spdif-tx@ff3a0000 { - compatible = "rockchip,rk3308-spdif", "rockchip,rk3066-spdif"; - reg = <0x0 0xff3a0000 0x0 0x1000>; - interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru SCLK_SPDIF_TX>, <&cru HCLK_SPDIFTX>; - clock-names = "mclk", "hclk"; - dmas = <&dmac1 13>; - dma-names = "tx"; - pinctrl-names = "default"; - pinctrl-0 = <&spdif_out>; - status = "disabled"; - }; - - usb20_otg: usb@ff400000 { - compatible = "rockchip,rk3308-usb", "rockchip,rk3066-usb", - "snps,dwc2"; - reg = <0x0 0xff400000 0x0 0x40000>; - interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru HCLK_OTG>; - clock-names = "otg"; - dr_mode = "otg"; - g-np-tx-fifo-size = <16>; - g-rx-fifo-size = <280>; - g-tx-fifo-size = <256 128 128 64 32 16>; - phys = <&u2phy_otg>; - phy-names = "usb2-phy"; - status = "disabled"; - }; - - usb_host_ehci: usb@ff440000 { - compatible = "generic-ehci"; - reg = <0x0 0xff440000 0x0 0x10000>; - interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, <&u2phy>; - phys = <&u2phy_host>; - phy-names = "usb"; - status = "disabled"; - }; - - usb_host_ohci: usb@ff450000 { - compatible = "generic-ohci"; - reg = <0x0 0xff450000 0x0 0x10000>; - interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, <&u2phy>; - phys = <&u2phy_host>; - phy-names = "usb"; - status = "disabled"; - }; - - sdmmc: mmc@ff480000 { - compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x0 0xff480000 0x0 0x4000>; - interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; - bus-width = <4>; - clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, - <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - max-frequency = <150000000>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; - status = "disabled"; - }; - - emmc: mmc@ff490000 { - compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x0 0xff490000 0x0 0x4000>; - interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; - bus-width = <8>; - clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, - <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - max-frequency = <150000000>; - status = "disabled"; - }; - - sdio: mmc@ff4a0000 { - compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x0 0xff4a0000 0x0 0x4000>; - interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; - bus-width = <4>; - clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, - <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - max-frequency = <150000000>; - pinctrl-names = "default"; - pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>; - status = "disabled"; - }; - - nfc: nand-controller@ff4b0000 { - compatible = "rockchip,rk3308-nfc", - "rockchip,rv1108-nfc"; - reg = <0x0 0xff4b0000 0x0 0x4000>; - interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>; - clock-names = "ahb", "nfc"; - assigned-clocks = <&cru SCLK_NANDC>; - assigned-clock-rates = <150000000>; - pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_csn0 - &flash_rdn &flash_rdy &flash_wrn>; - pinctrl-names = "default"; - status = "disabled"; - }; - - gmac: ethernet@ff4e0000 { - compatible = "rockchip,rk3308-gmac"; - reg = <0x0 0xff4e0000 0x0 0x10000>; - interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "macirq"; - clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX_TX>, - <&cru SCLK_MAC_RX_TX>, <&cru SCLK_MAC_REF>, - <&cru SCLK_MAC>, <&cru ACLK_MAC>, - <&cru PCLK_MAC>, <&cru SCLK_MAC_RMII>; - clock-names = "stmmaceth", "mac_clk_rx", - "mac_clk_tx", "clk_mac_ref", - "clk_mac_refout", "aclk_mac", - "pclk_mac", "clk_mac_speed"; - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&rmii_pins &mac_refclk_12ma>; - resets = <&cru SRST_MAC_A>; - reset-names = "stmmaceth"; - rockchip,grf = <&grf>; - status = "disabled"; - }; - - sfc: spi@ff4c0000 { - compatible = "rockchip,sfc"; - reg = <0x0 0xff4c0000 0x0 0x4000>; - interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; - clock-names = "clk_sfc", "hclk_sfc"; - pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>; - pinctrl-names = "default"; - status = "disabled"; - }; - - cru: clock-controller@ff500000 { - compatible = "rockchip,rk3308-cru"; - reg = <0x0 0xff500000 0x0 0x1000>; - clocks = <&xin24m>; - clock-names = "xin24m"; - rockchip,grf = <&grf>; - #clock-cells = <1>; - #reset-cells = <1>; - assigned-clocks = <&cru SCLK_RTC32K>; - assigned-clock-rates = <32768>; - }; - - gic: interrupt-controller@ff580000 { - compatible = "arm,gic-400"; - reg = <0x0 0xff581000 0x0 0x1000>, - <0x0 0xff582000 0x0 0x2000>, - <0x0 0xff584000 0x0 0x2000>, - <0x0 0xff586000 0x0 0x2000>; - interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; - #interrupt-cells = <3>; - interrupt-controller; - #address-cells = <0>; - }; - - sram: sram@fff80000 { - compatible = "mmio-sram"; - reg = <0x0 0xfff80000 0x0 0x40000>; - ranges = <0 0x0 0xfff80000 0x40000>; - #address-cells = <1>; - #size-cells = <1>; - - /* reserved for ddr dvfs and system suspend/resume */ - ddr-sram@0 { - reg = <0x0 0x8000>; - }; - - /* reserved for vad audio buffer */ - vad_sram: vad-sram@8000 { - reg = <0x8000 0x38000>; - }; - }; - - pinctrl: pinctrl { - compatible = "rockchip,rk3308-pinctrl"; - rockchip,grf = <&grf>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - gpio0: gpio@ff220000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff220000 0x0 0x100>; - interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_GPIO0>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio@ff230000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff230000 0x0 0x100>; - interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_GPIO1>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@ff240000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff240000 0x0 0x100>; - interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_GPIO2>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio@ff250000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff250000 0x0 0x100>; - interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_GPIO3>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio4: gpio@ff260000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff260000 0x0 0x100>; - interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_GPIO4>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - pcfg_pull_up: pcfg-pull-up { - bias-pull-up; - }; - - pcfg_pull_down: pcfg-pull-down { - bias-pull-down; - }; - - pcfg_pull_none: pcfg-pull-none { - bias-disable; - }; - - pcfg_pull_none_2ma: pcfg-pull-none-2ma { - bias-disable; - drive-strength = <2>; - }; - - pcfg_pull_up_2ma: pcfg-pull-up-2ma { - bias-pull-up; - drive-strength = <2>; - }; - - pcfg_pull_up_4ma: pcfg-pull-up-4ma { - bias-pull-up; - drive-strength = <4>; - }; - - pcfg_pull_none_4ma: pcfg-pull-none-4ma { - bias-disable; - drive-strength = <4>; - }; - - pcfg_pull_down_4ma: pcfg-pull-down-4ma { - bias-pull-down; - drive-strength = <4>; - }; - - pcfg_pull_none_8ma: pcfg-pull-none-8ma { - bias-disable; - drive-strength = <8>; - }; - - pcfg_pull_up_8ma: pcfg-pull-up-8ma { - bias-pull-up; - drive-strength = <8>; - }; - - pcfg_pull_none_12ma: pcfg-pull-none-12ma { - bias-disable; - drive-strength = <12>; - }; - - pcfg_pull_up_12ma: pcfg-pull-up-12ma { - bias-pull-up; - drive-strength = <12>; - }; - - pcfg_pull_none_smt: pcfg-pull-none-smt { - bias-disable; - input-schmitt-enable; - }; - - pcfg_output_high: pcfg-output-high { - output-high; - }; - - pcfg_output_low: pcfg-output-low { - output-low; - }; - - pcfg_input_high: pcfg-input-high { - bias-pull-up; - input-enable; - }; - - pcfg_input: pcfg-input { - input-enable; - }; - - emmc { - emmc_clk: emmc-clk { - rockchip,pins = - <3 RK_PB1 2 &pcfg_pull_none_8ma>; - }; - - emmc_cmd: emmc-cmd { - rockchip,pins = - <3 RK_PB0 2 &pcfg_pull_up_8ma>; - }; - - emmc_pwren: emmc-pwren { - rockchip,pins = - <3 RK_PB3 2 &pcfg_pull_none>; - }; - - emmc_rstn: emmc-rstn { - rockchip,pins = - <3 RK_PB2 2 &pcfg_pull_none>; - }; - - emmc_bus1: emmc-bus1 { - rockchip,pins = - <3 RK_PA0 2 &pcfg_pull_up_8ma>; - }; - - emmc_bus4: emmc-bus4 { - rockchip,pins = - <3 RK_PA0 2 &pcfg_pull_up_8ma>, - <3 RK_PA1 2 &pcfg_pull_up_8ma>, - <3 RK_PA2 2 &pcfg_pull_up_8ma>, - <3 RK_PA3 2 &pcfg_pull_up_8ma>; - }; - - emmc_bus8: emmc-bus8 { - rockchip,pins = - <3 RK_PA0 2 &pcfg_pull_up_8ma>, - <3 RK_PA1 2 &pcfg_pull_up_8ma>, - <3 RK_PA2 2 &pcfg_pull_up_8ma>, - <3 RK_PA3 2 &pcfg_pull_up_8ma>, - <3 RK_PA4 2 &pcfg_pull_up_8ma>, - <3 RK_PA5 2 &pcfg_pull_up_8ma>, - <3 RK_PA6 2 &pcfg_pull_up_8ma>, - <3 RK_PA7 2 &pcfg_pull_up_8ma>; - }; - }; - - flash { - flash_csn0: flash-csn0 { - rockchip,pins = - <3 RK_PB5 1 &pcfg_pull_none>; - }; - - flash_rdy: flash-rdy { - rockchip,pins = - <3 RK_PB4 1 &pcfg_pull_none>; - }; - - flash_ale: flash-ale { - rockchip,pins = - <3 RK_PB3 1 &pcfg_pull_none>; - }; - - flash_cle: flash-cle { - rockchip,pins = - <3 RK_PB1 1 &pcfg_pull_none>; - }; - - flash_wrn: flash-wrn { - rockchip,pins = - <3 RK_PB0 1 &pcfg_pull_none>; - }; - - flash_rdn: flash-rdn { - rockchip,pins = - <3 RK_PB2 1 &pcfg_pull_none>; - }; - - flash_bus8: flash-bus8 { - rockchip,pins = - <3 RK_PA0 1 &pcfg_pull_up_12ma>, - <3 RK_PA1 1 &pcfg_pull_up_12ma>, - <3 RK_PA2 1 &pcfg_pull_up_12ma>, - <3 RK_PA3 1 &pcfg_pull_up_12ma>, - <3 RK_PA4 1 &pcfg_pull_up_12ma>, - <3 RK_PA5 1 &pcfg_pull_up_12ma>, - <3 RK_PA6 1 &pcfg_pull_up_12ma>, - <3 RK_PA7 1 &pcfg_pull_up_12ma>; - }; - }; - - sfc { - sfc_bus4: sfc-bus4 { - rockchip,pins = - <3 RK_PA0 3 &pcfg_pull_none>, - <3 RK_PA1 3 &pcfg_pull_none>, - <3 RK_PA2 3 &pcfg_pull_none>, - <3 RK_PA3 3 &pcfg_pull_none>; - }; - - sfc_bus2: sfc-bus2 { - rockchip,pins = - <3 RK_PA0 3 &pcfg_pull_none>, - <3 RK_PA1 3 &pcfg_pull_none>; - }; - - sfc_cs0: sfc-cs0 { - rockchip,pins = - <3 RK_PA4 3 &pcfg_pull_none>; - }; - - sfc_clk: sfc-clk { - rockchip,pins = - <3 RK_PA5 3 &pcfg_pull_none>; - }; - }; - - gmac { - rmii_pins: rmii-pins { - rockchip,pins = - /* mac_txen */ - <1 RK_PC1 3 &pcfg_pull_none_12ma>, - /* mac_txd1 */ - <1 RK_PC3 3 &pcfg_pull_none_12ma>, - /* mac_txd0 */ - <1 RK_PC2 3 &pcfg_pull_none_12ma>, - /* mac_rxd0 */ - <1 RK_PC4 3 &pcfg_pull_none>, - /* mac_rxd1 */ - <1 RK_PC5 3 &pcfg_pull_none>, - /* mac_rxer */ - <1 RK_PB7 3 &pcfg_pull_none>, - /* mac_rxdv */ - <1 RK_PC0 3 &pcfg_pull_none>, - /* mac_mdio */ - <1 RK_PB6 3 &pcfg_pull_none>, - /* mac_mdc */ - <1 RK_PB5 3 &pcfg_pull_none>; - }; - - mac_refclk_12ma: mac-refclk-12ma { - rockchip,pins = - <1 RK_PB4 3 &pcfg_pull_none_12ma>; - }; - - mac_refclk: mac-refclk { - rockchip,pins = - <1 RK_PB4 3 &pcfg_pull_none>; - }; - }; - - gmac-m1 { - rmiim1_pins: rmiim1-pins { - rockchip,pins = - /* mac_txen */ - <4 RK_PB7 2 &pcfg_pull_none_12ma>, - /* mac_txd1 */ - <4 RK_PA5 2 &pcfg_pull_none_12ma>, - /* mac_txd0 */ - <4 RK_PA4 2 &pcfg_pull_none_12ma>, - /* mac_rxd0 */ - <4 RK_PA2 2 &pcfg_pull_none>, - /* mac_rxd1 */ - <4 RK_PA3 2 &pcfg_pull_none>, - /* mac_rxer */ - <4 RK_PA0 2 &pcfg_pull_none>, - /* mac_rxdv */ - <4 RK_PA1 2 &pcfg_pull_none>, - /* mac_mdio */ - <4 RK_PB6 2 &pcfg_pull_none>, - /* mac_mdc */ - <4 RK_PB5 2 &pcfg_pull_none>; - }; - - macm1_refclk_12ma: macm1-refclk-12ma { - rockchip,pins = - <4 RK_PB4 2 &pcfg_pull_none_12ma>; - }; - - macm1_refclk: macm1-refclk { - rockchip,pins = - <4 RK_PB4 2 &pcfg_pull_none>; - }; - }; - - i2c0 { - i2c0_xfer: i2c0-xfer { - rockchip,pins = - <1 RK_PD0 2 &pcfg_pull_none_smt>, - <1 RK_PD1 2 &pcfg_pull_none_smt>; - }; - }; - - i2c1 { - i2c1_xfer: i2c1-xfer { - rockchip,pins = - <0 RK_PB3 1 &pcfg_pull_none_smt>, - <0 RK_PB4 1 &pcfg_pull_none_smt>; - }; - }; - - i2c2 { - i2c2_xfer: i2c2-xfer { - rockchip,pins = - <2 RK_PA2 3 &pcfg_pull_none_smt>, - <2 RK_PA3 3 &pcfg_pull_none_smt>; - }; - }; - - i2c3-m0 { - i2c3m0_xfer: i2c3m0-xfer { - rockchip,pins = - <0 RK_PB7 2 &pcfg_pull_none_smt>, - <0 RK_PC0 2 &pcfg_pull_none_smt>; - }; - }; - - i2c3-m1 { - i2c3m1_xfer: i2c3m1-xfer { - rockchip,pins = - <3 RK_PB4 2 &pcfg_pull_none_smt>, - <3 RK_PB5 2 &pcfg_pull_none_smt>; - }; - }; - - i2c3-m2 { - i2c3m2_xfer: i2c3m2-xfer { - rockchip,pins = - <2 RK_PA1 3 &pcfg_pull_none_smt>, - <2 RK_PA0 3 &pcfg_pull_none_smt>; - }; - }; - - i2s_2ch_0 { - i2s_2ch_0_mclk: i2s-2ch-0-mclk { - rockchip,pins = - <4 RK_PB4 1 &pcfg_pull_none>; - }; - - i2s_2ch_0_sclk: i2s-2ch-0-sclk { - rockchip,pins = - <4 RK_PB5 1 &pcfg_pull_none>; - }; - - i2s_2ch_0_lrck: i2s-2ch-0-lrck { - rockchip,pins = - <4 RK_PB6 1 &pcfg_pull_none>; - }; - - i2s_2ch_0_sdo: i2s-2ch-0-sdo { - rockchip,pins = - <4 RK_PB7 1 &pcfg_pull_none>; - }; - - i2s_2ch_0_sdi: i2s-2ch-0-sdi { - rockchip,pins = - <4 RK_PC0 1 &pcfg_pull_none>; - }; - }; - - i2s_8ch_0 { - i2s_8ch_0_mclk: i2s-8ch-0-mclk { - rockchip,pins = - <2 RK_PA4 1 &pcfg_pull_none>; - }; - - i2s_8ch_0_sclktx: i2s-8ch-0-sclktx { - rockchip,pins = - <2 RK_PA5 1 &pcfg_pull_none>; - }; - - i2s_8ch_0_sclkrx: i2s-8ch-0-sclkrx { - rockchip,pins = - <2 RK_PA6 1 &pcfg_pull_none>; - }; - - i2s_8ch_0_lrcktx: i2s-8ch-0-lrcktx { - rockchip,pins = - <2 RK_PA7 1 &pcfg_pull_none>; - }; - - i2s_8ch_0_lrckrx: i2s-8ch-0-lrckrx { - rockchip,pins = - <2 RK_PB0 1 &pcfg_pull_none>; - }; - - i2s_8ch_0_sdo0: i2s-8ch-0-sdo0 { - rockchip,pins = - <2 RK_PB1 1 &pcfg_pull_none>; - }; - - i2s_8ch_0_sdo1: i2s-8ch-0-sdo1 { - rockchip,pins = - <2 RK_PB2 1 &pcfg_pull_none>; - }; - - i2s_8ch_0_sdo2: i2s-8ch-0-sdo2 { - rockchip,pins = - <2 RK_PB3 1 &pcfg_pull_none>; - }; - - i2s_8ch_0_sdo3: i2s-8ch-0-sdo3 { - rockchip,pins = - <2 RK_PB4 1 &pcfg_pull_none>; - }; - - i2s_8ch_0_sdi0: i2s-8ch-0-sdi0 { - rockchip,pins = - <2 RK_PB5 1 &pcfg_pull_none>; - }; - - i2s_8ch_0_sdi1: i2s-8ch-0-sdi1 { - rockchip,pins = - <2 RK_PB6 1 &pcfg_pull_none>; - }; - - i2s_8ch_0_sdi2: i2s-8ch-0-sdi2 { - rockchip,pins = - <2 RK_PB7 1 &pcfg_pull_none>; - }; - - i2s_8ch_0_sdi3: i2s-8ch-0-sdi3 { - rockchip,pins = - <2 RK_PC0 1 &pcfg_pull_none>; - }; - }; - - i2s_8ch_1_m0 { - i2s_8ch_1_m0_mclk: i2s-8ch-1-m0-mclk { - rockchip,pins = - <1 RK_PA2 2 &pcfg_pull_none>; - }; - - i2s_8ch_1_m0_sclktx: i2s-8ch-1-m0-sclktx { - rockchip,pins = - <1 RK_PA3 2 &pcfg_pull_none>; - }; - - i2s_8ch_1_m0_sclkrx: i2s-8ch-1-m0-sclkrx { - rockchip,pins = - <1 RK_PA4 2 &pcfg_pull_none>; - }; - - i2s_8ch_1_m0_lrcktx: i2s-8ch-1-m0-lrcktx { - rockchip,pins = - <1 RK_PA5 2 &pcfg_pull_none>; - }; - - i2s_8ch_1_m0_lrckrx: i2s-8ch-1-m0-lrckrx { - rockchip,pins = - <1 RK_PA6 2 &pcfg_pull_none>; - }; - - i2s_8ch_1_m0_sdo0: i2s-8ch-1-m0-sdo0 { - rockchip,pins = - <1 RK_PA7 2 &pcfg_pull_none>; - }; - - i2s_8ch_1_m0_sdo1_sdi3: i2s-8ch-1-m0-sdo1-sdi3 { - rockchip,pins = - <1 RK_PB0 2 &pcfg_pull_none>; - }; - - i2s_8ch_1_m0_sdo2_sdi2: i2s-8ch-1-m0-sdo2-sdi2 { - rockchip,pins = - <1 RK_PB1 2 &pcfg_pull_none>; - }; - - i2s_8ch_1_m0_sdo3_sdi1: i2s-8ch-1-m0-sdo3_sdi1 { - rockchip,pins = - <1 RK_PB2 2 &pcfg_pull_none>; - }; - - i2s_8ch_1_m0_sdi0: i2s-8ch-1-m0-sdi0 { - rockchip,pins = - <1 RK_PB3 2 &pcfg_pull_none>; - }; - }; - - i2s_8ch_1_m1 { - i2s_8ch_1_m1_mclk: i2s-8ch-1-m1-mclk { - rockchip,pins = - <1 RK_PB4 2 &pcfg_pull_none>; - }; - - i2s_8ch_1_m1_sclktx: i2s-8ch-1-m1-sclktx { - rockchip,pins = - <1 RK_PB5 2 &pcfg_pull_none>; - }; - - i2s_8ch_1_m1_sclkrx: i2s-8ch-1-m1-sclkrx { - rockchip,pins = - <1 RK_PB6 2 &pcfg_pull_none>; - }; - - i2s_8ch_1_m1_lrcktx: i2s-8ch-1-m1-lrcktx { - rockchip,pins = - <1 RK_PB7 2 &pcfg_pull_none>; - }; - - i2s_8ch_1_m1_lrckrx: i2s-8ch-1-m1-lrckrx { - rockchip,pins = - <1 RK_PC0 2 &pcfg_pull_none>; - }; - - i2s_8ch_1_m1_sdo0: i2s-8ch-1-m1-sdo0 { - rockchip,pins = - <1 RK_PC1 2 &pcfg_pull_none>; - }; - - i2s_8ch_1_m1_sdo1_sdi3: i2s-8ch-1-m1-sdo1-sdi3 { - rockchip,pins = - <1 RK_PC2 2 &pcfg_pull_none>; - }; - - i2s_8ch_1_m1_sdo2_sdi2: i2s-8ch-1-m1-sdo2-sdi2 { - rockchip,pins = - <1 RK_PC3 2 &pcfg_pull_none>; - }; - - i2s_8ch_1_m1_sdo3_sdi1: i2s-8ch-1-m1-sdo3_sdi1 { - rockchip,pins = - <1 RK_PC4 2 &pcfg_pull_none>; - }; - - i2s_8ch_1_m1_sdi0: i2s-8ch-1-m1-sdi0 { - rockchip,pins = - <1 RK_PC5 2 &pcfg_pull_none>; - }; - }; - - pdm_m0 { - pdm_m0_clk: pdm-m0-clk { - rockchip,pins = - <1 RK_PA4 3 &pcfg_pull_none>; - }; - - pdm_m0_sdi0: pdm-m0-sdi0 { - rockchip,pins = - <1 RK_PB3 3 &pcfg_pull_none>; - }; - - pdm_m0_sdi1: pdm-m0-sdi1 { - rockchip,pins = - <1 RK_PB2 3 &pcfg_pull_none>; - }; - - pdm_m0_sdi2: pdm-m0-sdi2 { - rockchip,pins = - <1 RK_PB1 3 &pcfg_pull_none>; - }; - - pdm_m0_sdi3: pdm-m0-sdi3 { - rockchip,pins = - <1 RK_PB0 3 &pcfg_pull_none>; - }; - }; - - pdm_m1 { - pdm_m1_clk: pdm-m1-clk { - rockchip,pins = - <1 RK_PB6 4 &pcfg_pull_none>; - }; - - pdm_m1_sdi0: pdm-m1-sdi0 { - rockchip,pins = - <1 RK_PC5 4 &pcfg_pull_none>; - }; - - pdm_m1_sdi1: pdm-m1-sdi1 { - rockchip,pins = - <1 RK_PC4 4 &pcfg_pull_none>; - }; - - pdm_m1_sdi2: pdm-m1-sdi2 { - rockchip,pins = - <1 RK_PC3 4 &pcfg_pull_none>; - }; - - pdm_m1_sdi3: pdm-m1-sdi3 { - rockchip,pins = - <1 RK_PC2 4 &pcfg_pull_none>; - }; - }; - - pdm_m2 { - pdm_m2_clkm: pdm-m2-clkm { - rockchip,pins = - <2 RK_PA4 3 &pcfg_pull_none>; - }; - - pdm_m2_clk: pdm-m2-clk { - rockchip,pins = - <2 RK_PA6 2 &pcfg_pull_none>; - }; - - pdm_m2_sdi0: pdm-m2-sdi0 { - rockchip,pins = - <2 RK_PB5 2 &pcfg_pull_none>; - }; - - pdm_m2_sdi1: pdm-m2-sdi1 { - rockchip,pins = - <2 RK_PB6 2 &pcfg_pull_none>; - }; - - pdm_m2_sdi2: pdm-m2-sdi2 { - rockchip,pins = - <2 RK_PB7 2 &pcfg_pull_none>; - }; - - pdm_m2_sdi3: pdm-m2-sdi3 { - rockchip,pins = - <2 RK_PC0 2 &pcfg_pull_none>; - }; - }; - - pwm0 { - pwm0_pin: pwm0-pin { - rockchip,pins = - <0 RK_PB5 1 &pcfg_pull_none>; - }; - - pwm0_pin_pull_down: pwm0-pin-pull-down { - rockchip,pins = - <0 RK_PB5 1 &pcfg_pull_down>; - }; - }; - - pwm1 { - pwm1_pin: pwm1-pin { - rockchip,pins = - <0 RK_PB6 1 &pcfg_pull_none>; - }; - - pwm1_pin_pull_down: pwm1-pin-pull-down { - rockchip,pins = - <0 RK_PB6 1 &pcfg_pull_down>; - }; - }; - - pwm2 { - pwm2_pin: pwm2-pin { - rockchip,pins = - <0 RK_PB7 1 &pcfg_pull_none>; - }; - - pwm2_pin_pull_down: pwm2-pin-pull-down { - rockchip,pins = - <0 RK_PB7 1 &pcfg_pull_down>; - }; - }; - - pwm3 { - pwm3_pin: pwm3-pin { - rockchip,pins = - <0 RK_PC0 1 &pcfg_pull_none>; - }; - - pwm3_pin_pull_down: pwm3-pin-pull-down { - rockchip,pins = - <0 RK_PC0 1 &pcfg_pull_down>; - }; - }; - - pwm4 { - pwm4_pin: pwm4-pin { - rockchip,pins = - <0 RK_PA1 2 &pcfg_pull_none>; - }; - - pwm4_pin_pull_down: pwm4-pin-pull-down { - rockchip,pins = - <0 RK_PA1 2 &pcfg_pull_down>; - }; - }; - - pwm5 { - pwm5_pin: pwm5-pin { - rockchip,pins = - <0 RK_PC1 2 &pcfg_pull_none>; - }; - - pwm5_pin_pull_down: pwm5-pin-pull-down { - rockchip,pins = - <0 RK_PC1 2 &pcfg_pull_down>; - }; - }; - - pwm6 { - pwm6_pin: pwm6-pin { - rockchip,pins = - <0 RK_PC2 2 &pcfg_pull_none>; - }; - - pwm6_pin_pull_down: pwm6-pin-pull-down { - rockchip,pins = - <0 RK_PC2 2 &pcfg_pull_down>; - }; - }; - - pwm7 { - pwm7_pin: pwm7-pin { - rockchip,pins = - <2 RK_PB0 2 &pcfg_pull_none>; - }; - - pwm7_pin_pull_down: pwm7-pin-pull-down { - rockchip,pins = - <2 RK_PB0 2 &pcfg_pull_down>; - }; - }; - - pwm8 { - pwm8_pin: pwm8-pin { - rockchip,pins = - <2 RK_PB2 2 &pcfg_pull_none>; - }; - - pwm8_pin_pull_down: pwm8-pin-pull-down { - rockchip,pins = - <2 RK_PB2 2 &pcfg_pull_down>; - }; - }; - - pwm9 { - pwm9_pin: pwm9-pin { - rockchip,pins = - <2 RK_PB3 2 &pcfg_pull_none>; - }; - - pwm9_pin_pull_down: pwm9-pin-pull-down { - rockchip,pins = - <2 RK_PB3 2 &pcfg_pull_down>; - }; - }; - - pwm10 { - pwm10_pin: pwm10-pin { - rockchip,pins = - <2 RK_PB4 2 &pcfg_pull_none>; - }; - - pwm10_pin_pull_down: pwm10-pin-pull-down { - rockchip,pins = - <2 RK_PB4 2 &pcfg_pull_down>; - }; - }; - - pwm11 { - pwm11_pin: pwm11-pin { - rockchip,pins = - <2 RK_PC0 4 &pcfg_pull_none>; - }; - - pwm11_pin_pull_down: pwm11-pin-pull-down { - rockchip,pins = - <2 RK_PC0 4 &pcfg_pull_down>; - }; - }; - - rtc { - rtc_32k: rtc-32k { - rockchip,pins = - <0 RK_PC3 1 &pcfg_pull_none>; - }; - }; - - sdmmc { - sdmmc_clk: sdmmc-clk { - rockchip,pins = - <4 RK_PD5 1 &pcfg_pull_none_4ma>; - }; - - sdmmc_cmd: sdmmc-cmd { - rockchip,pins = - <4 RK_PD4 1 &pcfg_pull_up_4ma>; - }; - - sdmmc_det: sdmmc-det { - rockchip,pins = - <0 RK_PA3 1 &pcfg_pull_up_4ma>; - }; - - sdmmc_pwren: sdmmc-pwren { - rockchip,pins = - <4 RK_PD6 1 &pcfg_pull_none_4ma>; - }; - - sdmmc_bus1: sdmmc-bus1 { - rockchip,pins = - <4 RK_PD0 1 &pcfg_pull_up_4ma>; - }; - - sdmmc_bus4: sdmmc-bus4 { - rockchip,pins = - <4 RK_PD0 1 &pcfg_pull_up_4ma>, - <4 RK_PD1 1 &pcfg_pull_up_4ma>, - <4 RK_PD2 1 &pcfg_pull_up_4ma>, - <4 RK_PD3 1 &pcfg_pull_up_4ma>; - }; - }; - - sdio { - sdio_clk: sdio-clk { - rockchip,pins = - <4 RK_PA5 1 &pcfg_pull_none_8ma>; - }; - - sdio_cmd: sdio-cmd { - rockchip,pins = - <4 RK_PA4 1 &pcfg_pull_up_8ma>; - }; - - sdio_pwren: sdio-pwren { - rockchip,pins = - <0 RK_PA2 1 &pcfg_pull_none_8ma>; - }; - - sdio_wrpt: sdio-wrpt { - rockchip,pins = - <0 RK_PA1 1 &pcfg_pull_none_8ma>; - }; - - sdio_intn: sdio-intn { - rockchip,pins = - <0 RK_PA0 1 &pcfg_pull_none_8ma>; - }; - - sdio_bus1: sdio-bus1 { - rockchip,pins = - <4 RK_PA0 1 &pcfg_pull_up_8ma>; - }; - - sdio_bus4: sdio-bus4 { - rockchip,pins = - <4 RK_PA0 1 &pcfg_pull_up_8ma>, - <4 RK_PA1 1 &pcfg_pull_up_8ma>, - <4 RK_PA2 1 &pcfg_pull_up_8ma>, - <4 RK_PA3 1 &pcfg_pull_up_8ma>; - }; - }; - - spdif_in { - spdif_in: spdif-in { - rockchip,pins = - <0 RK_PC2 1 &pcfg_pull_none>; - }; - }; - - spdif_out { - spdif_out: spdif-out { - rockchip,pins = - <0 RK_PC1 1 &pcfg_pull_none>; - }; - }; - - spi0 { - spi0_clk: spi0-clk { - rockchip,pins = - <2 RK_PA2 2 &pcfg_pull_up_4ma>; - }; - - spi0_csn0: spi0-csn0 { - rockchip,pins = - <2 RK_PA3 2 &pcfg_pull_up_4ma>; - }; - - spi0_miso: spi0-miso { - rockchip,pins = - <2 RK_PA0 2 &pcfg_pull_up_4ma>; - }; - - spi0_mosi: spi0-mosi { - rockchip,pins = - <2 RK_PA1 2 &pcfg_pull_up_4ma>; - }; - }; - - spi1 { - spi1_clk: spi1-clk { - rockchip,pins = - <3 RK_PB3 3 &pcfg_pull_up_4ma>; - }; - - spi1_csn0: spi1-csn0 { - rockchip,pins = - <3 RK_PB5 3 &pcfg_pull_up_4ma>; - }; - - spi1_miso: spi1-miso { - rockchip,pins = - <3 RK_PB2 3 &pcfg_pull_up_4ma>; - }; - - spi1_mosi: spi1-mosi { - rockchip,pins = - <3 RK_PB4 3 &pcfg_pull_up_4ma>; - }; - }; - - spi1-m1 { - spi1m1_miso: spi1m1-miso { - rockchip,pins = - <2 RK_PA4 2 &pcfg_pull_up_4ma>; - }; - - spi1m1_mosi: spi1m1-mosi { - rockchip,pins = - <2 RK_PA5 2 &pcfg_pull_up_4ma>; - }; - - spi1m1_clk: spi1m1-clk { - rockchip,pins = - <2 RK_PA7 2 &pcfg_pull_up_4ma>; - }; - - spi1m1_csn0: spi1m1-csn0 { - rockchip,pins = - <2 RK_PB1 2 &pcfg_pull_up_4ma>; - }; - }; - - spi2 { - spi2_clk: spi2-clk { - rockchip,pins = - <1 RK_PD0 3 &pcfg_pull_up_4ma>; - }; - - spi2_csn0: spi2-csn0 { - rockchip,pins = - <1 RK_PD1 3 &pcfg_pull_up_4ma>; - }; - - spi2_miso: spi2-miso { - rockchip,pins = - <1 RK_PC6 3 &pcfg_pull_up_4ma>; - }; - - spi2_mosi: spi2-mosi { - rockchip,pins = - <1 RK_PC7 3 &pcfg_pull_up_4ma>; - }; - }; - - tsadc { - tsadc_otp_pin: tsadc-otp-pin { - rockchip,pins = - <0 RK_PB2 0 &pcfg_pull_none>; - }; - - tsadc_otp_out: tsadc-otp-out { - rockchip,pins = - <0 RK_PB2 1 &pcfg_pull_none>; - }; - }; - - uart0 { - uart0_xfer: uart0-xfer { - rockchip,pins = - <2 RK_PA1 1 &pcfg_pull_up>, - <2 RK_PA0 1 &pcfg_pull_up>; - }; - - uart0_cts: uart0-cts { - rockchip,pins = - <2 RK_PA2 1 &pcfg_pull_none>; - }; - - uart0_rts: uart0-rts { - rockchip,pins = - <2 RK_PA3 1 &pcfg_pull_none>; - }; - - uart0_rts_pin: uart0-rts-pin { - rockchip,pins = - <2 RK_PA3 0 &pcfg_pull_none>; - }; - }; - - uart1 { - uart1_xfer: uart1-xfer { - rockchip,pins = - <1 RK_PD1 1 &pcfg_pull_up>, - <1 RK_PD0 1 &pcfg_pull_up>; - }; - - uart1_cts: uart1-cts { - rockchip,pins = - <1 RK_PC6 1 &pcfg_pull_none>; - }; - - uart1_rts: uart1-rts { - rockchip,pins = - <1 RK_PC7 1 &pcfg_pull_none>; - }; - }; - - uart2-m0 { - uart2m0_xfer: uart2m0-xfer { - rockchip,pins = - <1 RK_PC7 2 &pcfg_pull_up>, - <1 RK_PC6 2 &pcfg_pull_up>; - }; - }; - - uart2-m1 { - uart2m1_xfer: uart2m1-xfer { - rockchip,pins = - <4 RK_PD3 2 &pcfg_pull_up>, - <4 RK_PD2 2 &pcfg_pull_up>; - }; - }; - - uart3 { - uart3_xfer: uart3-xfer { - rockchip,pins = - <3 RK_PB5 4 &pcfg_pull_up>, - <3 RK_PB4 4 &pcfg_pull_up>; - }; - }; - - uart3-m1 { - uart3m1_xfer: uart3m1-xfer { - rockchip,pins = - <0 RK_PC2 3 &pcfg_pull_up>, - <0 RK_PC1 3 &pcfg_pull_up>; - }; - }; - - uart4 { - uart4_xfer: uart4-xfer { - rockchip,pins = - <4 RK_PB1 1 &pcfg_pull_up>, - <4 RK_PB0 1 &pcfg_pull_up>; - }; - - uart4_cts: uart4-cts { - rockchip,pins = - <4 RK_PA6 1 &pcfg_pull_none>; - }; - - uart4_rts: uart4-rts { - rockchip,pins = - <4 RK_PA7 1 &pcfg_pull_none>; - }; - - uart4_rts_pin: uart4-rts-pin { - rockchip,pins = - <4 RK_PA7 0 &pcfg_pull_none>; - }; - }; - }; -}; diff --git a/include/dt-bindings/clock/rk3308-cru.h b/include/dt-bindings/clock/rk3308-cru.h deleted file mode 100644 index d97840f9ee2e..000000000000 --- a/include/dt-bindings/clock/rk3308-cru.h +++ /dev/null @@ -1,387 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2019 Rockchip Electronics Co. Ltd. - * Author: Finley Xiao finley.xiao@rock-chips.com - */ - -#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3308_H -#define _DT_BINDINGS_CLK_ROCKCHIP_RK3308_H - -/* core clocks */ -#define PLL_APLL 1 -#define PLL_DPLL 2 -#define PLL_VPLL0 3 -#define PLL_VPLL1 4 -#define ARMCLK 5 - -/* sclk (special clocks) */ -#define USB480M 14 -#define SCLK_RTC32K 15 -#define SCLK_PVTM_CORE 16 -#define SCLK_UART0 17 -#define SCLK_UART1 18 -#define SCLK_UART2 19 -#define SCLK_UART3 20 -#define SCLK_UART4 21 -#define SCLK_I2C0 22 -#define SCLK_I2C1 23 -#define SCLK_I2C2 24 -#define SCLK_I2C3 25 -#define SCLK_PWM0 26 -#define SCLK_SPI0 27 -#define SCLK_SPI1 28 -#define SCLK_SPI2 29 -#define SCLK_TIMER0 30 -#define SCLK_TIMER1 31 -#define SCLK_TIMER2 32 -#define SCLK_TIMER3 33 -#define SCLK_TIMER4 34 -#define SCLK_TIMER5 35 -#define SCLK_TSADC 36 -#define SCLK_SARADC 37 -#define SCLK_OTP 38 -#define SCLK_OTP_USR 39 -#define SCLK_CPU_BOOST 40 -#define SCLK_CRYPTO 41 -#define SCLK_CRYPTO_APK 42 -#define SCLK_NANDC_DIV 43 -#define SCLK_NANDC_DIV50 44 -#define SCLK_NANDC 45 -#define SCLK_SDMMC_DIV 46 -#define SCLK_SDMMC_DIV50 47 -#define SCLK_SDMMC 48 -#define SCLK_SDMMC_DRV 49 -#define SCLK_SDMMC_SAMPLE 50 -#define SCLK_SDIO_DIV 51 -#define SCLK_SDIO_DIV50 52 -#define SCLK_SDIO 53 -#define SCLK_SDIO_DRV 54 -#define SCLK_SDIO_SAMPLE 55 -#define SCLK_EMMC_DIV 56 -#define SCLK_EMMC_DIV50 57 -#define SCLK_EMMC 58 -#define SCLK_EMMC_DRV 59 -#define SCLK_EMMC_SAMPLE 60 -#define SCLK_SFC 61 -#define SCLK_OTG_ADP 62 -#define SCLK_MAC_SRC 63 -#define SCLK_MAC 64 -#define SCLK_MAC_REF 65 -#define SCLK_MAC_RX_TX 66 -#define SCLK_MAC_RMII 67 -#define SCLK_DDR_MON_TIMER 68 -#define SCLK_DDR_MON 69 -#define SCLK_DDRCLK 70 -#define SCLK_PMU 71 -#define SCLK_USBPHY_REF 72 -#define SCLK_WIFI 73 -#define SCLK_PVTM_PMU 74 -#define SCLK_PDM 75 -#define SCLK_I2S0_8CH_TX 76 -#define SCLK_I2S0_8CH_TX_OUT 77 -#define SCLK_I2S0_8CH_RX 78 -#define SCLK_I2S0_8CH_RX_OUT 79 -#define SCLK_I2S1_8CH_TX 80 -#define SCLK_I2S1_8CH_TX_OUT 81 -#define SCLK_I2S1_8CH_RX 82 -#define SCLK_I2S1_8CH_RX_OUT 83 -#define SCLK_I2S2_8CH_TX 84 -#define SCLK_I2S2_8CH_TX_OUT 85 -#define SCLK_I2S2_8CH_RX 86 -#define SCLK_I2S2_8CH_RX_OUT 87 -#define SCLK_I2S3_8CH_TX 88 -#define SCLK_I2S3_8CH_TX_OUT 89 -#define SCLK_I2S3_8CH_RX 90 -#define SCLK_I2S3_8CH_RX_OUT 91 -#define SCLK_I2S0_2CH 92 -#define SCLK_I2S0_2CH_OUT 93 -#define SCLK_I2S1_2CH 94 -#define SCLK_I2S1_2CH_OUT 95 -#define SCLK_SPDIF_TX_DIV 96 -#define SCLK_SPDIF_TX_DIV50 97 -#define SCLK_SPDIF_TX 98 -#define SCLK_SPDIF_RX_DIV 99 -#define SCLK_SPDIF_RX_DIV50 100 -#define SCLK_SPDIF_RX 101 -#define SCLK_I2S0_8CH_TX_MUX 102 -#define SCLK_I2S0_8CH_RX_MUX 103 -#define SCLK_I2S1_8CH_TX_MUX 104 -#define SCLK_I2S1_8CH_RX_MUX 105 -#define SCLK_I2S2_8CH_TX_MUX 106 -#define SCLK_I2S2_8CH_RX_MUX 107 -#define SCLK_I2S3_8CH_TX_MUX 108 -#define SCLK_I2S3_8CH_RX_MUX 109 -#define SCLK_I2S0_8CH_TX_SRC 110 -#define SCLK_I2S0_8CH_RX_SRC 111 -#define SCLK_I2S1_8CH_TX_SRC 112 -#define SCLK_I2S1_8CH_RX_SRC 113 -#define SCLK_I2S2_8CH_TX_SRC 114 -#define SCLK_I2S2_8CH_RX_SRC 115 -#define SCLK_I2S3_8CH_TX_SRC 116 -#define SCLK_I2S3_8CH_RX_SRC 117 -#define SCLK_I2S0_2CH_SRC 118 -#define SCLK_I2S1_2CH_SRC 119 -#define SCLK_PWM1 120 -#define SCLK_PWM2 121 -#define SCLK_OWIRE 122 - -/* dclk */ -#define DCLK_VOP 125 - -/* aclk */ -#define ACLK_BUS_SRC 130 -#define ACLK_BUS 131 -#define ACLK_PERI_SRC 132 -#define ACLK_PERI 133 -#define ACLK_MAC 134 -#define ACLK_CRYPTO 135 -#define ACLK_VOP 136 -#define ACLK_GIC 137 -#define ACLK_DMAC0 138 -#define ACLK_DMAC1 139 - -/* hclk */ -#define HCLK_BUS 150 -#define HCLK_PERI 151 -#define HCLK_AUDIO 152 -#define HCLK_NANDC 153 -#define HCLK_SDMMC 154 -#define HCLK_SDIO 155 -#define HCLK_EMMC 156 -#define HCLK_SFC 157 -#define HCLK_OTG 158 -#define HCLK_HOST 159 -#define HCLK_HOST_ARB 160 -#define HCLK_PDM 161 -#define HCLK_SPDIFTX 162 -#define HCLK_SPDIFRX 163 -#define HCLK_I2S0_8CH 164 -#define HCLK_I2S1_8CH 165 -#define HCLK_I2S2_8CH 166 -#define HCLK_I2S3_8CH 167 -#define HCLK_I2S0_2CH 168 -#define HCLK_I2S1_2CH 169 -#define HCLK_VAD 170 -#define HCLK_CRYPTO 171 -#define HCLK_VOP 172 - -/* pclk */ -#define PCLK_BUS 190 -#define PCLK_DDR 191 -#define PCLK_PERI 192 -#define PCLK_PMU 193 -#define PCLK_AUDIO 194 -#define PCLK_MAC 195 -#define PCLK_ACODEC 196 -#define PCLK_UART0 197 -#define PCLK_UART1 198 -#define PCLK_UART2 199 -#define PCLK_UART3 200 -#define PCLK_UART4 201 -#define PCLK_I2C0 202 -#define PCLK_I2C1 203 -#define PCLK_I2C2 204 -#define PCLK_I2C3 205 -#define PCLK_PWM0 206 -#define PCLK_SPI0 207 -#define PCLK_SPI1 208 -#define PCLK_SPI2 209 -#define PCLK_SARADC 210 -#define PCLK_TSADC 211 -#define PCLK_TIMER 212 -#define PCLK_OTP_NS 213 -#define PCLK_WDT 214 -#define PCLK_GPIO0 215 -#define PCLK_GPIO1 216 -#define PCLK_GPIO2 217 -#define PCLK_GPIO3 218 -#define PCLK_GPIO4 219 -#define PCLK_SGRF 220 -#define PCLK_GRF 221 -#define PCLK_USBSD_DET 222 -#define PCLK_DDR_UPCTL 223 -#define PCLK_DDR_MON 224 -#define PCLK_DDRPHY 225 -#define PCLK_DDR_STDBY 226 -#define PCLK_USB_GRF 227 -#define PCLK_CRU 228 -#define PCLK_OTP_PHY 229 -#define PCLK_CPU_BOOST 230 -#define PCLK_PWM1 231 -#define PCLK_PWM2 232 -#define PCLK_CAN 233 -#define PCLK_OWIRE 234 - -#define CLK_NR_CLKS (PCLK_OWIRE + 1) - -/* soft-reset indices */ - -/* cru_softrst_con0 */ -#define SRST_CORE0_PO 0 -#define SRST_CORE1_PO 1 -#define SRST_CORE2_PO 2 -#define SRST_CORE3_PO 3 -#define SRST_CORE0 4 -#define SRST_CORE1 5 -#define SRST_CORE2 6 -#define SRST_CORE3 7 -#define SRST_CORE0_DBG 8 -#define SRST_CORE1_DBG 9 -#define SRST_CORE2_DBG 10 -#define SRST_CORE3_DBG 11 -#define SRST_TOPDBG 12 -#define SRST_CORE_NOC 13 -#define SRST_STRC_A 14 -#define SRST_L2C 15 - -/* cru_softrst_con1 */ -#define SRST_DAP 16 -#define SRST_CORE_PVTM 17 -#define SRST_CORE_PRF 18 -#define SRST_CORE_GRF 19 -#define SRST_DDRUPCTL 20 -#define SRST_DDRUPCTL_P 22 -#define SRST_MSCH 23 -#define SRST_DDRMON_P 25 -#define SRST_DDRSTDBY_P 26 -#define SRST_DDRSTDBY 27 -#define SRST_DDRPHY 28 -#define SRST_DDRPHY_DIV 29 -#define SRST_DDRPHY_P 30 - -/* cru_softrst_con2 */ -#define SRST_BUS_NIU_H 32 -#define SRST_USB_NIU_P 33 -#define SRST_CRYPTO_A 34 -#define SRST_CRYPTO_H 35 -#define SRST_CRYPTO 36 -#define SRST_CRYPTO_APK 37 -#define SRST_VOP_A 38 -#define SRST_VOP_H 39 -#define SRST_VOP_D 40 -#define SRST_INTMEM_A 41 -#define SRST_ROM_H 42 -#define SRST_GIC_A 43 -#define SRST_UART0_P 44 -#define SRST_UART0 45 -#define SRST_UART1_P 46 -#define SRST_UART1 47 - -/* cru_softrst_con3 */ -#define SRST_UART2_P 48 -#define SRST_UART2 49 -#define SRST_UART3_P 50 -#define SRST_UART3 51 -#define SRST_UART4_P 52 -#define SRST_UART4 53 -#define SRST_I2C0_P 54 -#define SRST_I2C0 55 -#define SRST_I2C1_P 56 -#define SRST_I2C1 57 -#define SRST_I2C2_P 58 -#define SRST_I2C2 59 -#define SRST_I2C3_P 60 -#define SRST_I2C3 61 -#define SRST_PWM0_P 62 -#define SRST_PWM0 63 - -/* cru_softrst_con4 */ -#define SRST_SPI0_P 64 -#define SRST_SPI0 65 -#define SRST_SPI1_P 66 -#define SRST_SPI1 67 -#define SRST_SPI2_P 68 -#define SRST_SPI2 69 -#define SRST_SARADC_P 70 -#define SRST_TSADC_P 71 -#define SRST_TSADC 72 -#define SRST_TIMER0_P 73 -#define SRST_TIMER0 74 -#define SRST_TIMER1 75 -#define SRST_TIMER2 76 -#define SRST_TIMER3 77 -#define SRST_TIMER4 78 -#define SRST_TIMER5 79 - -/* cru_softrst_con5 */ -#define SRST_OTP_NS_P 80 -#define SRST_OTP_NS_SBPI 81 -#define SRST_OTP_NS_USR 82 -#define SRST_OTP_PHY_P 83 -#define SRST_OTP_PHY 84 -#define SRST_GPIO0_P 86 -#define SRST_GPIO1_P 87 -#define SRST_GPIO2_P 88 -#define SRST_GPIO3_P 89 -#define SRST_GPIO4_P 90 -#define SRST_GRF_P 91 -#define SRST_USBSD_DET_P 92 -#define SRST_PMU 93 -#define SRST_PMU_PVTM 94 -#define SRST_USB_GRF_P 95 - -/* cru_softrst_con6 */ -#define SRST_CPU_BOOST 96 -#define SRST_CPU_BOOST_P 97 -#define SRST_PWM1_P 98 -#define SRST_PWM1 99 -#define SRST_PWM2_P 100 -#define SRST_PWM2 101 -#define SRST_PERI_NIU_A 104 -#define SRST_PERI_NIU_H 105 -#define SRST_PERI_NIU_p 106 -#define SRST_USB2OTG_H 107 -#define SRST_USB2OTG 108 -#define SRST_USB2OTG_ADP 109 -#define SRST_USB2HOST_H 110 -#define SRST_USB2HOST_ARB_H 111 - -/* cru_softrst_con7 */ -#define SRST_USB2HOST_AUX_H 112 -#define SRST_USB2HOST_EHCI 113 -#define SRST_USB2HOST 114 -#define SRST_USBPHYPOR 115 -#define SRST_UTMI0 116 -#define SRST_UTMI1 117 -#define SRST_SDIO_H 118 -#define SRST_EMMC_H 119 -#define SRST_SFC_H 120 -#define SRST_SFC 121 -#define SRST_SD_H 122 -#define SRST_NANDC_H 123 -#define SRST_NANDC_N 124 -#define SRST_MAC_A 125 -#define SRST_CAN_P 126 -#define SRST_OWIRE_P 127 - -/* cru_softrst_con8 */ -#define SRST_AUDIO_NIU_H 128 -#define SRST_AUDIO_NIU_P 129 -#define SRST_PDM_H 130 -#define SRST_PDM_M 131 -#define SRST_SPDIFTX_H 132 -#define SRST_SPDIFTX_M 133 -#define SRST_SPDIFRX_H 134 -#define SRST_SPDIFRX_M 135 -#define SRST_I2S0_8CH_H 136 -#define SRST_I2S0_8CH_TX_M 137 -#define SRST_I2S0_8CH_RX_M 138 -#define SRST_I2S1_8CH_H 139 -#define SRST_I2S1_8CH_TX_M 140 -#define SRST_I2S1_8CH_RX_M 141 -#define SRST_I2S2_8CH_H 142 -#define SRST_I2S2_8CH_TX_M 143 - -/* cru_softrst_con9 */ -#define SRST_I2S2_8CH_RX_M 144 -#define SRST_I2S3_8CH_H 145 -#define SRST_I2S3_8CH_TX_M 146 -#define SRST_I2S3_8CH_RX_M 147 -#define SRST_I2S0_2CH_H 148 -#define SRST_I2S0_2CH_M 149 -#define SRST_I2S1_2CH_H 150 -#define SRST_I2S1_2CH_M 151 -#define SRST_VAD_H 152 -#define SRST_ACODEC_P 153 - -#endif

All RK3328 boards has now been synced to Linux kernel v6.8 DTs and can migrate to use OF_UPSTREAM.

Migrate all RK3328 boards to use OF_UPSTREAM.

Signed-off-by: Jonas Karlman jonas@kwiboo.se --- arch/arm/dts/Makefile | 11 ----------- arch/arm/mach-rockchip/Kconfig | 1 + configs/evb-rk3328_defconfig | 2 +- configs/nanopi-r2c-plus-rk3328_defconfig | 2 +- configs/nanopi-r2c-rk3328_defconfig | 2 +- configs/nanopi-r2s-rk3328_defconfig | 2 +- configs/orangepi-r1-plus-lts-rk3328_defconfig | 2 +- configs/orangepi-r1-plus-rk3328_defconfig | 2 +- configs/roc-cc-rk3328_defconfig | 2 +- configs/rock-pi-e-rk3328_defconfig | 2 +- configs/rock64-rk3328_defconfig | 2 +- 11 files changed, 10 insertions(+), 20 deletions(-)

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 319ec23a4fee..b7ada58695be 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -92,17 +92,6 @@ dtb-$(CONFIG_ROCKCHIP_RK3288) += \ rk3288-veyron-speedy.dtb \ rk3288-vyasa.dtb

-dtb-$(CONFIG_ROCKCHIP_RK3328) += \ - rk3328-evb.dtb \ - rk3328-nanopi-r2c.dtb \ - rk3328-nanopi-r2c-plus.dtb \ - rk3328-nanopi-r2s.dtb \ - rk3328-orangepi-r1-plus.dtb \ - rk3328-orangepi-r1-plus-lts.dtb \ - rk3328-roc-cc.dtb \ - rk3328-rock64.dtb \ - rk3328-rock-pi-e.dtb - dtb-$(CONFIG_ROCKCHIP_RK3368) += \ rk3368-lion-haikou.dtb \ rk3368-sheep.dtb \ diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index f1caf4f3738b..a492b0885c03 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -197,6 +197,7 @@ config ROCKCHIP_RK3328 imply MISC imply MISC_INIT_R imply OF_LIVE + imply OF_UPSTREAM imply PRE_CONSOLE_BUFFER imply ROCKCHIP_COMMON_BOARD imply ROCKCHIP_EFUSE diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig index 53ad6777ec50..bfb85223437d 100644 --- a/configs/evb-rk3328_defconfig +++ b/configs/evb-rk3328_defconfig @@ -5,7 +5,7 @@ CONFIG_ARCH_ROCKCHIP=y CONFIG_NR_DRAM_BANKS=1 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_ENV_OFFSET=0x3F8000 -CONFIG_DEFAULT_DEVICE_TREE="rk3328-evb" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3328-evb" CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3328=y CONFIG_DEBUG_UART_BASE=0xFF130000 diff --git a/configs/nanopi-r2c-plus-rk3328_defconfig b/configs/nanopi-r2c-plus-rk3328_defconfig index beef682a582e..f311a0a80ba7 100644 --- a/configs/nanopi-r2c-plus-rk3328_defconfig +++ b/configs/nanopi-r2c-plus-rk3328_defconfig @@ -6,7 +6,7 @@ CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_ENV_OFFSET=0x3F8000 -CONFIG_DEFAULT_DEVICE_TREE="rk3328-nanopi-r2c-plus" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3328-nanopi-r2c-plus" CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3328=y CONFIG_DEBUG_UART_BASE=0xFF130000 diff --git a/configs/nanopi-r2c-rk3328_defconfig b/configs/nanopi-r2c-rk3328_defconfig index 8960c1afaba5..533dc1029f73 100644 --- a/configs/nanopi-r2c-rk3328_defconfig +++ b/configs/nanopi-r2c-rk3328_defconfig @@ -6,7 +6,7 @@ CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_ENV_OFFSET=0x3F8000 -CONFIG_DEFAULT_DEVICE_TREE="rk3328-nanopi-r2c" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3328-nanopi-r2c" CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3328=y CONFIG_DEBUG_UART_BASE=0xFF130000 diff --git a/configs/nanopi-r2s-rk3328_defconfig b/configs/nanopi-r2s-rk3328_defconfig index 96e67e248d32..2591a9cc8ab2 100644 --- a/configs/nanopi-r2s-rk3328_defconfig +++ b/configs/nanopi-r2s-rk3328_defconfig @@ -6,7 +6,7 @@ CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_ENV_OFFSET=0x3F8000 -CONFIG_DEFAULT_DEVICE_TREE="rk3328-nanopi-r2s" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3328-nanopi-r2s" CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3328=y CONFIG_DEBUG_UART_BASE=0xFF130000 diff --git a/configs/orangepi-r1-plus-lts-rk3328_defconfig b/configs/orangepi-r1-plus-lts-rk3328_defconfig index 5fbbd5fc6558..14cdbd813c81 100644 --- a/configs/orangepi-r1-plus-lts-rk3328_defconfig +++ b/configs/orangepi-r1-plus-lts-rk3328_defconfig @@ -6,7 +6,7 @@ CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_ENV_OFFSET=0x3F8000 -CONFIG_DEFAULT_DEVICE_TREE="rk3328-orangepi-r1-plus-lts" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3328-orangepi-r1-plus-lts" CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3328=y CONFIG_ROCKCHIP_SPI_IMAGE=y diff --git a/configs/orangepi-r1-plus-rk3328_defconfig b/configs/orangepi-r1-plus-rk3328_defconfig index c5afe5ea6e5c..7fe58e7a1467 100644 --- a/configs/orangepi-r1-plus-rk3328_defconfig +++ b/configs/orangepi-r1-plus-rk3328_defconfig @@ -6,7 +6,7 @@ CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_ENV_OFFSET=0x3F8000 -CONFIG_DEFAULT_DEVICE_TREE="rk3328-orangepi-r1-plus" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3328-orangepi-r1-plus" CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3328=y CONFIG_ROCKCHIP_SPI_IMAGE=y diff --git a/configs/roc-cc-rk3328_defconfig b/configs/roc-cc-rk3328_defconfig index 1dbd39e6b5e7..91b9422e26fb 100644 --- a/configs/roc-cc-rk3328_defconfig +++ b/configs/roc-cc-rk3328_defconfig @@ -6,7 +6,7 @@ CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_ENV_OFFSET=0x3F8000 -CONFIG_DEFAULT_DEVICE_TREE="rk3328-roc-cc" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3328-roc-cc" CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3328=y CONFIG_DEBUG_UART_BASE=0xFF130000 diff --git a/configs/rock-pi-e-rk3328_defconfig b/configs/rock-pi-e-rk3328_defconfig index 23029255bca2..5cc54af3ca56 100644 --- a/configs/rock-pi-e-rk3328_defconfig +++ b/configs/rock-pi-e-rk3328_defconfig @@ -6,7 +6,7 @@ CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_ENV_OFFSET=0x3F8000 -CONFIG_DEFAULT_DEVICE_TREE="rk3328-rock-pi-e" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3328-rock-pi-e" CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3328=y CONFIG_DEBUG_UART_BASE=0xFF130000 diff --git a/configs/rock64-rk3328_defconfig b/configs/rock64-rk3328_defconfig index b0be1d1d7633..9d77dfb7098a 100644 --- a/configs/rock64-rk3328_defconfig +++ b/configs/rock64-rk3328_defconfig @@ -6,7 +6,7 @@ CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_ENV_OFFSET=0x3F8000 -CONFIG_DEFAULT_DEVICE_TREE="rk3328-rock64" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3328-rock64" CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3328=y CONFIG_ROCKCHIP_SPI_IMAGE=y

Remove redundant device tree files now that RK3328 boards have been migrated to use OF_UPSTREAM.

Signed-off-by: Jonas Karlman jonas@kwiboo.se --- arch/arm/dts/rk3328-evb.dts | 289 --- arch/arm/dts/rk3328-nanopi-r2c-plus.dts | 33 - arch/arm/dts/rk3328-nanopi-r2c.dts | 40 - arch/arm/dts/rk3328-nanopi-r2s.dts | 410 ---- arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts | 42 - arch/arm/dts/rk3328-orangepi-r1-plus.dts | 374 ---- arch/arm/dts/rk3328-roc-cc.dts | 384 ---- arch/arm/dts/rk3328-rock-pi-e.dts | 445 ---- arch/arm/dts/rk3328-rock64.dts | 394 ---- arch/arm/dts/rk3328.dtsi | 1944 ------------------ include/dt-bindings/clock/rk3328-cru.h | 393 ---- include/dt-bindings/power/rk3328-power.h | 19 - 12 files changed, 4767 deletions(-) delete mode 100644 arch/arm/dts/rk3328-evb.dts delete mode 100644 arch/arm/dts/rk3328-nanopi-r2c-plus.dts delete mode 100644 arch/arm/dts/rk3328-nanopi-r2c.dts delete mode 100644 arch/arm/dts/rk3328-nanopi-r2s.dts delete mode 100644 arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts delete mode 100644 arch/arm/dts/rk3328-orangepi-r1-plus.dts delete mode 100644 arch/arm/dts/rk3328-roc-cc.dts delete mode 100644 arch/arm/dts/rk3328-rock-pi-e.dts delete mode 100644 arch/arm/dts/rk3328-rock64.dts delete mode 100644 arch/arm/dts/rk3328.dtsi delete mode 100644 include/dt-bindings/clock/rk3328-cru.h delete mode 100644 include/dt-bindings/power/rk3328-power.h

diff --git a/arch/arm/dts/rk3328-evb.dts b/arch/arm/dts/rk3328-evb.dts deleted file mode 100644 index 1eef5504445f..000000000000 --- a/arch/arm/dts/rk3328-evb.dts +++ /dev/null @@ -1,289 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd - */ - -/dts-v1/; -#include "rk3328.dtsi" - -/ { - model = "Rockchip RK3328 EVB"; - compatible = "rockchip,rk3328-evb", "rockchip,rk3328"; - - aliases { - ethernet0 = &gmac2phy; - mmc0 = &sdmmc; - mmc1 = &sdio; - mmc2 = &emmc; - }; - - chosen { - stdout-path = "serial2:1500000n8"; - }; - - dc_12v: dc-12v { - compatible = "regulator-fixed"; - regulator-name = "dc_12v"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_enable_h>; - - /* - * On the module itself this is one of these (depending - * on the actual card populated): - * - SDIO_RESET_L_WL_REG_ON - * - PDN (power down when low) - */ - reset-gpios = <&gpio1 18 GPIO_ACTIVE_LOW>; - }; - - vcc_sd: sdmmc-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio0 30 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc0m1_pin>; - regulator-name = "vcc_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_io>; - }; - - vcc_sys: vcc-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&dc_12v>; - }; - - vcc_phy: vcc-phy-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_phy"; - regulator-always-on; - regulator-boot-on; - }; -}; - -&cpu0 { - cpu-supply = <&vdd_arm>; -}; - -&cpu1 { - cpu-supply = <&vdd_arm>; -}; - -&cpu2 { - cpu-supply = <&vdd_arm>; -}; - -&cpu3 { - cpu-supply = <&vdd_arm>; -}; - -&emmc { - bus-width = <8>; - cap-mmc-highspeed; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; - status = "okay"; -}; - -&gmac2phy { - phy-supply = <&vcc_phy>; - clock_in_out = "output"; - assigned-clock-rate = <50000000>; - assigned-clocks = <&cru SCLK_MAC2PHY>; - assigned-clock-parents = <&cru SCLK_MAC2PHY_SRC>; - status = "okay"; -}; - -&i2c1 { - status = "okay"; - - rk805: pmic@18 { - compatible = "rockchip,rk805"; - reg = <0x18>; - interrupt-parent = <&gpio2>; - interrupts = <6 IRQ_TYPE_LEVEL_LOW>; - #clock-cells = <1>; - clock-output-names = "xin32k", "rk805-clkout2"; - gpio-controller; - #gpio-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l>; - rockchip,system-power-controller; - wakeup-source; - - vcc1-supply = <&vcc_sys>; - vcc2-supply = <&vcc_sys>; - vcc3-supply = <&vcc_sys>; - vcc4-supply = <&vcc_sys>; - vcc5-supply = <&vcc_io>; - vcc6-supply = <&vcc_io>; - - regulators { - vdd_logic: DCDC_REG1 { - regulator-name = "vdd_logic"; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1450000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vdd_arm: DCDC_REG2 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1450000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <950000>; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_io: DCDC_REG4 { - regulator-name = "vcc_io"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc_18: LDO_REG1 { - regulator-name = "vcc_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc18_emmc: LDO_REG2 { - regulator-name = "vcc18_emmc"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vdd_10: LDO_REG3 { - regulator-name = "vdd_10"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - }; - }; -}; - -&pinctrl { - pmic { - pmic_int_l: pmic-int-l { - rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - sdio-pwrseq { - wifi_enable_h: wifi-enable-h { - rockchip,pins = - <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&sdio { - bus-width = <4>; - cap-sd-highspeed; - cap-sdio-irq; - keep-power-in-suspend; - max-frequency = <150000000>; - mmc-pwrseq = <&sdio_pwrseq>; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; - status = "okay"; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - disable-wp; - max-frequency = <150000000>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>; - vmmc-supply = <&vcc_sd>; - status = "okay"; -}; - -&tsadc { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&u2phy { - status = "okay"; -}; - -&u2phy_host { - status = "okay"; -}; - -&u2phy_otg { - status = "okay"; -}; - -&usb20_otg { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; diff --git a/arch/arm/dts/rk3328-nanopi-r2c-plus.dts b/arch/arm/dts/rk3328-nanopi-r2c-plus.dts deleted file mode 100644 index 16a1958e4572..000000000000 --- a/arch/arm/dts/rk3328-nanopi-r2c-plus.dts +++ /dev/null @@ -1,33 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd. - * (http://www.friendlyarm.com) - * - * Copyright (c) 2023 Tianling Shen cnsztl@gmail.com - */ - -/dts-v1/; -#include "rk3328-nanopi-r2c.dts" - -/ { - model = "FriendlyElec NanoPi R2C Plus"; - compatible = "friendlyarm,nanopi-r2c-plus", "rockchip,rk3328"; - - aliases { - mmc1 = &emmc; - }; -}; - -&emmc { - bus-width = <8>; - cap-mmc-highspeed; - max-frequency = <150000000>; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; - vmmc-supply = <&vcc_io_33>; - vqmmc-supply = <&vcc18_emmc>; - status = "okay"; -}; diff --git a/arch/arm/dts/rk3328-nanopi-r2c.dts b/arch/arm/dts/rk3328-nanopi-r2c.dts deleted file mode 100644 index a07a26b944a0..000000000000 --- a/arch/arm/dts/rk3328-nanopi-r2c.dts +++ /dev/null @@ -1,40 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd. - * (http://www.friendlyarm.com) - * - * Copyright (c) 2021-2023 Tianling Shen cnsztl@gmail.com - */ - -/dts-v1/; -#include "rk3328-nanopi-r2s.dts" - -/ { - model = "FriendlyElec NanoPi R2C"; - compatible = "friendlyarm,nanopi-r2c", "rockchip,rk3328"; -}; - -&gmac2io { - phy-handle = <&yt8521s>; - tx_delay = <0x22>; - rx_delay = <0x12>; - - mdio { - /delete-node/ ethernet-phy@1; - - yt8521s: ethernet-phy@3 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <3>; - - motorcomm,clk-out-frequency-hz = <125000000>; - motorcomm,keep-pll-enabled; - motorcomm,auto-sleep-disabled; - - pinctrl-0 = <&eth_phy_reset_pin>; - pinctrl-names = "default"; - reset-assert-us = <10000>; - reset-deassert-us = <50000>; - reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; - }; - }; -}; diff --git a/arch/arm/dts/rk3328-nanopi-r2s.dts b/arch/arm/dts/rk3328-nanopi-r2s.dts deleted file mode 100644 index a4399da7d8b1..000000000000 --- a/arch/arm/dts/rk3328-nanopi-r2s.dts +++ /dev/null @@ -1,410 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2020 David Bauer mail@david-bauer.net - */ - -/dts-v1/; - -#include <dt-bindings/input/input.h> -#include <dt-bindings/gpio/gpio.h> -#include "rk3328.dtsi" - -/ { - model = "FriendlyElec NanoPi R2S"; - compatible = "friendlyarm,nanopi-r2s", "rockchip,rk3328"; - - aliases { - ethernet0 = &gmac2io; - ethernet1 = &rtl8153; - mmc0 = &sdmmc; - }; - - chosen { - stdout-path = "serial2:1500000n8"; - }; - - gmac_clk: gmac-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "gmac_clkin"; - #clock-cells = <0>; - }; - - keys { - compatible = "gpio-keys"; - pinctrl-0 = <&reset_button_pin>; - pinctrl-names = "default"; - - key-reset { - label = "reset"; - gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>; - linux,code = <KEY_RESTART>; - debounce-interval = <50>; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>; - pinctrl-names = "default"; - - lan_led: led-0 { - gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; - label = "nanopi-r2s:green:lan"; - }; - - sys_led: led-1 { - gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; - label = "nanopi-r2s:red:sys"; - default-state = "on"; - }; - - wan_led: led-2 { - gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>; - label = "nanopi-r2s:green:wan"; - }; - }; - - vcc_io_sdio: sdmmcio-regulator { - compatible = "regulator-gpio"; - enable-active-high; - gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>; - pinctrl-0 = <&sdio_vcc_pin>; - pinctrl-names = "default"; - regulator-name = "vcc_io_sdio"; - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-settling-time-us = <5000>; - regulator-type = "voltage"; - startup-delay-us = <2000>; - states = <1800000 0x1>, - <3300000 0x0>; - vin-supply = <&vcc_io_33>; - }; - - vcc_sd: sdmmc-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&sdmmc0m1_pin>; - pinctrl-names = "default"; - regulator-name = "vcc_sd"; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_io_33>; - }; - - vdd_5v: vdd-5v { - compatible = "regulator-fixed"; - regulator-name = "vdd_5v"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - vdd_5v_lan: vdd-5v-lan { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>; - pinctrl-0 = <&lan_vdd_pin>; - pinctrl-names = "default"; - regulator-name = "vdd_5v_lan"; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vdd_5v>; - }; -}; - -&cpu0 { - cpu-supply = <&vdd_arm>; -}; - -&cpu1 { - cpu-supply = <&vdd_arm>; -}; - -&cpu2 { - cpu-supply = <&vdd_arm>; -}; - -&cpu3 { - cpu-supply = <&vdd_arm>; -}; - -&display_subsystem { - status = "disabled"; -}; - -&gmac2io { - assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; - assigned-clock-parents = <&gmac_clk>, <&gmac_clk>; - clock_in_out = "input"; - phy-handle = <&rtl8211e>; - phy-mode = "rgmii"; - phy-supply = <&vcc_io_33>; - pinctrl-0 = <&rgmiim1_pins>; - pinctrl-names = "default"; - rx_delay = <0x18>; - snps,aal; - tx_delay = <0x24>; - status = "okay"; - - mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - rtl8211e: ethernet-phy@1 { - reg = <1>; - pinctrl-0 = <&eth_phy_reset_pin>; - pinctrl-names = "default"; - reset-assert-us = <10000>; - reset-deassert-us = <50000>; - reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&i2c1 { - status = "okay"; - - rk805: pmic@18 { - compatible = "rockchip,rk805"; - reg = <0x18>; - interrupt-parent = <&gpio1>; - interrupts = <24 IRQ_TYPE_LEVEL_LOW>; - #clock-cells = <1>; - clock-output-names = "xin32k", "rk805-clkout2"; - gpio-controller; - #gpio-cells = <2>; - pinctrl-0 = <&pmic_int_l>; - pinctrl-names = "default"; - rockchip,system-power-controller; - wakeup-source; - - vcc1-supply = <&vdd_5v>; - vcc2-supply = <&vdd_5v>; - vcc3-supply = <&vdd_5v>; - vcc4-supply = <&vdd_5v>; - vcc5-supply = <&vcc_io_33>; - vcc6-supply = <&vdd_5v>; - - regulators { - vdd_log: DCDC_REG1 { - regulator-name = "vdd_log"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1450000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vdd_arm: DCDC_REG2 { - regulator-name = "vdd_arm"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1450000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <950000>; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_io_33: DCDC_REG4 { - regulator-name = "vcc_io_33"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc_18: LDO_REG1 { - regulator-name = "vcc_18"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc18_emmc: LDO_REG2 { - regulator-name = "vcc18_emmc"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vdd_10: LDO_REG3 { - regulator-name = "vdd_10"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - }; - }; -}; - -&io_domains { - pmuio-supply = <&vcc_io_33>; - vccio1-supply = <&vcc_io_33>; - vccio2-supply = <&vcc18_emmc>; - vccio3-supply = <&vcc_io_sdio>; - vccio4-supply = <&vcc_18>; - vccio5-supply = <&vcc_io_33>; - vccio6-supply = <&vcc_io_33>; - status = "okay"; -}; - -&pinctrl { - button { - reset_button_pin: reset-button-pin { - rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - gmac2io { - eth_phy_reset_pin: eth-phy-reset-pin { - rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; - - leds { - lan_led_pin: lan-led-pin { - rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - sys_led_pin: sys-led-pin { - rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - wan_led_pin: wan-led-pin { - rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - lan { - lan_vdd_pin: lan-vdd-pin { - rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - pmic_int_l: pmic-int-l { - rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - sd { - sdio_vcc_pin: sdio-vcc-pin { - rockchip,pins = <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; -}; - -&pwm2 { - status = "okay"; -}; - -&sdmmc { - bus-width = <4>; - cap-sd-highspeed; - disable-wp; - pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>; - pinctrl-names = "default"; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-sdr104; - vmmc-supply = <&vcc_sd>; - vqmmc-supply = <&vcc_io_sdio>; - status = "okay"; -}; - -&tsadc { - rockchip,hw-tshut-mode = <0>; - rockchip,hw-tshut-polarity = <0>; - status = "okay"; -}; - -&u2phy { - status = "okay"; -}; - -&u2phy_host { - status = "okay"; -}; - -&u2phy_otg { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&usb20_otg { - status = "okay"; - dr_mode = "host"; -}; - -&usbdrd3 { - dr_mode = "host"; - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - - /* Second port is for USB 3.0 */ - rtl8153: device@2 { - compatible = "usbbda,8153"; - reg = <2>; - }; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; diff --git a/arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts b/arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts deleted file mode 100644 index 4237f2ee8fee..000000000000 --- a/arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts +++ /dev/null @@ -1,42 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright (c) 2016 Xunlong Software. Co., Ltd. - * (http://www.orangepi.org) - * - * Copyright (c) 2021-2023 Tianling Shen cnsztl@gmail.com - */ - -/dts-v1/; -#include "rk3328-orangepi-r1-plus.dts" - -/ { - model = "Xunlong Orange Pi R1 Plus LTS"; - compatible = "xunlong,orangepi-r1-plus-lts", "rockchip,rk3328"; -}; - -&gmac2io { - phy-handle = <&yt8531c>; - tx_delay = <0x19>; - rx_delay = <0x05>; - - mdio { - /delete-node/ ethernet-phy@1; - - yt8531c: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - - motorcomm,auto-sleep-disabled; - motorcomm,clk-out-frequency-hz = <125000000>; - motorcomm,keep-pll-enabled; - motorcomm,rx-clk-drv-microamp = <5020>; - motorcomm,rx-data-drv-microamp = <5020>; - - pinctrl-0 = <&eth_phy_reset_pin>; - pinctrl-names = "default"; - reset-assert-us = <15000>; - reset-deassert-us = <50000>; - reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; - }; - }; -}; diff --git a/arch/arm/dts/rk3328-orangepi-r1-plus.dts b/arch/arm/dts/rk3328-orangepi-r1-plus.dts deleted file mode 100644 index f20662929c77..000000000000 --- a/arch/arm/dts/rk3328-orangepi-r1-plus.dts +++ /dev/null @@ -1,374 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Based on rk3328-nanopi-r2s.dts, which is: - * Copyright (c) 2020 David Bauer mail@david-bauer.net - */ - -/dts-v1/; - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/leds/common.h> -#include "rk3328.dtsi" - -/ { - model = "Xunlong Orange Pi R1 Plus"; - compatible = "xunlong,orangepi-r1-plus", "rockchip,rk3328"; - - aliases { - ethernet0 = &gmac2io; - ethernet1 = &rtl8153; - mmc0 = &sdmmc; - }; - - chosen { - stdout-path = "serial2:1500000n8"; - }; - - gmac_clk: gmac-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "gmac_clkin"; - #clock-cells = <0>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>; - pinctrl-names = "default"; - - led-0 { - function = LED_FUNCTION_LAN; - color = <LED_COLOR_ID_GREEN>; - gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; - }; - - led-1 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_RED>; - gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - - led-2 { - function = LED_FUNCTION_WAN; - color = <LED_COLOR_ID_GREEN>; - gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>; - }; - }; - - vcc_sd: sdmmc-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&sdmmc0m1_pin>; - pinctrl-names = "default"; - regulator-name = "vcc_sd"; - regulator-boot-on; - vin-supply = <&vcc_io>; - }; - - vcc_sys: vcc-sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - vdd_5v_lan: vdd-5v-lan-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>; - pinctrl-0 = <&lan_vdd_pin>; - pinctrl-names = "default"; - regulator-name = "vdd_5v_lan"; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_sys>; - }; -}; - -&cpu0 { - cpu-supply = <&vdd_arm>; -}; - -&cpu1 { - cpu-supply = <&vdd_arm>; -}; - -&cpu2 { - cpu-supply = <&vdd_arm>; -}; - -&cpu3 { - cpu-supply = <&vdd_arm>; -}; - -&display_subsystem { - status = "disabled"; -}; - -&gmac2io { - assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; - assigned-clock-parents = <&gmac_clk>, <&gmac_clk>; - clock_in_out = "input"; - phy-handle = <&rtl8211e>; - phy-mode = "rgmii"; - phy-supply = <&vcc_io>; - pinctrl-0 = <&rgmiim1_pins>; - pinctrl-names = "default"; - snps,aal; - rx_delay = <0x18>; - tx_delay = <0x24>; - status = "okay"; - - mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - rtl8211e: ethernet-phy@1 { - reg = <1>; - pinctrl-0 = <&eth_phy_reset_pin>; - pinctrl-names = "default"; - reset-assert-us = <10000>; - reset-deassert-us = <50000>; - reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&i2c1 { - status = "okay"; - - rk805: pmic@18 { - compatible = "rockchip,rk805"; - reg = <0x18>; - interrupt-parent = <&gpio1>; - interrupts = <24 IRQ_TYPE_LEVEL_LOW>; - #clock-cells = <1>; - clock-output-names = "xin32k", "rk805-clkout2"; - gpio-controller; - #gpio-cells = <2>; - pinctrl-0 = <&pmic_int_l>; - pinctrl-names = "default"; - rockchip,system-power-controller; - wakeup-source; - - vcc1-supply = <&vcc_sys>; - vcc2-supply = <&vcc_sys>; - vcc3-supply = <&vcc_sys>; - vcc4-supply = <&vcc_sys>; - vcc5-supply = <&vcc_io>; - vcc6-supply = <&vcc_sys>; - - regulators { - vdd_log: DCDC_REG1 { - regulator-name = "vdd_log"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1450000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vdd_arm: DCDC_REG2 { - regulator-name = "vdd_arm"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1450000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <950000>; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_io: DCDC_REG4 { - regulator-name = "vcc_io"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc_18: LDO_REG1 { - regulator-name = "vcc_18"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc18_emmc: LDO_REG2 { - regulator-name = "vcc18_emmc"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vdd_10: LDO_REG3 { - regulator-name = "vdd_10"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - }; - }; -}; - -&io_domains { - pmuio-supply = <&vcc_io>; - vccio1-supply = <&vcc_io>; - vccio2-supply = <&vcc18_emmc>; - vccio3-supply = <&vcc_io>; - vccio4-supply = <&vcc_io>; - vccio5-supply = <&vcc_io>; - vccio6-supply = <&vcc_io>; - status = "okay"; -}; - -&pinctrl { - gmac2io { - eth_phy_reset_pin: eth-phy-reset-pin { - rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; - - leds { - lan_led_pin: lan-led-pin { - rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - sys_led_pin: sys-led-pin { - rockchip,pins = <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - wan_led_pin: wan-led-pin { - rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - lan { - lan_vdd_pin: lan-vdd-pin { - rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - pmic_int_l: pmic-int-l { - rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; -}; - -&pwm2 { - status = "okay"; -}; - -&sdmmc { - bus-width = <4>; - cap-sd-highspeed; - disable-wp; - pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>; - pinctrl-names = "default"; - vmmc-supply = <&vcc_sd>; - status = "okay"; -}; - -&spi0 { - status = "okay"; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <50000000>; - }; -}; - -&tsadc { - rockchip,hw-tshut-mode = <0>; - rockchip,hw-tshut-polarity = <0>; - status = "okay"; -}; - -&u2phy { - status = "okay"; -}; - -&u2phy_host { - status = "okay"; -}; - -&u2phy_otg { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&usb20_otg { - dr_mode = "host"; - status = "okay"; -}; - -&usbdrd3 { - dr_mode = "host"; - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - - /* Second port is for USB 3.0 */ - rtl8153: device@2 { - compatible = "usbbda,8153"; - reg = <2>; - }; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; diff --git a/arch/arm/dts/rk3328-roc-cc.dts b/arch/arm/dts/rk3328-roc-cc.dts deleted file mode 100644 index 414897a57e75..000000000000 --- a/arch/arm/dts/rk3328-roc-cc.dts +++ /dev/null @@ -1,384 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2017 T-Chip Intelligent Technology Co., Ltd - */ - -/dts-v1/; -#include "rk3328.dtsi" - -/ { - model = "Firefly roc-rk3328-cc"; - compatible = "firefly,roc-rk3328-cc", "rockchip,rk3328"; - - aliases { - ethernet0 = &gmac2io; - mmc0 = &sdmmc; - mmc1 = &emmc; - }; - - chosen { - stdout-path = "serial2:1500000n8"; - }; - - gmac_clkin: external-gmac-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "gmac_clkin"; - #clock-cells = <0>; - }; - - dc_12v: dc-12v { - compatible = "regulator-fixed"; - regulator-name = "dc_12v"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - vcc_sd: sdmmc-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc0m1_pin>; - regulator-boot-on; - regulator-name = "vcc_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_io>; - }; - - vcc_sdio: sdmmcio-regulator { - compatible = "regulator-gpio"; - gpios = <&grf_gpio 0 GPIO_ACTIVE_HIGH>; - states = <1800000 0x1>, - <3300000 0x0>; - regulator-name = "vcc_sdio"; - regulator-type = "voltage"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - vin-supply = <&vcc_sys>; - }; - - vcc_host1_5v: vcc_otg_5v: vcc-host1-5v-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&usb20_host_drv>; - regulator-name = "vcc_host1_5v"; - regulator-always-on; - vin-supply = <&vcc_sys>; - }; - - vcc_sys: vcc-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&dc_12v>; - }; - - vcc_phy: vcc-phy-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_phy"; - regulator-always-on; - regulator-boot-on; - }; - - leds { - compatible = "gpio-leds"; - - power_led: led-0 { - label = "firefly:blue:power"; - linux,default-trigger = "heartbeat"; - gpios = <&rk805 1 GPIO_ACTIVE_LOW>; - default-state = "on"; - }; - - user_led: led-1 { - label = "firefly:yellow:user"; - linux,default-trigger = "mmc1"; - gpios = <&rk805 0 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - }; -}; - -&analog_sound { - status = "okay"; -}; - -&codec { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <&vdd_arm>; -}; - -&cpu1 { - cpu-supply = <&vdd_arm>; -}; - -&cpu2 { - cpu-supply = <&vdd_arm>; -}; - -&cpu3 { - cpu-supply = <&vdd_arm>; -}; - -&emmc { - bus-width = <8>; - cap-mmc-highspeed; - max-frequency = <150000000>; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; - vmmc-supply = <&vcc_io>; - vqmmc-supply = <&vcc18_emmc>; - status = "okay"; -}; - -&gmac2io { - assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; - assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>; - clock_in_out = "input"; - phy-supply = <&vcc_phy>; - phy-mode = "rgmii"; - pinctrl-names = "default"; - pinctrl-0 = <&rgmiim1_pins>; - snps,aal; - snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 50000>; - snps,rxpbl = <0x4>; - snps,txpbl = <0x4>; - tx_delay = <0x24>; - rx_delay = <0x18>; - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmiphy { - status = "okay"; -}; - -&hdmi_sound { - status = "okay"; -}; - -&i2c1 { - status = "okay"; - - rk805: pmic@18 { - compatible = "rockchip,rk805"; - reg = <0x18>; - interrupt-parent = <&gpio1>; - interrupts = <24 IRQ_TYPE_LEVEL_LOW>; - #clock-cells = <1>; - clock-output-names = "xin32k", "rk805-clkout2"; - gpio-controller; - #gpio-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l>; - rockchip,system-power-controller; - wakeup-source; - - vcc1-supply = <&vcc_sys>; - vcc2-supply = <&vcc_sys>; - vcc3-supply = <&vcc_sys>; - vcc4-supply = <&vcc_sys>; - vcc5-supply = <&vcc_io>; - vcc6-supply = <&vcc_io>; - - regulators { - vdd_logic: DCDC_REG1 { - regulator-name = "vdd_logic"; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1450000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vdd_arm: DCDC_REG2 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1450000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <950000>; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_io: DCDC_REG4 { - regulator-name = "vcc_io"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc_18: LDO_REG1 { - regulator-name = "vcc_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc18_emmc: LDO_REG2 { - regulator-name = "vcc18_emmc"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vdd_10: LDO_REG3 { - regulator-name = "vdd_10"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - }; - }; -}; - -&i2s0 { - status = "okay"; -}; - -&i2s1 { - status = "okay"; -}; - -&io_domains { - status = "okay"; - - vccio1-supply = <&vcc_io>; - vccio2-supply = <&vcc18_emmc>; - vccio3-supply = <&vcc_sdio>; - vccio4-supply = <&vcc_18>; - vccio5-supply = <&vcc_io>; - vccio6-supply = <&vcc_io>; - pmuio-supply = <&vcc_io>; -}; - -&pinctrl { - pmic { - pmic_int_l: pmic-int-l { - rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - usb2 { - usb20_host_drv: usb20-host-drv { - rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - disable-wp; - max-frequency = <150000000>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-sdr104; - vmmc-supply = <&vcc_sd>; - vqmmc-supply = <&vcc_sdio>; - status = "okay"; -}; - -&tsadc { - status = "okay"; -}; - -&u2phy { - status = "okay"; -}; - -&u2phy_host { - status = "okay"; -}; - -&u2phy_otg { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&usb20_otg { - dr_mode = "host"; - status = "okay"; -}; - -&usbdrd3 { - dr_mode = "host"; - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&vop { - status = "okay"; -}; - -&vop_mmu { - status = "okay"; -}; diff --git a/arch/arm/dts/rk3328-rock-pi-e.dts b/arch/arm/dts/rk3328-rock-pi-e.dts deleted file mode 100644 index 3cda6c627b68..000000000000 --- a/arch/arm/dts/rk3328-rock-pi-e.dts +++ /dev/null @@ -1,445 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * (C) Copyright 2020 Chen-Yu Tsai wens@csie.org - * - * Based on ./rk3328-rock64.dts, which is - * - * Copyright (c) 2017 PINE64 - */ - -/dts-v1/; - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/input.h> -#include <dt-bindings/leds/common.h> -#include <dt-bindings/pinctrl/rockchip.h> - -#include "rk3328.dtsi" - -/ { - model = "Radxa ROCK Pi E"; - compatible = "radxa,rockpi-e", "rockchip,rk3328"; - - aliases { - ethernet0 = &gmac2io; - ethernet1 = &gmac2phy; - mmc0 = &sdmmc; - mmc1 = &emmc; - }; - - chosen { - stdout-path = "serial2:1500000n8"; - }; - - adc-keys { - compatible = "adc-keys"; - io-channels = <&saradc 0>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1750000>; - - /* This button is unpopulated out of the factory. */ - button-recovery { - label = "Recovery"; - linux,code = <KEY_VENDOR>; - press-threshold-microvolt = <10000>; - }; - }; - - gmac_clkin: external-gmac-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "gmac_clkin"; - #clock-cells = <0>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-0 = <&led_pin>; - pinctrl-names = "default"; - - led-0 { - color = <LED_COLOR_ID_BLUE>; - gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - }; - }; - - vcc_sd: sdmmc-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc0m1_pin>; - regulator-name = "vcc_sd"; - regulator-boot-on; - vin-supply = <&vcc_io>; - }; - - vcc_host_5v: vcc-host-5v-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&usb30_host_drv>; - enable-active-high; - regulator-name = "vcc_host_5v"; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_sys>; - }; - - vcc_sys: vcc-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - vcc_wifi: vcc-wifi-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_en>; - regulator-name = "vcc_wifi"; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_io>; - }; -}; - -&analog_sound { - status = "okay"; -}; - -&codec { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <&vdd_arm>; -}; - -&cpu1 { - cpu-supply = <&vdd_arm>; -}; - -&cpu2 { - cpu-supply = <&vdd_arm>; -}; - -&cpu3 { - cpu-supply = <&vdd_arm>; -}; - -&emmc { - bus-width = <8>; - cap-mmc-highspeed; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_bus8>; - vmmc-supply = <&vcc_io>; - vqmmc-supply = <&vcc18_emmc>; - status = "okay"; -}; - -&gmac2io { - assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; - assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>; - clock_in_out = "input"; - phy-handle = <&rtl8211e>; - phy-mode = "rgmii"; - phy-supply = <&vcc_io>; - pinctrl-names = "default"; - pinctrl-0 = <&rgmiim1_pins>; - snps,aal; - snps,rxpbl = <0x4>; - snps,txpbl = <0x4>; - tx_delay = <0x26>; - rx_delay = <0x11>; - status = "okay"; - - mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - rtl8211e: ethernet-phy@1 { - reg = <1>; - pinctrl-0 = <&eth_phy_int_pin>, <&eth_phy_reset_pin>; - pinctrl-names = "default"; - interrupt-parent = <&gpio1>; - interrupts = <24 IRQ_TYPE_LEVEL_LOW>; - reset-assert-us = <10000>; - reset-deassert-us = <50000>; - reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&gmac2phy { - status = "okay"; -}; - -&gpio0 { - gpio-line-names = - /* GPIO0_A0 - A7 */ - "", "", "", "", "", "", "", "", - /* GPIO0_B0 - B7 */ - "", "", "", "", "", "", "", "", - /* GPIO0_C0 - C7 */ - "", "", "", "", "", "", "", "", - /* GPIO0_D0 - D7 */ - "", "", "", "pin-15 [GPIO0_D3]", "", "", "", ""; -}; - -&gpio1 { - gpio-line-names = - /* GPIO1_A0 - A7 */ - "", "", "", "", "", "", "", "", - /* GPIO1_B0 - B7 */ - "", "", "", "", "", "", "", "", - /* GPIO1_C0 - C7 */ - "", "", "", "", "", "", "", "", - /* GPIO1_D0 - D7 */ - "", "", "", "", "pin-07 [GPIO1_D4]", "", "", ""; -}; - -&gpio2 { - gpio-line-names = - /* GPIO2_A0 - A7 */ - "pin-08 [GPIO2_A0]", "pin-10 [GPIO2_A1]", "pin-11 [GPIO2_A2]", - "pin-13 [GPIO2-A3]", "pin-27 [GPIO2_A4]", "pin-28 [GPIO2_A5]", - "pin-33 [GPIO2_A6]", "", - /* GPIO2_B0 - B7 */ - "", "", "", "", "pin-26 [GPIO2_B4]", "", "", "pin-36 [GPIO2_B7]", - /* GPIO2_C0 - C7 */ - "pin-32 [GPIO2_C0]", "pin-35 [GPIO2_C1]", "pin-12 [GPIO2_C2]", - "pin-38 [GPIO2_C3]", "pin-29 [GPIO2_C4]", "pin-31 [GPIO2_C5]", - "pin-37 [GPIO2_C6]", "pin-40 [GPIO2_C7]", - /* GPIO2_D0 - D7 */ - "", "", "", "", "", "", "", ""; -}; - -&gpio3 { - gpio-line-names = - /* GPIO3_A0 - A7 */ - "pin-23 [GPIO3_A0]", "pin-19 [GPIO3_A1]", "pin-21 [GPIO3_A2]", - "", "pin-03 [GPIO3_A4]", "", "pin-05 [GPIO3_A6]", "", - /* GPIO3_B0 - B7 */ - "pin-24 [GPIO3_B0]", "", "", "", "", "", "", "", - /* GPIO3_C0 - C7 */ - "", "", "", "", "", "", "", "", - /* GPIO3_D0 - D7 */ - "", "", "", "", "", "", "", ""; -}; - -&i2c1 { - status = "okay"; - - rk805: pmic@18 { - compatible = "rockchip,rk805"; - reg = <0x18>; - interrupt-parent = <&gpio2>; - interrupts = <6 IRQ_TYPE_LEVEL_LOW>; - #clock-cells = <1>; - clock-output-names = "xin32k", "rk805-clkout2"; - gpio-controller; - #gpio-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l>; - rockchip,system-power-controller; - wakeup-source; - - vcc1-supply = <&vcc_sys>; - vcc2-supply = <&vcc_sys>; - vcc3-supply = <&vcc_sys>; - vcc4-supply = <&vcc_sys>; - vcc5-supply = <&vcc_io>; - vcc6-supply = <&vcc_sys>; - - regulators { - vdd_log: DCDC_REG1 { - regulator-name = "vdd_log"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1450000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vdd_arm: DCDC_REG2 { - regulator-name = "vdd_arm"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1450000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <950000>; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_io: DCDC_REG4 { - regulator-name = "vcc_io"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc_18: LDO_REG1 { - regulator-name = "vcc_18"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc18_emmc: LDO_REG2 { - regulator-name = "vcc18_emmc"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vdd_10: LDO_REG3 { - regulator-name = "vdd_10"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - }; - }; -}; - -&i2s1 { - status = "okay"; -}; - -&io_domains { - pmuio-supply = <&vcc_io>; - vccio1-supply = <&vcc_io>; - vccio2-supply = <&vcc18_emmc>; - vccio3-supply = <&vcc_io>; - vccio4-supply = <&vcc_io>; - vccio5-supply = <&vcc_io>; - vccio6-supply = <&vcc_io>; - status = "okay"; -}; - -&pinctrl { - ephy { - eth_phy_int_pin: eth-phy-int-pin { - rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - eth_phy_reset_pin: eth-phy-reset-pin { - rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; - - leds { - led_pin: led-pin { - rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - pmic_int_l: pmic-int-l { - rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - usb3 { - usb30_host_drv: usb30-host-drv { - rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - wifi { - wifi_en: wifi-en { - rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&sdmmc { - bus-width = <4>; - cap-sd-highspeed; - disable-wp; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>; - vmmc-supply = <&vcc_sd>; - status = "okay"; -}; - -&saradc { - vref-supply = <&vcc_18>; - status = "okay"; -}; - -&tsadc { - status = "okay"; -}; - -&u2phy { - status = "okay"; -}; - -&u2phy_host { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&usbdrd3 { - dr_mode = "host"; - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; diff --git a/arch/arm/dts/rk3328-rock64.dts b/arch/arm/dts/rk3328-rock64.dts deleted file mode 100644 index 229fe9da9c2d..000000000000 --- a/arch/arm/dts/rk3328-rock64.dts +++ /dev/null @@ -1,394 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2017 PINE64 - */ - -/dts-v1/; -#include "rk3328.dtsi" - -/ { - model = "Pine64 Rock64"; - compatible = "pine64,rock64", "rockchip,rk3328"; - - aliases { - ethernet0 = &gmac2io; - mmc0 = &sdmmc; - mmc1 = &emmc; - }; - - chosen { - stdout-path = "serial2:1500000n8"; - }; - - gmac_clkin: external-gmac-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "gmac_clkin"; - #clock-cells = <0>; - }; - - vcc_sd: sdmmc-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc0m1_pin>; - regulator-name = "vcc_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_io>; - }; - - /* Common enable line for all of the rails mentioned in the labels */ - vcc_host_5v: vcc_host1_5v: vcc_otg_5v: vcc-host-5v-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&usb20_host_drv>; - regulator-name = "vcc_host_5v"; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_sys>; - }; - - vcc_sys: vcc-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - ir-receiver { - compatible = "gpio-ir-receiver"; - gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&ir_int>; - pinctrl-names = "default"; - }; - - leds { - compatible = "gpio-leds"; - - power_led: led-0 { - gpios = <&rk805 1 GPIO_ACTIVE_LOW>; - linux,default-trigger = "mmc0"; - }; - - standby_led: led-1 { - gpios = <&rk805 0 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - }; - }; - - spdif_sound: spdif-sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "SPDIF"; - - simple-audio-card,cpu { - sound-dai = <&spdif>; - }; - - simple-audio-card,codec { - sound-dai = <&spdif_dit>; - }; - }; - - spdif_dit: spdif-dit { - compatible = "linux,spdif-dit"; - #sound-dai-cells = <0>; - }; -}; - -&analog_sound { - status = "okay"; -}; - -&codec { - mute-gpios = <&grf_gpio 0 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&cpu0 { - cpu-supply = <&vdd_arm>; -}; - -&cpu1 { - cpu-supply = <&vdd_arm>; -}; - -&cpu2 { - cpu-supply = <&vdd_arm>; -}; - -&cpu3 { - cpu-supply = <&vdd_arm>; -}; - -&emmc { - bus-width = <8>; - cap-mmc-highspeed; - mmc-hs200-1_8v; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; - vmmc-supply = <&vcc_io>; - vqmmc-supply = <&vcc18_emmc>; - status = "okay"; -}; - -&gmac2io { - assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; - assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>; - clock_in_out = "input"; - phy-supply = <&vcc_io>; - phy-mode = "rgmii"; - pinctrl-names = "default"; - pinctrl-0 = <&rgmiim1_pins>; - snps,force_thresh_dma_mode; - snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 50000>; - tx_delay = <0x24>; - rx_delay = <0x18>; - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_sound { - status = "okay"; -}; - -&hdmiphy { - status = "okay"; -}; - -&i2c1 { - status = "okay"; - - rk805: pmic@18 { - compatible = "rockchip,rk805"; - reg = <0x18>; - interrupt-parent = <&gpio2>; - interrupts = <6 IRQ_TYPE_LEVEL_LOW>; - #clock-cells = <1>; - clock-output-names = "xin32k", "rk805-clkout2"; - gpio-controller; - #gpio-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l>; - rockchip,system-power-controller; - wakeup-source; - - vcc1-supply = <&vcc_sys>; - vcc2-supply = <&vcc_sys>; - vcc3-supply = <&vcc_sys>; - vcc4-supply = <&vcc_sys>; - vcc5-supply = <&vcc_io>; - vcc6-supply = <&vcc_sys>; - - regulators { - vdd_logic: DCDC_REG1 { - regulator-name = "vdd_logic"; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1450000>; - regulator-ramp-delay = <12500>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vdd_arm: DCDC_REG2 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1450000>; - regulator-ramp-delay = <12500>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <950000>; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_io: DCDC_REG4 { - regulator-name = "vcc_io"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc_18: LDO_REG1 { - regulator-name = "vcc_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc18_emmc: LDO_REG2 { - regulator-name = "vcc18_emmc"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vdd_10: LDO_REG3 { - regulator-name = "vdd_10"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - }; - }; -}; - -&i2s0 { - status = "okay"; -}; - -&i2s1 { - status = "okay"; -}; - -&io_domains { - status = "okay"; - - vccio1-supply = <&vcc_io>; - vccio2-supply = <&vcc18_emmc>; - vccio3-supply = <&vcc_io>; - vccio4-supply = <&vcc_18>; - vccio5-supply = <&vcc_io>; - vccio6-supply = <&vcc_io>; - pmuio-supply = <&vcc_io>; -}; - -&pinctrl { - ir { - ir_int: ir-int { - rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - pmic_int_l: pmic-int-l { - rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - usb2 { - usb20_host_drv: usb20-host-drv { - rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - disable-wp; - max-frequency = <150000000>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>; - vmmc-supply = <&vcc_sd>; - status = "okay"; -}; - -&spdif { - pinctrl-0 = <&spdifm0_tx>; - status = "okay"; -}; - -&spi0 { - status = "okay"; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - - /* maximum speed for Rockchip SPI */ - spi-max-frequency = <50000000>; - }; -}; - -&tsadc { - rockchip,hw-tshut-mode = <0>; - rockchip,hw-tshut-polarity = <0>; - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&u2phy { - status = "okay"; - - u2phy_host: host-port { - status = "okay"; - }; - - u2phy_otg: otg-port { - status = "okay"; - }; -}; - -&usb20_otg { - dr_mode = "host"; - status = "okay"; -}; - -&usbdrd3 { - dr_mode = "host"; - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&vop { - status = "okay"; -}; - -&vop_mmu { - status = "okay"; -}; diff --git a/arch/arm/dts/rk3328.dtsi b/arch/arm/dts/rk3328.dtsi deleted file mode 100644 index fb5dcf6e9327..000000000000 --- a/arch/arm/dts/rk3328.dtsi +++ /dev/null @@ -1,1944 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd - */ - -#include <dt-bindings/clock/rk3328-cru.h> -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/pinctrl/rockchip.h> -#include <dt-bindings/power/rk3328-power.h> -#include <dt-bindings/soc/rockchip,boot-mode.h> -#include <dt-bindings/thermal/thermal.h> - -/ { - compatible = "rockchip,rk3328"; - - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - gpio0 = &gpio0; - gpio1 = &gpio1; - gpio2 = &gpio2; - gpio3 = &gpio3; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - }; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x0>; - clocks = <&cru ARMCLK>; - #cooling-cells = <2>; - cpu-idle-states = <&CPU_SLEEP>; - dynamic-power-coefficient = <120>; - enable-method = "psci"; - next-level-cache = <&l2>; - operating-points-v2 = <&cpu0_opp_table>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x1>; - clocks = <&cru ARMCLK>; - #cooling-cells = <2>; - cpu-idle-states = <&CPU_SLEEP>; - dynamic-power-coefficient = <120>; - enable-method = "psci"; - next-level-cache = <&l2>; - operating-points-v2 = <&cpu0_opp_table>; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x2>; - clocks = <&cru ARMCLK>; - #cooling-cells = <2>; - cpu-idle-states = <&CPU_SLEEP>; - dynamic-power-coefficient = <120>; - enable-method = "psci"; - next-level-cache = <&l2>; - operating-points-v2 = <&cpu0_opp_table>; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x3>; - clocks = <&cru ARMCLK>; - #cooling-cells = <2>; - cpu-idle-states = <&CPU_SLEEP>; - dynamic-power-coefficient = <120>; - enable-method = "psci"; - next-level-cache = <&l2>; - operating-points-v2 = <&cpu0_opp_table>; - }; - - idle-states { - entry-method = "psci"; - - CPU_SLEEP: cpu-sleep { - compatible = "arm,idle-state"; - local-timer-stop; - arm,psci-suspend-param = <0x0010000>; - entry-latency-us = <120>; - exit-latency-us = <250>; - min-residency-us = <900>; - }; - }; - - l2: l2-cache0 { - compatible = "cache"; - cache-level = <2>; - cache-unified; - }; - }; - - cpu0_opp_table: opp-table-0 { - compatible = "operating-points-v2"; - opp-shared; - - opp-408000000 { - opp-hz = /bits/ 64 <408000000>; - opp-microvolt = <950000>; - clock-latency-ns = <40000>; - opp-suspend; - }; - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <950000>; - clock-latency-ns = <40000>; - }; - opp-816000000 { - opp-hz = /bits/ 64 <816000000>; - opp-microvolt = <1000000>; - clock-latency-ns = <40000>; - }; - opp-1008000000 { - opp-hz = /bits/ 64 <1008000000>; - opp-microvolt = <1100000>; - clock-latency-ns = <40000>; - }; - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <1225000>; - clock-latency-ns = <40000>; - }; - opp-1296000000 { - opp-hz = /bits/ 64 <1296000000>; - opp-microvolt = <1300000>; - clock-latency-ns = <40000>; - }; - }; - - analog_sound: analog-sound { - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,mclk-fs = <256>; - simple-audio-card,name = "Analog"; - status = "disabled"; - - simple-audio-card,cpu { - sound-dai = <&i2s1>; - }; - - simple-audio-card,codec { - sound-dai = <&codec>; - }; - }; - - arm-pmu { - compatible = "arm,cortex-a53-pmu"; - interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; - }; - - display_subsystem: display-subsystem { - compatible = "rockchip,display-subsystem"; - ports = <&vop_out>; - }; - - hdmi_sound: hdmi-sound { - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,mclk-fs = <128>; - simple-audio-card,name = "HDMI"; - status = "disabled"; - - simple-audio-card,cpu { - sound-dai = <&i2s0>; - }; - - simple-audio-card,codec { - sound-dai = <&hdmi>; - }; - }; - - psci { - compatible = "arm,psci-1.0", "arm,psci-0.2"; - method = "smc"; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; - }; - - xin24m: xin24m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "xin24m"; - }; - - i2s0: i2s@ff000000 { - compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; - reg = <0x0 0xff000000 0x0 0x1000>; - interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>; - clock-names = "i2s_clk", "i2s_hclk"; - dmas = <&dmac 11>, <&dmac 12>; - dma-names = "tx", "rx"; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - i2s1: i2s@ff010000 { - compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; - reg = <0x0 0xff010000 0x0 0x1000>; - interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>; - clock-names = "i2s_clk", "i2s_hclk"; - dmas = <&dmac 14>, <&dmac 15>; - dma-names = "tx", "rx"; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - i2s2: i2s@ff020000 { - compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; - reg = <0x0 0xff020000 0x0 0x1000>; - interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>; - clock-names = "i2s_clk", "i2s_hclk"; - dmas = <&dmac 0>, <&dmac 1>; - dma-names = "tx", "rx"; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - spdif: spdif@ff030000 { - compatible = "rockchip,rk3328-spdif"; - reg = <0x0 0xff030000 0x0 0x1000>; - interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>; - clock-names = "mclk", "hclk"; - dmas = <&dmac 10>; - dma-names = "tx"; - pinctrl-names = "default"; - pinctrl-0 = <&spdifm2_tx>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - pdm: pdm@ff040000 { - compatible = "rockchip,pdm"; - reg = <0x0 0xff040000 0x0 0x1000>; - clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>; - clock-names = "pdm_clk", "pdm_hclk"; - dmas = <&dmac 16>; - dma-names = "rx"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&pdmm0_clk - &pdmm0_sdi0 - &pdmm0_sdi1 - &pdmm0_sdi2 - &pdmm0_sdi3>; - pinctrl-1 = <&pdmm0_clk_sleep - &pdmm0_sdi0_sleep - &pdmm0_sdi1_sleep - &pdmm0_sdi2_sleep - &pdmm0_sdi3_sleep>; - status = "disabled"; - }; - - grf: syscon@ff100000 { - compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd"; - reg = <0x0 0xff100000 0x0 0x1000>; - - io_domains: io-domains { - compatible = "rockchip,rk3328-io-voltage-domain"; - status = "disabled"; - }; - - grf_gpio: gpio { - compatible = "rockchip,rk3328-grf-gpio"; - gpio-controller; - #gpio-cells = <2>; - }; - - power: power-controller { - compatible = "rockchip,rk3328-power-controller"; - #power-domain-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - - power-domain@RK3328_PD_HEVC { - reg = <RK3328_PD_HEVC>; - #power-domain-cells = <0>; - }; - power-domain@RK3328_PD_VIDEO { - reg = <RK3328_PD_VIDEO>; - clocks = <&cru ACLK_RKVDEC>, - <&cru HCLK_RKVDEC>, - <&cru SCLK_VDEC_CABAC>, - <&cru SCLK_VDEC_CORE>; - #power-domain-cells = <0>; - }; - power-domain@RK3328_PD_VPU { - reg = <RK3328_PD_VPU>; - clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; - #power-domain-cells = <0>; - }; - }; - - reboot-mode { - compatible = "syscon-reboot-mode"; - offset = <0x5c8>; - mode-normal = <BOOT_NORMAL>; - mode-recovery = <BOOT_RECOVERY>; - mode-bootloader = <BOOT_FASTBOOT>; - mode-loader = <BOOT_BL_DOWNLOAD>; - }; - }; - - uart0: serial@ff110000 { - compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; - reg = <0x0 0xff110000 0x0 0x100>; - interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac 2>, <&dmac 3>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart1: serial@ff120000 { - compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; - reg = <0x0 0xff120000 0x0 0x100>; - interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac 4>, <&dmac 5>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart2: serial@ff130000 { - compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; - reg = <0x0 0xff130000 0x0 0x100>; - interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac 6>, <&dmac 7>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&uart2m1_xfer>; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - i2c0: i2c@ff150000 { - compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xff150000 0x0 0x1000>; - interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>; - clock-names = "i2c", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_xfer>; - status = "disabled"; - }; - - i2c1: i2c@ff160000 { - compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xff160000 0x0 0x1000>; - interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; - clock-names = "i2c", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_xfer>; - status = "disabled"; - }; - - i2c2: i2c@ff170000 { - compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xff170000 0x0 0x1000>; - interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; - clock-names = "i2c", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_xfer>; - status = "disabled"; - }; - - i2c3: i2c@ff180000 { - compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xff180000 0x0 0x1000>; - interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; - clock-names = "i2c", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_xfer>; - status = "disabled"; - }; - - spi0: spi@ff190000 { - compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi"; - reg = <0x0 0xff190000 0x0 0x1000>; - interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>; - clock-names = "spiclk", "apb_pclk"; - dmas = <&dmac 8>, <&dmac 9>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>; - status = "disabled"; - }; - - wdt: watchdog@ff1a0000 { - compatible = "rockchip,rk3328-wdt", "snps,dw-wdt"; - reg = <0x0 0xff1a0000 0x0 0x100>; - interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_WDT>; - }; - - pwm0: pwm@ff1b0000 { - compatible = "rockchip,rk3328-pwm"; - reg = <0x0 0xff1b0000 0x0 0x10>; - clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; - clock-names = "pwm", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pin>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm1: pwm@ff1b0010 { - compatible = "rockchip,rk3328-pwm"; - reg = <0x0 0xff1b0010 0x0 0x10>; - clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; - clock-names = "pwm", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm1_pin>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm2: pwm@ff1b0020 { - compatible = "rockchip,rk3328-pwm"; - reg = <0x0 0xff1b0020 0x0 0x10>; - clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; - clock-names = "pwm", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm2_pin>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm3: pwm@ff1b0030 { - compatible = "rockchip,rk3328-pwm"; - reg = <0x0 0xff1b0030 0x0 0x10>; - interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; - clock-names = "pwm", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&pwmir_pin>; - #pwm-cells = <3>; - status = "disabled"; - }; - - dmac: dma-controller@ff1f0000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x0 0xff1f0000 0x0 0x4000>; - interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; - arm,pl330-periph-burst; - clocks = <&cru ACLK_DMAC>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - }; - - thermal-zones { - soc_thermal: soc-thermal { - polling-delay-passive = <20>; - polling-delay = <1000>; - sustainable-power = <1000>; - - thermal-sensors = <&tsadc 0>; - - trips { - threshold: trip-point0 { - temperature = <70000>; - hysteresis = <2000>; - type = "passive"; - }; - target: trip-point1 { - temperature = <85000>; - hysteresis = <2000>; - type = "passive"; - }; - soc_crit: soc-crit { - temperature = <95000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&target>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - contribution = <4096>; - }; - }; - }; - - }; - - tsadc: tsadc@ff250000 { - compatible = "rockchip,rk3328-tsadc"; - reg = <0x0 0xff250000 0x0 0x100>; - interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; - assigned-clocks = <&cru SCLK_TSADC>; - assigned-clock-rates = <50000>; - clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; - clock-names = "tsadc", "apb_pclk"; - pinctrl-names = "init", "default", "sleep"; - pinctrl-0 = <&otp_pin>; - pinctrl-1 = <&otp_out>; - pinctrl-2 = <&otp_pin>; - resets = <&cru SRST_TSADC>; - reset-names = "tsadc-apb"; - rockchip,grf = <&grf>; - rockchip,hw-tshut-temp = <100000>; - #thermal-sensor-cells = <1>; - status = "disabled"; - }; - - efuse: efuse@ff260000 { - compatible = "rockchip,rk3328-efuse"; - reg = <0x0 0xff260000 0x0 0x50>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&cru SCLK_EFUSE>; - clock-names = "pclk_efuse"; - rockchip,efuse-size = <0x20>; - - /* Data cells */ - efuse_id: id@7 { - reg = <0x07 0x10>; - }; - cpu_leakage: cpu-leakage@17 { - reg = <0x17 0x1>; - }; - logic_leakage: logic-leakage@19 { - reg = <0x19 0x1>; - }; - efuse_cpu_version: cpu-version@1a { - reg = <0x1a 0x1>; - bits = <3 3>; - }; - }; - - saradc: adc@ff280000 { - compatible = "rockchip,rk3328-saradc", "rockchip,rk3399-saradc"; - reg = <0x0 0xff280000 0x0 0x100>; - interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; - #io-channel-cells = <1>; - clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; - clock-names = "saradc", "apb_pclk"; - resets = <&cru SRST_SARADC_P>; - reset-names = "saradc-apb"; - status = "disabled"; - }; - - gpu: gpu@ff300000 { - compatible = "rockchip,rk3328-mali", "arm,mali-450"; - reg = <0x0 0xff300000 0x0 0x30000>; - interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "gp", - "gpmmu", - "pp", - "pp0", - "ppmmu0", - "pp1", - "ppmmu1"; - clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>; - clock-names = "bus", "core"; - resets = <&cru SRST_GPU_A>; - }; - - h265e_mmu: iommu@ff330200 { - compatible = "rockchip,iommu"; - reg = <0x0 0xff330200 0 0x100>; - interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru ACLK_H265>, <&cru PCLK_H265>; - clock-names = "aclk", "iface"; - #iommu-cells = <0>; - status = "disabled"; - }; - - vepu_mmu: iommu@ff340800 { - compatible = "rockchip,iommu"; - reg = <0x0 0xff340800 0x0 0x40>; - interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; - clock-names = "aclk", "iface"; - #iommu-cells = <0>; - status = "disabled"; - }; - - vpu: video-codec@ff350000 { - compatible = "rockchip,rk3328-vpu"; - reg = <0x0 0xff350000 0x0 0x800>; - interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "vdpu"; - clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; - clock-names = "aclk", "hclk"; - iommus = <&vpu_mmu>; - power-domains = <&power RK3328_PD_VPU>; - }; - - vpu_mmu: iommu@ff350800 { - compatible = "rockchip,iommu"; - reg = <0x0 0xff350800 0x0 0x40>; - interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; - clock-names = "aclk", "iface"; - #iommu-cells = <0>; - power-domains = <&power RK3328_PD_VPU>; - }; - - vdec: video-codec@ff360000 { - compatible = "rockchip,rk3328-vdec", "rockchip,rk3399-vdec"; - reg = <0x0 0xff360000 0x0 0x480>; - interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>, - <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>; - clock-names = "axi", "ahb", "cabac", "core"; - assigned-clocks = <&cru ACLK_RKVDEC>, <&cru SCLK_VDEC_CABAC>, - <&cru SCLK_VDEC_CORE>; - assigned-clock-rates = <400000000>, <400000000>, <300000000>; - iommus = <&vdec_mmu>; - power-domains = <&power RK3328_PD_VIDEO>; - }; - - vdec_mmu: iommu@ff360480 { - compatible = "rockchip,iommu"; - reg = <0x0 0xff360480 0x0 0x40>, <0x0 0xff3604c0 0x0 0x40>; - interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>; - clock-names = "aclk", "iface"; - #iommu-cells = <0>; - power-domains = <&power RK3328_PD_VIDEO>; - }; - - vop: vop@ff370000 { - compatible = "rockchip,rk3328-vop"; - reg = <0x0 0xff370000 0x0 0x3efc>; - interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru ACLK_VOP>, <&cru DCLK_LCDC>, <&cru HCLK_VOP>; - clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; - resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>; - reset-names = "axi", "ahb", "dclk"; - iommus = <&vop_mmu>; - status = "disabled"; - - vop_out: port { - #address-cells = <1>; - #size-cells = <0>; - - vop_out_hdmi: endpoint@0 { - reg = <0>; - remote-endpoint = <&hdmi_in_vop>; - }; - }; - }; - - vop_mmu: iommu@ff373f00 { - compatible = "rockchip,iommu"; - reg = <0x0 0xff373f00 0x0 0x100>; - interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; - clock-names = "aclk", "iface"; - #iommu-cells = <0>; - status = "disabled"; - }; - - hdmi: hdmi@ff3c0000 { - compatible = "rockchip,rk3328-dw-hdmi"; - reg = <0x0 0xff3c0000 0x0 0x20000>; - reg-io-width = <4>; - interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_HDMI>, - <&cru SCLK_HDMI_SFC>, - <&cru SCLK_RTC32K>; - clock-names = "iahb", - "isfr", - "cec"; - phys = <&hdmiphy>; - phy-names = "hdmi"; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_cec &hdmii2c_xfer &hdmi_hpd>; - rockchip,grf = <&grf>; - #sound-dai-cells = <0>; - status = "disabled"; - - ports { - hdmi_in: port { - hdmi_in_vop: endpoint { - remote-endpoint = <&vop_out_hdmi>; - }; - }; - }; - }; - - codec: codec@ff410000 { - compatible = "rockchip,rk3328-codec"; - reg = <0x0 0xff410000 0x0 0x1000>; - clocks = <&cru PCLK_ACODECPHY>, <&cru SCLK_I2S1>; - clock-names = "pclk", "mclk"; - rockchip,grf = <&grf>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - hdmiphy: phy@ff430000 { - compatible = "rockchip,rk3328-hdmi-phy"; - reg = <0x0 0xff430000 0x0 0x10000>; - interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_HDMIPHY>, <&xin24m>, <&cru DCLK_HDMIPHY>; - clock-names = "sysclk", "refoclk", "refpclk"; - clock-output-names = "hdmi_phy"; - #clock-cells = <0>; - nvmem-cells = <&efuse_cpu_version>; - nvmem-cell-names = "cpu-version"; - #phy-cells = <0>; - status = "disabled"; - }; - - cru: clock-controller@ff440000 { - compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon"; - reg = <0x0 0xff440000 0x0 0x1000>; - rockchip,grf = <&grf>; - #clock-cells = <1>; - #reset-cells = <1>; - assigned-clocks = - /* - * CPLL should run at 1200, but that is to high for - * the initial dividers of most of its children. - * We need set cpll child clk div first, - * and then set the cpll frequency. - */ - <&cru DCLK_LCDC>, <&cru SCLK_PDM>, - <&cru SCLK_RTC32K>, <&cru SCLK_UART0>, - <&cru SCLK_UART1>, <&cru SCLK_UART2>, - <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, - <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>, - <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>, - <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>, - <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>, - <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>, - <&cru SCLK_SDIO>, <&cru SCLK_TSP>, - <&cru SCLK_WIFI>, <&cru ARMCLK>, - <&cru PLL_GPLL>, <&cru PLL_CPLL>, - <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>, - <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, - <&cru HCLK_PERI>, <&cru PCLK_PERI>, - <&cru SCLK_RTC32K>; - assigned-clock-parents = - <&cru HDMIPHY>, <&cru PLL_APLL>, - <&cru PLL_GPLL>, <&xin24m>, - <&xin24m>, <&xin24m>; - assigned-clock-rates = - <0>, <61440000>, - <0>, <24000000>, - <24000000>, <24000000>, - <15000000>, <15000000>, - <100000000>, <100000000>, - <100000000>, <100000000>, - <50000000>, <100000000>, - <100000000>, <100000000>, - <50000000>, <50000000>, - <50000000>, <50000000>, - <24000000>, <600000000>, - <491520000>, <1200000000>, - <150000000>, <75000000>, - <75000000>, <150000000>, - <75000000>, <75000000>, - <32768>; - }; - - usb2phy_grf: syscon@ff450000 { - compatible = "rockchip,rk3328-usb2phy-grf", "syscon", - "simple-mfd"; - reg = <0x0 0xff450000 0x0 0x10000>; - #address-cells = <1>; - #size-cells = <1>; - - u2phy: usb2phy@100 { - compatible = "rockchip,rk3328-usb2phy"; - reg = <0x100 0x10>; - clocks = <&xin24m>; - clock-names = "phyclk"; - clock-output-names = "usb480m_phy"; - #clock-cells = <0>; - assigned-clocks = <&cru USB480M>; - assigned-clock-parents = <&u2phy>; - status = "disabled"; - - u2phy_otg: otg-port { - #phy-cells = <0>; - interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "otg-bvalid", "otg-id", - "linestate"; - status = "disabled"; - }; - - u2phy_host: host-port { - #phy-cells = <0>; - interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "linestate"; - status = "disabled"; - }; - }; - }; - - sdmmc: mmc@ff500000 { - compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x0 0xff500000 0x0 0x4000>; - interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, - <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - max-frequency = <150000000>; - status = "disabled"; - }; - - sdio: mmc@ff510000 { - compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x0 0xff510000 0x0 0x4000>; - interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, - <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - max-frequency = <150000000>; - status = "disabled"; - }; - - emmc: mmc@ff520000 { - compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x0 0xff520000 0x0 0x4000>; - interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, - <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - max-frequency = <150000000>; - status = "disabled"; - }; - - gmac2io: ethernet@ff540000 { - compatible = "rockchip,rk3328-gmac"; - reg = <0x0 0xff540000 0x0 0x10000>; - interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "macirq"; - clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>, - <&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>, - <&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>, - <&cru PCLK_MAC2IO>; - clock-names = "stmmaceth", "mac_clk_rx", - "mac_clk_tx", "clk_mac_ref", - "clk_mac_refout", "aclk_mac", - "pclk_mac"; - resets = <&cru SRST_GMAC2IO_A>; - reset-names = "stmmaceth"; - rockchip,grf = <&grf>; - tx-fifo-depth = <2048>; - rx-fifo-depth = <4096>; - snps,txpbl = <0x4>; - status = "disabled"; - }; - - gmac2phy: ethernet@ff550000 { - compatible = "rockchip,rk3328-gmac"; - reg = <0x0 0xff550000 0x0 0x10000>; - rockchip,grf = <&grf>; - interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "macirq"; - clocks = <&cru SCLK_MAC2PHY_SRC>, <&cru SCLK_MAC2PHY_RXTX>, - <&cru SCLK_MAC2PHY_RXTX>, <&cru SCLK_MAC2PHY_REF>, - <&cru ACLK_MAC2PHY>, <&cru PCLK_MAC2PHY>, - <&cru SCLK_MAC2PHY_OUT>; - clock-names = "stmmaceth", "mac_clk_rx", - "mac_clk_tx", "clk_mac_ref", - "aclk_mac", "pclk_mac", - "clk_macphy"; - resets = <&cru SRST_GMAC2PHY_A>; - reset-names = "stmmaceth"; - phy-mode = "rmii"; - phy-handle = <&phy>; - tx-fifo-depth = <2048>; - rx-fifo-depth = <4096>; - snps,txpbl = <0x4>; - clock_in_out = "output"; - status = "disabled"; - - mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - phy: ethernet-phy@0 { - compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22"; - reg = <0>; - clocks = <&cru SCLK_MAC2PHY_OUT>; - resets = <&cru SRST_MACPHY>; - pinctrl-names = "default"; - pinctrl-0 = <&fephyled_rxm1 &fephyled_linkm1>; - phy-is-integrated; - }; - }; - }; - - usb20_otg: usb@ff580000 { - compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb", - "snps,dwc2"; - reg = <0x0 0xff580000 0x0 0x40000>; - interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru HCLK_OTG>; - clock-names = "otg"; - dr_mode = "otg"; - g-np-tx-fifo-size = <16>; - g-rx-fifo-size = <280>; - g-tx-fifo-size = <256 128 128 64 32 16>; - phys = <&u2phy_otg>; - phy-names = "usb2-phy"; - status = "disabled"; - }; - - usb_host0_ehci: usb@ff5c0000 { - compatible = "generic-ehci"; - reg = <0x0 0xff5c0000 0x0 0x10000>; - interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru HCLK_HOST0>, <&u2phy>; - phys = <&u2phy_host>; - phy-names = "usb"; - status = "disabled"; - }; - - usb_host0_ohci: usb@ff5d0000 { - compatible = "generic-ohci"; - reg = <0x0 0xff5d0000 0x0 0x10000>; - interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru HCLK_HOST0>, <&u2phy>; - phys = <&u2phy_host>; - phy-names = "usb"; - status = "disabled"; - }; - - usbdrd3: usb@ff600000 { - compatible = "rockchip,rk3328-dwc3", "snps,dwc3"; - reg = <0x0 0xff600000 0x0 0x100000>; - interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru SCLK_USB3OTG_REF>, <&cru SCLK_USB3OTG_SUSPEND>, - <&cru ACLK_USB3OTG>; - clock-names = "ref_clk", "suspend_clk", - "bus_clk"; - dr_mode = "otg"; - phy_type = "utmi_wide"; - snps,dis-del-phy-power-chg-quirk; - snps,dis_enblslpm_quirk; - snps,dis-tx-ipgap-linecheck-quirk; - snps,dis-u2-freeclk-exists-quirk; - snps,dis_u2_susphy_quirk; - snps,dis_u3_susphy_quirk; - status = "disabled"; - }; - - gic: interrupt-controller@ff811000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x0 0xff811000 0 0x1000>, - <0x0 0xff812000 0 0x2000>, - <0x0 0xff814000 0 0x2000>, - <0x0 0xff816000 0 0x2000>; - interrupts = <GIC_PPI 9 - (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; - }; - - crypto: crypto@ff060000 { - compatible = "rockchip,rk3328-crypto"; - reg = <0x0 0xff060000 0x0 0x4000>; - interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru HCLK_CRYPTO_MST>, <&cru HCLK_CRYPTO_SLV>, - <&cru SCLK_CRYPTO>; - clock-names = "hclk_master", "hclk_slave", "sclk"; - resets = <&cru SRST_CRYPTO>; - reset-names = "crypto-rst"; - }; - - pinctrl: pinctrl { - compatible = "rockchip,rk3328-pinctrl"; - rockchip,grf = <&grf>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - gpio0: gpio@ff210000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff210000 0x0 0x100>; - interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_GPIO0>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio@ff220000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff220000 0x0 0x100>; - interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_GPIO1>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@ff230000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff230000 0x0 0x100>; - interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_GPIO2>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio@ff240000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff240000 0x0 0x100>; - interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_GPIO3>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - pcfg_pull_up: pcfg-pull-up { - bias-pull-up; - }; - - pcfg_pull_down: pcfg-pull-down { - bias-pull-down; - }; - - pcfg_pull_none: pcfg-pull-none { - bias-disable; - }; - - pcfg_pull_none_2ma: pcfg-pull-none-2ma { - bias-disable; - drive-strength = <2>; - }; - - pcfg_pull_up_2ma: pcfg-pull-up-2ma { - bias-pull-up; - drive-strength = <2>; - }; - - pcfg_pull_up_4ma: pcfg-pull-up-4ma { - bias-pull-up; - drive-strength = <4>; - }; - - pcfg_pull_none_4ma: pcfg-pull-none-4ma { - bias-disable; - drive-strength = <4>; - }; - - pcfg_pull_down_4ma: pcfg-pull-down-4ma { - bias-pull-down; - drive-strength = <4>; - }; - - pcfg_pull_none_8ma: pcfg-pull-none-8ma { - bias-disable; - drive-strength = <8>; - }; - - pcfg_pull_up_8ma: pcfg-pull-up-8ma { - bias-pull-up; - drive-strength = <8>; - }; - - pcfg_pull_none_12ma: pcfg-pull-none-12ma { - bias-disable; - drive-strength = <12>; - }; - - pcfg_pull_up_12ma: pcfg-pull-up-12ma { - bias-pull-up; - drive-strength = <12>; - }; - - pcfg_output_high: pcfg-output-high { - output-high; - }; - - pcfg_output_low: pcfg-output-low { - output-low; - }; - - pcfg_input_high: pcfg-input-high { - bias-pull-up; - input-enable; - }; - - pcfg_input: pcfg-input { - input-enable; - }; - - i2c0 { - i2c0_xfer: i2c0-xfer { - rockchip,pins = <2 RK_PD0 1 &pcfg_pull_none>, - <2 RK_PD1 1 &pcfg_pull_none>; - }; - }; - - i2c1 { - i2c1_xfer: i2c1-xfer { - rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>, - <2 RK_PA5 2 &pcfg_pull_none>; - }; - }; - - i2c2 { - i2c2_xfer: i2c2-xfer { - rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>, - <2 RK_PB6 1 &pcfg_pull_none>; - }; - }; - - i2c3 { - i2c3_xfer: i2c3-xfer { - rockchip,pins = <0 RK_PA5 2 &pcfg_pull_none>, - <0 RK_PA6 2 &pcfg_pull_none>; - }; - i2c3_pins: i2c3-pins { - rockchip,pins = - <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>, - <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - hdmi_i2c { - hdmii2c_xfer: hdmii2c-xfer { - rockchip,pins = <0 RK_PA5 1 &pcfg_pull_none>, - <0 RK_PA6 1 &pcfg_pull_none>; - }; - }; - - pdm-0 { - pdmm0_clk: pdmm0-clk { - rockchip,pins = <2 RK_PC2 2 &pcfg_pull_none>; - }; - - pdmm0_fsync: pdmm0-fsync { - rockchip,pins = <2 RK_PC7 2 &pcfg_pull_none>; - }; - - pdmm0_sdi0: pdmm0-sdi0 { - rockchip,pins = <2 RK_PC3 2 &pcfg_pull_none>; - }; - - pdmm0_sdi1: pdmm0-sdi1 { - rockchip,pins = <2 RK_PC4 2 &pcfg_pull_none>; - }; - - pdmm0_sdi2: pdmm0-sdi2 { - rockchip,pins = <2 RK_PC5 2 &pcfg_pull_none>; - }; - - pdmm0_sdi3: pdmm0-sdi3 { - rockchip,pins = <2 RK_PC6 2 &pcfg_pull_none>; - }; - - pdmm0_clk_sleep: pdmm0-clk-sleep { - rockchip,pins = - <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>; - }; - - pdmm0_sdi0_sleep: pdmm0-sdi0-sleep { - rockchip,pins = - <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>; - }; - - pdmm0_sdi1_sleep: pdmm0-sdi1-sleep { - rockchip,pins = - <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>; - }; - - pdmm0_sdi2_sleep: pdmm0-sdi2-sleep { - rockchip,pins = - <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>; - }; - - pdmm0_sdi3_sleep: pdmm0-sdi3-sleep { - rockchip,pins = - <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>; - }; - - pdmm0_fsync_sleep: pdmm0-fsync-sleep { - rockchip,pins = - <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>; - }; - }; - - tsadc { - otp_pin: otp-pin { - rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - otp_out: otp-out { - rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>; - }; - }; - - uart0 { - uart0_xfer: uart0-xfer { - rockchip,pins = <1 RK_PB1 1 &pcfg_pull_none>, - <1 RK_PB0 1 &pcfg_pull_up>; - }; - - uart0_cts: uart0-cts { - rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>; - }; - - uart0_rts: uart0-rts { - rockchip,pins = <1 RK_PB2 1 &pcfg_pull_none>; - }; - - uart0_rts_pin: uart0-rts-pin { - rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - uart1 { - uart1_xfer: uart1-xfer { - rockchip,pins = <3 RK_PA4 4 &pcfg_pull_none>, - <3 RK_PA6 4 &pcfg_pull_up>; - }; - - uart1_cts: uart1-cts { - rockchip,pins = <3 RK_PA7 4 &pcfg_pull_none>; - }; - - uart1_rts: uart1-rts { - rockchip,pins = <3 RK_PA5 4 &pcfg_pull_none>; - }; - - uart1_rts_pin: uart1-rts-pin { - rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - uart2-0 { - uart2m0_xfer: uart2m0-xfer { - rockchip,pins = <1 RK_PA0 2 &pcfg_pull_none>, - <1 RK_PA1 2 &pcfg_pull_up>; - }; - }; - - uart2-1 { - uart2m1_xfer: uart2m1-xfer { - rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>, - <2 RK_PA1 1 &pcfg_pull_up>; - }; - }; - - spi0-0 { - spi0m0_clk: spi0m0-clk { - rockchip,pins = <2 RK_PB0 1 &pcfg_pull_up>; - }; - - spi0m0_cs0: spi0m0-cs0 { - rockchip,pins = <2 RK_PB3 1 &pcfg_pull_up>; - }; - - spi0m0_tx: spi0m0-tx { - rockchip,pins = <2 RK_PB1 1 &pcfg_pull_up>; - }; - - spi0m0_rx: spi0m0-rx { - rockchip,pins = <2 RK_PB2 1 &pcfg_pull_up>; - }; - - spi0m0_cs1: spi0m0-cs1 { - rockchip,pins = <2 RK_PB4 1 &pcfg_pull_up>; - }; - }; - - spi0-1 { - spi0m1_clk: spi0m1-clk { - rockchip,pins = <3 RK_PC7 2 &pcfg_pull_up>; - }; - - spi0m1_cs0: spi0m1-cs0 { - rockchip,pins = <3 RK_PD2 2 &pcfg_pull_up>; - }; - - spi0m1_tx: spi0m1-tx { - rockchip,pins = <3 RK_PD1 2 &pcfg_pull_up>; - }; - - spi0m1_rx: spi0m1-rx { - rockchip,pins = <3 RK_PD0 2 &pcfg_pull_up>; - }; - - spi0m1_cs1: spi0m1-cs1 { - rockchip,pins = <3 RK_PD3 2 &pcfg_pull_up>; - }; - }; - - spi0-2 { - spi0m2_clk: spi0m2-clk { - rockchip,pins = <3 RK_PA0 4 &pcfg_pull_up>; - }; - - spi0m2_cs0: spi0m2-cs0 { - rockchip,pins = <3 RK_PB0 3 &pcfg_pull_up>; - }; - - spi0m2_tx: spi0m2-tx { - rockchip,pins = <3 RK_PA1 4 &pcfg_pull_up>; - }; - - spi0m2_rx: spi0m2-rx { - rockchip,pins = <3 RK_PA2 4 &pcfg_pull_up>; - }; - }; - - i2s1 { - i2s1_mclk: i2s1-mclk { - rockchip,pins = <2 RK_PB7 1 &pcfg_pull_none>; - }; - - i2s1_sclk: i2s1-sclk { - rockchip,pins = <2 RK_PC2 1 &pcfg_pull_none>; - }; - - i2s1_lrckrx: i2s1-lrckrx { - rockchip,pins = <2 RK_PC0 1 &pcfg_pull_none>; - }; - - i2s1_lrcktx: i2s1-lrcktx { - rockchip,pins = <2 RK_PC1 1 &pcfg_pull_none>; - }; - - i2s1_sdi: i2s1-sdi { - rockchip,pins = <2 RK_PC3 1 &pcfg_pull_none>; - }; - - i2s1_sdo: i2s1-sdo { - rockchip,pins = <2 RK_PC7 1 &pcfg_pull_none>; - }; - - i2s1_sdio1: i2s1-sdio1 { - rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>; - }; - - i2s1_sdio2: i2s1-sdio2 { - rockchip,pins = <2 RK_PC5 1 &pcfg_pull_none>; - }; - - i2s1_sdio3: i2s1-sdio3 { - rockchip,pins = <2 RK_PC6 1 &pcfg_pull_none>; - }; - - i2s1_sleep: i2s1-sleep { - rockchip,pins = - <2 RK_PB7 RK_FUNC_GPIO &pcfg_input_high>, - <2 RK_PC0 RK_FUNC_GPIO &pcfg_input_high>, - <2 RK_PC1 RK_FUNC_GPIO &pcfg_input_high>, - <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>, - <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>, - <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>, - <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>, - <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>, - <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>; - }; - }; - - i2s2-0 { - i2s2m0_mclk: i2s2m0-mclk { - rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>; - }; - - i2s2m0_sclk: i2s2m0-sclk { - rockchip,pins = <1 RK_PC6 1 &pcfg_pull_none>; - }; - - i2s2m0_lrckrx: i2s2m0-lrckrx { - rockchip,pins = <1 RK_PD2 1 &pcfg_pull_none>; - }; - - i2s2m0_lrcktx: i2s2m0-lrcktx { - rockchip,pins = <1 RK_PC7 1 &pcfg_pull_none>; - }; - - i2s2m0_sdi: i2s2m0-sdi { - rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>; - }; - - i2s2m0_sdo: i2s2m0-sdo { - rockchip,pins = <1 RK_PD1 1 &pcfg_pull_none>; - }; - - i2s2m0_sleep: i2s2m0-sleep { - rockchip,pins = - <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>, - <1 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>, - <1 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>, - <1 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>, - <1 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>, - <1 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>; - }; - }; - - i2s2-1 { - i2s2m1_mclk: i2s2m1-mclk { - rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>; - }; - - i2s2m1_sclk: i2s2m1-sclk { - rockchip,pins = <3 RK_PA0 6 &pcfg_pull_none>; - }; - - i2s2m1_lrckrx: i2sm1-lrckrx { - rockchip,pins = <3 RK_PB0 6 &pcfg_pull_none>; - }; - - i2s2m1_lrcktx: i2s2m1-lrcktx { - rockchip,pins = <3 RK_PB0 4 &pcfg_pull_none>; - }; - - i2s2m1_sdi: i2s2m1-sdi { - rockchip,pins = <3 RK_PA2 6 &pcfg_pull_none>; - }; - - i2s2m1_sdo: i2s2m1-sdo { - rockchip,pins = <3 RK_PA1 6 &pcfg_pull_none>; - }; - - i2s2m1_sleep: i2s2m1-sleep { - rockchip,pins = - <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>, - <3 RK_PA0 RK_FUNC_GPIO &pcfg_input_high>, - <3 RK_PB0 RK_FUNC_GPIO &pcfg_input_high>, - <3 RK_PA2 RK_FUNC_GPIO &pcfg_input_high>, - <3 RK_PA1 RK_FUNC_GPIO &pcfg_input_high>; - }; - }; - - spdif-0 { - spdifm0_tx: spdifm0-tx { - rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>; - }; - }; - - spdif-1 { - spdifm1_tx: spdifm1-tx { - rockchip,pins = <2 RK_PC1 2 &pcfg_pull_none>; - }; - }; - - spdif-2 { - spdifm2_tx: spdifm2-tx { - rockchip,pins = <0 RK_PA2 2 &pcfg_pull_none>; - }; - }; - - sdmmc0-0 { - sdmmc0m0_pwren: sdmmc0m0-pwren { - rockchip,pins = <2 RK_PA7 1 &pcfg_pull_up_4ma>; - }; - - sdmmc0m0_pin: sdmmc0m0-pin { - rockchip,pins = <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; - }; - }; - - sdmmc0-1 { - sdmmc0m1_pwren: sdmmc0m1-pwren { - rockchip,pins = <0 RK_PD6 3 &pcfg_pull_up_4ma>; - }; - - sdmmc0m1_pin: sdmmc0m1-pin { - rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>; - }; - }; - - sdmmc0 { - sdmmc0_clk: sdmmc0-clk { - rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none_8ma>; - }; - - sdmmc0_cmd: sdmmc0-cmd { - rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up_8ma>; - }; - - sdmmc0_dectn: sdmmc0-dectn { - rockchip,pins = <1 RK_PA5 1 &pcfg_pull_up_4ma>; - }; - - sdmmc0_wrprt: sdmmc0-wrprt { - rockchip,pins = <1 RK_PA7 1 &pcfg_pull_up_4ma>; - }; - - sdmmc0_bus1: sdmmc0-bus1 { - rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>; - }; - - sdmmc0_bus4: sdmmc0-bus4 { - rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>, - <1 RK_PA1 1 &pcfg_pull_up_8ma>, - <1 RK_PA2 1 &pcfg_pull_up_8ma>, - <1 RK_PA3 1 &pcfg_pull_up_8ma>; - }; - - sdmmc0_pins: sdmmc0-pins { - rockchip,pins = - <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>; - }; - }; - - sdmmc0ext { - sdmmc0ext_clk: sdmmc0ext-clk { - rockchip,pins = <3 RK_PA2 3 &pcfg_pull_none_4ma>; - }; - - sdmmc0ext_cmd: sdmmc0ext-cmd { - rockchip,pins = <3 RK_PA0 3 &pcfg_pull_up_4ma>; - }; - - sdmmc0ext_wrprt: sdmmc0ext-wrprt { - rockchip,pins = <3 RK_PA3 3 &pcfg_pull_up_4ma>; - }; - - sdmmc0ext_dectn: sdmmc0ext-dectn { - rockchip,pins = <3 RK_PA1 3 &pcfg_pull_up_4ma>; - }; - - sdmmc0ext_bus1: sdmmc0ext-bus1 { - rockchip,pins = <3 RK_PA4 3 &pcfg_pull_up_4ma>; - }; - - sdmmc0ext_bus4: sdmmc0ext-bus4 { - rockchip,pins = - <3 RK_PA4 3 &pcfg_pull_up_4ma>, - <3 RK_PA5 3 &pcfg_pull_up_4ma>, - <3 RK_PA6 3 &pcfg_pull_up_4ma>, - <3 RK_PA7 3 &pcfg_pull_up_4ma>; - }; - - sdmmc0ext_pins: sdmmc0ext-pins { - rockchip,pins = - <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; - }; - }; - - sdmmc1 { - sdmmc1_clk: sdmmc1-clk { - rockchip,pins = <1 RK_PB4 1 &pcfg_pull_none_8ma>; - }; - - sdmmc1_cmd: sdmmc1-cmd { - rockchip,pins = <1 RK_PB5 1 &pcfg_pull_up_8ma>; - }; - - sdmmc1_pwren: sdmmc1-pwren { - rockchip,pins = <1 RK_PC2 1 &pcfg_pull_up_8ma>; - }; - - sdmmc1_wrprt: sdmmc1-wrprt { - rockchip,pins = <1 RK_PC4 1 &pcfg_pull_up_8ma>; - }; - - sdmmc1_dectn: sdmmc1-dectn { - rockchip,pins = <1 RK_PC3 1 &pcfg_pull_up_8ma>; - }; - - sdmmc1_bus1: sdmmc1-bus1 { - rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>; - }; - - sdmmc1_bus4: sdmmc1-bus4 { - rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>, - <1 RK_PB7 1 &pcfg_pull_up_8ma>, - <1 RK_PC0 1 &pcfg_pull_up_8ma>, - <1 RK_PC1 1 &pcfg_pull_up_8ma>; - }; - - sdmmc1_pins: sdmmc1-pins { - rockchip,pins = - <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up_4ma>; - }; - }; - - emmc { - emmc_clk: emmc-clk { - rockchip,pins = <3 RK_PC5 2 &pcfg_pull_none_12ma>; - }; - - emmc_cmd: emmc-cmd { - rockchip,pins = <3 RK_PC3 2 &pcfg_pull_up_12ma>; - }; - - emmc_pwren: emmc-pwren { - rockchip,pins = <3 RK_PC6 2 &pcfg_pull_none>; - }; - - emmc_rstnout: emmc-rstnout { - rockchip,pins = <3 RK_PC4 2 &pcfg_pull_none>; - }; - - emmc_bus1: emmc-bus1 { - rockchip,pins = <0 RK_PA7 2 &pcfg_pull_up_12ma>; - }; - - emmc_bus4: emmc-bus4 { - rockchip,pins = - <0 RK_PA7 2 &pcfg_pull_up_12ma>, - <2 RK_PD4 2 &pcfg_pull_up_12ma>, - <2 RK_PD5 2 &pcfg_pull_up_12ma>, - <2 RK_PD6 2 &pcfg_pull_up_12ma>; - }; - - emmc_bus8: emmc-bus8 { - rockchip,pins = - <0 RK_PA7 2 &pcfg_pull_up_12ma>, - <2 RK_PD4 2 &pcfg_pull_up_12ma>, - <2 RK_PD5 2 &pcfg_pull_up_12ma>, - <2 RK_PD6 2 &pcfg_pull_up_12ma>, - <2 RK_PD7 2 &pcfg_pull_up_12ma>, - <3 RK_PC0 2 &pcfg_pull_up_12ma>, - <3 RK_PC1 2 &pcfg_pull_up_12ma>, - <3 RK_PC2 2 &pcfg_pull_up_12ma>; - }; - }; - - pwm0 { - pwm0_pin: pwm0-pin { - rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>; - }; - }; - - pwm1 { - pwm1_pin: pwm1-pin { - rockchip,pins = <2 RK_PA5 1 &pcfg_pull_none>; - }; - }; - - pwm2 { - pwm2_pin: pwm2-pin { - rockchip,pins = <2 RK_PA6 1 &pcfg_pull_none>; - }; - }; - - pwmir { - pwmir_pin: pwmir-pin { - rockchip,pins = <2 RK_PA2 1 &pcfg_pull_none>; - }; - }; - - gmac-1 { - rgmiim1_pins: rgmiim1-pins { - rockchip,pins = - /* mac_txclk */ - <1 RK_PB4 2 &pcfg_pull_none_8ma>, - /* mac_rxclk */ - <1 RK_PB5 2 &pcfg_pull_none_4ma>, - /* mac_mdio */ - <1 RK_PC3 2 &pcfg_pull_none_4ma>, - /* mac_txen */ - <1 RK_PD1 2 &pcfg_pull_none_8ma>, - /* mac_clk */ - <1 RK_PC5 2 &pcfg_pull_none_4ma>, - /* mac_rxdv */ - <1 RK_PC6 2 &pcfg_pull_none_4ma>, - /* mac_mdc */ - <1 RK_PC7 2 &pcfg_pull_none_4ma>, - /* mac_rxd1 */ - <1 RK_PB2 2 &pcfg_pull_none_4ma>, - /* mac_rxd0 */ - <1 RK_PB3 2 &pcfg_pull_none_4ma>, - /* mac_txd1 */ - <1 RK_PB0 2 &pcfg_pull_none_8ma>, - /* mac_txd0 */ - <1 RK_PB1 2 &pcfg_pull_none_8ma>, - /* mac_rxd3 */ - <1 RK_PB6 2 &pcfg_pull_none_4ma>, - /* mac_rxd2 */ - <1 RK_PB7 2 &pcfg_pull_none_4ma>, - /* mac_txd3 */ - <1 RK_PC0 2 &pcfg_pull_none_8ma>, - /* mac_txd2 */ - <1 RK_PC1 2 &pcfg_pull_none_8ma>, - - /* mac_txclk */ - <0 RK_PB0 1 &pcfg_pull_none_8ma>, - /* mac_txen */ - <0 RK_PB4 1 &pcfg_pull_none_8ma>, - /* mac_clk */ - <0 RK_PD0 1 &pcfg_pull_none_4ma>, - /* mac_txd1 */ - <0 RK_PC0 1 &pcfg_pull_none_8ma>, - /* mac_txd0 */ - <0 RK_PC1 1 &pcfg_pull_none_8ma>, - /* mac_txd3 */ - <0 RK_PC7 1 &pcfg_pull_none_8ma>, - /* mac_txd2 */ - <0 RK_PC6 1 &pcfg_pull_none_8ma>; - }; - - rmiim1_pins: rmiim1-pins { - rockchip,pins = - /* mac_mdio */ - <1 RK_PC3 2 &pcfg_pull_none_2ma>, - /* mac_txen */ - <1 RK_PD1 2 &pcfg_pull_none_12ma>, - /* mac_clk */ - <1 RK_PC5 2 &pcfg_pull_none_2ma>, - /* mac_rxer */ - <1 RK_PD0 2 &pcfg_pull_none_2ma>, - /* mac_rxdv */ - <1 RK_PC6 2 &pcfg_pull_none_2ma>, - /* mac_mdc */ - <1 RK_PC7 2 &pcfg_pull_none_2ma>, - /* mac_rxd1 */ - <1 RK_PB2 2 &pcfg_pull_none_2ma>, - /* mac_rxd0 */ - <1 RK_PB3 2 &pcfg_pull_none_2ma>, - /* mac_txd1 */ - <1 RK_PB0 2 &pcfg_pull_none_12ma>, - /* mac_txd0 */ - <1 RK_PB1 2 &pcfg_pull_none_12ma>, - - /* mac_mdio */ - <0 RK_PB3 1 &pcfg_pull_none>, - /* mac_txen */ - <0 RK_PB4 1 &pcfg_pull_none>, - /* mac_clk */ - <0 RK_PD0 1 &pcfg_pull_none>, - /* mac_mdc */ - <0 RK_PC3 1 &pcfg_pull_none>, - /* mac_txd1 */ - <0 RK_PC0 1 &pcfg_pull_none>, - /* mac_txd0 */ - <0 RK_PC1 1 &pcfg_pull_none>; - }; - }; - - gmac2phy { - fephyled_speed10: fephyled-speed10 { - rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>; - }; - - fephyled_duplex: fephyled-duplex { - rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>; - }; - - fephyled_rxm1: fephyled-rxm1 { - rockchip,pins = <2 RK_PD1 2 &pcfg_pull_none>; - }; - - fephyled_txm1: fephyled-txm1 { - rockchip,pins = <2 RK_PD1 3 &pcfg_pull_none>; - }; - - fephyled_linkm1: fephyled-linkm1 { - rockchip,pins = <2 RK_PD0 2 &pcfg_pull_none>; - }; - }; - - tsadc_pin { - tsadc_int: tsadc-int { - rockchip,pins = <2 RK_PB5 2 &pcfg_pull_none>; - }; - tsadc_pin: tsadc-pin { - rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - hdmi_pin { - hdmi_cec: hdmi-cec { - rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>; - }; - - hdmi_hpd: hdmi-hpd { - rockchip,pins = <0 RK_PA4 1 &pcfg_pull_down>; - }; - }; - - cif-0 { - dvp_d2d9_m0:dvp-d2d9-m0 { - rockchip,pins = - /* cif_d0 */ - <3 RK_PA4 2 &pcfg_pull_none>, - /* cif_d1 */ - <3 RK_PA5 2 &pcfg_pull_none>, - /* cif_d2 */ - <3 RK_PA6 2 &pcfg_pull_none>, - /* cif_d3 */ - <3 RK_PA7 2 &pcfg_pull_none>, - /* cif_d4 */ - <3 RK_PB0 2 &pcfg_pull_none>, - /* cif_d5m0 */ - <3 RK_PB1 2 &pcfg_pull_none>, - /* cif_d6m0 */ - <3 RK_PB2 2 &pcfg_pull_none>, - /* cif_d7m0 */ - <3 RK_PB3 2 &pcfg_pull_none>, - /* cif_href */ - <3 RK_PA1 2 &pcfg_pull_none>, - /* cif_vsync */ - <3 RK_PA0 2 &pcfg_pull_none>, - /* cif_clkoutm0 */ - <3 RK_PA3 2 &pcfg_pull_none>, - /* cif_clkin */ - <3 RK_PA2 2 &pcfg_pull_none>; - }; - }; - - cif-1 { - dvp_d2d9_m1:dvp-d2d9-m1 { - rockchip,pins = - /* cif_d0 */ - <3 RK_PA4 2 &pcfg_pull_none>, - /* cif_d1 */ - <3 RK_PA5 2 &pcfg_pull_none>, - /* cif_d2 */ - <3 RK_PA6 2 &pcfg_pull_none>, - /* cif_d3 */ - <3 RK_PA7 2 &pcfg_pull_none>, - /* cif_d4 */ - <3 RK_PB0 2 &pcfg_pull_none>, - /* cif_d5m1 */ - <2 RK_PC0 4 &pcfg_pull_none>, - /* cif_d6m1 */ - <2 RK_PC1 4 &pcfg_pull_none>, - /* cif_d7m1 */ - <2 RK_PC2 4 &pcfg_pull_none>, - /* cif_href */ - <3 RK_PA1 2 &pcfg_pull_none>, - /* cif_vsync */ - <3 RK_PA0 2 &pcfg_pull_none>, - /* cif_clkoutm1 */ - <2 RK_PB7 4 &pcfg_pull_none>, - /* cif_clkin */ - <3 RK_PA2 2 &pcfg_pull_none>; - }; - }; - }; -}; diff --git a/include/dt-bindings/clock/rk3328-cru.h b/include/dt-bindings/clock/rk3328-cru.h deleted file mode 100644 index 555b4ff660ae..000000000000 --- a/include/dt-bindings/clock/rk3328-cru.h +++ /dev/null @@ -1,393 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright (c) 2016 Rockchip Electronics Co. Ltd. - * Author: Elaine zhangqing@rock-chips.com - */ - -#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3328_H -#define _DT_BINDINGS_CLK_ROCKCHIP_RK3328_H - -/* core clocks */ -#define PLL_APLL 1 -#define PLL_DPLL 2 -#define PLL_CPLL 3 -#define PLL_GPLL 4 -#define PLL_NPLL 5 -#define ARMCLK 6 - -/* sclk gates (special clocks) */ -#define SCLK_RTC32K 30 -#define SCLK_SDMMC_EXT 31 -#define SCLK_SPI 32 -#define SCLK_SDMMC 33 -#define SCLK_SDIO 34 -#define SCLK_EMMC 35 -#define SCLK_TSADC 36 -#define SCLK_SARADC 37 -#define SCLK_UART0 38 -#define SCLK_UART1 39 -#define SCLK_UART2 40 -#define SCLK_I2S0 41 -#define SCLK_I2S1 42 -#define SCLK_I2S2 43 -#define SCLK_I2S1_OUT 44 -#define SCLK_I2S2_OUT 45 -#define SCLK_SPDIF 46 -#define SCLK_TIMER0 47 -#define SCLK_TIMER1 48 -#define SCLK_TIMER2 49 -#define SCLK_TIMER3 50 -#define SCLK_TIMER4 51 -#define SCLK_TIMER5 52 -#define SCLK_WIFI 53 -#define SCLK_CIF_OUT 54 -#define SCLK_I2C0 55 -#define SCLK_I2C1 56 -#define SCLK_I2C2 57 -#define SCLK_I2C3 58 -#define SCLK_CRYPTO 59 -#define SCLK_PWM 60 -#define SCLK_PDM 61 -#define SCLK_EFUSE 62 -#define SCLK_OTP 63 -#define SCLK_DDRCLK 64 -#define SCLK_VDEC_CABAC 65 -#define SCLK_VDEC_CORE 66 -#define SCLK_VENC_DSP 67 -#define SCLK_VENC_CORE 68 -#define SCLK_RGA 69 -#define SCLK_HDMI_SFC 70 -#define SCLK_HDMI_CEC 71 -#define SCLK_USB3_REF 72 -#define SCLK_USB3_SUSPEND 73 -#define SCLK_SDMMC_DRV 74 -#define SCLK_SDIO_DRV 75 -#define SCLK_EMMC_DRV 76 -#define SCLK_SDMMC_EXT_DRV 77 -#define SCLK_SDMMC_SAMPLE 78 -#define SCLK_SDIO_SAMPLE 79 -#define SCLK_EMMC_SAMPLE 80 -#define SCLK_SDMMC_EXT_SAMPLE 81 -#define SCLK_VOP 82 -#define SCLK_MAC2PHY_RXTX 83 -#define SCLK_MAC2PHY_SRC 84 -#define SCLK_MAC2PHY_REF 85 -#define SCLK_MAC2PHY_OUT 86 -#define SCLK_MAC2IO_RX 87 -#define SCLK_MAC2IO_TX 88 -#define SCLK_MAC2IO_REFOUT 89 -#define SCLK_MAC2IO_REF 90 -#define SCLK_MAC2IO_OUT 91 -#define SCLK_TSP 92 -#define SCLK_HSADC_TSP 93 -#define SCLK_USB3PHY_REF 94 -#define SCLK_REF_USB3OTG 95 -#define SCLK_USB3OTG_REF 96 -#define SCLK_USB3OTG_SUSPEND 97 -#define SCLK_REF_USB3OTG_SRC 98 -#define SCLK_MAC2IO_SRC 99 -#define SCLK_MAC2IO 100 -#define SCLK_MAC2PHY 101 -#define SCLK_MAC2IO_EXT 102 - -/* dclk gates */ -#define DCLK_LCDC 120 -#define DCLK_HDMIPHY 121 -#define HDMIPHY 122 -#define USB480M 123 -#define DCLK_LCDC_SRC 124 - -/* aclk gates */ -#define ACLK_AXISRAM 130 -#define ACLK_VOP_PRE 131 -#define ACLK_USB3OTG 132 -#define ACLK_RGA_PRE 133 -#define ACLK_DMAC 134 -#define ACLK_GPU 135 -#define ACLK_BUS_PRE 136 -#define ACLK_PERI_PRE 137 -#define ACLK_RKVDEC_PRE 138 -#define ACLK_RKVDEC 139 -#define ACLK_RKVENC 140 -#define ACLK_VPU_PRE 141 -#define ACLK_VIO_PRE 142 -#define ACLK_VPU 143 -#define ACLK_VIO 144 -#define ACLK_VOP 145 -#define ACLK_GMAC 146 -#define ACLK_H265 147 -#define ACLK_H264 148 -#define ACLK_MAC2PHY 149 -#define ACLK_MAC2IO 150 -#define ACLK_DCF 151 -#define ACLK_TSP 152 -#define ACLK_PERI 153 -#define ACLK_RGA 154 -#define ACLK_IEP 155 -#define ACLK_CIF 156 -#define ACLK_HDCP 157 - -/* pclk gates */ -#define PCLK_GPIO0 200 -#define PCLK_GPIO1 201 -#define PCLK_GPIO2 202 -#define PCLK_GPIO3 203 -#define PCLK_GRF 204 -#define PCLK_I2C0 205 -#define PCLK_I2C1 206 -#define PCLK_I2C2 207 -#define PCLK_I2C3 208 -#define PCLK_SPI 209 -#define PCLK_UART0 210 -#define PCLK_UART1 211 -#define PCLK_UART2 212 -#define PCLK_TSADC 213 -#define PCLK_PWM 214 -#define PCLK_TIMER 215 -#define PCLK_BUS_PRE 216 -#define PCLK_PERI_PRE 217 -#define PCLK_HDMI_CTRL 218 -#define PCLK_HDMI_PHY 219 -#define PCLK_GMAC 220 -#define PCLK_H265 221 -#define PCLK_MAC2PHY 222 -#define PCLK_MAC2IO 223 -#define PCLK_USB3PHY_OTG 224 -#define PCLK_USB3PHY_PIPE 225 -#define PCLK_USB3_GRF 226 -#define PCLK_USB2_GRF 227 -#define PCLK_HDMIPHY 228 -#define PCLK_DDR 229 -#define PCLK_PERI 230 -#define PCLK_HDMI 231 -#define PCLK_HDCP 232 -#define PCLK_DCF 233 -#define PCLK_SARADC 234 -#define PCLK_ACODECPHY 235 -#define PCLK_WDT 236 - -/* hclk gates */ -#define HCLK_PERI 308 -#define HCLK_TSP 309 -#define HCLK_GMAC 310 -#define HCLK_I2S0_8CH 311 -#define HCLK_I2S1_8CH 312 -#define HCLK_I2S2_2CH 313 -#define HCLK_SPDIF_8CH 314 -#define HCLK_VOP 315 -#define HCLK_NANDC 316 -#define HCLK_SDMMC 317 -#define HCLK_SDIO 318 -#define HCLK_EMMC 319 -#define HCLK_SDMMC_EXT 320 -#define HCLK_RKVDEC_PRE 321 -#define HCLK_RKVDEC 322 -#define HCLK_RKVENC 323 -#define HCLK_VPU_PRE 324 -#define HCLK_VIO_PRE 325 -#define HCLK_VPU 326 -#define HCLK_BUS_PRE 328 -#define HCLK_PERI_PRE 329 -#define HCLK_H264 330 -#define HCLK_CIF 331 -#define HCLK_OTG_PMU 332 -#define HCLK_OTG 333 -#define HCLK_HOST0 334 -#define HCLK_HOST0_ARB 335 -#define HCLK_CRYPTO_MST 336 -#define HCLK_CRYPTO_SLV 337 -#define HCLK_PDM 338 -#define HCLK_IEP 339 -#define HCLK_RGA 340 -#define HCLK_HDCP 341 - -#define CLK_NR_CLKS (HCLK_HDCP + 1) - -/* soft-reset indices */ -#define SRST_CORE0_PO 0 -#define SRST_CORE1_PO 1 -#define SRST_CORE2_PO 2 -#define SRST_CORE3_PO 3 -#define SRST_CORE0 4 -#define SRST_CORE1 5 -#define SRST_CORE2 6 -#define SRST_CORE3 7 -#define SRST_CORE0_DBG 8 -#define SRST_CORE1_DBG 9 -#define SRST_CORE2_DBG 10 -#define SRST_CORE3_DBG 11 -#define SRST_TOPDBG 12 -#define SRST_CORE_NIU 13 -#define SRST_STRC_A 14 -#define SRST_L2C 15 - -#define SRST_A53_GIC 18 -#define SRST_DAP 19 -#define SRST_PMU_P 21 -#define SRST_EFUSE 22 -#define SRST_BUSSYS_H 23 -#define SRST_BUSSYS_P 24 -#define SRST_SPDIF 25 -#define SRST_INTMEM 26 -#define SRST_ROM 27 -#define SRST_GPIO0 28 -#define SRST_GPIO1 29 -#define SRST_GPIO2 30 -#define SRST_GPIO3 31 - -#define SRST_I2S0 32 -#define SRST_I2S1 33 -#define SRST_I2S2 34 -#define SRST_I2S0_H 35 -#define SRST_I2S1_H 36 -#define SRST_I2S2_H 37 -#define SRST_UART0 38 -#define SRST_UART1 39 -#define SRST_UART2 40 -#define SRST_UART0_P 41 -#define SRST_UART1_P 42 -#define SRST_UART2_P 43 -#define SRST_I2C0 44 -#define SRST_I2C1 45 -#define SRST_I2C2 46 -#define SRST_I2C3 47 - -#define SRST_I2C0_P 48 -#define SRST_I2C1_P 49 -#define SRST_I2C2_P 50 -#define SRST_I2C3_P 51 -#define SRST_EFUSE_SE_P 52 -#define SRST_EFUSE_NS_P 53 -#define SRST_PWM0 54 -#define SRST_PWM0_P 55 -#define SRST_DMA 56 -#define SRST_TSP_A 57 -#define SRST_TSP_H 58 -#define SRST_TSP 59 -#define SRST_TSP_HSADC 60 -#define SRST_DCF_A 61 -#define SRST_DCF_P 62 - -#define SRST_SCR 64 -#define SRST_SPI 65 -#define SRST_TSADC 66 -#define SRST_TSADC_P 67 -#define SRST_CRYPTO 68 -#define SRST_SGRF 69 -#define SRST_GRF 70 -#define SRST_USB_GRF 71 -#define SRST_TIMER_6CH_P 72 -#define SRST_TIMER0 73 -#define SRST_TIMER1 74 -#define SRST_TIMER2 75 -#define SRST_TIMER3 76 -#define SRST_TIMER4 77 -#define SRST_TIMER5 78 -#define SRST_USB3GRF 79 - -#define SRST_PHYNIU 80 -#define SRST_HDMIPHY 81 -#define SRST_VDAC 82 -#define SRST_ACODEC_p 83 -#define SRST_SARADC 85 -#define SRST_SARADC_P 86 -#define SRST_GRF_DDR 87 -#define SRST_DFIMON 88 -#define SRST_MSCH 89 -#define SRST_DDRMSCH 91 -#define SRST_DDRCTRL 92 -#define SRST_DDRCTRL_P 93 -#define SRST_DDRPHY 94 -#define SRST_DDRPHY_P 95 - -#define SRST_GMAC_NIU_A 96 -#define SRST_GMAC_NIU_P 97 -#define SRST_GMAC2PHY_A 98 -#define SRST_GMAC2IO_A 99 -#define SRST_MACPHY 100 -#define SRST_OTP_PHY 101 -#define SRST_GPU_A 102 -#define SRST_GPU_NIU_A 103 -#define SRST_SDMMCEXT 104 -#define SRST_PERIPH_NIU_A 105 -#define SRST_PERIHP_NIU_H 106 -#define SRST_PERIHP_P 107 -#define SRST_PERIPHSYS_H 108 -#define SRST_MMC0 109 -#define SRST_SDIO 110 -#define SRST_EMMC 111 - -#define SRST_USB2OTG_H 112 -#define SRST_USB2OTG 113 -#define SRST_USB2OTG_ADP 114 -#define SRST_USB2HOST_H 115 -#define SRST_USB2HOST_ARB 116 -#define SRST_USB2HOST_AUX 117 -#define SRST_USB2HOST_EHCIPHY 118 -#define SRST_USB2HOST_UTMI 119 -#define SRST_USB3OTG 120 -#define SRST_USBPOR 121 -#define SRST_USB2OTG_UTMI 122 -#define SRST_USB2HOST_PHY_UTMI 123 -#define SRST_USB3OTG_UTMI 124 -#define SRST_USB3PHY_U2 125 -#define SRST_USB3PHY_U3 126 -#define SRST_USB3PHY_PIPE 127 - -#define SRST_VIO_A 128 -#define SRST_VIO_BUS_H 129 -#define SRST_VIO_H2P_H 130 -#define SRST_VIO_ARBI_H 131 -#define SRST_VOP_NIU_A 132 -#define SRST_VOP_A 133 -#define SRST_VOP_H 134 -#define SRST_VOP_D 135 -#define SRST_RGA 136 -#define SRST_RGA_NIU_A 137 -#define SRST_RGA_A 138 -#define SRST_RGA_H 139 -#define SRST_IEP_A 140 -#define SRST_IEP_H 141 -#define SRST_HDMI 142 -#define SRST_HDMI_P 143 - -#define SRST_HDCP_A 144 -#define SRST_HDCP 145 -#define SRST_HDCP_H 146 -#define SRST_CIF_A 147 -#define SRST_CIF_H 148 -#define SRST_CIF_P 149 -#define SRST_OTP_P 150 -#define SRST_OTP_SBPI 151 -#define SRST_OTP_USER 152 -#define SRST_DDRCTRL_A 153 -#define SRST_DDRSTDY_P 154 -#define SRST_DDRSTDY 155 -#define SRST_PDM_H 156 -#define SRST_PDM 157 -#define SRST_USB3PHY_OTG_P 158 -#define SRST_USB3PHY_PIPE_P 159 - -#define SRST_VCODEC_A 160 -#define SRST_VCODEC_NIU_A 161 -#define SRST_VCODEC_H 162 -#define SRST_VCODEC_NIU_H 163 -#define SRST_VDEC_A 164 -#define SRST_VDEC_NIU_A 165 -#define SRST_VDEC_H 166 -#define SRST_VDEC_NIU_H 167 -#define SRST_VDEC_CORE 168 -#define SRST_VDEC_CABAC 169 -#define SRST_DDRPHYDIV 175 - -#define SRST_RKVENC_NIU_A 176 -#define SRST_RKVENC_NIU_H 177 -#define SRST_RKVENC_H265_A 178 -#define SRST_RKVENC_H265_P 179 -#define SRST_RKVENC_H265_CORE 180 -#define SRST_RKVENC_H265_DSP 181 -#define SRST_RKVENC_H264_A 182 -#define SRST_RKVENC_H264_H 183 -#define SRST_RKVENC_INTMEM 184 - -#endif diff --git a/include/dt-bindings/power/rk3328-power.h b/include/dt-bindings/power/rk3328-power.h deleted file mode 100644 index 02e3d7fc1cce..000000000000 --- a/include/dt-bindings/power/rk3328-power.h +++ /dev/null @@ -1,19 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __DT_BINDINGS_POWER_RK3328_POWER_H__ -#define __DT_BINDINGS_POWER_RK3328_POWER_H__ - -/** - * RK3328 idle id Summary. - */ -#define RK3328_PD_CORE 0 -#define RK3328_PD_GPU 1 -#define RK3328_PD_BUS 2 -#define RK3328_PD_MSCH 3 -#define RK3328_PD_PERI 4 -#define RK3328_PD_VIDEO 5 -#define RK3328_PD_HEVC 6 -#define RK3328_PD_SYS 7 -#define RK3328_PD_VPU 8 -#define RK3328_PD_VIO 9 - -#endif