Hi all,

MPC8567 u-boot question for the experts out there...

I must be doing something stupid, or I just don't understand how the 8567 boots from rom..., law entries, tables, etc...

Our board is using a MPC8567 with a 4 MEGByte boot rom flash (16 bit).... It has just 512MB of DDR2 memory(no ram on the local bus). I can get u-boot to come up to the prompt ok but only with a rom image(u-boot.bin) of 4MEG BYTE size and the settings in the files, see below. I am using the BDI to write the 4meg image to the rom.

I guess I don't understand TEXT_BASE very well.. and how it relates to the boot location:

From the manual:

4.4.3.3 Boot ROM Location The MPC8568E defines the default boot ROM address range to be 8 Mbytes at address 0x0_FF80_0000 to 0x0_FFFF_FFFF. However, which peripheral interface handles these boot ROM accesses can be selected at power on.

What do I need to change to get a uboot image for the rom of reasonable size(say 512k instead of the 4meg)??? I have tried to change the value of TEXT_BASE to (xFFF8_0000) in the config.mk file(and other entries) but I must not be doing something else right.. Any suggestions/help would be greatly appreciated!! Am I writng the u-boot.bin to the wrong location in the flash when it is 512k?

Below is the relevant info from the files I think:

Thanks for your help in advance!

Bob

*********** config.mk file

TEXT_BASE = 0xffc00000

********** from the include/configs/sevis8567.h file

/* * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) */ #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_SYS_FLASH_BASE 0xfe000000 /* start of FLASH 8M */ #define CONFIG_SYS_LBC_FLASH_BASE CONFIG_SYS_FLASH_BASE

/*Chip select 0 - Flash*/ #define CONFIG_SYS_BR0_PRELIM 0xfe001001 #define CONFIG_SYS_OR0_PRELIM 0xfe006ff7 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */

I have OR's and BR's for the others also, but should not be relevant to the question so I didnt include.

#define CONFIG_SYS_LBC_LCRR 0x00030002 /* LB clock ratio reg */ #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 #define CONFIG_SYS_CPLD_BASE 0xD0000000 #define CONFIG_SYS_E1_IF_BASE 0xD1000000 #define CONFIG_SYS_DSP_BASE 0xD2000000 #define CONFIG_SYS_FPGA_BASE 0xD3000000

#define CONFIG_SYS_LBC_CPLD_BASE CONFIG_SYS_CPLD_BASE #define CONFIG_SYS_LBC_E1_IF_BASE CONFIG_SYS_E1_IF_BASE #define CONFIG_SYS_LBC_DSP_BASE CONFIG_SYS_DSP_BASE #define CONFIG_SYS_LBC_FPGA_BASE CONFIG_SYS_FPGA_BASE #define CONFIG_SYS_INIT_RAM_LOCK 1 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */

#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_LEN (~TEXT_BASE + 1)/* Reserved for Monitor */ #define CONFIG_SYS_MALLOC_LEN (384 * 1024) /* Reserved for malloc */ /* * Environment */ #define CONFIG_ENV_IS_IN_FLASH 1 #define CONFIG_ENV_SECT_SIZE 0x2000 /* 256K(one sector) for env */ #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0xD0000) #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_OVERWRITE /* allow user to overwrite serial and ethaddr */

#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */

**************** from board/sevis/law.c struct law_entry law_table[] = { SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR),

/* LBC window */ SET_LAW(CONFIG_SYS_LBC_CPLD_BASE, LAW_SIZE_16M, LAW_TRGT_IF_LBC), SET_LAW(CONFIG_SYS_LBC_E1_IF_BASE, LAW_SIZE_16M, LAW_TRGT_IF_LBC), SET_LAW(CONFIG_SYS_LBC_DSP_BASE, LAW_SIZE_16M, LAW_TRGT_IF_LBC), SET_LAW(CONFIG_SYS_LBC_FPGA_BASE, LAW_SIZE_16M, LAW_TRGT_IF_LBC), SET_LAW(CONFIG_SYS_LBC_FLASH_BASE, LAW_SIZE_16M, LAW_TRGT_IF_LBC), };

int num_law_entries = ARRAY_SIZE(law_table);

****************** from board/sevis/tlb.c (the flash table entries I know must be wrong but the uboot comes up when these are set this way)

struct fsl_e_tlb_entry tlb_table[] = { /* TLB 0 - for temp stack in cache */ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0),

/* TLB 1 Initializations */ /* * TLBe 0: 16M Non-cacheable, guarded * 0xff000000 16M FLASH (upper half) * Out of reset this entry is only 4K. */ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE + 0x1000000, CONFIG_SYS_FLASH_BASE + 0x1000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_16M, 1),

/* * TLBe 1: 16M Non-cacheable, guarded * 0xfe000000 16M FLASH (lower half) */ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 1, BOOKE_PAGESZ_16M, 1),

/* * TLBe 2: 64M Non-cacheable, guarded * 0xe000_0000 1M CCSRBAR * 0xe200_0000 8M PCI1 IO * 0xe280_0000 8M PCIe IO */ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 2, BOOKE_PAGESZ_64M, 1), /* * TLB 3+4: 512M DDR, cache disabled (needed for memory test) * 0x00000000 512M DDR System memory * Without SPD EEPROM configured DDR, this must be setup manually. */ SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 3, BOOKE_PAGESZ_256M, 1),

SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 4, BOOKE_PAGESZ_256M, 1),

SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 5, BOOKE_PAGESZ_16M, 1), SET_TLB_ENTRY(1, CONFIG_SYS_E1_IF_BASE, CONFIG_SYS_E1_IF_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 6, BOOKE_PAGESZ_16M, 1), SET_TLB_ENTRY(1, CONFIG_SYS_DSP_BASE, CONFIG_SYS_DSP_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 7, BOOKE_PAGESZ_16M, 1), SET_TLB_ENTRY(1, CONFIG_SYS_FPGA_BASE, CONFIG_SYS_FPGA_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 8, BOOKE_PAGESZ_16M, 1),

};

int num_tlb_entries = ARRAY_SIZE(tlb_table);