Since commit 957731ed (ARM: remove broken "lpd7a40x" boards), lh7a40x cpu and serial driver have become unused. Remove them.

Signed-off-by: Albert ARIBAUD albert.u.boot@aribaud.net --- A full MAKEALL -a arm shows no difference (271 boards built, two with yaffs warnings) between before and after removal.

arch/arm/cpu/lh7a40x/Makefile | 47 ---- arch/arm/cpu/lh7a40x/config.mk | 33 --- arch/arm/cpu/lh7a40x/cpu.c | 65 ----- arch/arm/cpu/lh7a40x/speed.c | 83 ------ arch/arm/cpu/lh7a40x/start.S | 506 ------------------------------------- arch/arm/cpu/lh7a40x/timer.c | 182 ------------- doc/driver-model/UDM-serial.txt | 32 +-- drivers/serial/Makefile | 1 - drivers/serial/serial_lh7a40x.c | 184 -------------- drivers/usb/gadget/gadget_chips.h | 34 +-- include/lh7a400.h | 75 ------ include/lh7a404.h | 83 ------ include/lh7a40x.h | 279 -------------------- include/lpd7a400_cpld.h | 195 -------------- 14 files changed, 27 insertions(+), 1772 deletions(-) delete mode 100644 arch/arm/cpu/lh7a40x/Makefile delete mode 100644 arch/arm/cpu/lh7a40x/config.mk delete mode 100644 arch/arm/cpu/lh7a40x/cpu.c delete mode 100644 arch/arm/cpu/lh7a40x/speed.c delete mode 100644 arch/arm/cpu/lh7a40x/start.S delete mode 100644 arch/arm/cpu/lh7a40x/timer.c delete mode 100644 drivers/serial/serial_lh7a40x.c delete mode 100644 include/lh7a400.h delete mode 100644 include/lh7a404.h delete mode 100644 include/lh7a40x.h delete mode 100644 include/lpd7a400_cpld.h

diff --git a/arch/arm/cpu/lh7a40x/Makefile b/arch/arm/cpu/lh7a40x/Makefile deleted file mode 100644 index 01cf7f5..0000000 --- a/arch/arm/cpu/lh7a40x/Makefile +++ /dev/null @@ -1,47 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(CPU).o - -START = start.o -COBJS = cpu.o speed.o timer.o - -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) -START := $(addprefix $(obj),$(START)) - -all: $(obj).depend $(START) $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/arch/arm/cpu/lh7a40x/config.mk b/arch/arm/cpu/lh7a40x/config.mk deleted file mode 100644 index 1c4aa97..0000000 --- a/arch/arm/cpu/lh7a40x/config.mk +++ /dev/null @@ -1,33 +0,0 @@ -# -# (C) Copyright 2002 -# Gary Jennejohn, DENX Software Engineering, garyj@denx.de -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float - -PLATFORM_CPPFLAGS += -march=armv4 -# ========================================================================= -# -# Supply options according to compiler version -# -# ======================================================================== -PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) -PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT) diff --git a/arch/arm/cpu/lh7a40x/cpu.c b/arch/arm/cpu/lh7a40x/cpu.c deleted file mode 100644 index b193189..0000000 --- a/arch/arm/cpu/lh7a40x/cpu.c +++ /dev/null @@ -1,65 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger mgroeger@sysgo.de - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, garyj@denx.de - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * CPU specific code - */ - -#include <common.h> -#include <command.h> -#include <asm/system.h> - -static void cache_flush(void); - -int cleanup_before_linux (void) -{ - /* - * this function is called just before we call linux - * it prepares the processor for linux - * - * we turn off caches etc ... - */ - - disable_interrupts (); - - /* turn off I/D-cache */ - icache_disable(); - dcache_disable(); - - /* flush I/D-cache */ - cache_flush(); - - return 0; -} - -/* flush I/D-cache */ -static void cache_flush (void) -{ - unsigned long i = 0; - - asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i)); -} diff --git a/arch/arm/cpu/lh7a40x/speed.c b/arch/arm/cpu/lh7a40x/speed.c deleted file mode 100644 index 333ebb5..0000000 --- a/arch/arm/cpu/lh7a40x/speed.c +++ /dev/null @@ -1,83 +0,0 @@ -/* - * (C) Copyright 2001-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2002 - * David Mueller, ELSOFT AG, d.mueller@elsoft.ch - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <lh7a40x.h> - - -/* ------------------------------------------------------------------------- */ -/* NOTE: This describes the proper use of this file. - * - * CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL. - * - * get_FCLK(), get_HCLK(), get_PCLK() return the clock of - * the specified bus in HZ. - */ -/* ------------------------------------------------------------------------- */ - -ulong get_PLLCLK (void) -{ - return CONFIG_SYS_CLK_FREQ; -} - -/* return FCLK frequency */ -ulong get_FCLK (void) -{ - lh7a40x_csc_t* csc = LH7A40X_CSC_PTR; - ulong maindiv1, maindiv2, prediv, ps; - - /* - * from userguide 6.1.1.2 - * - * FCLK = ((MAINDIV1 +2) * (MAINDIV2 +2) * 14.7456MHz) / - * ((PREDIV+2) * (2^PS)) - */ - maindiv2 = (csc->clkset & CLKSET_MAINDIV2) >> 11; - maindiv1 = (csc->clkset & CLKSET_MAINDIV1) >> 7; - prediv = (csc->clkset & CLKSET_PREDIV) >> 2; - ps = (csc->clkset & CLKSET_PS) >> 16; - - return (((maindiv2 + 2) * (maindiv1 + 2) * CONFIG_SYS_CLK_FREQ) / - ((prediv + 2) * (1 << ps))); -} - - -/* return HCLK frequency */ -ulong get_HCLK (void) -{ - lh7a40x_csc_t* csc = LH7A40X_CSC_PTR; - - return (get_FCLK () / ((csc->clkset & CLKSET_HCLKDIV) + 1)); -} - -/* return PCLK frequency */ -ulong get_PCLK (void) -{ - lh7a40x_csc_t* csc = LH7A40X_CSC_PTR; - - return (get_HCLK () / - (1 << (((csc->clkset & CLKSET_PCLKDIV) >> 16) + 1))); -} diff --git a/arch/arm/cpu/lh7a40x/start.S b/arch/arm/cpu/lh7a40x/start.S deleted file mode 100644 index 33b9269..0000000 --- a/arch/arm/cpu/lh7a40x/start.S +++ /dev/null @@ -1,506 +0,0 @@ -/* - * armboot - Startup Code for ARM920 CPU-core - * - * Copyright (c) 2001 Marius Gröger mag@sysgo.de - * Copyright (c) 2002 Alex Züpke azu@sysgo.de - * Copyright (c) 2002 Gary Jennejohn garyj@denx.de - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <asm-offsets.h> -#include <config.h> -#include <version.h> - -/* - ************************************************************************* - * - * Jump vector table as in table 3.1 in [1] - * - ************************************************************************* - */ - - -.globl _start -_start: b reset - ldr pc, _undefined_instruction - ldr pc, _software_interrupt - ldr pc, _prefetch_abort - ldr pc, _data_abort - ldr pc, _not_used - ldr pc, _irq - ldr pc, _fiq - -_undefined_instruction: .word undefined_instruction -_software_interrupt: .word software_interrupt -_prefetch_abort: .word prefetch_abort -_data_abort: .word data_abort -_not_used: .word not_used -_irq: .word irq -_fiq: .word fiq - - .balignl 16,0xdeadbeef - - -/* - ************************************************************************* - * - * Startup Code (reset vector) - * - * do important init only if we don't start from memory! - * relocate armboot to ram - * setup stack - * jump to second stage - * - ************************************************************************* - */ - -.globl _TEXT_BASE -_TEXT_BASE: - .word CONFIG_SYS_TEXT_BASE - -/* - * These are defined in the board-specific linker script. - * Subtracting _start from them lets the linker put their - * relative position in the executable instead of leaving - * them null. - */ -.globl _bss_start_ofs -_bss_start_ofs: - .word __bss_start - _start - -.globl _bss_end_ofs -_bss_end_ofs: - .word __bss_end__ - _start - -.globl _end_ofs -_end_ofs: - .word _end - _start - -#ifdef CONFIG_USE_IRQ -/* IRQ stack memory (calculated at run-time) */ -.globl IRQ_STACK_START -IRQ_STACK_START: - .word 0x0badc0de - -/* IRQ stack memory (calculated at run-time) */ -.globl FIQ_STACK_START -FIQ_STACK_START: - .word 0x0badc0de -#endif - -/* IRQ stack memory (calculated at run-time) + 8 bytes */ -.globl IRQ_STACK_START_IN -IRQ_STACK_START_IN: - .word 0x0badc0de - -/* - * the actual reset code - */ - -reset: - /* - * set the cpu to SVC32 mode - */ - mrs r0,cpsr - bic r0,r0,#0x1f - orr r0,r0,#0xd3 - msr cpsr,r0 - -#define pWDTCTL 0x80001400 /* Watchdog Timer control register */ -#define pINTENC 0x8000050C /* Interrupt-Controller enable clear register */ -#define pCLKSET 0x80000420 /* clock divisor register */ - - /* disable watchdog, set watchdog control register to - * all zeros (default reset) - */ - ldr r0, =pWDTCTL - mov r1, #0x0 - str r1, [r0] - - /* - * mask all IRQs by setting all bits in the INTENC register (default) - */ - mov r1, #0xffffffff - ldr r0, =pINTENC - str r1, [r0] - - /* FCLK:HCLK:PCLK = 1:2:2 */ - /* default FCLK is 200 MHz, using 14.7456 MHz fin */ - ldr r0, =pCLKSET - ldr r1, =0x0004ee39 -@ ldr r1, =0x0005ee39 @ 1: 2: 4 - str r1, [r0] - - /* - * we do sys-critical inits only at reboot, - * not when booting from ram! - */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT - bl cpu_init_crit -#endif - -/* Set stackpointer in internal RAM to call board_init_f */ -call_board_init_f: - ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) - bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ - ldr r0,=0x00000000 - bl board_init_f - -/*------------------------------------------------------------------------------*/ - -/* - * void relocate_code (addr_sp, gd, addr_moni) - * - * This "function" does not return, instead it continues in RAM - * after relocating the monitor code. - * - */ - .globl relocate_code -relocate_code: - mov r4, r0 /* save addr_sp */ - mov r5, r1 /* save addr of gd */ - mov r6, r2 /* save addr of destination */ - - /* Set up the stack */ -stack_setup: - mov sp, r4 - - adr r0, _start - cmp r0, r6 - moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ - beq clear_bss /* skip relocation */ - mov r1, r6 /* r1 <- scratch for copy_loop */ - ldr r3, _bss_start_ofs - add r2, r0, r3 /* r2 <- source end address */ - -copy_loop: - ldmia r0!, {r9-r10} /* copy from source address [r0] */ - stmia r1!, {r9-r10} /* copy to target address [r1] */ - cmp r0, r2 /* until source end address [r2] */ - blo copy_loop - -#ifndef CONFIG_SPL_BUILD - /* - * fix .rel.dyn relocations - */ - ldr r0, _TEXT_BASE /* r0 <- Text base */ - sub r9, r6, r0 /* r9 <- relocation offset */ - ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */ - add r10, r10, r0 /* r10 <- sym table in FLASH */ - ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */ - add r2, r2, r0 /* r2 <- rel dyn start in FLASH */ - ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */ - add r3, r3, r0 /* r3 <- rel dyn end in FLASH */ -fixloop: - ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */ - add r0, r0, r9 /* r0 <- location to fix up in RAM */ - ldr r1, [r2, #4] - and r7, r1, #0xff - cmp r7, #23 /* relative fixup? */ - beq fixrel - cmp r7, #2 /* absolute fixup? */ - beq fixabs - /* ignore unknown type of fixup */ - b fixnext -fixabs: - /* absolute fix: set location to (offset) symbol value */ - mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */ - add r1, r10, r1 /* r1 <- address of symbol in table */ - ldr r1, [r1, #4] /* r1 <- symbol value */ - add r1, r1, r9 /* r1 <- relocated sym addr */ - b fixnext -fixrel: - /* relative fix: increase location by offset */ - ldr r1, [r0] - add r1, r1, r9 -fixnext: - str r1, [r0] - add r2, r2, #8 /* each rel.dyn entry is 8 bytes */ - cmp r2, r3 - blo fixloop -#endif - -clear_bss: -#ifndef CONFIG_SPL_BUILD - ldr r0, _bss_start_ofs - ldr r1, _bss_end_ofs - mov r4, r6 /* reloc addr */ - add r0, r0, r4 - add r1, r1, r4 - mov r2, #0x00000000 /* clear */ - -clbss_l:cmp r0, r1 /* clear loop... */ - bhs clbss_e /* if reached end of bss, exit */ - str r2, [r0] - add r0, r0, #4 - b clbss_l -clbss_e: -#endif - -/* - * We are done. Do not return, instead branch to second part of board - * initialization, now running from RAM. - */ - ldr r0, _board_init_r_ofs - adr r1, _start - add lr, r0, r1 - add lr, lr, r9 - /* setup parameters for board_init_r */ - mov r0, r5 /* gd_t */ - mov r1, r6 /* dest_addr */ - /* jump to it ... */ - mov pc, lr - -_board_init_r_ofs: - .word board_init_r - _start - -_rel_dyn_start_ofs: - .word __rel_dyn_start - _start -_rel_dyn_end_ofs: - .word __rel_dyn_end - _start -_dynsym_start_ofs: - .word __dynsym_start - _start - -/* - ************************************************************************* - * - * CPU_init_critical registers - * - * setup important registers - * setup memory timing - * - ************************************************************************* - */ - - -cpu_init_crit: - /* - * flush v4 I/D caches - */ - mov r0, #0 - mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ - mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ - - /* - * disable MMU stuff and caches - */ - mrc p15, 0, r0, c1, c0, 0 - bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) - bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) - orr r0, r0, #0x00000002 @ set bit 2 (A) Align - orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache - orr r0, r0, #0x40000000 @ set bit 30 (nF) notFastBus - mcr p15, 0, r0, c1, c0, 0 - - - /* - * before relocating, we have to setup RAM timing - * because memory timing is board-dependend, you will - * find a lowlevel_init.S in your board directory. - */ - mov ip, lr - bl lowlevel_init - mov lr, ip - - mov pc, lr - - -/* - ************************************************************************* - * - * Interrupt handling - * - ************************************************************************* - */ - -@ -@ IRQ stack frame. -@ -#define S_FRAME_SIZE 72 - -#define S_OLD_R0 68 -#define S_PSR 64 -#define S_PC 60 -#define S_LR 56 -#define S_SP 52 - -#define S_IP 48 -#define S_FP 44 -#define S_R10 40 -#define S_R9 36 -#define S_R8 32 -#define S_R7 28 -#define S_R6 24 -#define S_R5 20 -#define S_R4 16 -#define S_R3 12 -#define S_R2 8 -#define S_R1 4 -#define S_R0 0 - -#define MODE_SVC 0x13 -#define I_BIT 0x80 - -/* - * use bad_save_user_regs for abort/prefetch/undef/swi ... - * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling - */ - - .macro bad_save_user_regs - sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} @ Calling r0-r12 - ldr r2, IRQ_STACK_START_IN - ldmia r2, {r2 - r3} @ get pc, cpsr - add r0, sp, #S_FRAME_SIZE @ restore sp_SVC - - add r5, sp, #S_SP - mov r1, lr - stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr - mov r0, sp - .endm - - .macro irq_save_user_regs - sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} @ Calling r0-r12 - add r8, sp, #S_PC - stmdb r8, {sp, lr}^ @ Calling SP, LR - str lr, [r8, #0] @ Save calling PC - mrs r6, spsr - str r6, [r8, #4] @ Save CPSR - str r0, [r8, #8] @ Save OLD_R0 - mov r0, sp - .endm - - .macro irq_restore_user_regs - ldmia sp, {r0 - lr}^ @ Calling r0 - lr - mov r0, r0 - ldr lr, [sp, #S_PC] @ Get PC - add sp, sp, #S_FRAME_SIZE - subs pc, lr, #4 @ return & move spsr_svc into cpsr - .endm - - .macro get_bad_stack - ldr r13, IRQ_STACK_START_IN @ setup our mode stack - - str lr, [r13] @ save caller lr / spsr - mrs lr, spsr - str lr, [r13, #4] - - mov r13, #MODE_SVC @ prepare SVC-Mode - @ msr spsr_c, r13 - msr spsr, r13 - mov lr, pc - movs pc, lr - .endm - - .macro get_irq_stack @ setup IRQ stack - ldr sp, IRQ_STACK_START - .endm - - .macro get_fiq_stack @ setup FIQ stack - ldr sp, FIQ_STACK_START - .endm - -/* - * exception handlers - */ - .align 5 -undefined_instruction: - get_bad_stack - bad_save_user_regs - bl do_undefined_instruction - - .align 5 -software_interrupt: - get_bad_stack - bad_save_user_regs - bl do_software_interrupt - - .align 5 -prefetch_abort: - get_bad_stack - bad_save_user_regs - bl do_prefetch_abort - - .align 5 -data_abort: - get_bad_stack - bad_save_user_regs - bl do_data_abort - - .align 5 -not_used: - get_bad_stack - bad_save_user_regs - bl do_not_used - -#ifdef CONFIG_USE_IRQ - - .align 5 -irq: - get_irq_stack - irq_save_user_regs - bl do_irq - irq_restore_user_regs - - .align 5 -fiq: - get_fiq_stack - /* someone ought to write a more effiction fiq_save_user_regs */ - irq_save_user_regs - bl do_fiq - irq_restore_user_regs - -#else - - .align 5 -irq: - get_bad_stack - bad_save_user_regs - bl do_irq - - .align 5 -fiq: - get_bad_stack - bad_save_user_regs - bl do_fiq - -#endif - - .align 5 -.globl reset_cpu -reset_cpu: - bl disable_interrupts - - /* Disable watchdog */ - ldr r1, =pWDTCTL - mov r3, #0 - str r3, [r1] - - /* reset counter */ - ldr r3, =0x00001984 - str r3, [r1, #4] - - /* Enable the watchdog */ - mov r3, #1 - str r3, [r1] - -_loop_forever: - b _loop_forever diff --git a/arch/arm/cpu/lh7a40x/timer.c b/arch/arm/cpu/lh7a40x/timer.c deleted file mode 100644 index 58b35b1..0000000 --- a/arch/arm/cpu/lh7a40x/timer.c +++ /dev/null @@ -1,182 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger mgroeger@sysgo.de - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Alex Zuepke azu@sysgo.de - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, garyj@denx.de - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <lh7a40x.h> - -static ulong timer_load_val = 0; - -/* macro to read the 16 bit timer */ -static inline ulong READ_TIMER(void) -{ - lh7a40x_timers_t* timers = LH7A40X_TIMERS_PTR; - lh7a40x_timer_t* timer = &timers->timer1; - - return (timer->value & 0x0000ffff); -} - -static ulong timestamp; -static ulong lastdec; - -int timer_init (void) -{ - lh7a40x_timers_t* timers = LH7A40X_TIMERS_PTR; - lh7a40x_timer_t* timer = &timers->timer1; - - /* a periodic timer using the 508kHz source */ - timer->control = (TIMER_PER | TIMER_CLK508K); - - if (timer_load_val == 0) { - /* - * 10ms period with 508.469kHz clock = 5084 - */ - timer_load_val = CONFIG_SYS_HZ/100; - } - - /* load value for 10 ms timeout */ - lastdec = timer->load = timer_load_val; - - /* auto load, start timer */ - timer->control = timer->control | TIMER_EN; - timestamp = 0; - - return (0); -} - -/* - * timer without interrupts - */ -ulong get_timer (ulong base) -{ - return (get_timer_masked() - base); -} - -void __udelay (unsigned long usec) -{ - ulong tmo,tmp; - - /* normalize */ - if (usec >= 1000) { - tmo = usec / 1000; - tmo *= CONFIG_SYS_HZ; - tmo /= 1000; - } - else { - if (usec > 1) { - tmo = usec * CONFIG_SYS_HZ; - tmo /= (1000*1000); - } - else - tmo = 1; - } - - /* check for rollover during this delay */ - tmp = get_timer (0); - if ((tmp + tmo) < tmp ) - reset_timer_masked(); /* timer would roll over */ - else - tmo += tmp; - - while (get_timer_masked () < tmo); -} - -void reset_timer_masked (void) -{ - /* reset time */ - lastdec = READ_TIMER(); - timestamp = 0; -} - -ulong get_timer_masked (void) -{ - ulong now = READ_TIMER(); - - if (lastdec >= now) { - /* normal mode */ - timestamp += (lastdec - now); - } else { - /* we have an overflow ... */ - timestamp += ((lastdec + timer_load_val) - now); - } - lastdec = now; - - return timestamp; -} - -void udelay_masked (unsigned long usec) -{ - ulong tmo; - ulong endtime; - signed long diff; - - /* normalize */ - if (usec >= 1000) { - tmo = usec / 1000; - tmo *= CONFIG_SYS_HZ; - tmo /= 1000; - } else { - if (usec > 1) { - tmo = usec * CONFIG_SYS_HZ; - tmo /= (1000*1000); - } else { - tmo = 1; - } - } - - endtime = get_timer_masked () + tmo; - - do { - ulong now = get_timer_masked (); - diff = endtime - now; - } while (diff >= 0); -} - -/* - * This function is derived from PowerPC code (read timebase as long long). - * On ARM it just returns the timer value. - */ -unsigned long long get_ticks(void) -{ - return get_timer(0); -} - -/* - * This function is derived from PowerPC code (timebase clock frequency). - * On ARM it returns the number of timer ticks per second. - */ -ulong get_tbclk (void) -{ - ulong tbclk; - - tbclk = timer_load_val * 100; - - return tbclk; -} diff --git a/doc/driver-model/UDM-serial.txt b/doc/driver-model/UDM-serial.txt index e9c274d..9feb2e5 100644 --- a/doc/driver-model/UDM-serial.txt +++ b/doc/driver-model/UDM-serial.txt @@ -125,67 +125,63 @@ III) Analysis of in-tree drivers ------------------- No support for CONFIG_SERIAL_MULTI. Simple conversion possible.

- 17) serial_lh7a40x.c + 17) serial_lpc2292.c -------------------- No support for CONFIG_SERIAL_MULTI. Simple conversion possible.

- 18) serial_lpc2292.c + 18) serial_max3100.c -------------------- No support for CONFIG_SERIAL_MULTI. Simple conversion possible.

- 19) serial_max3100.c - -------------------- - No support for CONFIG_SERIAL_MULTI. Simple conversion possible. - - 20) serial_mxc.c + 19) serial_mxc.c ---------------- No support for CONFIG_SERIAL_MULTI. Simple conversion possible.

- 21) serial_netarm.c + 20) serial_netarm.c ------------------- No support for CONFIG_SERIAL_MULTI. Simple conversion possible.

- 22) serial_pl01x.c + 21) serial_pl01x.c ------------------ No support for CONFIG_SERIAL_MULTI. Simple conversion possible, though this driver in fact contains two drivers in total.

- 23) serial_pxa.c + 22) serial_pxa.c ---------------- This driver is a bit complicated, but due to clean support for CONFIG_SERIAL_MULTI, there are no expected obstructions throughout the conversion process.

- 24) serial_s3c24x0.c + 23) serial_s3c24x0.c -------------------- This driver, being quite ad-hoc might need some work to bring back to shape.

- 25) serial_s3c44b0.c + 24) serial_s3c44b0.c -------------------- No support for CONFIG_SERIAL_MULTI. Simple conversion possible.

- 26) serial_s5p.c + 25) serial_s5p.c ---------------- No support for CONFIG_SERIAL_MULTI. Simple conversion possible.

- 27) serial_sa1100.c + 26) serial_sa1100.c ------------------- No support for CONFIG_SERIAL_MULTI. Simple conversion possible.

- 28) serial_sh.c + 27) serial_sh.c --------------- No support for CONFIG_SERIAL_MULTI. Simple conversion possible.

- 29) serial_xuartlite.c + 28) serial_xuartlite.c ---------------------- No support for CONFIG_SERIAL_MULTI. Simple conversion possible.

- 30) usbtty.c + 29) usbtty.c ------------ This driver seems very complicated and entangled with USB framework. The conversion might be complicated here.

- 31) arch/powerpc/cpu/mpc512x/serial.c + 30) arch/powerpc/cpu/mpc512x/serial.c ------------------------------------- This driver supports CONFIG_SERIAL_MULTI. This driver will need to be moved to proper place. diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index dfc22a4..341c755 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -43,7 +43,6 @@ COBJS-$(CONFIG_IMX_SERIAL) += serial_imx.o COBJS-$(CONFIG_IXP_SERIAL) += serial_ixp.o COBJS-$(CONFIG_KS8695_SERIAL) += serial_ks8695.o COBJS-$(CONFIG_LPC2292_SERIAL) += serial_lpc2292.o -COBJS-$(CONFIG_LH7A40X_SERIAL) += serial_lh7a40x.o COBJS-$(CONFIG_MAX3100_SERIAL) += serial_max3100.o COBJS-$(CONFIG_MXC_UART) += serial_mxc.o COBJS-$(CONFIG_NETARM_SERIAL) += serial_netarm.o diff --git a/drivers/serial/serial_lh7a40x.c b/drivers/serial/serial_lh7a40x.c deleted file mode 100644 index 4767489..0000000 --- a/drivers/serial/serial_lh7a40x.c +++ /dev/null @@ -1,184 +0,0 @@ -/* - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, garyj@denx.de - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - */ - -#include <common.h> -#include <lh7a40x.h> - -DECLARE_GLOBAL_DATA_PTR; - -#if defined(CONFIG_CONSOLE_UART1) -# define UART_CONSOLE 1 -#elif defined(CONFIG_CONSOLE_UART2) -# define UART_CONSOLE 2 -#elif defined(CONFIG_CONSOLE_UART3) -# define UART_CONSOLE 3 -#else -# error "No console configured ... " -#endif - -void serial_setbrg (void) -{ - lh7a40x_uart_t* uart = LH7A40X_UART_PTR(UART_CONSOLE); - int i; - unsigned int reg = 0; - - /* - * userguide 15.1.2.4 - * - * BAUDDIV is (UART_REF_FREQ/(16 X BAUD))-1 - * - * UART_REF_FREQ = external system clock input / 2 (Hz) - * BAUD is desired baudrate (bits/s) - * - * NOTE: we add (divisor/2) to numerator to round for - * more precision - */ - reg = (((get_PLLCLK()/2) + ((16*gd->baudrate)/2)) / (16 * gd->baudrate)) - 1; - uart->brcon = reg; - - for (i = 0; i < 100; i++); -} - -/* - * Initialise the serial port with the given baudrate. The settings - * are always 8 data bits, no parity, 1 stop bit, no start bits. - * - */ -int serial_init (void) -{ - lh7a40x_uart_t* uart = LH7A40X_UART_PTR(UART_CONSOLE); - - /* UART must be enabled before writing to any config registers */ - uart->con |= (UART_EN); - -#ifdef CONFIG_CONSOLE_UART1 - /* infrared disabled */ - uart->con |= UART_SIRD; -#endif - /* loopback disabled */ - uart->con &= ~(UART_LBE); - - /* modem lines and tx/rx polarities */ - uart->con &= ~(UART_MXP | UART_TXP | UART_RXP); - - /* FIFO enable, N81 */ - uart->fcon = (UART_WLEN_8 | UART_FEN | UART_STP2_1); - - /* set baudrate */ - serial_setbrg (); - - /* enable rx interrupt */ - uart->inten |= UART_RI; - - return (0); -} - -/* - * Read a single byte from the serial port. Returns 1 on success, 0 - * otherwise. When the function is succesfull, the character read is - * written into its argument c. - */ -int serial_getc (void) -{ - lh7a40x_uart_t* uart = LH7A40X_UART_PTR(UART_CONSOLE); - - /* wait for character to arrive */ - while (uart->status & UART_RXFE); - - return(uart->data & 0xff); -} - -#ifdef CONFIG_HWFLOW -static int hwflow = 0; /* turned off by default */ -int hwflow_onoff(int on) -{ - switch(on) { - case 0: - default: - break; /* return current */ - case 1: - hwflow = 1; /* turn on */ - break; - case -1: - hwflow = 0; /* turn off */ - break; - } - return hwflow; -} -#endif - -#ifdef CONFIG_MODEM_SUPPORT -static int be_quiet = 0; -void disable_putc(void) -{ - be_quiet = 1; -} - -void enable_putc(void) -{ - be_quiet = 0; -} -#endif - - -/* - * Output a single byte to the serial port. - */ -void serial_putc (const char c) -{ - lh7a40x_uart_t* uart = LH7A40X_UART_PTR(UART_CONSOLE); - -#ifdef CONFIG_MODEM_SUPPORT - if (be_quiet) - return; -#endif - - /* wait for room in the tx FIFO */ - while (!(uart->status & UART_TXFE)); - -#ifdef CONFIG_HWFLOW - /* Wait for CTS up */ - while(hwflow && !(uart->status & UART_CTS)); -#endif - - uart->data = c; - - /* If \n, also do \r */ - if (c == '\n') - serial_putc ('\r'); -} - -/* - * Test whether a character is in the RX buffer - */ -int serial_tstc (void) -{ - lh7a40x_uart_t* uart = LH7A40X_UART_PTR(UART_CONSOLE); - - return(!(uart->status & UART_RXFE)); -} - -void -serial_puts (const char *s) -{ - while (*s) { - serial_putc (*s++); - } -} diff --git a/drivers/usb/gadget/gadget_chips.h b/drivers/usb/gadget/gadget_chips.h index 5d7b638..02cae0f 100644 --- a/drivers/usb/gadget/gadget_chips.h +++ b/drivers/usb/gadget/gadget_chips.h @@ -58,12 +58,6 @@ #define gadget_is_sa1100(g) 0 #endif

-#ifdef CONFIG_USB_GADGET_LH7A40X -#define gadget_is_lh7a40x(g) (!strcmp("lh7a40x_udc", (g)->name)) -#else -#define gadget_is_lh7a40x(g) 0 -#endif - /* handhelds.org tree (?) */ #ifdef CONFIG_USB_GADGET_MQ11XX #define gadget_is_mq11xx(g) (!strcmp("mq11xx_udc", (g)->name)) @@ -195,33 +189,31 @@ static inline int usb_gadget_controller_number(struct usb_gadget *gadget) return 0x07; else if (gadget_is_omap(gadget)) return 0x08; - else if (gadget_is_lh7a40x(gadget)) - return 0x09; else if (gadget_is_n9604(gadget)) - return 0x10; + return 0x09; else if (gadget_is_pxa27x(gadget)) - return 0x11; + return 0x10; else if (gadget_is_s3c2410(gadget)) - return 0x12; + return 0x11; else if (gadget_is_at91(gadget)) - return 0x13; + return 0x12; else if (gadget_is_imx(gadget)) - return 0x14; + return 0x13; else if (gadget_is_musbhsfc(gadget)) - return 0x15; + return 0x14; else if (gadget_is_musbhdrc(gadget)) - return 0x16; + return 0x15; else if (gadget_is_mpc8272(gadget)) - return 0x17; + return 0x16; else if (gadget_is_atmel_usba(gadget)) - return 0x18; + return 0x17; else if (gadget_is_fsl_usb2(gadget)) - return 0x19; + return 0x18; else if (gadget_is_amd5536udc(gadget)) - return 0x20; + return 0x19; else if (gadget_is_m66592(gadget)) - return 0x21; + return 0x20; else if (gadget_is_mv(gadget)) - return 0x22; + return 0x21; return -ENOENT; } diff --git a/include/lh7a400.h b/include/lh7a400.h deleted file mode 100644 index d1e70a2..0000000 --- a/include/lh7a400.h +++ /dev/null @@ -1,75 +0,0 @@ -/* - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * lh7a400 SoC interface - */ - -#ifndef __LH7A400_H__ -#define __LH7A400_H__ - -#include "lh7a40x.h" - -/* Interrupt Controller (userguide 8.2.1) */ -typedef struct { - volatile u32 intsr; - volatile u32 intrsr; - volatile u32 intens; - volatile u32 intenc; - volatile u32 rsvd1; - volatile u32 rsvd2; - volatile u32 rsvd3; -} /*__attribute__((__packed__))*/ lh7a400_interrupt_t; -#define LH7A400_INTERRUPT_BASE (0x80000500) -#define LH7A400_INTERRUPT_PTR ((lh7a400_interrupt_t*) LH7A400_INTERRUPT_BASE) - -/* (DMA) Direct Memory Access Controller (userguide 9.2.1) */ -typedef struct { - lh7a40x_dmachan_t chan[15]; - volatile u32 glblint; - volatile u32 rsvd1; - volatile u32 rsvd2; - volatile u32 rsvd3; -} /*__attribute__((__packed__))*/ lh7a400_dma_t; - -#define LH7A400_DMA_BASE (0x80002800) -#define DMA_USBTX_OFFSET (0x000) -#define DMA_USBRX_OFFSET (0x040) -#define DMA_MMCTX_OFFSET (0x080) -#define DMA_MMCRX_OFFSET (0x0C0) -#define DMA_AC97_BASE (0x80002A00) - -#define LH7A400_DMA_PTR ((lh7a400_dma_t*) LH7A400_DMA_BASE) -#define LH7A400_DMA_USBTX \ - ((lh7a400_dmachan_t*) (LH7A400_DMA_BASE + DMA_USBTX_OFFSET)) -#define LH7A400_DMA_USBRX \ - ((lh7a400_dmachan_t*) (LH7A400_DMA_BASE + DMA_USBRX_OFFSET)) -#define LH7A400_DMA_MMCTX \ - ((lh7a400_dmachan_t*) (LH7A400_DMA_BASE + DMA_MMCTX_OFFSET)) -#define LH7A400_DMA_MMCRX \ - ((lh7a400_dmachan_t*) (LH7A400_DMA_BASE + DMA_MMCRX_OFFSET)) -#define LH7A400_AC97RX(n) \ - ((lh7a400_dmachan_t*) (LH7A400_AC97_BASE + \ - ((2*n) * sizeof(lh7a400_dmachan_t)))) -#define LH7A400_AC97TX(n) \ - ((lh7a400_dmachan_t*) (LH7A400_AC97_BASE + \ - (((2*n)+1) * sizeof(lh7a400_dmachan_t)))) - -#endif /* __LH7A400_H__ */ diff --git a/include/lh7a404.h b/include/lh7a404.h deleted file mode 100644 index 4098af3..0000000 --- a/include/lh7a404.h +++ /dev/null @@ -1,83 +0,0 @@ -/* - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * lh7a404 SoC interface - */ - -#ifndef __LH7A404_H__ -#define __LH7A404_H__ - -#include "lh7a40x.h" - -/* Interrupt Controller (userguide 8.2.1) */ -typedef struct { - volatile u32 irqstatus; - volatile u32 fiqstatus; - volatile u32 rawintr; - volatile u32 intsel; - volatile u32 inten; - volatile u32 intenclr; - volatile u32 softint; - volatile u32 softintclr; - volatile u32 protect; - volatile u32 unused1; - volatile u32 unused2; - volatile u32 vectaddr; - volatile u32 nvaddr; - volatile u32 unused3[32]; - volatile u32 vad[16]; - volatile u32 unused4[44]; - volatile u32 vectcntl[16]; - volatile u32 unused5[44]; - volatile u32 itcr; - volatile u32 itip1; - volatile u32 itip2; - volatile u32 itop1; - volatile u32 itop2; - volatile u32 unused6[333]; - volatile u32 periphid[4]; - volatile u32 pcellid[4]; -} /*__attribute__((__packed__))*/ lh7a404_vic_t; -#define LH7A404_VIC_BASE (0x80008000) -#define LH7A400_VIC_PTR(x) ((lh7a404_vic_t*)(LH7A400_VIC_BASE + (x*0x2000))) - - -typedef struct { - lh7a40x_dmachan_t m2p0_tx; - lh7a40x_dmachan_t m2p1_rx; - lh7a40x_dmachan_t m2p2_tx; - lh7a40x_dmachan_t m2p3_rx; - lh7a40x_dmachan_t m2m0; - lh7a40x_dmachan_t m2m1; - lh7a40x_dmachan_t unused1; - lh7a40x_dmachan_t unused2; - lh7a40x_dmachan_t m2p5_rx; - lh7a40x_dmachan_t m2p4_tx; - lh7a40x_dmachan_t m2p7_rx; - lh7a40x_dmachan_t m2p6_tx; - lh7a40x_dmachan_t m2p9_rx; - lh7a40x_dmachan_t m2p8_tx; - volatile u32 chanarb; - volatile u32 glblint; -} /*__attribute__((__packed__))*/ lh7a400_dma_t; - - -#endif /* __LH7A404_H__ */ diff --git a/include/lh7a40x.h b/include/lh7a40x.h deleted file mode 100644 index 09a463c..0000000 --- a/include/lh7a40x.h +++ /dev/null @@ -1,279 +0,0 @@ -/* - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * lh7a40x SoC series common interface - */ - -#ifndef __LH7A40X_H__ -#define __LH7A40X_H__ - -/* (SMC) Static Memory Controller (usersguide 4.2.1) */ -typedef struct { - volatile u32 attib; - volatile u32 com; - volatile u32 io; - volatile u32 rsvd1; -} /*__attribute__((__packed__))*/ lh7a40x_pccard_t; - -typedef struct { - volatile u32 bcr[8]; - lh7a40x_pccard_t pccard[2]; - volatile u32 pcmciacon; -} /*__attribute__((__packed__))*/ lh7a40x_smc_t; -#define LH7A40X_SMC_BASE (0x80002000) -#define LH7A40X_SMC_PTR ((lh7a40x_smc_t*) LH7A40X_SMC_BASE) - -/* (SDMC) Synchronous Dynamic Ram Controller (usersguide 5.3.1) */ -typedef struct { - volatile u32 rsvd1; - volatile u32 gblcnfg; - volatile u32 rfshtmr; - volatile u32 bootstat; - volatile u32 sdcsc[4]; -} /*__attribute__((__packed__))*/ lh7a40x_sdmc_t; -#define LH7A40X_SDMC_BASE (0x80002400) -#define LH7A40X_SDMC_PTR ((lh7a40x_sdmc_t*) LH7A40X_SDMC_BASE) - -/* (CSC) Clock and State Controller (userguide 6.2.1) */ -typedef struct { - volatile u32 pwrsr; - volatile u32 pwrcnt; - volatile u32 halt; - volatile u32 stby; - volatile u32 bleoi; - volatile u32 mceoi; - volatile u32 teoi; - volatile u32 stfclr; - volatile u32 clkset; - volatile u32 scrreg[2]; - volatile u32 rsvd1; - volatile u32 usbreset; -} /*__attribute__((__packed__))*/ lh7a40x_csc_t; -#define LH7A40X_STPWR_BASE (0x80000400) -#define LH7A40X_CSC_PTR ((lh7a40x_csc_t*) LH7A40X_STPWR_BASE) - -#define CLKSET_SMCROM (0x01000000) -#define CLKSET_PS (0x000C0000) -#define CLKSET_PS_0 (0x00000000) -#define CLKSET_PS_1 (0x00040000) -#define CLKSET_PS_2 (0x00080000) -#define CLKSET_PS_3 (0x000C0000) -#define CLKSET_PCLKDIV (0x00030000) -#define CLKSET_PCLKDIV_2 (0x00000000) -#define CLKSET_PCLKDIV_4 (0x00010000) -#define CLKSET_PCLKDIV_8 (0x00020000) -#define CLKSET_MAINDIV2 (0x0000f800) -#define CLKSET_MAINDIV1 (0x00000780) -#define CLKSET_PREDIV (0x0000007C) -#define CLKSET_HCLKDIV (0x00000003) - -/* (DMA) Direct Memory Access Controller (userguide 9.2.1) */ -typedef struct { - volatile u32 maxcnt; - volatile u32 base; - volatile u32 current; - volatile u32 rsvd1; -} lh7a40x_dmabuf_t; - -typedef struct { - volatile u32 control; - volatile u32 interrupt; - volatile u32 rsvd1; - volatile u32 status; - volatile u32 rsvd2; - volatile u32 remain; - volatile u32 rsvd3; - volatile u32 rsvd4; - lh7a40x_dmabuf_t buf[2]; -} /*__attribute__((__packed__))*/ lh7a40x_dmachan_t; - - -/* (WDT) Watchdog Timer (userguide 11.2.1) */ -typedef struct { - volatile u32 ctl; - volatile u32 rst; - volatile u32 status; - volatile u32 count[4]; -} /*__attribute__((__packed__))*/ lh7a40x_wdt_t; -#define LH7A40X_WDT_BASE (0x80001400) -#define LH7A40X_WDT_PTR ((lh7a40x_wdt_t*) LH7A40X_WDT_BASE) - -/* (RTC) Real Time Clock (lh7a400 userguide 12.2.1, lh7a404 userguide 13.2.1) */ -typedef struct { - volatile u32 rtcdr; - volatile u32 rtclr; - volatile u32 rtcmr; - volatile u32 unk1; - volatile u32 rtcstat_eoi; - volatile u32 rtccr; - volatile u32 rsvd1[58]; -} /*__attribute__((__packed__))*/ lh7a40x_rtc_t; -#define LH7A40X_RTC_BASE (0x80000D00) -#define LH7A40X_RTC_PTR ((lh7a40x_rtc_t*) LH7A40X_RTC_BASE) - -/* Timers (lh7a400 userguide 13.2.1, lh7a404 userguide 11.2.1) */ -typedef struct { - volatile u32 load; - volatile u32 value; - volatile u32 control; - volatile u32 tceoi; -} /*__attribute__((__packed__))*/ lh7a40x_timer_t; - -typedef struct { - lh7a40x_timer_t timer1; - volatile u32 rsvd1[4]; - lh7a40x_timer_t timer2; - volatile u32 unk1[4]; - volatile u32 bzcon; - volatile u32 unk2[15]; - lh7a40x_timer_t timer3; - /*volatile u32 rsvd2;*/ -} /*__attribute__((__packed__))*/ lh7a40x_timers_t; -#define LH7A40X_TIMERS_BASE (0x80000C00) -#define LH7A40X_TIMERS_PTR ((lh7a40x_timers_t*) LH7A40X_TIMERS_BASE) - -#define TIMER_EN (0x00000080) -#define TIMER_PER (0x00000040) -#define TIMER_FREE (0x00000000) -#define TIMER_CLK508K (0x00000008) -#define TIMER_CLK2K (0x00000000) - -/* (SSP) Sychronous Serial Ports (lh7a400 userguide 14.2.1, lh7a404 userguide 14.2.1) */ -typedef struct { - volatile u32 cr0; - volatile u32 cr1; - volatile u32 irr_roeoi; - volatile u32 dr; - volatile u32 cpr; - volatile u32 sr; - /*volatile u32 rsvd1[58];*/ -} /*__attribute__((__packed__))*/ lh7a40x_ssp_t; -#define LH7A40X_SSP_BASE (0x80000B00) -#define LH7A40X_SSP_PTR ((lh7a40x_ssp_t*) LH7A40X_SSP_BASE) - -/* (UART) Universal Asychronous Receiver/Transmitter (lh7a400 userguide 15.2.1, lh7a404 userguide 15.2.1) */ -typedef struct { - volatile u32 data; - volatile u32 fcon; - volatile u32 brcon; - volatile u32 con; - volatile u32 status; - volatile u32 rawisr; - volatile u32 inten; - volatile u32 isr; - volatile u32 rsvd1[56]; -} /*__attribute__((__packed__))*/ lh7a40x_uart_t; -#define LH7A40X_UART_BASE (0x80000600) -#define LH7A40X_UART_PTR(n) \ - ((lh7a40x_uart_t*) (LH7A40X_UART_BASE + ((n-1) * sizeof(lh7a40x_uart_t)))) - -#define UART_BE (0x00000800) /* the rx error bits */ -#define UART_OE (0x00000400) -#define UART_PE (0x00000200) -#define UART_FE (0x00000100) - -#define UART_WLEN (0x00000060) /* fcon bits */ -#define UART_WLEN_8 (0x00000060) -#define UART_WLEN_7 (0x00000040) -#define UART_WLEN_6 (0x00000020) -#define UART_WLEN_5 (0x00000000) -#define UART_FEN (0x00000010) -#define UART_STP2 (0x00000008) -#define UART_STP2_2 (0x00000008) -#define UART_STP2_1 (0x00000000) -#define UART_EPS (0x00000004) -#define UART_EPS_EVEN (0x00000004) -#define UART_EPS_ODD (0x00000000) -#define UART_PEN (0x00000002) -#define UART_BRK (0x00000001) - -#define UART_BAUDDIV (0x0000ffff) /* brcon bits */ - -#define UART_SIRBD (0x00000080) /* con bits */ -#define UART_LBE (0x00000040) -#define UART_MXP (0x00000020) -#define UART_TXP (0x00000010) -#define UART_RXP (0x00000008) -#define UART_SIRLP (0x00000004) -#define UART_SIRD (0x00000002) -#define UART_EN (0x00000001) - -#define UART_TXFE (0x00000080) /* status bits */ -#define UART_RXFF (0x00000040) -#define UART_TXFF (0x00000020) -#define UART_RXFE (0x00000010) -#define UART_BUSY (0x00000008) -#define UART_DCD (0x00000004) -#define UART_DSR (0x00000002) -#define UART_CTS (0x00000001) - -#define UART_MSEOI (0xfffffff0) /* rawisr interrupt bits */ - -#define UART_RTI (0x00000008) /* generic interrupt bits */ -#define UART_MI (0x00000004) -#define UART_TI (0x00000002) -#define UART_RI (0x00000001) - -/* (GPIO) General Purpose IO and External Interrupts (userguide 16.2.1) */ -typedef struct { - volatile u32 pad; - volatile u32 pbd; - volatile u32 pcd; - volatile u32 pdd; - volatile u32 padd; - volatile u32 pbdd; - volatile u32 pcdd; - volatile u32 pddd; - volatile u32 ped; - volatile u32 pedd; - volatile u32 kbdctl; - volatile u32 pinmux; - volatile u32 pfd; - volatile u32 pfdd; - volatile u32 pgd; - volatile u32 pgdd; - volatile u32 phd; - volatile u32 phdd; - volatile u32 rsvd1; - volatile u32 inttype1; - volatile u32 inttype2; - volatile u32 gpiofeoi; - volatile u32 gpiointen; - volatile u32 intstatus; - volatile u32 rawintstatus; - volatile u32 gpiodb; - volatile u32 papd; - volatile u32 pbpd; - volatile u32 pcpd; - volatile u32 pdpd; - volatile u32 pepd; - volatile u32 pfpd; - volatile u32 pgpd; - volatile u32 phpd; -} /*__attribute__((__packed__))*/ lh7a40x_gpioint_t; -#define LH7A40X_GPIOINT_BASE (0x80000E00) -#define LH7A40X_GPIOINT_PTR ((lh7a40x_gpioint_t*) LH7A40X_GPIOINT_BASE) - -/* Embedded SRAM */ -#define CONFIG_SYS_SRAM_BASE (0xB0000000) -#define CONFIG_SYS_SRAM_SIZE (80*1024) /* 80kB */ - -#endif /* __LH7A40X_H__ */ diff --git a/include/lpd7a400_cpld.h b/include/lpd7a400_cpld.h deleted file mode 100644 index c70af09..0000000 --- a/include/lpd7a400_cpld.h +++ /dev/null @@ -1,195 +0,0 @@ -/* - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * Logic lh7a400-10 Card Engine CPLD interface - */ - -#ifndef __LPD7A400_CPLD_H_ -#define __LPD7A400_CPLD_H_ - - -/* - * IO Controller Address and Register Definitions - * - using LH7A400-10 Card Engine IO Controller Specification - * (logic PN: 70000079) - */ - -/*------------------------------------------------------------------ - * Slow Peripherals (nCS6) - */ -#define LPD7A400_CPLD_CF (0x60200000) -#define LPD7A400_CPLD_ISA (0x60400000) - -/*------------------------------------------------------------------ - * Fast Peripherals (nCS7) - * - * The CPLD directs access to 0x70000000-0x701fffff to the onboard - * ethernet controller - */ -#define LPD7A400_CPLD_WLAN_BASE (0x70000000) - -/* All registers are 8 bit */ -#define LPD7A400_CPLD_CECTL_REG (0x70200000) -#define LPD7A400_CPLD_SPIDATA_REG (0x70600000) -#define LPD7A400_CPLD_SPICTL_REG (0x70800000) -#define LPD7A400_CPLD_EEPSPI_REG (0x70a00000) -#define LPD7A400_CPLD_INTMASK_REG (0x70c00000) -#define LPD7A400_CPLD_MODE_REG (0x70e00000) -#define LPD7A400_CPLD_FLASH_REG (0x71000000) -#define LPD7A400_CPLD_PWRMG_REG (0x71200000) -#define LPD7A400_CPLD_REV_REG (0x71400000) -#define LPD7A400_CPLD_EXTGPIO_REG (0x71600000) -#define LPD7A400_CPLD_GPIODATA_REG (0x71800000) -#define LPD7A400_CPLD_GPIODIR_REG (0x71a00000) - -#define LPD7A400_CPLD_REGPTR (volatile u8*) - -/* Card Engine Control Register (section 3.1.2) */ -#define CECTL_SWINT (0x80) /* Software settable interrupt source - (routed to uP PF3) - 0 = generate interrupt, 1 = do not */ -#define CECTL_OCMSK (0x40) /* USB1 connection interrupt mask - 0 = not masked, 1 = masked */ -#define CECTL_PDRV (0x20) /* PCC_nDRV output - 0 = active, 1 = inactive */ -#define CECTL_USB1C (0x10) /* USB1 connection interrupt - 0 = active, 1 = inactive */ -#define CECTL_USB1P (0x08) /* USB1 Power enable - 0 = enabled, 1 = disabled */ -#define CECTL_AWKP (0x04) /* Auto-Wakeup enable - 0 = enabled, 1 = disabled */ -#define CECTL_LCDV (0x02) /* LCD VEE enable - 0 = disabled, 1 = enabled */ -#define CECTL_WLPE (0x01) /* Wired LAN power enable - 0 = enabled, 1 = disabled */ - -/* SPI Control Register (section 3.1.5) */ -#define SPICTL_SPLD (0x20) /* SPI load (R) - 0 = data reg. has not been loaded, shift - count has not been reset - 1 = data reg. loaded, shift count reset */ -#define SPICTL_SPST (0x10) /* SPI start (RW) - 0 = don't load data reg. and reset shift count - 1 = ready to load data reg and reset shift count */ -#define SPICTL_SPDN (0x08) /* SPI done (R) - 0 = not done - 1 = access done */ -#define SPICTL_SPRW (0x04) /* SPI read/write (RW) - 0 = SPI write access - 1 = SPI read access */ -#define SPICTL_STCS (0x02) /* SPI touch chip select (RW) - 0 = not selected - 1 = selected */ -#define SPICTL_SCCS (0x01) /* SPI CODEC chip select (RW) {not used} - 0 = not selected - 1 = selected */ - -/* EEPROM SPI Interface Register (section 3.1.6) */ -#define EEPSPI_EECS (0x08) /* EEPROM chip select (RW) - 0 = not selected - 1 = selected */ -#define EEPSPI_EECK (0x04) /* EEPROM SPI clock (RW) */ -#define EEPSPI_EETX (0x02) /* EEPROM SPI tx data (RW) */ -#define EEPSPI_EERX (0x01) /* EEPROM SPI rx data (R) */ - -/* Interrupt/Mask Register (section 3.1.7) */ -#define INTMASK_CMSK (0x80) /* CPLD_nIRQD interrupt mask (RW) - 0 = not masked - 1 = masked */ -#define INTMASK_CIRQ (0x40) /* interrupt signal to CPLD (R) - 0 = interrupt active - 1 = no interrupt */ -#define INTMASK_PIRQ (0x10) /* legacy, no effect */ -#define INTMASK_TMSK (0x08) /* Touch chip interrupt mask (RW) - 0 = not masked - 1 = masked */ -#define INTMASK_WMSK (0x04) /* Wired LAN interrupt mask (RW) - 0 = not masked - 1 = masked */ -#define INTMASK_TIRQ (0x02) /* Touch chip interrupt request (R) - 0 = interrupt active - 1 = no interrupt */ -#define INTMASK_WIRQ (0x01) /* Wired LAN interrupt request (R) - 0 = interrupt active - 1 = no interrupt */ - -/* Mode Register (section 3.1.8) */ -#define MODE_VS1 (0x80) /* PCMCIA Voltage Sense 1 input (PCC_VS1) (R) - 0 = active slot VS1 pin is low - 1 = active slot VS1 pin is high */ -#define MODE_CD2 (0x40) /* PCMCIA Card Detect 2 input (PCC_nCD2) (R) - 0 = active slot CD2 is low - 1 = active slot CD2 is high */ -#define MODE_IOIS16 (0x20) /* PCMCIA IOIS16 input (PCC_nIOIS16) (R) - 0 = 16 bit access area - 1 = 8 bit access area */ -#define MODE_CD1 (0x10) /* PCMCIA Card Detect 1 input (PCC_nCD1) (R) - 0 = active slot CD1 is low - 1 = active slot CD1 is high */ -#define MODE_upMODE3 (0x08) /* Mode Pin 3 (R) - 0 = off-board boot device - 1 = on-board boot device (flash) */ -#define MODE_upMODE2 (0x04) /* Mode Pin 2 (R) (LH7A400 Little Endian only) - 0 = big endian - 1 = little endian */ -#define MODE_upMODE1 (0x02) /* Mode Pin 1 and Mode Pin 2 (R) */ -#define MODE_upMODE0 (0x01) /* - bus width at boot */ - - -/* Flash Register (section 3.1.9) */ -#define FLASH_FPOP (0x08) /* Flash populated (RW) - 0 = populated, 1 = not */ -#define FLASH_FST2 (0x04) /* Flash status (R) (RY/BY# pin for upper 16 bit chip - 0 = busy, 1 = ready */ -#define FLASH_FST1 (0x02) /* Flash status (R) (RY/BY# pin for lower 16 bit chip - 0 = busy, 1 = ready */ -#define FLASH_FPEN (0x01) /* Flash program enable (RW) - 0 = flash write protected - 1 = programming enabled */ - -/* Power Management Register (section 3.1.10) - * - when either of these is low an unmaskable interrupt to cpu - * is generated - */ -#define PWRMG_STBY (0x10) /* state of nSTANDBY signal to CPLD (R) - 0 = low, 1 = high */ -#define PWRMG_SPND (0x04) /* state of nSUSPEND signal to CPLD (R) - 0 = low, 1 = high */ - - -/* Extended GPIO Register (section 3.1.12) */ -#define EXTGPIO_STATUS1 (0x04) /* Status 1 output (RW) (uP_STATUS_1) - 0 = set pin low, 1 = set pin high */ -#define EXTGPIO_STATUS2 (0x02) /* Status 2 output (RW) (uP_STATUS_2) - 0 = set pin low, 1 = set pin high */ -#define EXTGPIO_GPIO1 (0x01) /* General purpose output (RW) (CPLD_GPIO_1) - 0 = set pin low, 1 = set pin high */ - -/* GPIO Data Register (section 3.1.13) */ -#define GPIODATA_GPIO2 (0x01) /* General purpose input/output (RW) (CPLD_GPIO_2) - 0 = set low (output) / read low (input) - 1 = set high (output) / read high (input) */ - -/* GPIO Direction Register (section 3.1.14) */ -#define GPIODIR_GPDR0 (0x01) /* GPIO2 direction (RW) - 0 = output, 1 = input */ - -#endif /* __LH7A400_H__ */