[U-Boot] [PATCH 2/3] Add EP93xx ethernet driver
Added ethernet driver for EP93xx SoCs
Signed-off-by: Matthias Kaehlcke matthias@kaehlcke.net --- drivers/net/Makefile | 1 + drivers/net/ep93xx_eth.c | 654 ++++++++++++++++++++++++++++++++++++++++++++++ drivers/net/ep93xx_eth.h | 144 ++++++++++ include/common.h | 5 + include/netdev.h | 1 + 5 files changed, 805 insertions(+), 0 deletions(-) create mode 100644 drivers/net/ep93xx_eth.c create mode 100644 drivers/net/ep93xx_eth.h
diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 904727e..dc3107c 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -37,6 +37,7 @@ COBJS-$(CONFIG_DNET) += dnet.o COBJS-$(CONFIG_E1000) += e1000.o COBJS-$(CONFIG_EEPRO100) += eepro100.o COBJS-$(CONFIG_ENC28J60) += enc28j60.o +COBJS-$(CONFIG_EP93XX) += ep93xx_eth.o COBJS-$(CONFIG_FEC_MXC) += fec_mxc.o COBJS-$(CONFIG_FSLDMAFEC) += fsl_mcdmafec.o mcfmii.o COBJS-$(CONFIG_FTMAC100) += ftmac100.o diff --git a/drivers/net/ep93xx_eth.c b/drivers/net/ep93xx_eth.c new file mode 100644 index 0000000..33d14df --- /dev/null +++ b/drivers/net/ep93xx_eth.c @@ -0,0 +1,654 @@ +/* + * Cirrus Logic EP93xx ethernet MAC / MII driver. + * + * Copyright (C) 2010, 2009 + * Matthias Kaehlcke matthias@kaehlcke.net + * + * Copyright (C) 2004, 2005 + * Cory T. Tusar, Videon Central, Inc., ctusar@videon-central.com + * + * Based on the original eth.[ch] Cirrus Logic EP93xx Rev D. Ethernet Driver, + * which is + * + * (C) Copyright 2002 2003 + * Adam Bezanson, Network Audio Technologies, Inc. + * bezanson@netaudiotech.com + * + * See file CREDITS for list of people who contributed to this project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <command.h> +#include <common.h> +#include <asm/arch/ep93xx.h> +#include <asm/io.h> +#include <malloc.h> +#include <miiphy.h> +#include <linux/types.h> +#include "ep93xx_eth.h" + +#define GET_PRIV(eth_dev) ((struct ep93xx_priv *)eth_dev->priv) +#define GET_REGS(eth_dev) (GET_PRIV(eth_dev)->regs) + +/* ep93xx_miiphy ops forward declarations */ +static int ep93xx_miiphy_read(char * const dev, unsigned char const addr, + unsigned char const reg, unsigned short * const value); +static int ep93xx_miiphy_write(char * const dev, unsigned char const addr, + unsigned char const reg, unsigned short const value); + +#if defined(EP93XX_MAC_DEBUG) +/** + * Dump ep93xx_mac values to the terminal. + */ +inline void dump_dev(struct eth_device *dev) +{ + struct ep93xx_priv *priv = GET_PRIV(dev); + int i; + + printf("\ndump_dev()\n"); + printf(" rx_dq.base %08X\n", (uint32_t)priv->rx_dq.base); + printf(" rx_dq.current %08X\n", (uint32_t)priv->rx_dq.current); + printf(" rx_dq.end %08X\n", (uint32_t)priv->rx_dq.end); + printf(" rx_sq.base %08X\n", (uint32_t)priv->rx_sq.base); + printf(" rx_sq.current %08X\n", (uint32_t)priv->rx_sq.current); + printf(" rx_sq.end %08X\n", (uint32_t)priv->rx_sq.end); + + for (i = 0; i < NUMRXDESC; i++) + printf(" rx_buffer[%2.d] %08X\n", i, + (uint32_t)NetRxPackets[i]); + + printf(" tx_dq.base %08X\n", (uint32_t)priv->tx_dq.base); + printf(" tx_dq.current %08X\n", (uint32_t)priv->tx_dq.current); + printf(" tx_dq.end %08X\n", (uint32_t)priv->tx_dq.end); + printf(" tx_sq.base %08X\n", (uint32_t)priv->tx_sq.base); + printf(" tx_sq.current %08X\n", (uint32_t)priv->tx_sq.current); + printf(" tx_sq.end %08X\n", (uint32_t)priv->tx_sq.end); +} + +/** + * Dump all RX status queue entries to the terminal. + */ +inline void dump_rx_status_queue(struct eth_device *dev) +{ + struct ep93xx_priv *priv = GET_PRIV(dev); + int i; + + printf("\ndump_rx_status_queue()\n"); + printf(" descriptor address word1 word2\n"); + for (i = 0; i < NUMRXDESC; i++) { + printf(" [ %08X ] %08X %08X\n", + (uint32_t)(priv->rx_sq.base + i), + (uint32_t)(priv->rx_sq.base + i)->word1, + (uint32_t)(priv->rx_sq.base + i)->word2); + } +} + +/** + * Dump all RX descriptor queue entries to the terminal. + */ +inline void dump_rx_descriptor_queue(struct eth_device *dev) +{ + struct ep93xx_priv *priv = GET_PRIV(dev); + int i; + + printf("\ndump_rx_descriptor_queue()\n"); + printf(" descriptor address word1 word2\n"); + for (i = 0; i < NUMRXDESC; i++) { + printf(" [ %08X ] %08X %08X\n", + (uint32_t)(priv->rx_dq.base + i), + (uint32_t)(priv->rx_dq.base + i)->word1, + (uint32_t)(priv->rx_dq.base + i)->word2); + } +} + +/** + * Dump all TX descriptor queue entries to the terminal. + */ +inline void dump_tx_descriptor_queue(struct eth_device *dev) +{ + struct ep93xx_priv *priv = GET_PRIV(dev); + int i; + + printf("\ndump_tx_descriptor_queue()\n"); + printf(" descriptor address word1 word2\n"); + for (i = 0; i < NUMTXDESC; i++) { + printf(" [ %08X ] %08X %08X\n", + (uint32_t)(priv->tx_dq.base + i), + (uint32_t)(priv->tx_dq.base + i)->word1, + (uint32_t)(priv->tx_dq.base + i)->word2); + } +} + +/** + * Dump all TX status queue entries to the terminal. + */ +inline void dump_tx_status_queue(struct eth_device *dev) +{ + struct ep93xx_priv *priv = GET_PRIV(dev); + int i; + + printf("\ndump_tx_status_queue()\n"); + printf(" descriptor address word1\n"); + for (i = 0; i < NUMTXDESC; i++) { + printf(" [ %08X ] %08X\n", + (uint32_t)(priv->rx_sq.base + i), + (uint32_t)(priv->rx_sq.base + i)->word1); + } +} +#else +#define dump_dev(x) +#define dump_rx_descriptor_queue(x) +#define dump_rx_status_queue(x) +#define dump_tx_descriptor_queue(x) +#define dump_tx_status_queue(x) +#endif /* defined(EP93XX_MAC_DEBUG) */ + +/** + * Reset the EP93xx MAC by twiddling the soft reset bit and spinning until + * it's cleared. + */ +static void ep93xx_mac_reset(struct eth_device *dev) +{ + struct mac_regs *mac = GET_REGS(dev); + uint32_t value; + + debug("+ep93xx_mac_reset"); + + value = readl(&mac->selfctl); + value |= SELFCTL_RESET; + writel(value, &mac->selfctl); + + while (readl(&mac->selfctl) & SELFCTL_RESET) + ; /* noop */ + + debug("-ep93xx_mac_reset"); +} + +/* Eth device open */ +static int ep93xx_eth_open(struct eth_device *dev, bd_t *bd) +{ + struct ep93xx_priv *priv = GET_PRIV(dev); + struct mac_regs *mac = GET_REGS(dev); + uchar *mac_addr = dev->enetaddr; + int i; + + debug("+ep93xx_eth_open"); + + /* Reset the MAC */ + ep93xx_mac_reset(dev); + + /* Reset the descriptor queues' current and end address values */ + priv->tx_dq.current = priv->tx_dq.base; + priv->tx_dq.end = (priv->tx_dq.base + NUMTXDESC); + + priv->tx_sq.current = priv->tx_sq.base; + priv->tx_sq.end = (priv->tx_sq.base + NUMTXDESC); + + priv->rx_dq.current = priv->rx_dq.base; + priv->rx_dq.end = (priv->rx_dq.base + NUMRXDESC); + + priv->rx_sq.current = priv->rx_sq.base; + priv->rx_sq.end = (priv->rx_sq.base + NUMRXDESC); + + /* + * Set the transmit descriptor and status queues' base address, + * current address, and length registers. Set the maximum frame + * length and threshold. Enable the transmit descriptor processor. + */ + writel((uint32_t)priv->tx_dq.base, &mac->txdq.badd); + writel((uint32_t)priv->tx_dq.base, &mac->txdq.curadd); + writel(sizeof(struct tx_descriptor) * NUMTXDESC, &mac->txdq.blen); + + writel((uint32_t)priv->tx_sq.base, &mac->txstsq.badd); + writel((uint32_t)priv->tx_sq.base, &mac->txstsq.curadd); + writel(sizeof(struct tx_status) * NUMTXDESC, &mac->txstsq.blen); + + writel(0x00040000, &mac->txdthrshld); + writel(0x00040000, &mac->txststhrshld); + + writel((TXSTARTMAX << 0) | (PKTSIZE_ALIGN << 16), &mac->maxfrmlen); + writel(BMCTL_TXEN, &mac->bmctl); + + /* + * Set the receive descriptor and status queues' base address, + * current address, and length registers. Enable the receive + * descriptor processor. + */ + writel((uint32_t)priv->rx_dq.base, &mac->rxdq.badd); + writel((uint32_t)priv->rx_dq.base, &mac->rxdq.curadd); + writel(sizeof(struct rx_descriptor) * NUMRXDESC, &mac->rxdq.blen); + + writel((uint32_t)priv->rx_sq.base, &mac->rxstsq.badd); + writel((uint32_t)priv->rx_sq.base, &mac->rxstsq.curadd); + writel(sizeof(struct rx_status) * NUMRXDESC, &mac->rxstsq.blen); + + writel(0x00040000, &mac->rxdthrshld); + + writel(BMCTL_RXEN, &mac->bmctl); + + writel(0x00040000, &mac->rxststhrshld); + + /* Wait until the receive descriptor processor is active */ + while (!(readl(&mac->bmsts) & BMSTS_RXACT)) + ; /* noop */ + + /* + * Initialize the RX descriptor queue. Clear the TX descriptor queue. + * Clear the RX and TX status queues. Enqueue the RX descriptor and + * status entries to the MAC. + */ + for (i = 0; i < NUMRXDESC; i++) { + /* set buffer address */ + (priv->rx_dq.base + i)->word1 = (uint32_t)NetRxPackets[i]; + + /* set buffer length, clear buffer index and NSOF */ + (priv->rx_dq.base + i)->word2 = PKTSIZE_ALIGN; + } + + memset(priv->tx_dq.base, 0, + (sizeof(struct tx_descriptor) * NUMTXDESC)); + memset(priv->rx_sq.base, 0, + (sizeof(struct rx_status) * NUMRXDESC)); + memset(priv->tx_sq.base, 0, + (sizeof(struct tx_status) * NUMTXDESC)); + + writel(NUMRXDESC, &mac->rxdqenq); + writel(NUMRXDESC, &mac->rxstsqenq); + + /* Set the primary MAC address */ + writel(AFP_IAPRIMARY, &mac->afp); + writel(mac_addr[0] | (mac_addr[1] << 8) | + (mac_addr[2] << 16) | (mac_addr[3] << 24), + &mac->indad); + writel(mac_addr[4] | (mac_addr[5] << 8), &mac->indad_upper); + + /* Turn on RX and TX */ + writel(RXCTL_IA0 | RXCTL_BA | RXCTL_SRXON | + RXCTL_RCRCA | RXCTL_MA, &mac->rxctl); + writel(TXCTL_STXON, &mac->txctl); + + /* Dump data structures if we're debugging */ + dump_dev(dev); + dump_rx_descriptor_queue(dev); + dump_rx_status_queue(dev); + dump_tx_descriptor_queue(dev); + dump_tx_status_queue(dev); + + debug("-ep93xx_eth_open"); + + return 1; +} + +/** + * Halt EP93xx MAC transmit and receive by clearing the TxCTL and RxCTL + * registers. + */ +static void ep93xx_eth_close(struct eth_device *dev) +{ + struct mac_regs *mac = GET_REGS(dev); + + debug("+ep93xx_eth_close"); + + writel(0x00000000, &mac->rxctl); + writel(0x00000000, &mac->txctl); + + debug("-ep93xx_eth_close"); +} + +/** + * Copy a frame of data from the MAC into the protocol layer for further + * processing. + */ +static int ep93xx_eth_rcv_packet(struct eth_device *dev) +{ + struct mac_regs *mac = GET_REGS(dev); + struct ep93xx_priv *priv = GET_PRIV(dev); + int len = -1; + + debug("+ep93xx_eth_rcv_packet"); + + if (RX_STATUS_RFP(priv->rx_sq.current)) { + if (RX_STATUS_RWE(priv->rx_sq.current)) { + /* + * We have a good frame. Extract the frame's length + * from the current rx_status_queue entry, and copy + * the frame's data into NetRxPackets[] of the + * protocol stack. We track the total number of + * bytes in the frame (nbytes_frame) which will be + * used when we pass the data off to the protocol + * layer via NetReceive(). + */ + len = RX_STATUS_FRAME_LEN(priv->rx_sq.current); + + NetReceive((uchar *)priv->rx_dq.current->word1, len); + + debug("reporting %d bytes...\n", len); + } else { + /* Do we have an erroneous packet? */ + error("packet rx error, status %08X %08X", + priv->rx_sq.current->word1, + priv->rx_sq.current->word2); + dump_rx_descriptor_queue(dev); + dump_rx_status_queue(dev); + } + + /* + * Clear the associated status queue entry, and + * increment our current pointers to the next RX + * descriptor and status queue entries (making sure + * we wrap properly). + */ + memset((void *)priv->rx_sq.current, 0, + sizeof(struct rx_status)); + + priv->rx_sq.current++; + if (priv->rx_sq.current >= priv->rx_sq.end) + priv->rx_sq.current = priv->rx_sq.base; + + priv->rx_dq.current++; + if (priv->rx_dq.current >= priv->rx_dq.end) + priv->rx_dq.current = priv->rx_dq.base; + + /* + * Finally, return the RX descriptor and status entries + * back to the MAC engine, and loop again, checking for + * more descriptors to process. + */ + writel(1, &mac->rxdqenq); + writel(1, &mac->rxstsqenq); + } else { + len = 0; + } + + debug("-ep93xx_eth_rcv_packet %d", len); + return len; +} + +/** + * Send a block of data via ethernet. + */ +static int ep93xx_eth_send_packet(struct eth_device *dev, + volatile void * const packet, int const length) +{ + struct mac_regs *mac = GET_REGS(dev); + struct ep93xx_priv *priv = GET_PRIV(dev); + int ret = -1; + + debug("+ep93xx_eth_send_packet"); + + /* Parameter check */ + BUG_ON(packet == NULL); + + /* + * Initialize the TX descriptor queue with the new packet's info. + * Clear the associated status queue entry. Enqueue the packet + * to the MAC for transmission. + */ + + /* set buffer address */ + priv->tx_dq.current->word1 = (uint32_t)packet; + + /* set buffer length and EOF bit */ + priv->tx_dq.current->word2 = length | TX_DESC_EOF; + + /* clear tx status */ + priv->tx_sq.current->word1 = 0; + + /* enqueue the TX descriptor */ + writel(1, &mac->txdqenq); + + /* wait for the frame to become processed */ + while (!TX_STATUS_TXFP(priv->tx_sq.current)) + ; /* noop */ + + if (!TX_STATUS_TXWE(priv->tx_sq.current)) { + error("packet tx error, status %08X", + priv->tx_sq.current->word1); + dump_tx_descriptor_queue(dev); + dump_tx_status_queue(dev); + + /* TODO: Add better error handling? */ + goto eth_send_failed_0; + } + + ret = 0; + /* Fall through */ + +eth_send_failed_0: + debug("-ep93xx_eth_send_packet %d", ret); + return ret; +} + +#if defined(CONFIG_MII) +int ep93xx_miiphy_initialize(bd_t * const bd) +{ + miiphy_register("ep93xx_eth0", ep93xx_miiphy_read, ep93xx_miiphy_write); + return 0; +} +#endif + +/** + * Initialize the EP93xx MAC. The MAC hardware is reset. Buffers are + * allocated, if necessary, for the TX and RX descriptor and status queues, + * as well as for received packets. The EP93XX MAC hardware is initialized. + * Transmit and receive operations are enabled. + */ +int ep93xx_eth_initialize(u8 dev_num, int base_addr) +{ + int ret = -1; + struct eth_device *dev; + struct ep93xx_priv *priv; + + debug("+ep93xx_eth_initialize"); + + priv = malloc(sizeof(*priv)); + if (!priv) { + error("malloc() failed"); + goto eth_init_failed_0; + } + memset(priv, 0, sizeof(*priv)); + + priv->regs = (struct mac_regs *)base_addr; + + priv->tx_dq.base = calloc(NUMTXDESC, + sizeof(struct tx_descriptor)); + if (priv->tx_dq.base == NULL) { + error("calloc() failed"); + goto eth_init_failed_1; + } + + priv->tx_sq.base = calloc(NUMTXDESC, + sizeof(struct tx_status)); + if (priv->tx_sq.base == NULL) { + error("calloc() failed"); + goto eth_init_failed_2; + } + + priv->rx_dq.base = calloc(NUMRXDESC, + sizeof(struct rx_descriptor)); + if (priv->rx_dq.base == NULL) { + error("calloc() failed"); + goto eth_init_failed_3; + } + + priv->rx_sq.base = calloc(NUMRXDESC, + sizeof(struct rx_status)); + if (priv->rx_sq.base == NULL) { + error("calloc() failed"); + goto eth_init_failed_4; + } + + dev = malloc(sizeof *dev); + if (dev == NULL) { + error("malloc() failed"); + goto eth_init_failed_5; + } + memset(dev, 0, sizeof *dev); + + dev->iobase = base_addr; + dev->priv = priv; + dev->init = ep93xx_eth_open; + dev->halt = ep93xx_eth_close; + dev->send = ep93xx_eth_send_packet; + dev->recv = ep93xx_eth_rcv_packet; + + sprintf(dev->name, "ep93xx_eth-%hu", dev_num); + + eth_register(dev); + + /* Done! */ + ret = 0; + goto eth_init_done; + +eth_init_failed_5: + free(priv->rx_sq.base); + /* Fall through */ + +eth_init_failed_4: + free(priv->rx_dq.base); + /* Fall through */ + +eth_init_failed_3: + free(priv->tx_sq.base); + /* Fall through */ + +eth_init_failed_2: + free(priv->tx_dq.base); + /* Fall through */ + +eth_init_failed_1: + free(priv); + /* Fall through */ + +eth_init_failed_0: + /* Fall through */ + +eth_init_done: + debug("-ep93xx_eth_initialize %d", ret); + return ret; +} + +#if defined(CONFIG_MII) + +/** + * Maximum MII address we support + */ +#define MII_ADDRESS_MAX 31 + +/** + * Maximum MII register address we support + */ +#define MII_REGISTER_MAX 31 + +/** + * Read a 16-bit value from an MII register. + */ +static int ep93xx_miiphy_read(char * const dev, unsigned char const addr, + unsigned char const reg, unsigned short * const value) +{ + struct mac_regs *mac = (struct mac_regs *)MAC_BASE; + int ret = -1; + uint32_t self_ctl; + + debug("+ep93xx_miiphy_read"); + + /* Parameter checks */ + BUG_ON(dev == NULL); + BUG_ON(addr > MII_ADDRESS_MAX); + BUG_ON(reg > MII_REGISTER_MAX); + BUG_ON(value == NULL); + + /* + * Save the current SelfCTL register value. Set MAC to suppress + * preamble bits. Wait for any previous MII command to complete + * before issuing the new command. + */ + self_ctl = readl(&mac->selfctl); +#if defined(CONFIG_MII_SUPPRESS_PREAMBLE) + writel(self_ctl & ~(1 << 8), &mac->selfctl); +#endif /* defined(CONFIG_MII_SUPPRESS_PREAMBLE) */ + + while (readl(&mac->miists) & MIISTS_BUSY) + ; /* noop */ + + /* + * Issue the MII 'read' command. Wait for the command to complete. + * Read the MII data value. + */ + writel(MIICMD_OPCODE_READ | ((uint32_t)addr << 5) | (uint32_t)reg, + &mac->miicmd); + while (readl(&mac->miists) & MIISTS_BUSY) + ; /* noop */ + + *value = (unsigned short)readl(&mac->miidata); + + /* Restore the saved SelfCTL value and return. */ + writel(self_ctl, &mac->selfctl); + + ret = 0; + /* Fall through */ + + debug("-ep93xx_miiphy_read"); + return ret; +} + +/** + * Write a 16-bit value to an MII register. + */ +static int ep93xx_miiphy_write(char * const dev, unsigned char const addr, + unsigned char const reg, unsigned short const value) +{ + struct mac_regs *mac = (struct mac_regs *)MAC_BASE; + int ret = -1; + uint32_t self_ctl; + + debug("+ep93xx_miiphy_write"); + + /* Parameter checks */ + BUG_ON(dev == NULL); + BUG_ON(addr > MII_ADDRESS_MAX); + BUG_ON(reg > MII_REGISTER_MAX); + + /* + * Save the current SelfCTL register value. Set MAC to suppress + * preamble bits. Wait for any previous MII command to complete + * before issuing the new command. + */ + self_ctl = readl(&mac->selfctl); +#if defined(CONFIG_MII_SUPPRESS_PREAMBLE) + writel(self_ctl & ~(1 << 8), &mac->selfctl); +#endif /* defined(CONFIG_MII_SUPPRESS_PREAMBLE) */ + + while (readl(&mac->miists) & MIISTS_BUSY) + ; /* noop */ + + /* Issue the MII 'write' command. Wait for the command to complete. */ + writel((uint32_t)value, &mac->miidata); + writel(MIICMD_OPCODE_WRITE | ((uint32_t)addr << 5) | (uint32_t)reg, + &mac->miicmd); + while (readl(&mac->miists) & MIISTS_BUSY) + ; /* noop */ + + /* Restore the saved SelfCTL value and return. */ + writel(self_ctl, &mac->selfctl); + + ret = 0; + /* Fall through */ + + debug("-ep93xx_miiphy_write"); + return ret; +} +#endif /* defined(CONFIG_MII) */ diff --git a/drivers/net/ep93xx_eth.h b/drivers/net/ep93xx_eth.h new file mode 100644 index 0000000..5f7bf13 --- /dev/null +++ b/drivers/net/ep93xx_eth.h @@ -0,0 +1,144 @@ +/* + * Copyright (C) 2009 Matthias Kaehlcke matthias@kaehlcke.net + * + * Copyright (C) 2004, 2005 + * Cory T. Tusar, Videon Central, Inc., ctusar@videon-central.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef _ETH_H +#define _ETH_H + +#include <net.h> + +/** + * #define this to dump device status and queue info during initialization and + * following errors. + */ +#undef EP93XX_MAC_DEBUG + +/** + * Number of descriptor and status entries in our RX queues. + * It must be power of 2 ! + */ +#define NUMRXDESC PKTBUFSRX + +/** + * Number of descriptor and status entries in our TX queues. + */ +#define NUMTXDESC 1 + +/** + * 944 = (1024 - 64) - 16, Fifo size - Minframesize - 16 (Chip FACT) + */ +#define TXSTARTMAX 944 + +/** + * Receive descriptor queue entry + */ +struct rx_descriptor { + uint32_t word1; + uint32_t word2; +}; + +/** + * Receive status queue entry + */ +struct rx_status { + uint32_t word1; + uint32_t word2; +}; + +#define RX_STATUS_RWE(rx_status) ((rx_status->word1 >> 30) & 0x01) +#define RX_STATUS_RFP(rx_status) ((rx_status->word1 >> 31) & 0x01) +#define RX_STATUS_FRAME_LEN(rx_status) (rx_status->word2 & 0xFFFF) + +/** + * Transmit descriptor queue entry + */ +struct tx_descriptor { + uint32_t word1; + uint32_t word2; +}; + +#define TX_DESC_EOF (1 << 31) + +/** + * Transmit status queue entry + */ +struct tx_status { + uint32_t word1; +}; + +#define TX_STATUS_TXWE(tx_status) (((tx_status)->word1 >> 30) & 0x01) +#define TX_STATUS_TXFP(tx_status) (((tx_status)->word1 >> 31) & 0x01) + +/** + * Transmit descriptor queue + */ +struct tx_descriptor_queue { + struct tx_descriptor *base; + struct tx_descriptor *current; + struct tx_descriptor *end; +}; + +/** + * Transmit status queue + */ +struct tx_status_queue { + struct tx_status *base; + volatile struct tx_status *current; + struct tx_status *end; +}; + +/** + * Receive descriptor queue + */ +struct rx_descriptor_queue { + struct rx_descriptor *base; + struct rx_descriptor *current; + struct rx_descriptor *end; +}; + +/** + * Receive status queue + */ +struct rx_status_queue { + struct rx_status *base; + volatile struct rx_status *current; + struct rx_status *end; +}; + +/** + * EP93xx MAC private data structure + */ +struct ep93xx_priv { + struct rx_descriptor_queue rx_dq; + struct rx_status_queue rx_sq; + void *rx_buffer[NUMRXDESC]; + + struct tx_descriptor_queue tx_dq; + struct tx_status_queue tx_sq; + + struct mac_regs *regs; +}; + +#endif diff --git a/include/common.h b/include/common.h index f2a7067..c0dfc45 100644 --- a/include/common.h +++ b/include/common.h @@ -123,6 +123,11 @@ typedef volatile unsigned char vu_char; #define debugX(level,fmt,args...) #endif /* DEBUG */
+#define error(fmt, args...) do { \ + printf("ERROR: " fmt "\nat %s:%d/%s()\n", \ + ##args, __FILE__, __LINE__, __func__); \ +} while (0) + #ifndef BUG #define BUG() do { \ printf("BUG: failure at %s:%d/%s()!\n", __FILE__, __LINE__, __FUNCTION__); \ diff --git a/include/netdev.h b/include/netdev.h index a9d5ec9..1e0484f 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -49,6 +49,7 @@ int davinci_emac_initialize(void); int dnet_eth_initialize(int id, void *regs, unsigned int phy_addr); int e1000_initialize(bd_t *bis); int eepro100_initialize(bd_t *bis); +int ep93xx_eth_initialize(u8 dev_num, int base_addr); int eth_3com_initialize (bd_t * bis); int fec_initialize (bd_t *bis); int fecmxc_initialize (bd_t *bis);
Hi Matthias,
On Sun, Jan 24, 2010 at 8:56 AM, Matthias Kaehlcke matthias@kaehlcke.netwrote:
Added ethernet driver for EP93xx SoCs
Signed-off-by: Matthias Kaehlcke matthias@kaehlcke.net
drivers/net/Makefile | 1 + drivers/net/ep93xx_eth.c | 654 ++++++++++++++++++++++++++++++++++++++++++++++ drivers/net/ep93xx_eth.h | 144 ++++++++++ include/common.h | 5 + include/netdev.h | 1 + 5 files changed, 805 insertions(+), 0 deletions(-) create mode 100644 drivers/net/ep93xx_eth.c create mode 100644 drivers/net/ep93xx_eth.h
diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 904727e..dc3107c 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -37,6 +37,7 @@ COBJS-$(CONFIG_DNET) += dnet.o COBJS-$(CONFIG_E1000) += e1000.o COBJS-$(CONFIG_EEPRO100) += eepro100.o COBJS-$(CONFIG_ENC28J60) += enc28j60.o +COBJS-$(CONFIG_EP93XX) += ep93xx_eth.o COBJS-$(CONFIG_FEC_MXC) += fec_mxc.o COBJS-$(CONFIG_FSLDMAFEC) += fsl_mcdmafec.o mcfmii.o COBJS-$(CONFIG_FTMAC100) += ftmac100.o diff --git a/drivers/net/ep93xx_eth.c b/drivers/net/ep93xx_eth.c new file mode 100644 index 0000000..33d14df --- /dev/null +++ b/drivers/net/ep93xx_eth.c @@ -0,0 +1,654 @@ +/*
- Cirrus Logic EP93xx ethernet MAC / MII driver.
- Copyright (C) 2010, 2009
- Matthias Kaehlcke matthias@kaehlcke.net
- Copyright (C) 2004, 2005
- Cory T. Tusar, Videon Central, Inc., ctusar@videon-central.com
- Based on the original eth.[ch] Cirrus Logic EP93xx Rev D. Ethernet
Driver,
- which is
- (C) Copyright 2002 2003
- Adam Bezanson, Network Audio Technologies, Inc.
- See file CREDITS for list of people who contributed to this project.
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
- This program is distributed in the hope that it will be useful, but
- WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY
- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
- for more details.
- You should have received a copy of the GNU General Public License along
- with this program; if not, write to the Free Software Foundation, Inc.,
- 675 Mass Ave, Cambridge, MA 02139, USA.
- */
+#include <command.h> +#include <common.h> +#include <asm/arch/ep93xx.h> +#include <asm/io.h> +#include <malloc.h> +#include <miiphy.h> +#include <linux/types.h> +#include "ep93xx_eth.h"
+#define GET_PRIV(eth_dev) ((struct ep93xx_priv *)eth_dev->priv)
You should probably have parens around "eth_dev", although problems would be found at compile time.
+#define GET_REGS(eth_dev) (GET_PRIV(eth_dev)->regs)
+/* ep93xx_miiphy ops forward declarations */ +static int ep93xx_miiphy_read(char * const dev, unsigned char const addr,
unsigned char const reg, unsigned short * constvalue); +static int ep93xx_miiphy_write(char * const dev, unsigned char const addr,
unsigned char const reg, unsigned short constvalue);
+#if defined(EP93XX_MAC_DEBUG) +/**
- Dump ep93xx_mac values to the terminal.
- */
+inline void dump_dev(struct eth_device *dev)
All of these local functions should be static. inline is probably pointless, especially since they're only compiled in when you're debugging.
+{
struct ep93xx_priv *priv = GET_PRIV(dev);int i;printf("\ndump_dev()\n");printf(" rx_dq.base %08X\n", (uint32_t)priv->rx_dq.base);
If these are pointers, why not use %p instead of all this casting?
printf(" rx_dq.current %08X\n",(uint32_t)priv->rx_dq.current);
printf(" rx_dq.end %08X\n", (uint32_t)priv->rx_dq.end);printf(" rx_sq.base %08X\n", (uint32_t)priv->rx_sq.base);printf(" rx_sq.current %08X\n",(uint32_t)priv->rx_sq.current);
printf(" rx_sq.end %08X\n", (uint32_t)priv->rx_sq.end);for (i = 0; i < NUMRXDESC; i++)printf(" rx_buffer[%2.d] %08X\n", i,(uint32_t)NetRxPackets[i]);printf(" tx_dq.base %08X\n", (uint32_t)priv->tx_dq.base);printf(" tx_dq.current %08X\n",(uint32_t)priv->tx_dq.current);
printf(" tx_dq.end %08X\n", (uint32_t)priv->tx_dq.end);printf(" tx_sq.base %08X\n", (uint32_t)priv->tx_sq.base);printf(" tx_sq.current %08X\n",(uint32_t)priv->tx_sq.current);
printf(" tx_sq.end %08X\n", (uint32_t)priv->tx_sq.end);+}
+/**
- Dump all RX status queue entries to the terminal.
- */
+inline void dump_rx_status_queue(struct eth_device *dev) +{
struct ep93xx_priv *priv = GET_PRIV(dev);int i;printf("\ndump_rx_status_queue()\n");printf(" descriptor address word1 word2\n");for (i = 0; i < NUMRXDESC; i++) {printf(" [ %08X ] %08X %08X\n",(uint32_t)(priv->rx_sq.base + i),(uint32_t)(priv->rx_sq.base + i)->word1,(uint32_t)(priv->rx_sq.base + i)->word2);
word1 and word2 are defined as uint32_t, so no cast required.
}+}
+/**
- Dump all RX descriptor queue entries to the terminal.
- */
+inline void dump_rx_descriptor_queue(struct eth_device *dev) +{
struct ep93xx_priv *priv = GET_PRIV(dev);int i;printf("\ndump_rx_descriptor_queue()\n");printf(" descriptor address word1 word2\n");for (i = 0; i < NUMRXDESC; i++) {printf(" [ %08X ] %08X %08X\n",(uint32_t)(priv->rx_dq.base + i),(uint32_t)(priv->rx_dq.base + i)->word1,(uint32_t)(priv->rx_dq.base + i)->word2);}+}
+/**
- Dump all TX descriptor queue entries to the terminal.
- */
+inline void dump_tx_descriptor_queue(struct eth_device *dev) +{
struct ep93xx_priv *priv = GET_PRIV(dev);int i;printf("\ndump_tx_descriptor_queue()\n");printf(" descriptor address word1 word2\n");for (i = 0; i < NUMTXDESC; i++) {printf(" [ %08X ] %08X %08X\n",(uint32_t)(priv->tx_dq.base + i),(uint32_t)(priv->tx_dq.base + i)->word1,(uint32_t)(priv->tx_dq.base + i)->word2);}+}
+/**
- Dump all TX status queue entries to the terminal.
- */
+inline void dump_tx_status_queue(struct eth_device *dev) +{
struct ep93xx_priv *priv = GET_PRIV(dev);int i;printf("\ndump_tx_status_queue()\n");printf(" descriptor address word1\n");for (i = 0; i < NUMTXDESC; i++) {printf(" [ %08X ] %08X\n",(uint32_t)(priv->rx_sq.base + i),(uint32_t)(priv->rx_sq.base + i)->word1);}+} +#else +#define dump_dev(x) +#define dump_rx_descriptor_queue(x) +#define dump_rx_status_queue(x) +#define dump_tx_descriptor_queue(x) +#define dump_tx_status_queue(x) +#endif /* defined(EP93XX_MAC_DEBUG) */
+/**
- Reset the EP93xx MAC by twiddling the soft reset bit and spinning until
- it's cleared.
- */
+static void ep93xx_mac_reset(struct eth_device *dev) +{
struct mac_regs *mac = GET_REGS(dev);uint32_t value;debug("+ep93xx_mac_reset");value = readl(&mac->selfctl);value |= SELFCTL_RESET;writel(value, &mac->selfctl);while (readl(&mac->selfctl) & SELFCTL_RESET); /* noop */debug("-ep93xx_mac_reset");+}
+/* Eth device open */ +static int ep93xx_eth_open(struct eth_device *dev, bd_t *bd) +{
struct ep93xx_priv *priv = GET_PRIV(dev);struct mac_regs *mac = GET_REGS(dev);uchar *mac_addr = dev->enetaddr;int i;debug("+ep93xx_eth_open");/* Reset the MAC */ep93xx_mac_reset(dev);/* Reset the descriptor queues' current and end address values */priv->tx_dq.current = priv->tx_dq.base;priv->tx_dq.end = (priv->tx_dq.base + NUMTXDESC);priv->tx_sq.current = priv->tx_sq.base;priv->tx_sq.end = (priv->tx_sq.base + NUMTXDESC);priv->rx_dq.current = priv->rx_dq.base;priv->rx_dq.end = (priv->rx_dq.base + NUMRXDESC);priv->rx_sq.current = priv->rx_sq.base;priv->rx_sq.end = (priv->rx_sq.base + NUMRXDESC);/** Set the transmit descriptor and status queues' base address,* current address, and length registers. Set the maximum frame* length and threshold. Enable the transmit descriptor processor.*/writel((uint32_t)priv->tx_dq.base, &mac->txdq.badd);writel((uint32_t)priv->tx_dq.base, &mac->txdq.curadd);writel(sizeof(struct tx_descriptor) * NUMTXDESC, &mac->txdq.blen);writel((uint32_t)priv->tx_sq.base, &mac->txstsq.badd);writel((uint32_t)priv->tx_sq.base, &mac->txstsq.curadd);writel(sizeof(struct tx_status) * NUMTXDESC, &mac->txstsq.blen);writel(0x00040000, &mac->txdthrshld);writel(0x00040000, &mac->txststhrshld);writel((TXSTARTMAX << 0) | (PKTSIZE_ALIGN << 16), &mac->maxfrmlen);writel(BMCTL_TXEN, &mac->bmctl);/** Set the receive descriptor and status queues' base address,* current address, and length registers. Enable the receive* descriptor processor.*/writel((uint32_t)priv->rx_dq.base, &mac->rxdq.badd);writel((uint32_t)priv->rx_dq.base, &mac->rxdq.curadd);writel(sizeof(struct rx_descriptor) * NUMRXDESC, &mac->rxdq.blen);writel((uint32_t)priv->rx_sq.base, &mac->rxstsq.badd);writel((uint32_t)priv->rx_sq.base, &mac->rxstsq.curadd);writel(sizeof(struct rx_status) * NUMRXDESC, &mac->rxstsq.blen);writel(0x00040000, &mac->rxdthrshld);writel(BMCTL_RXEN, &mac->bmctl);writel(0x00040000, &mac->rxststhrshld);/* Wait until the receive descriptor processor is active */while (!(readl(&mac->bmsts) & BMSTS_RXACT)); /* noop *//** Initialize the RX descriptor queue. Clear the TX descriptorqueue.
* Clear the RX and TX status queues. Enqueue the RX descriptor and* status entries to the MAC.*/for (i = 0; i < NUMRXDESC; i++) {/* set buffer address */(priv->rx_dq.base + i)->word1 = (uint32_t)NetRxPackets[i];/* set buffer length, clear buffer index and NSOF */(priv->rx_dq.base + i)->word2 = PKTSIZE_ALIGN;}memset(priv->tx_dq.base, 0,(sizeof(struct tx_descriptor) * NUMTXDESC));memset(priv->rx_sq.base, 0,(sizeof(struct rx_status) * NUMRXDESC));memset(priv->tx_sq.base, 0,(sizeof(struct tx_status) * NUMTXDESC));writel(NUMRXDESC, &mac->rxdqenq);writel(NUMRXDESC, &mac->rxstsqenq);/* Set the primary MAC address */writel(AFP_IAPRIMARY, &mac->afp);writel(mac_addr[0] | (mac_addr[1] << 8) |(mac_addr[2] << 16) | (mac_addr[3] << 24),&mac->indad);writel(mac_addr[4] | (mac_addr[5] << 8), &mac->indad_upper);/* Turn on RX and TX */writel(RXCTL_IA0 | RXCTL_BA | RXCTL_SRXON |RXCTL_RCRCA | RXCTL_MA, &mac->rxctl);writel(TXCTL_STXON, &mac->txctl);/* Dump data structures if we're debugging */dump_dev(dev);dump_rx_descriptor_queue(dev);dump_rx_status_queue(dev);dump_tx_descriptor_queue(dev);dump_tx_status_queue(dev);debug("-ep93xx_eth_open");return 1;+}
+/**
- Halt EP93xx MAC transmit and receive by clearing the TxCTL and RxCTL
- registers.
- */
+static void ep93xx_eth_close(struct eth_device *dev) +{
struct mac_regs *mac = GET_REGS(dev);debug("+ep93xx_eth_close");writel(0x00000000, &mac->rxctl);writel(0x00000000, &mac->txctl);debug("-ep93xx_eth_close");+}
+/**
- Copy a frame of data from the MAC into the protocol layer for further
- processing.
- */
+static int ep93xx_eth_rcv_packet(struct eth_device *dev) +{
struct mac_regs *mac = GET_REGS(dev);struct ep93xx_priv *priv = GET_PRIV(dev);int len = -1;debug("+ep93xx_eth_rcv_packet");if (RX_STATUS_RFP(priv->rx_sq.current)) {if (RX_STATUS_RWE(priv->rx_sq.current)) {/** We have a good frame. Extract the frame's length* from the current rx_status_queue entry, and copy* the frame's data into NetRxPackets[] of the* protocol stack. We track the total number of* bytes in the frame (nbytes_frame) which will be* used when we pass the data off to the protocol* layer via NetReceive().*/len = RX_STATUS_FRAME_LEN(priv->rx_sq.current);NetReceive((uchar *)priv->rx_dq.current->word1,len);
debug("reporting %d bytes...\n", len);} else {/* Do we have an erroneous packet? */error("packet rx error, status %08X %08X",priv->rx_sq.current->word1,priv->rx_sq.current->word2);dump_rx_descriptor_queue(dev);dump_rx_status_queue(dev);}/** Clear the associated status queue entry, and* increment our current pointers to the next RX* descriptor and status queue entries (making sure* we wrap properly).*/memset((void *)priv->rx_sq.current, 0,sizeof(struct rx_status));priv->rx_sq.current++;if (priv->rx_sq.current >= priv->rx_sq.end)priv->rx_sq.current = priv->rx_sq.base;priv->rx_dq.current++;if (priv->rx_dq.current >= priv->rx_dq.end)priv->rx_dq.current = priv->rx_dq.base;/** Finally, return the RX descriptor and status entries* back to the MAC engine, and loop again, checking for* more descriptors to process.*/writel(1, &mac->rxdqenq);writel(1, &mac->rxstsqenq);} else {len = 0;}debug("-ep93xx_eth_rcv_packet %d", len);return len;+}
+/**
- Send a block of data via ethernet.
- */
+static int ep93xx_eth_send_packet(struct eth_device *dev,
volatile void * const packet, int constlength) +{
struct mac_regs *mac = GET_REGS(dev);struct ep93xx_priv *priv = GET_PRIV(dev);int ret = -1;debug("+ep93xx_eth_send_packet");/* Parameter check */BUG_ON(packet == NULL);/** Initialize the TX descriptor queue with the new packet's info.* Clear the associated status queue entry. Enqueue the packet* to the MAC for transmission.*//* set buffer address */priv->tx_dq.current->word1 = (uint32_t)packet;/* set buffer length and EOF bit */priv->tx_dq.current->word2 = length | TX_DESC_EOF;/* clear tx status */priv->tx_sq.current->word1 = 0;/* enqueue the TX descriptor */writel(1, &mac->txdqenq);/* wait for the frame to become processed */while (!TX_STATUS_TXFP(priv->tx_sq.current)); /* noop */if (!TX_STATUS_TXWE(priv->tx_sq.current)) {error("packet tx error, status %08X",priv->tx_sq.current->word1);dump_tx_descriptor_queue(dev);dump_tx_status_queue(dev);/* TODO: Add better error handling? */goto eth_send_failed_0;}ret = 0;/* Fall through */+eth_send_failed_0:
Strange label here. This isn't just a fail path.
debug("-ep93xx_eth_send_packet %d", ret);return ret;+}
+#if defined(CONFIG_MII) +int ep93xx_miiphy_initialize(bd_t * const bd) +{
miiphy_register("ep93xx_eth0", ep93xx_miiphy_read,ep93xx_miiphy_write);
return 0;+} +#endif
+/**
- Initialize the EP93xx MAC. The MAC hardware is reset. Buffers are
- allocated, if necessary, for the TX and RX descriptor and status
queues,
- as well as for received packets. The EP93XX MAC hardware is
initialized.
- Transmit and receive operations are enabled.
- */
+int ep93xx_eth_initialize(u8 dev_num, int base_addr) +{
int ret = -1;struct eth_device *dev;struct ep93xx_priv *priv;debug("+ep93xx_eth_initialize");priv = malloc(sizeof(*priv));if (!priv) {error("malloc() failed");goto eth_init_failed_0;}memset(priv, 0, sizeof(*priv));priv->regs = (struct mac_regs *)base_addr;priv->tx_dq.base = calloc(NUMTXDESC,sizeof(struct tx_descriptor));if (priv->tx_dq.base == NULL) {error("calloc() failed");goto eth_init_failed_1;}priv->tx_sq.base = calloc(NUMTXDESC,sizeof(struct tx_status));if (priv->tx_sq.base == NULL) {error("calloc() failed");goto eth_init_failed_2;}priv->rx_dq.base = calloc(NUMRXDESC,sizeof(struct rx_descriptor));if (priv->rx_dq.base == NULL) {error("calloc() failed");goto eth_init_failed_3;}priv->rx_sq.base = calloc(NUMRXDESC,sizeof(struct rx_status));if (priv->rx_sq.base == NULL) {error("calloc() failed");goto eth_init_failed_4;}dev = malloc(sizeof *dev);if (dev == NULL) {error("malloc() failed");goto eth_init_failed_5;}memset(dev, 0, sizeof *dev);dev->iobase = base_addr;dev->priv = priv;dev->init = ep93xx_eth_open;dev->halt = ep93xx_eth_close;dev->send = ep93xx_eth_send_packet;dev->recv = ep93xx_eth_rcv_packet;sprintf(dev->name, "ep93xx_eth-%hu", dev_num);eth_register(dev);/* Done! */ret = 0;
Remember, -1 means critical error, 0 means non-critical error and >0 means # of devices initialized. I expect you want this to be '1'.
goto eth_init_done;+eth_init_failed_5:
free(priv->rx_sq.base);/* Fall through */+eth_init_failed_4:
free(priv->rx_dq.base);/* Fall through */+eth_init_failed_3:
free(priv->tx_sq.base);/* Fall through */+eth_init_failed_2:
free(priv->tx_dq.base);/* Fall through */+eth_init_failed_1:
free(priv);/* Fall through */+eth_init_failed_0:
/* Fall through */+eth_init_done:
debug("-ep93xx_eth_initialize %d", ret);return ret;+}
+#if defined(CONFIG_MII)
+/**
- Maximum MII address we support
- */
+#define MII_ADDRESS_MAX 31
+/**
- Maximum MII register address we support
- */
+#define MII_REGISTER_MAX 31
+/**
- Read a 16-bit value from an MII register.
- */
+static int ep93xx_miiphy_read(char * const dev, unsigned char const addr,
unsigned char const reg, unsigned short * constvalue) +{
struct mac_regs *mac = (struct mac_regs *)MAC_BASE;int ret = -1;uint32_t self_ctl;debug("+ep93xx_miiphy_read");/* Parameter checks */BUG_ON(dev == NULL);BUG_ON(addr > MII_ADDRESS_MAX);BUG_ON(reg > MII_REGISTER_MAX);BUG_ON(value == NULL);/** Save the current SelfCTL register value. Set MAC to suppress* preamble bits. Wait for any previous MII command to complete* before issuing the new command.*/self_ctl = readl(&mac->selfctl);+#if defined(CONFIG_MII_SUPPRESS_PREAMBLE)
writel(self_ctl & ~(1 << 8), &mac->selfctl);+#endif /* defined(CONFIG_MII_SUPPRESS_PREAMBLE) */
while (readl(&mac->miists) & MIISTS_BUSY); /* noop *//** Issue the MII 'read' command. Wait for the command to complete.* Read the MII data value.*/writel(MIICMD_OPCODE_READ | ((uint32_t)addr << 5) | (uint32_t)reg,&mac->miicmd);while (readl(&mac->miists) & MIISTS_BUSY); /* noop */*value = (unsigned short)readl(&mac->miidata);/* Restore the saved SelfCTL value and return. */writel(self_ctl, &mac->selfctl);ret = 0;/* Fall through */debug("-ep93xx_miiphy_read");return ret;+}
+/**
- Write a 16-bit value to an MII register.
- */
+static int ep93xx_miiphy_write(char * const dev, unsigned char const addr,
unsigned char const reg, unsigned short constvalue) +{
struct mac_regs *mac = (struct mac_regs *)MAC_BASE;int ret = -1;uint32_t self_ctl;debug("+ep93xx_miiphy_write");/* Parameter checks */BUG_ON(dev == NULL);BUG_ON(addr > MII_ADDRESS_MAX);BUG_ON(reg > MII_REGISTER_MAX);/** Save the current SelfCTL register value. Set MAC to suppress* preamble bits. Wait for any previous MII command to complete* before issuing the new command.*/self_ctl = readl(&mac->selfctl);+#if defined(CONFIG_MII_SUPPRESS_PREAMBLE)
writel(self_ctl & ~(1 << 8), &mac->selfctl);+#endif /* defined(CONFIG_MII_SUPPRESS_PREAMBLE) */
while (readl(&mac->miists) & MIISTS_BUSY); /* noop *//* Issue the MII 'write' command. Wait for the command tocomplete. */
writel((uint32_t)value, &mac->miidata);writel(MIICMD_OPCODE_WRITE | ((uint32_t)addr << 5) | (uint32_t)reg,&mac->miicmd);while (readl(&mac->miists) & MIISTS_BUSY); /* noop *//* Restore the saved SelfCTL value and return. */writel(self_ctl, &mac->selfctl);ret = 0;/* Fall through */debug("-ep93xx_miiphy_write");return ret;+} +#endif /* defined(CONFIG_MII) */ diff --git a/drivers/net/ep93xx_eth.h b/drivers/net/ep93xx_eth.h new file mode 100644 index 0000000..5f7bf13 --- /dev/null +++ b/drivers/net/ep93xx_eth.h @@ -0,0 +1,144 @@ +/*
- Copyright (C) 2009 Matthias Kaehlcke matthias@kaehlcke.net
- Copyright (C) 2004, 2005
- Cory T. Tusar, Videon Central, Inc., ctusar@videon-central.com
- See file CREDITS for list of people who contributed to this
- project.
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 2 of
- the License, or (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- MA 02111-1307 USA
- */
+#ifndef _ETH_H +#define _ETH_H
This should have a more specific namespace
+#include <net.h>
+/**
- #define this to dump device status and queue info during initialization
and
- following errors.
- */
+#undef EP93XX_MAC_DEBUG
+/**
- Number of descriptor and status entries in our RX queues.
- It must be power of 2 !
- */
+#define NUMRXDESC PKTBUFSRX
+/**
- Number of descriptor and status entries in our TX queues.
- */
+#define NUMTXDESC 1
+/**
- 944 = (1024 - 64) - 16, Fifo size - Minframesize - 16 (Chip FACT)
- */
+#define TXSTARTMAX 944
+/**
- Receive descriptor queue entry
- */
+struct rx_descriptor {
uint32_t word1;uint32_t word2;+};
+/**
- Receive status queue entry
- */
+struct rx_status {
uint32_t word1;uint32_t word2;+};
+#define RX_STATUS_RWE(rx_status) ((rx_status->word1 >> 30) & 0x01) +#define RX_STATUS_RFP(rx_status) ((rx_status->word1 >> 31) & 0x01) +#define RX_STATUS_FRAME_LEN(rx_status) (rx_status->word2 & 0xFFFF)
+/**
- Transmit descriptor queue entry
- */
+struct tx_descriptor {
uint32_t word1;uint32_t word2;+};
+#define TX_DESC_EOF (1 << 31)
+/**
- Transmit status queue entry
- */
+struct tx_status {
uint32_t word1;+};
+#define TX_STATUS_TXWE(tx_status) (((tx_status)->word1 >> 30) & 0x01) +#define TX_STATUS_TXFP(tx_status) (((tx_status)->word1 >> 31) & 0x01)
+/**
- Transmit descriptor queue
- */
+struct tx_descriptor_queue {
struct tx_descriptor *base;struct tx_descriptor *current;struct tx_descriptor *end;+};
+/**
- Transmit status queue
- */
+struct tx_status_queue {
struct tx_status *base;volatile struct tx_status *current;struct tx_status *end;+};
+/**
- Receive descriptor queue
- */
+struct rx_descriptor_queue {
struct rx_descriptor *base;struct rx_descriptor *current;struct rx_descriptor *end;+};
+/**
- Receive status queue
- */
+struct rx_status_queue {
struct rx_status *base;volatile struct rx_status *current;struct rx_status *end;+};
+/**
- EP93xx MAC private data structure
- */
+struct ep93xx_priv {
struct rx_descriptor_queue rx_dq;struct rx_status_queue rx_sq;void *rx_buffer[NUMRXDESC];struct tx_descriptor_queue tx_dq;struct tx_status_queue tx_sq;struct mac_regs *regs;+};
+#endif diff --git a/include/common.h b/include/common.h index f2a7067..c0dfc45 100644 --- a/include/common.h +++ b/include/common.h @@ -123,6 +123,11 @@ typedef volatile unsigned char vu_char; #define debugX(level,fmt,args...) #endif /* DEBUG */
+#define error(fmt, args...) do { \
printf("ERROR: " fmt "\nat %s:%d/%s()\n", \##args, __FILE__, __LINE__, __func__); \+} while (0)
#ifndef BUG #define BUG() do { \ printf("BUG: failure at %s:%d/%s()!\n", __FILE__, __LINE__, __FUNCTION__); \ diff --git a/include/netdev.h b/include/netdev.h index a9d5ec9..1e0484f 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -49,6 +49,7 @@ int davinci_emac_initialize(void); int dnet_eth_initialize(int id, void *regs, unsigned int phy_addr); int e1000_initialize(bd_t *bis); int eepro100_initialize(bd_t *bis); +int ep93xx_eth_initialize(u8 dev_num, int base_addr); int eth_3com_initialize (bd_t * bis); int fec_initialize (bd_t *bis); int fecmxc_initialize (bd_t *bis);
regards, Ben
participants (2)
-
Ben Warren -
Matthias Kaehlcke