Subject: [PATCH] README file for mpc8360epb board

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doc/README.mpc8360epb | 120 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 120 insertions(+), 0 deletions(-) create mode 100644 doc/README.mpc8360epb

ed6dc7598b748cf7176bfa4ed5be679674e088a9 diff --git a/doc/README.mpc8360epb b/doc/README.mpc8360epb new file mode 100644 index 0000000..85bf0e5 --- /dev/null +++ b/doc/README.mpc8360epb @@ -0,0 +1,120 @@ +Freescale MPC8360E PB Board +----------------------------------------- +1. Board Switches and Jumpers +1.0 There are four Dual-In-Line Packages(DIP) Switches on MPC8360E PB board + For some reason, the HW designers describe the switch settings + in terms of 0 and 1, and then map that to physical switches where + the label "On" refers to logic 0 and "Off" is logic 1. + + Switch bits are numbered 1 through, like, 4 6 8 or 10, but the + bits may contribute to signals that are numbered based at 0, + and some of those signals may be high-bit-number-0 too. Heed + well the names and labels and do not get confused. + + "Off" == 1 + "On" == 0 + + SW18 is switch 18 as silk-screened onto the board. + SW4[8] is the bit labled 8 on Switch 4. + SW2[1:6] refers to bits labeled 1 through 6 in order on switch 2. + SW3[7:1] refers to bits labeled 7 through 1 in order on switch 3. + SW3[1:8]= 0000_0001 refers to bits labeled 1 through 6 is set as "On" + and bits labeled 8 is set as "Off". + +1.1 For the MPC8360E PB PROTO Board + + First, make sure the board default setting is consistent with the document shipped with your board. Then apply the following setting: + SW3[1-8]= 0000_0100 (HRCW setting value is performed on local bus) + SW4[1-8]= 0011_0000 (Flash boot on local bus) + SW9[1-8]= 0100_0110 (PCI Mode enabled. HRCW is read from BCSR when CPU bootup) + SW10[1-8]= 0000_1000 (core PLL setting) + SW11[1-8]= 0000_0100 (SW11 is on the another side of the board) + JP6 1-2 + on board Oscillator: 66M + + +2. Memory Map + +2.1. The memory map should look pretty much like this: + + 0x0000_0000 0x7fff_ffff DDR 2G + 0x8000_0000 0x9fff_ffff PCI MEM 512M + 0xc000_0000 0xdfff_ffff Empty 512M + 0xe000_0000 0xe01f_ffff Int Mem Reg Space 1M + 0xf000_0000 0xf7ff_ffff Local Bus SDRAM 128M + 0xf800_0000 0xf800_7fff BCSR on CS1 32K + 0xf800_8000 0xf800_ffff PIB CS4 32K + 0xf801_0000 0xf801_7fff PIB CS5 32K + 0xfe00_0000 0xfeff_ffff FLASH on CS0 16M + + +3. Definitions + +3.1 Explanation of NEW definitions in: + + include/configs/MPC8360EPB.h + + CONFIG_MPC83XX MPC83xx family for both MPC8349 and MPC8360 + CONFIG_MPC8360 MPC8360 specific + CONFIG_MPC8360EPB MPC8360E PB board specific + +4. Compilation + + Assuming you're using BASH shell: + + export CROSS_COMPILE=your-cross-compile-prefix + cd u-boot + make distclean + make MPC8360EPB_config + make + + MPC8360 support PCI in host and slave mode. + + To make u-boot support PCI host 66M : + 1) DIP SW support PCI mode as described in Section 1.1. + 2) Make MPC8360EPB_HOST_66_config + + To make u-boot support PCI host 33M : + 1) DIP SW setting is similar as Section 1.1, except for SW3[4] is 1 + 2) Make MPC8360EPB_HOST_33_config + + To make u-boot support PCI slave 66M : + 1) DIP SW setting is similar as Section 1.1, except for SW9[3] is 1 + 2) Make MPC8360EPB_HOST_33_config + + +5. Downloading and Flashing Images + +5.0 Download over serial line using Kermit: + + loadb + [Drop to kermit: + ^\c + send <u-boot-bin-image> + c + ] + + + Or via tftp: + + tftp 10000 u-boot.bin + +5.1 Reflash U-boot Image using U-boot + + tftp 20000 u-boot.bin + protect off fef00000 fef3ffff + erase fef00000 fef3ffff + + cp.b 20000 fef00000 xxxx + + or + + cp.b 20000 fef00000 3ffff + + +You have to supply the correct byte count with 'xxxx' from the TFTP result log. +Maybe 3ffff will work too, that corresponds to the erased sectors. + + +6. Notes + 1) The console baudrate for MPC8360EPB is 115200bps.