[U-Boot] [PATCH 00/14] Set of fixes for Exynos4xxx boards
Hello Simon, Tom,
The last driver-model changes was merged too fast and I was not able to test it well on all my boards. It was worked well for the first look, but after deep testing - it required some additional work to do.
So this is a set of fixes required for Exynos4xxx boards. I am not sure what about the Origen.
The patchset was rebased on the top of u-boot-dm/master, which is now: c2ded96 serial: remove uniphier_serial_initialize() call
Tested on: - Trats (E4210) - UniversalC210 (E4210) - Trats2 (E4412) - Odroid U3 (E4412) - Odroid X2 (E4412)
Best Regards, Przemyslaw Marczak
Przemyslaw Marczak (14): mmc: s5p: set SD detection pin as input exynos: common: enable generic fs operations exynos4/4x12: cpu: add extra gpio base addresses exynos4/4x12: gpio: use gpio extra base addresses exynos4412: dts: fix bad gpio order in pinctrl exynos4412: dts: adjust pinctrl-uboot to changed gpio order exynos4210: dts: fix gpio offset in pinctrl-uboot universal: request soft i2c gpio universal: dts: adjust gpio numbers to new api trats: dts: adjust gpio numbers to new api trats2: dts: adjust gpio numbers after gpio rework odroid: dts: adjust sd cd-gpios for SD Card odroid: dts: fix name of included dtsi odroid: adjust gpio calls to dm gpio api
arch/arm/dts/exynos4210-pinctrl-uboot.dtsi | 2 +- arch/arm/dts/exynos4210-trats.dts | 4 +- arch/arm/dts/exynos4210-universal_c210.dts | 4 +- arch/arm/dts/exynos4412-odroid.dts | 4 +- arch/arm/dts/exynos4412-trats2.dts | 6 +-- arch/arm/dts/exynos4x12-pinctrl-uboot.dtsi | 5 +-- arch/arm/dts/exynos4x12-pinctrl.dtsi | 54 +++++++++++++-------------- arch/arm/include/asm/arch-exynos/cpu.h | 9 +++++ arch/arm/include/asm/arch-exynos/gpio.h | 59 ++++++++++++++++++++---------- board/samsung/odroid/odroid.c | 17 ++++++++- board/samsung/universal_c210/universal.c | 9 +++++ drivers/mmc/s5p_sdhci.c | 2 +- include/configs/exynos-common.h | 1 + 13 files changed, 113 insertions(+), 63 deletions(-)
The SD Card slot detection pin should be configured as input.
Signed-off-by: Przemyslaw Marczak p.marczak@samsung.com --- drivers/mmc/s5p_sdhci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mmc/s5p_sdhci.c b/drivers/mmc/s5p_sdhci.c index 0dea45d..a5d3487 100644 --- a/drivers/mmc/s5p_sdhci.c +++ b/drivers/mmc/s5p_sdhci.c @@ -123,7 +123,7 @@ static int do_sdhci_init(struct sdhci_host *host) if (fdt_gpio_isvalid(&host->cd_gpio)) { sprintf(str, "sdhci%d_cd", host->index & 0xf); gpio_request(host->cd_gpio.gpio, str); - gpio_direction_output(host->cd_gpio.gpio, 1); + gpio_direction_input(host->cd_gpio.gpio); if (gpio_get_value(host->cd_gpio.gpio)) return -ENODEV;
On 24 October 2014 09:44, Przemyslaw Marczak p.marczak@samsung.com wrote:
The SD Card slot detection pin should be configured as input.
Signed-off-by: Przemyslaw Marczak p.marczak@samsung.com
Acked-by: Simon Glass sjg@chromium.org
Hi Tom,
On 27 October 2014 19:01, Simon Glass sjg@chromium.org wrote:
On 24 October 2014 09:44, Przemyslaw Marczak p.marczak@samsung.com wrote:
The SD Card slot detection pin should be configured as input.
Signed-off-by: Przemyslaw Marczak p.marczak@samsung.com
Acked-by: Simon Glass sjg@chromium.org
As this directly relates to fixes for the driver model series, I will pick this up in the DM tree. Some of the patches need a respin but I will pull in those that are ready.
Regards, Simon
On 27 October 2014 19:15, Simon Glass sjg@chromium.org wrote:
Hi Tom,
On 27 October 2014 19:01, Simon Glass sjg@chromium.org wrote:
On 24 October 2014 09:44, Przemyslaw Marczak p.marczak@samsung.com wrote:
The SD Card slot detection pin should be configured as input.
Signed-off-by: Przemyslaw Marczak p.marczak@samsung.com
Acked-by: Simon Glass sjg@chromium.org
As this directly relates to fixes for the driver model series, I will pick this up in the DM tree. Some of the patches need a respin but I will pull in those that are ready.
Applied to u-boot-dm, thanks!
Hi, Przemyslaw.
On 10/25/2014 12:44 AM, Przemyslaw Marczak wrote:
The SD Card slot detection pin should be configured as input.
Signed-off-by: Przemyslaw Marczak p.marczak@samsung.com
drivers/mmc/s5p_sdhci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mmc/s5p_sdhci.c b/drivers/mmc/s5p_sdhci.c index 0dea45d..a5d3487 100644 --- a/drivers/mmc/s5p_sdhci.c +++ b/drivers/mmc/s5p_sdhci.c @@ -123,7 +123,7 @@ static int do_sdhci_init(struct sdhci_host *host) if (fdt_gpio_isvalid(&host->cd_gpio)) { sprintf(str, "sdhci%d_cd", host->index & 0xf); gpio_request(host->cd_gpio.gpio, str);
gpio_direction_output(host->cd_gpio.gpio, 1);
gpio_direction_input(host->cd_gpio.gpio);
Input is right?
Best Regards, Jaehoon Chung
if (gpio_get_value(host->cd_gpio.gpio)) return -ENODEV;
Hello,
On 10/28/2014 06:14 AM, Jaehoon Chung wrote:
Hi, Przemyslaw.
On 10/25/2014 12:44 AM, Przemyslaw Marczak wrote:
The SD Card slot detection pin should be configured as input.
Signed-off-by: Przemyslaw Marczak p.marczak@samsung.com
drivers/mmc/s5p_sdhci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mmc/s5p_sdhci.c b/drivers/mmc/s5p_sdhci.c index 0dea45d..a5d3487 100644 --- a/drivers/mmc/s5p_sdhci.c +++ b/drivers/mmc/s5p_sdhci.c @@ -123,7 +123,7 @@ static int do_sdhci_init(struct sdhci_host *host) if (fdt_gpio_isvalid(&host->cd_gpio)) { sprintf(str, "sdhci%d_cd", host->index & 0xf); gpio_request(host->cd_gpio.gpio, str);
gpio_direction_output(host->cd_gpio.gpio, 1);
gpio_direction_input(host->cd_gpio.gpio);Input is right?
Yes, this works fine. The input value changes when you insert or remove the card, so I don't know why there was output.
Best Regards, Jaehoon Chung
if (gpio_get_value(host->cd_gpio.gpio)) return -ENODEV;
Best Regards,
This config is required by Odroid, and could be also useful for the other boards.
Signed-off-by: Przemyslaw Marczak p.marczak@samsung.com --- include/configs/exynos-common.h | 1 + 1 file changed, 1 insertion(+)
diff --git a/include/configs/exynos-common.h b/include/configs/exynos-common.h index 6ba9bb7..b258cb9 100644 --- a/include/configs/exynos-common.h +++ b/include/configs/exynos-common.h @@ -75,6 +75,7 @@ #define CONFIG_CMD_EXT4_WRITE #define CONFIG_CMD_FAT #define CONFIG_FAT_WRITE +#define CONFIG_CMD_FS_GENERIC
#define CONFIG_DOS_PARTITION #define CONFIG_EFI_PARTITION
On 24 October 2014 09:44, Przemyslaw Marczak p.marczak@samsung.com wrote:
This config is required by Odroid, and could be also useful for the other boards.
Signed-off-by: Przemyslaw Marczak p.marczak@samsung.com
Acked-by: Simon Glass sjg@chromium.org
On 27 October 2014 19:09, Simon Glass sjg@chromium.org wrote:
On 24 October 2014 09:44, Przemyslaw Marczak p.marczak@samsung.com wrote:
This config is required by Odroid, and could be also useful for the other boards.
Signed-off-by: Przemyslaw Marczak p.marczak@samsung.com
Acked-by: Simon Glass sjg@chromium.org
Applied to u-boot-dm, thanks!
After remove the offsets in Exynos4/4x12 gpio enums, an addidional gpio base addresses are required.
Signed-off-by: Przemyslaw Marczak p.marczak@samsung.com --- arch/arm/include/asm/arch-exynos/cpu.h | 9 +++++++++ 1 file changed, 9 insertions(+)
diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h index ba71714..78aceef 100644 --- a/arch/arm/include/asm/arch-exynos/cpu.h +++ b/arch/arm/include/asm/arch-exynos/cpu.h @@ -29,6 +29,8 @@ #define EXYNOS4_MIU_BASE 0x10600000 #define EXYNOS4_ACE_SFR_BASE 0x10830000 #define EXYNOS4_GPIO_PART2_BASE 0x11000000 +#define EXYNOS4_GPIO_PART2_0 0x11000000 /* GPJ0 */ +#define EXYNOS4_GPIO_PART2_1 0x11000c00 /* GPX0 */ #define EXYNOS4_GPIO_PART1_BASE 0x11400000 #define EXYNOS4_FIMD_BASE 0x11C00000 #define EXYNOS4_MIPI_DSIM_BASE 0x11C80000 @@ -70,7 +72,14 @@ #define EXYNOS4X12_GPIO_PART4_BASE 0x106E0000 #define EXYNOS4X12_ACE_SFR_BASE 0x10830000 #define EXYNOS4X12_GPIO_PART2_BASE 0x11000000 +#define EXYNOS4X12_GPIO_PART2_0 0x11000000 +#define EXYNOS4X12_GPIO_PART2_1 0x11000040 /* GPK0 */ +#define EXYNOS4X12_GPIO_PART2_2 0x11000260 /* GPM0 */ +#define EXYNOS4X12_GPIO_PART2_3 0x11000c00 /* GPX0 */ #define EXYNOS4X12_GPIO_PART1_BASE 0x11400000 +#define EXYNOS4X12_GPIO_PART1_0 0x11400000 /* GPA0 */ +#define EXYNOS4X12_GPIO_PART1_1 0x11400180 /* GPF0 */ +#define EXYNOS4X12_GPIO_PART1_2 0x11400240 /* GPJ0 */ #define EXYNOS4X12_FIMD_BASE 0x11C00000 #define EXYNOS4X12_MIPI_DSIM_BASE 0x11C80000 #define EXYNOS4X12_USBOTG_BASE 0x12480000
Hi Przemyslaw,
On 24 October 2014 09:44, Przemyslaw Marczak p.marczak@samsung.com wrote:
After remove the offsets in Exynos4/4x12 gpio enums, an addidional gpio base
additional
addresses are required.
Signed-off-by: Przemyslaw Marczak p.marczak@samsung.com
arch/arm/include/asm/arch-exynos/cpu.h | 9 +++++++++ 1 file changed, 9 insertions(+)
diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h index ba71714..78aceef 100644 --- a/arch/arm/include/asm/arch-exynos/cpu.h +++ b/arch/arm/include/asm/arch-exynos/cpu.h @@ -29,6 +29,8 @@ #define EXYNOS4_MIU_BASE 0x10600000 #define EXYNOS4_ACE_SFR_BASE 0x10830000 #define EXYNOS4_GPIO_PART2_BASE 0x11000000 +#define EXYNOS4_GPIO_PART2_0 0x11000000 /* GPJ0 */ +#define EXYNOS4_GPIO_PART2_1 0x11000c00 /* GPX0 */ #define EXYNOS4_GPIO_PART1_BASE 0x11400000 #define EXYNOS4_FIMD_BASE 0x11C00000 #define EXYNOS4_MIPI_DSIM_BASE 0x11C80000 @@ -70,7 +72,14 @@ #define EXYNOS4X12_GPIO_PART4_BASE 0x106E0000 #define EXYNOS4X12_ACE_SFR_BASE 0x10830000 #define EXYNOS4X12_GPIO_PART2_BASE 0x11000000 +#define EXYNOS4X12_GPIO_PART2_0 0x11000000 +#define EXYNOS4X12_GPIO_PART2_1 0x11000040 /* GPK0 */ +#define EXYNOS4X12_GPIO_PART2_2 0x11000260 /* GPM0 */ +#define EXYNOS4X12_GPIO_PART2_3 0x11000c00 /* GPX0 */ #define EXYNOS4X12_GPIO_PART1_BASE 0x11400000 +#define EXYNOS4X12_GPIO_PART1_0 0x11400000 /* GPA0 */ +#define EXYNOS4X12_GPIO_PART1_1 0x11400180 /* GPF0 */ +#define EXYNOS4X12_GPIO_PART1_2 0x11400240 /* GPJ0 */
Why not just number them 0 to 7? It would be simpler.
Also what are these actually used for now? Are they used in SPL perhaps?
Regards, Simon
Hello Simon,
On 10/28/2014 02:10 AM, Simon Glass wrote:
Hi Przemyslaw,
On 24 October 2014 09:44, Przemyslaw Marczak p.marczak@samsung.com wrote:
After remove the offsets in Exynos4/4x12 gpio enums, an addidional gpio base
additional
ok :)
addresses are required.
Signed-off-by: Przemyslaw Marczak p.marczak@samsung.com
arch/arm/include/asm/arch-exynos/cpu.h | 9 +++++++++ 1 file changed, 9 insertions(+)
diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h index ba71714..78aceef 100644 --- a/arch/arm/include/asm/arch-exynos/cpu.h +++ b/arch/arm/include/asm/arch-exynos/cpu.h @@ -29,6 +29,8 @@ #define EXYNOS4_MIU_BASE 0x10600000 #define EXYNOS4_ACE_SFR_BASE 0x10830000 #define EXYNOS4_GPIO_PART2_BASE 0x11000000 +#define EXYNOS4_GPIO_PART2_0 0x11000000 /* GPJ0 */ +#define EXYNOS4_GPIO_PART2_1 0x11000c00 /* GPX0 */ #define EXYNOS4_GPIO_PART1_BASE 0x11400000 #define EXYNOS4_FIMD_BASE 0x11C00000 #define EXYNOS4_MIPI_DSIM_BASE 0x11C80000 @@ -70,7 +72,14 @@ #define EXYNOS4X12_GPIO_PART4_BASE 0x106E0000 #define EXYNOS4X12_ACE_SFR_BASE 0x10830000 #define EXYNOS4X12_GPIO_PART2_BASE 0x11000000 +#define EXYNOS4X12_GPIO_PART2_0 0x11000000 +#define EXYNOS4X12_GPIO_PART2_1 0x11000040 /* GPK0 */ +#define EXYNOS4X12_GPIO_PART2_2 0x11000260 /* GPM0 */ +#define EXYNOS4X12_GPIO_PART2_3 0x11000c00 /* GPX0 */ #define EXYNOS4X12_GPIO_PART1_BASE 0x11400000 +#define EXYNOS4X12_GPIO_PART1_0 0x11400000 /* GPA0 */ +#define EXYNOS4X12_GPIO_PART1_1 0x11400180 /* GPF0 */ +#define EXYNOS4X12_GPIO_PART1_2 0x11400240 /* GPJ0 */
Why not just number them 0 to 7? It would be simpler.
Also what are these actually used for now? Are they used in SPL perhaps?
Regards, Simon
I introduced those sub parts because the main base addresses can be used by macro samsung_get_base..., so this not require to change each call in the code, and this is equal to the SOC documentation. Part is a documented base address. And the sub-part is only a hack for the gpio.
The non-dm gpio calls are used by the spl and of course very early by the pinmux, so we must be sure that the numbering is right.
This hack can be easy removed in the future, when dm be available earlier.
Best regards,
This patch adds extra gpio part addresses to exynos4/4x12_gpio_data arrays, which are required since the gpio enum lists are linear
Signed-off-by: Przemyslaw Marczak p.marczak@samsung.com --- arch/arm/include/asm/arch-exynos/gpio.h | 59 ++++++++++++++++++++++----------- 1 file changed, 39 insertions(+), 20 deletions(-)
diff --git a/arch/arm/include/asm/arch-exynos/gpio.h b/arch/arm/include/asm/arch-exynos/gpio.h index ad2ece6..02287de 100644 --- a/arch/arm/include/asm/arch-exynos/gpio.h +++ b/arch/arm/include/asm/arch-exynos/gpio.h @@ -284,7 +284,10 @@ enum exynos4_gpio_pin { EXYNOS4_GPIO_Y65, EXYNOS4_GPIO_Y66, EXYNOS4_GPIO_Y67, - EXYNOS4_GPIO_X00, /* 256 0x100 */ + + /* GPIO_PART2_1 STARTS */ + EXYNOS4_GPIO_MAX_PORT_PART_2_0, /* 256 0x100 */ + EXYNOS4_GPIO_X00 = EXYNOS4_GPIO_MAX_PORT_PART_2_0, EXYNOS4_GPIO_X01, EXYNOS4_GPIO_X02, EXYNOS4_GPIO_X03, @@ -318,8 +321,8 @@ enum exynos4_gpio_pin { EXYNOS4_GPIO_X37,
/* GPIO_PART3_STARTS */ - EXYNOS4_GPIO_MAX_PORT_PART_2, /* 288 0x120 */ - EXYNOS4_GPIO_Z0 = EXYNOS4_GPIO_MAX_PORT_PART_2, + EXYNOS4_GPIO_MAX_PORT_PART_2_1, /* 288 0x120 */ + EXYNOS4_GPIO_Z0 = EXYNOS4_GPIO_MAX_PORT_PART_2_1, EXYNOS4_GPIO_Z1, EXYNOS4_GPIO_Z2, EXYNOS4_GPIO_Z3, @@ -332,7 +335,7 @@ enum exynos4_gpio_pin { };
enum exynos4X12_gpio_pin { - /* GPIO_PART1_STARTS */ + /* EXYNOS4X12_GPIO_PART1_0 starts here */ EXYNOS4X12_GPIO_A00, /* 0 */ EXYNOS4X12_GPIO_A01, EXYNOS4X12_GPIO_A02, @@ -389,7 +392,9 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_D15, EXYNOS4X12_GPIO_D16, EXYNOS4X12_GPIO_D17, - EXYNOS4X12_GPIO_F00, /* 56 0x38 */ + EXYNOS4X12_GPIO_MAX_PORT_PART_1_0, /* 56 0x38 */ + /* EXYNOS4X12_GPIO_PART1_1 starts here */ + EXYNOS4X12_GPIO_F00 = EXYNOS4X12_GPIO_MAX_PORT_PART_1_0, EXYNOS4X12_GPIO_F01, EXYNOS4X12_GPIO_F02, EXYNOS4X12_GPIO_F03, @@ -421,7 +426,9 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_F35, EXYNOS4X12_GPIO_F36, EXYNOS4X12_GPIO_F37, - EXYNOS4X12_GPIO_J00, /* 88 0x58 */ + EXYNOS4X12_GPIO_MAX_PORT_PART_1_1, /* 88 0x58 */ + /* EXYNOS4X12_GPIO_PART1_2 starts here */ + EXYNOS4X12_GPIO_J00 = EXYNOS4X12_GPIO_MAX_PORT_PART_1_1, EXYNOS4X12_GPIO_J01, EXYNOS4X12_GPIO_J02, EXYNOS4X12_GPIO_J03, @@ -438,9 +445,12 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_J16, EXYNOS4X12_GPIO_J17,
- /* GPIO_PART2_STARTS */ - EXYNOS4X12_GPIO_MAX_PORT_PART_1,/* 104 0x66 */ - EXYNOS4X12_GPIO_K00 = EXYNOS4X12_GPIO_MAX_PORT_PART_1, + /** + * EXYNOS4X12_GPIO_PART2_0 is not used + * EXYNOS4X12_GPIO_PART2_1 starts here + */ + EXYNOS4X12_GPIO_MAX_PORT_PART_1_2, /* 104 0x66 */ + EXYNOS4X12_GPIO_K00 = EXYNOS4X12_GPIO_MAX_PORT_PART_1_2, EXYNOS4X12_GPIO_K01, EXYNOS4X12_GPIO_K02, EXYNOS4X12_GPIO_K03, @@ -552,7 +562,9 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_Y65, EXYNOS4X12_GPIO_Y66, EXYNOS4X12_GPIO_Y67, - EXYNOS4X12_GPIO_M00, /* 216 0xd8 */ + EXYNOS4X12_GPIO_MAX_PORT_PART_2_1, /* 216 0xd8 */ + /* EXYNOS4X12_GPIO_PART2_2 starts here */ + EXYNOS4X12_GPIO_M00 = EXYNOS4X12_GPIO_MAX_PORT_PART_2_1, EXYNOS4X12_GPIO_M01, EXYNOS4X12_GPIO_M02, EXYNOS4X12_GPIO_M03, @@ -592,7 +604,9 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_M45, EXYNOS4X12_GPIO_M46, EXYNOS4X12_GPIO_M47, - EXYNOS4X12_GPIO_X00, /* 256 0x100 */ + EXYNOS4X12_GPIO_MAX_PORT_PART_2_2, /* 256 0x100 */ + /* EXYNOS4X12_GPIO_PART2_3 starts here */ + EXYNOS4X12_GPIO_X00 = EXYNOS4X12_GPIO_MAX_PORT_PART_2_2, EXYNOS4X12_GPIO_X01, EXYNOS4X12_GPIO_X02, EXYNOS4X12_GPIO_X03, @@ -625,9 +639,9 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_X36, EXYNOS4X12_GPIO_X37,
- /* GPIO_PART3_STARTS */ - EXYNOS4X12_GPIO_MAX_PORT_PART_2,/* 288 0x120 */ - EXYNOS4X12_GPIO_Z0 = EXYNOS4X12_GPIO_MAX_PORT_PART_2, + /* EXYNOS4X12_GPIO_PART3 starts here */ + EXYNOS4X12_GPIO_MAX_PORT_PART_2_3, /* 288 0x120 */ + EXYNOS4X12_GPIO_Z0 = EXYNOS4X12_GPIO_MAX_PORT_PART_2_3, EXYNOS4X12_GPIO_Z1, EXYNOS4X12_GPIO_Z2, EXYNOS4X12_GPIO_Z3, @@ -636,7 +650,7 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_Z6, EXYNOS4X12_GPIO_Z7,
- /* GPIO_PART4_STARTS */ + /* EXYNOS4X12_GPIO_PART4 starts here */ EXYNOS4X12_GPIO_MAX_PORT_PART_3,/* 296 0x128 */ EXYNOS4X12_GPIO_V00 = EXYNOS4X12_GPIO_MAX_PORT_PART_3, EXYNOS4X12_GPIO_V01, @@ -1339,17 +1353,22 @@ struct gpio_info { unsigned int max_gpio; /* Maximum GPIO in this part */ };
-#define EXYNOS4_GPIO_NUM_PARTS 3 +#define EXYNOS4_GPIO_NUM_PARTS 4 static struct gpio_info exynos4_gpio_data[EXYNOS4_GPIO_NUM_PARTS] = { { EXYNOS4_GPIO_PART1_BASE, EXYNOS4_GPIO_MAX_PORT_PART_1 }, - { EXYNOS4_GPIO_PART2_BASE, EXYNOS4_GPIO_MAX_PORT_PART_2 }, + { EXYNOS4_GPIO_PART2_0, EXYNOS4_GPIO_MAX_PORT_PART_2_0 }, + { EXYNOS4_GPIO_PART2_1, EXYNOS4_GPIO_MAX_PORT_PART_2_1 }, { EXYNOS4_GPIO_PART3_BASE, EXYNOS4_GPIO_MAX_PORT }, };
-#define EXYNOS4X12_GPIO_NUM_PARTS 4 +#define EXYNOS4X12_GPIO_NUM_PARTS 8 static struct gpio_info exynos4x12_gpio_data[EXYNOS4X12_GPIO_NUM_PARTS] = { - { EXYNOS4X12_GPIO_PART1_BASE, EXYNOS4X12_GPIO_MAX_PORT_PART_1 }, - { EXYNOS4X12_GPIO_PART2_BASE, EXYNOS4X12_GPIO_MAX_PORT_PART_2 }, + { EXYNOS4X12_GPIO_PART1_0, EXYNOS4X12_GPIO_MAX_PORT_PART_1_0 }, + { EXYNOS4X12_GPIO_PART1_1, EXYNOS4X12_GPIO_MAX_PORT_PART_1_1 }, + { EXYNOS4X12_GPIO_PART1_2, EXYNOS4X12_GPIO_MAX_PORT_PART_1_2 }, + { EXYNOS4X12_GPIO_PART2_1, EXYNOS4X12_GPIO_MAX_PORT_PART_2_1 }, + { EXYNOS4X12_GPIO_PART2_2, EXYNOS4X12_GPIO_MAX_PORT_PART_2_2 }, + { EXYNOS4X12_GPIO_PART2_3, EXYNOS4X12_GPIO_MAX_PORT_PART_2_3 }, { EXYNOS4X12_GPIO_PART3_BASE, EXYNOS4X12_GPIO_MAX_PORT_PART_3 }, { EXYNOS4X12_GPIO_PART4_BASE, EXYNOS4X12_GPIO_MAX_PORT }, };
Hi,
On 24 October 2014 09:44, Przemyslaw Marczak p.marczak@samsung.com wrote:
This patch adds extra gpio part addresses to exynos4/4x12_gpio_data arrays, which are required since the gpio enum lists are linear
Signed-off-by: Przemyslaw Marczak p.marczak@samsung.com
arch/arm/include/asm/arch-exynos/gpio.h | 59 ++++++++++++++++++++++----------- 1 file changed, 39 insertions(+), 20 deletions(-)
diff --git a/arch/arm/include/asm/arch-exynos/gpio.h b/arch/arm/include/asm/arch-exynos/gpio.h index ad2ece6..02287de 100644 --- a/arch/arm/include/asm/arch-exynos/gpio.h +++ b/arch/arm/include/asm/arch-exynos/gpio.h @@ -284,7 +284,10 @@ enum exynos4_gpio_pin { EXYNOS4_GPIO_Y65, EXYNOS4_GPIO_Y66, EXYNOS4_GPIO_Y67,
EXYNOS4_GPIO_X00, /* 256 0x100 */
/* GPIO_PART2_1 STARTS */EXYNOS4_GPIO_MAX_PORT_PART_2_0, /* 256 0x100 */EXYNOS4_GPIO_X00 = EXYNOS4_GPIO_MAX_PORT_PART_2_0, EXYNOS4_GPIO_X01, EXYNOS4_GPIO_X02, EXYNOS4_GPIO_X03,@@ -318,8 +321,8 @@ enum exynos4_gpio_pin { EXYNOS4_GPIO_X37,
/* GPIO_PART3_STARTS */
EXYNOS4_GPIO_MAX_PORT_PART_2, /* 288 0x120 */EXYNOS4_GPIO_Z0 = EXYNOS4_GPIO_MAX_PORT_PART_2,
EXYNOS4_GPIO_MAX_PORT_PART_2_1, /* 288 0x120 */EXYNOS4_GPIO_Z0 = EXYNOS4_GPIO_MAX_PORT_PART_2_1, EXYNOS4_GPIO_Z1, EXYNOS4_GPIO_Z2, EXYNOS4_GPIO_Z3,@@ -332,7 +335,7 @@ enum exynos4_gpio_pin { };
enum exynos4X12_gpio_pin {
/* GPIO_PART1_STARTS */
/* EXYNOS4X12_GPIO_PART1_0 starts here */ EXYNOS4X12_GPIO_A00, /* 0 */ EXYNOS4X12_GPIO_A01, EXYNOS4X12_GPIO_A02,@@ -389,7 +392,9 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_D15, EXYNOS4X12_GPIO_D16, EXYNOS4X12_GPIO_D17,
EXYNOS4X12_GPIO_F00, /* 56 0x38 */
EXYNOS4X12_GPIO_MAX_PORT_PART_1_0, /* 56 0x38 *//* EXYNOS4X12_GPIO_PART1_1 starts here */EXYNOS4X12_GPIO_F00 = EXYNOS4X12_GPIO_MAX_PORT_PART_1_0, EXYNOS4X12_GPIO_F01, EXYNOS4X12_GPIO_F02, EXYNOS4X12_GPIO_F03,@@ -421,7 +426,9 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_F35, EXYNOS4X12_GPIO_F36, EXYNOS4X12_GPIO_F37,
EXYNOS4X12_GPIO_J00, /* 88 0x58 */
EXYNOS4X12_GPIO_MAX_PORT_PART_1_1, /* 88 0x58 *//* EXYNOS4X12_GPIO_PART1_2 starts here */EXYNOS4X12_GPIO_J00 = EXYNOS4X12_GPIO_MAX_PORT_PART_1_1, EXYNOS4X12_GPIO_J01, EXYNOS4X12_GPIO_J02, EXYNOS4X12_GPIO_J03,@@ -438,9 +445,12 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_J16, EXYNOS4X12_GPIO_J17,
/* GPIO_PART2_STARTS */EXYNOS4X12_GPIO_MAX_PORT_PART_1,/* 104 0x66 */EXYNOS4X12_GPIO_K00 = EXYNOS4X12_GPIO_MAX_PORT_PART_1,
/*** EXYNOS4X12_GPIO_PART2_0 is not used* EXYNOS4X12_GPIO_PART2_1 starts here*/EXYNOS4X12_GPIO_MAX_PORT_PART_1_2, /* 104 0x66 */EXYNOS4X12_GPIO_K00 = EXYNOS4X12_GPIO_MAX_PORT_PART_1_2, EXYNOS4X12_GPIO_K01, EXYNOS4X12_GPIO_K02, EXYNOS4X12_GPIO_K03,@@ -552,7 +562,9 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_Y65, EXYNOS4X12_GPIO_Y66, EXYNOS4X12_GPIO_Y67,
EXYNOS4X12_GPIO_M00, /* 216 0xd8 */
EXYNOS4X12_GPIO_MAX_PORT_PART_2_1, /* 216 0xd8 *//* EXYNOS4X12_GPIO_PART2_2 starts here */EXYNOS4X12_GPIO_M00 = EXYNOS4X12_GPIO_MAX_PORT_PART_2_1, EXYNOS4X12_GPIO_M01, EXYNOS4X12_GPIO_M02, EXYNOS4X12_GPIO_M03,@@ -592,7 +604,9 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_M45, EXYNOS4X12_GPIO_M46, EXYNOS4X12_GPIO_M47,
EXYNOS4X12_GPIO_X00, /* 256 0x100 */
EXYNOS4X12_GPIO_MAX_PORT_PART_2_2, /* 256 0x100 *//* EXYNOS4X12_GPIO_PART2_3 starts here */EXYNOS4X12_GPIO_X00 = EXYNOS4X12_GPIO_MAX_PORT_PART_2_2, EXYNOS4X12_GPIO_X01, EXYNOS4X12_GPIO_X02, EXYNOS4X12_GPIO_X03,@@ -625,9 +639,9 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_X36, EXYNOS4X12_GPIO_X37,
/* GPIO_PART3_STARTS */EXYNOS4X12_GPIO_MAX_PORT_PART_2,/* 288 0x120 */EXYNOS4X12_GPIO_Z0 = EXYNOS4X12_GPIO_MAX_PORT_PART_2,
/* EXYNOS4X12_GPIO_PART3 starts here */EXYNOS4X12_GPIO_MAX_PORT_PART_2_3, /* 288 0x120 */EXYNOS4X12_GPIO_Z0 = EXYNOS4X12_GPIO_MAX_PORT_PART_2_3, EXYNOS4X12_GPIO_Z1, EXYNOS4X12_GPIO_Z2, EXYNOS4X12_GPIO_Z3,@@ -636,7 +650,7 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_Z6, EXYNOS4X12_GPIO_Z7,
/* GPIO_PART4_STARTS */
/* EXYNOS4X12_GPIO_PART4 starts here */ EXYNOS4X12_GPIO_MAX_PORT_PART_3,/* 296 0x128 */ EXYNOS4X12_GPIO_V00 = EXYNOS4X12_GPIO_MAX_PORT_PART_3, EXYNOS4X12_GPIO_V01,@@ -1339,17 +1353,22 @@ struct gpio_info { unsigned int max_gpio; /* Maximum GPIO in this part */ };
-#define EXYNOS4_GPIO_NUM_PARTS 3 +#define EXYNOS4_GPIO_NUM_PARTS 4 static struct gpio_info exynos4_gpio_data[EXYNOS4_GPIO_NUM_PARTS] = { { EXYNOS4_GPIO_PART1_BASE, EXYNOS4_GPIO_MAX_PORT_PART_1 },
{ EXYNOS4_GPIO_PART2_BASE, EXYNOS4_GPIO_MAX_PORT_PART_2 },
{ EXYNOS4_GPIO_PART2_0, EXYNOS4_GPIO_MAX_PORT_PART_2_0 },{ EXYNOS4_GPIO_PART2_1, EXYNOS4_GPIO_MAX_PORT_PART_2_1 }, { EXYNOS4_GPIO_PART3_BASE, EXYNOS4_GPIO_MAX_PORT },};
-#define EXYNOS4X12_GPIO_NUM_PARTS 4 +#define EXYNOS4X12_GPIO_NUM_PARTS 8 static struct gpio_info exynos4x12_gpio_data[EXYNOS4X12_GPIO_NUM_PARTS] = {
{ EXYNOS4X12_GPIO_PART1_BASE, EXYNOS4X12_GPIO_MAX_PORT_PART_1 },{ EXYNOS4X12_GPIO_PART2_BASE, EXYNOS4X12_GPIO_MAX_PORT_PART_2 },
{ EXYNOS4X12_GPIO_PART1_0, EXYNOS4X12_GPIO_MAX_PORT_PART_1_0 },{ EXYNOS4X12_GPIO_PART1_1, EXYNOS4X12_GPIO_MAX_PORT_PART_1_1 },{ EXYNOS4X12_GPIO_PART1_2, EXYNOS4X12_GPIO_MAX_PORT_PART_1_2 },{ EXYNOS4X12_GPIO_PART2_1, EXYNOS4X12_GPIO_MAX_PORT_PART_2_1 },{ EXYNOS4X12_GPIO_PART2_2, EXYNOS4X12_GPIO_MAX_PORT_PART_2_2 },{ EXYNOS4X12_GPIO_PART2_3, EXYNOS4X12_GPIO_MAX_PORT_PART_2_3 },
Again I wonder if we can just number these 0 to 7?
{ EXYNOS4X12_GPIO_PART3_BASE, EXYNOS4X12_GPIO_MAX_PORT_PART_3 }, { EXYNOS4X12_GPIO_PART4_BASE, EXYNOS4X12_GPIO_MAX_PORT },};
1.9.1
Regards, Simon
Hello,
On 10/28/2014 02:10 AM, Simon Glass wrote:
Hi,
On 24 October 2014 09:44, Przemyslaw Marczak p.marczak@samsung.com wrote:
This patch adds extra gpio part addresses to exynos4/4x12_gpio_data arrays, which are required since the gpio enum lists are linear
Signed-off-by: Przemyslaw Marczak p.marczak@samsung.com
arch/arm/include/asm/arch-exynos/gpio.h | 59 ++++++++++++++++++++++----------- 1 file changed, 39 insertions(+), 20 deletions(-)
diff --git a/arch/arm/include/asm/arch-exynos/gpio.h b/arch/arm/include/asm/arch-exynos/gpio.h index ad2ece6..02287de 100644 --- a/arch/arm/include/asm/arch-exynos/gpio.h +++ b/arch/arm/include/asm/arch-exynos/gpio.h @@ -284,7 +284,10 @@ enum exynos4_gpio_pin { EXYNOS4_GPIO_Y65, EXYNOS4_GPIO_Y66, EXYNOS4_GPIO_Y67,
EXYNOS4_GPIO_X00, /* 256 0x100 */
/* GPIO_PART2_1 STARTS */EXYNOS4_GPIO_MAX_PORT_PART_2_0, /* 256 0x100 */EXYNOS4_GPIO_X00 = EXYNOS4_GPIO_MAX_PORT_PART_2_0, EXYNOS4_GPIO_X01, EXYNOS4_GPIO_X02, EXYNOS4_GPIO_X03,@@ -318,8 +321,8 @@ enum exynos4_gpio_pin { EXYNOS4_GPIO_X37,
/* GPIO_PART3_STARTS */
EXYNOS4_GPIO_MAX_PORT_PART_2, /* 288 0x120 */EXYNOS4_GPIO_Z0 = EXYNOS4_GPIO_MAX_PORT_PART_2,
EXYNOS4_GPIO_MAX_PORT_PART_2_1, /* 288 0x120 */EXYNOS4_GPIO_Z0 = EXYNOS4_GPIO_MAX_PORT_PART_2_1, EXYNOS4_GPIO_Z1, EXYNOS4_GPIO_Z2, EXYNOS4_GPIO_Z3,@@ -332,7 +335,7 @@ enum exynos4_gpio_pin { };
enum exynos4X12_gpio_pin {
/* GPIO_PART1_STARTS */
/* EXYNOS4X12_GPIO_PART1_0 starts here */ EXYNOS4X12_GPIO_A00, /* 0 */ EXYNOS4X12_GPIO_A01, EXYNOS4X12_GPIO_A02,@@ -389,7 +392,9 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_D15, EXYNOS4X12_GPIO_D16, EXYNOS4X12_GPIO_D17,
EXYNOS4X12_GPIO_F00, /* 56 0x38 */
EXYNOS4X12_GPIO_MAX_PORT_PART_1_0, /* 56 0x38 *//* EXYNOS4X12_GPIO_PART1_1 starts here */EXYNOS4X12_GPIO_F00 = EXYNOS4X12_GPIO_MAX_PORT_PART_1_0, EXYNOS4X12_GPIO_F01, EXYNOS4X12_GPIO_F02, EXYNOS4X12_GPIO_F03,@@ -421,7 +426,9 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_F35, EXYNOS4X12_GPIO_F36, EXYNOS4X12_GPIO_F37,
EXYNOS4X12_GPIO_J00, /* 88 0x58 */
EXYNOS4X12_GPIO_MAX_PORT_PART_1_1, /* 88 0x58 *//* EXYNOS4X12_GPIO_PART1_2 starts here */EXYNOS4X12_GPIO_J00 = EXYNOS4X12_GPIO_MAX_PORT_PART_1_1, EXYNOS4X12_GPIO_J01, EXYNOS4X12_GPIO_J02, EXYNOS4X12_GPIO_J03,@@ -438,9 +445,12 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_J16, EXYNOS4X12_GPIO_J17,
/* GPIO_PART2_STARTS */EXYNOS4X12_GPIO_MAX_PORT_PART_1,/* 104 0x66 */EXYNOS4X12_GPIO_K00 = EXYNOS4X12_GPIO_MAX_PORT_PART_1,
/*** EXYNOS4X12_GPIO_PART2_0 is not used* EXYNOS4X12_GPIO_PART2_1 starts here*/EXYNOS4X12_GPIO_MAX_PORT_PART_1_2, /* 104 0x66 */EXYNOS4X12_GPIO_K00 = EXYNOS4X12_GPIO_MAX_PORT_PART_1_2, EXYNOS4X12_GPIO_K01, EXYNOS4X12_GPIO_K02, EXYNOS4X12_GPIO_K03,@@ -552,7 +562,9 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_Y65, EXYNOS4X12_GPIO_Y66, EXYNOS4X12_GPIO_Y67,
EXYNOS4X12_GPIO_M00, /* 216 0xd8 */
EXYNOS4X12_GPIO_MAX_PORT_PART_2_1, /* 216 0xd8 *//* EXYNOS4X12_GPIO_PART2_2 starts here */EXYNOS4X12_GPIO_M00 = EXYNOS4X12_GPIO_MAX_PORT_PART_2_1, EXYNOS4X12_GPIO_M01, EXYNOS4X12_GPIO_M02, EXYNOS4X12_GPIO_M03,@@ -592,7 +604,9 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_M45, EXYNOS4X12_GPIO_M46, EXYNOS4X12_GPIO_M47,
EXYNOS4X12_GPIO_X00, /* 256 0x100 */
EXYNOS4X12_GPIO_MAX_PORT_PART_2_2, /* 256 0x100 *//* EXYNOS4X12_GPIO_PART2_3 starts here */EXYNOS4X12_GPIO_X00 = EXYNOS4X12_GPIO_MAX_PORT_PART_2_2, EXYNOS4X12_GPIO_X01, EXYNOS4X12_GPIO_X02, EXYNOS4X12_GPIO_X03,@@ -625,9 +639,9 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_X36, EXYNOS4X12_GPIO_X37,
/* GPIO_PART3_STARTS */EXYNOS4X12_GPIO_MAX_PORT_PART_2,/* 288 0x120 */EXYNOS4X12_GPIO_Z0 = EXYNOS4X12_GPIO_MAX_PORT_PART_2,
/* EXYNOS4X12_GPIO_PART3 starts here */EXYNOS4X12_GPIO_MAX_PORT_PART_2_3, /* 288 0x120 */EXYNOS4X12_GPIO_Z0 = EXYNOS4X12_GPIO_MAX_PORT_PART_2_3, EXYNOS4X12_GPIO_Z1, EXYNOS4X12_GPIO_Z2, EXYNOS4X12_GPIO_Z3,@@ -636,7 +650,7 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_Z6, EXYNOS4X12_GPIO_Z7,
/* GPIO_PART4_STARTS */
/* EXYNOS4X12_GPIO_PART4 starts here */ EXYNOS4X12_GPIO_MAX_PORT_PART_3,/* 296 0x128 */ EXYNOS4X12_GPIO_V00 = EXYNOS4X12_GPIO_MAX_PORT_PART_3, EXYNOS4X12_GPIO_V01,@@ -1339,17 +1353,22 @@ struct gpio_info { unsigned int max_gpio; /* Maximum GPIO in this part */ };
-#define EXYNOS4_GPIO_NUM_PARTS 3 +#define EXYNOS4_GPIO_NUM_PARTS 4 static struct gpio_info exynos4_gpio_data[EXYNOS4_GPIO_NUM_PARTS] = { { EXYNOS4_GPIO_PART1_BASE, EXYNOS4_GPIO_MAX_PORT_PART_1 },
{ EXYNOS4_GPIO_PART2_BASE, EXYNOS4_GPIO_MAX_PORT_PART_2 },
{ EXYNOS4_GPIO_PART2_0, EXYNOS4_GPIO_MAX_PORT_PART_2_0 },{ EXYNOS4_GPIO_PART2_1, EXYNOS4_GPIO_MAX_PORT_PART_2_1 }, { EXYNOS4_GPIO_PART3_BASE, EXYNOS4_GPIO_MAX_PORT },-#define EXYNOS4X12_GPIO_NUM_PARTS 4 +#define EXYNOS4X12_GPIO_NUM_PARTS 8 static struct gpio_info exynos4x12_gpio_data[EXYNOS4X12_GPIO_NUM_PARTS] = {
{ EXYNOS4X12_GPIO_PART1_BASE, EXYNOS4X12_GPIO_MAX_PORT_PART_1 },{ EXYNOS4X12_GPIO_PART2_BASE, EXYNOS4X12_GPIO_MAX_PORT_PART_2 },
{ EXYNOS4X12_GPIO_PART1_0, EXYNOS4X12_GPIO_MAX_PORT_PART_1_0 },{ EXYNOS4X12_GPIO_PART1_1, EXYNOS4X12_GPIO_MAX_PORT_PART_1_1 },{ EXYNOS4X12_GPIO_PART1_2, EXYNOS4X12_GPIO_MAX_PORT_PART_1_2 },{ EXYNOS4X12_GPIO_PART2_1, EXYNOS4X12_GPIO_MAX_PORT_PART_2_1 },{ EXYNOS4X12_GPIO_PART2_2, EXYNOS4X12_GPIO_MAX_PORT_PART_2_2 },{ EXYNOS4X12_GPIO_PART2_3, EXYNOS4X12_GPIO_MAX_PORT_PART_2_3 },Again I wonder if we can just number these 0 to 7?
And again, if we want to remove this interface in the future, the old EXYNOS4X12_GPIO_PART[x]_BASE will be still unchanged an can be used as it is.
{ EXYNOS4X12_GPIO_PART3_BASE, EXYNOS4X12_GPIO_MAX_PORT_PART_3 }, { EXYNOS4X12_GPIO_PART4_BASE, EXYNOS4X12_GPIO_MAX_PORT },};
1.9.1
Regards, Simon
Best regards,
The pinctrl dts was imported from the kernel, but the order of GPM and GPY is wrong. The gpio enum in: asm/arch/gpio.h is proper.
Signed-off-by: Przemyslaw Marczak p.marczak@samsung.com --- arch/arm/dts/exynos4x12-pinctrl.dtsi | 54 ++++++++++++++++++------------------ 1 file changed, 27 insertions(+), 27 deletions(-)
diff --git a/arch/arm/dts/exynos4x12-pinctrl.dtsi b/arch/arm/dts/exynos4x12-pinctrl.dtsi index 93f3998..2306135 100644 --- a/arch/arm/dts/exynos4x12-pinctrl.dtsi +++ b/arch/arm/dts/exynos4x12-pinctrl.dtsi @@ -176,79 +176,79 @@ #interrupt-cells = <2>; };
- gpm0: gpm0 { + gpy0: gpy0 { gpio-controller; #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; };
- gpm1: gpm1 { + gpy1: gpy1 { gpio-controller; #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; };
- gpm2: gpm2 { + gpy2: gpy2 { gpio-controller; #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; };
- gpm3: gpm3 { + gpy3: gpy3 { gpio-controller; #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; };
- gpm4: gpm4 { + gpy4: gpy4 { gpio-controller; #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; };
- gpy0: gpy0 { + gpy5: gpy5 { gpio-controller; #gpio-cells = <2>; };
- gpy1: gpy1 { + gpy6: gpy6 { gpio-controller; #gpio-cells = <2>; };
- gpy2: gpy2 { + gpm0: gpm0 { gpio-controller; #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; };
- gpy3: gpy3 { + gpm1: gpm1 { gpio-controller; #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; };
- gpy4: gpy4 { + gpm2: gpm2 { gpio-controller; #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; };
- gpy5: gpy5 { + gpm3: gpm3 { gpio-controller; #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; };
- gpy6: gpy6 { + gpm4: gpm4 { gpio-controller; #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; };
gpx0: gpx0 {
On 24 October 2014 09:45, Przemyslaw Marczak p.marczak@samsung.com wrote:
The pinctrl dts was imported from the kernel, but the order of GPM and GPY is wrong. The gpio enum in: asm/arch/gpio.h is proper.
Signed-off-by: Przemyslaw Marczak p.marczak@samsung.com
Acked-by: Simon Glass sjg@chromium.org
On 27 October 2014 19:11, Simon Glass sjg@chromium.org wrote:
On 24 October 2014 09:45, Przemyslaw Marczak p.marczak@samsung.com wrote:
The pinctrl dts was imported from the kernel, but the order of GPM and GPY is wrong. The gpio enum in: asm/arch/gpio.h is proper.
Signed-off-by: Przemyslaw Marczak p.marczak@samsung.com
Acked-by: Simon Glass sjg@chromium.org
Applied to u-boot-dm, thanks!
The gpf0 offset was bad and it's now fixed. After fix gpio order in *pinctrl.dts , the gpy0 offset is not required now.
Signed-off-by: Przemyslaw Marczak p.marczak@samsung.com --- arch/arm/dts/exynos4x12-pinctrl-uboot.dtsi | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/arch/arm/dts/exynos4x12-pinctrl-uboot.dtsi b/arch/arm/dts/exynos4x12-pinctrl-uboot.dtsi index c02796d..c41d07b 100644 --- a/arch/arm/dts/exynos4x12-pinctrl-uboot.dtsi +++ b/arch/arm/dts/exynos4x12-pinctrl-uboot.dtsi @@ -9,7 +9,7 @@ #address-cells = <1>; #size-cells = <0>; gpf0: gpf0 { - reg = <0xc180>; + reg = <0x180>; }; gpj0: gpj0 { reg = <0x240>; @@ -25,9 +25,6 @@ gpm0: gpm0 { reg = <0x260>; }; - gpy0: gpy0 { - reg = <0x120>; - }; gpx0: gpx0 { reg = <0xc00>; };
On 24 October 2014 09:45, Przemyslaw Marczak p.marczak@samsung.com wrote:
The gpf0 offset was bad and it's now fixed. After fix gpio order in *pinctrl.dts , the gpy0 offset is not required now.
Signed-off-by: Przemyslaw Marczak p.marczak@samsung.com
Acked-by: Simon Glass sjg@chromium.org
On 27 October 2014 19:11, Simon Glass sjg@chromium.org wrote:
On 24 October 2014 09:45, Przemyslaw Marczak p.marczak@samsung.com wrote:
The gpf0 offset was bad and it's now fixed. After fix gpio order in *pinctrl.dts , the gpy0 offset is not required now.
Signed-off-by: Przemyslaw Marczak p.marczak@samsung.com
Acked-by: Simon Glass sjg@chromium.org
Applied to u-boot-dm, thanks!
The gpy0 don't need any additional register offset, but the gpx0 does, so now it is fixed.
Signed-off-by: Przemyslaw Marczak p.marczak@samsung.com --- arch/arm/dts/exynos4210-pinctrl-uboot.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/dts/exynos4210-pinctrl-uboot.dtsi b/arch/arm/dts/exynos4210-pinctrl-uboot.dtsi index ee071c1..f9b61ba 100644 --- a/arch/arm/dts/exynos4210-pinctrl-uboot.dtsi +++ b/arch/arm/dts/exynos4210-pinctrl-uboot.dtsi @@ -14,7 +14,7 @@ pinctrl_1: pinctrl@11000000 { #address-cells = <1>; #size-cells = <0>; - gpy0: gpy0 { + gpx0: gpx0 { reg = <0xc00>; }; };
On 24 October 2014 09:45, Przemyslaw Marczak p.marczak@samsung.com wrote:
The gpy0 don't need any additional register offset, but the gpx0 does, so now it is fixed.
Signed-off-by: Przemyslaw Marczak p.marczak@samsung.com
Acked-by: Simon Glass sjg@chromium.org
On 27 October 2014 19:11, Simon Glass sjg@chromium.org wrote:
On 24 October 2014 09:45, Przemyslaw Marczak p.marczak@samsung.com wrote:
The gpy0 don't need any additional register offset, but the gpx0 does, so now it is fixed.
Signed-off-by: Przemyslaw Marczak p.marczak@samsung.com
Acked-by: Simon Glass sjg@chromium.org
Applied to u-boot-dm, thanks!
Signed-off-by: Przemyslaw Marczak p.marczak@samsung.com --- board/samsung/universal_c210/universal.c | 9 +++++++++ 1 file changed, 9 insertions(+)
diff --git a/board/samsung/universal_c210/universal.c b/board/samsung/universal_c210/universal.c index 22b0849..df46713 100644 --- a/board/samsung/universal_c210/universal.c +++ b/board/samsung/universal_c210/universal.c @@ -328,6 +328,8 @@ void exynos_enable_ldo(unsigned int onoff)
int exynos_init(void) { + char buf[16]; + gd->bd->bi_arch_number = MACH_TYPE_UNIVERSAL_C210;
switch (get_hwrev()) { @@ -352,6 +354,13 @@ int exynos_init(void) break; }
+ /* Request soft I2C gpios */ + sprintf(buf, "soft_i2c_scl"); + gpio_request(CONFIG_SOFT_I2C_GPIO_SCL, buf); + + sprintf(buf, "soft_i2c_sda"); + gpio_request(CONFIG_SOFT_I2C_GPIO_SDA, buf); + check_hw_revision(); printf("HW Revision:\t0x%x\n", board_rev);
On 24 October 2014 09:45, Przemyslaw Marczak p.marczak@samsung.com wrote:
Signed-off-by: Przemyslaw Marczak p.marczak@samsung.com
Acked-by: Simon Glass sjg@chromium.org
2014-10-27 19:12 GMT-06:00 Simon Glass sjg@chromium.org:
On 24 October 2014 09:45, Przemyslaw Marczak p.marczak@samsung.com wrote:
Signed-off-by: Przemyslaw Marczak p.marczak@samsung.com
Acked-by: Simon Glass sjg@chromium.org
Applied to u-boot-dm, thanks!
Signed-off-by: Przemyslaw Marczak p.marczak@samsung.com --- board/samsung/universal_c210/universal.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+)
diff --git a/board/samsung/universal_c210/universal.c b/board/samsung/universal_c210/universal.c index c04f48c..b53def8 100644 --- a/board/samsung/universal_c210/universal.c +++ b/board/samsung/universal_c210/universal.c @@ -204,6 +204,21 @@ int exynos_early_init_f(void) #ifdef CONFIG_SOFT_SPI static void soft_spi_init(void) { + char buf[16]; + + /* Reserve gpios for soft SPI */ + sprintf(buf, "soft_spi_sclk"); + gpio_request(CONFIG_SOFT_SPI_GPIO_SCLK, buf); + + sprintf(buf, "soft_spi_mosi"); + gpio_request(CONFIG_SOFT_SPI_GPIO_MOSI, buf); + + sprintf(buf, "soft_spi_miso"); + gpio_request(CONFIG_SOFT_SPI_GPIO_MISO, buf); + + sprintf(buf, "soft_spi_cs"); + gpio_request(CONFIG_SOFT_SPI_GPIO_CS, buf); + gpio_direction_output(CONFIG_SOFT_SPI_GPIO_SCLK, CONFIG_SOFT_SPI_MODE & SPI_CPOL); gpio_direction_output(CONFIG_SOFT_SPI_GPIO_MOSI, 1); @@ -377,6 +392,8 @@ void exynos_enable_ldo(unsigned int onoff)
int exynos_init(void) { + char buf[16]; + gd->bd->bi_arch_number = MACH_TYPE_UNIVERSAL_C210;
switch (get_hwrev()) { @@ -401,6 +418,13 @@ int exynos_init(void) break; }
+ /* Request soft I2C gpios */ + sprintf(buf, "soft_i2c_scl"); + gpio_request(CONFIG_SOFT_I2C_GPIO_SCL, buf); + + sprintf(buf, "soft_i2c_sda"); + gpio_request(CONFIG_SOFT_I2C_GPIO_SDA, buf); + #ifdef CONFIG_SOFT_SPI soft_spi_init(); #endif
Hello,
This commit was send by a mistake, the previous one is proper. So please use the previous "8-th".
On 10/24/2014 05:45 PM, Przemyslaw Marczak wrote:
Signed-off-by: Przemyslaw Marczak p.marczak@samsung.com
board/samsung/universal_c210/universal.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+)
diff --git a/board/samsung/universal_c210/universal.c b/board/samsung/universal_c210/universal.c index c04f48c..b53def8 100644 --- a/board/samsung/universal_c210/universal.c +++ b/board/samsung/universal_c210/universal.c @@ -204,6 +204,21 @@ int exynos_early_init_f(void) #ifdef CONFIG_SOFT_SPI static void soft_spi_init(void) {
- char buf[16];
- /* Reserve gpios for soft SPI */
- sprintf(buf, "soft_spi_sclk");
- gpio_request(CONFIG_SOFT_SPI_GPIO_SCLK, buf);
- sprintf(buf, "soft_spi_mosi");
- gpio_request(CONFIG_SOFT_SPI_GPIO_MOSI, buf);
- sprintf(buf, "soft_spi_miso");
- gpio_request(CONFIG_SOFT_SPI_GPIO_MISO, buf);
- sprintf(buf, "soft_spi_cs");
- gpio_request(CONFIG_SOFT_SPI_GPIO_CS, buf);
- gpio_direction_output(CONFIG_SOFT_SPI_GPIO_SCLK, CONFIG_SOFT_SPI_MODE & SPI_CPOL); gpio_direction_output(CONFIG_SOFT_SPI_GPIO_MOSI, 1);
@@ -377,6 +392,8 @@ void exynos_enable_ldo(unsigned int onoff)
int exynos_init(void) {
char buf[16];
gd->bd->bi_arch_number = MACH_TYPE_UNIVERSAL_C210;
switch (get_hwrev()) {
@@ -401,6 +418,13 @@ int exynos_init(void) break; }
- /* Request soft I2C gpios */
- sprintf(buf, "soft_i2c_scl");
- gpio_request(CONFIG_SOFT_I2C_GPIO_SCL, buf);
- sprintf(buf, "soft_i2c_sda");
- gpio_request(CONFIG_SOFT_I2C_GPIO_SDA, buf);
- #ifdef CONFIG_SOFT_SPI soft_spi_init(); #endif
Best Regards,
There is no gaps in exynos gpio enum after rework, so the gpio numbers should be adjusted to the new numbering.
Signed-off-by: Przemyslaw Marczak p.marczak@samsung.com --- arch/arm/dts/exynos4210-universal_c210.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/dts/exynos4210-universal_c210.dts b/arch/arm/dts/exynos4210-universal_c210.dts index 9139810..808c3f7 100644 --- a/arch/arm/dts/exynos4210-universal_c210.dts +++ b/arch/arm/dts/exynos4210-universal_c210.dts @@ -24,7 +24,7 @@ sdhci@12510000 { samsung,bus-width = <8>; samsung,timing = <1 3 3>; - pwr-gpios = <&gpio 0xA2 0>; + pwr-gpios = <&gpio 146 0>; };
sdhci@12520000 { @@ -34,7 +34,7 @@ sdhci@12530000 { samsung,bus-width = <4>; samsung,timing = <1 2 3>; - cd-gpios = <&gpio 0x39C 0>; + cd-gpios = <&gpio 284 0>; };
sdhci@12540000 {
On 24 October 2014 09:45, Przemyslaw Marczak p.marczak@samsung.com wrote:
There is no gaps in exynos gpio enum after rework, so the gpio numbers should be adjusted to the new numbering.
Signed-off-by: Przemyslaw Marczak p.marczak@samsung.com
Acked-by: Simon Glass sjg@chromium.org
On 27 October 2014 19:12, Simon Glass sjg@chromium.org wrote:
On 24 October 2014 09:45, Przemyslaw Marczak p.marczak@samsung.com wrote:
There is no gaps in exynos gpio enum after rework, so the gpio numbers should be adjusted to the new numbering.
Signed-off-by: Przemyslaw Marczak p.marczak@samsung.com
Acked-by: Simon Glass sjg@chromium.org
Applied to u-boot-dm, thanks!
There is no gaps in exynos gpio enum after rework, so the gpio numbers should be adjusted to the new numbering.
Signed-off-by: Przemyslaw Marczak p.marczak@samsung.com --- arch/arm/dts/exynos4210-trats.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/dts/exynos4210-trats.dts b/arch/arm/dts/exynos4210-trats.dts index 81188bc..8c7a2c3 100644 --- a/arch/arm/dts/exynos4210-trats.dts +++ b/arch/arm/dts/exynos4210-trats.dts @@ -101,7 +101,7 @@ sdhci@12510000 { samsung,bus-width = <8>; samsung,timing = <1 3 3>; - pwr-gpios = <&gpio 0xA2 0>; + pwr-gpios = <&gpio 146 0>; };
sdhci@12520000 { @@ -111,7 +111,7 @@ sdhci@12530000 { samsung,bus-width = <4>; samsung,timing = <1 2 3>; - cd-gpios = <&gpio 0x39C 0>; + cd-gpios = <&gpio 284 0>; };
sdhci@12540000 {
On 24 October 2014 09:45, Przemyslaw Marczak p.marczak@samsung.com wrote:
There is no gaps in exynos gpio enum after rework, so the gpio numbers should be adjusted to the new numbering.
Signed-off-by: Przemyslaw Marczak p.marczak@samsung.com
Acked-by: Simon Glass sjg@chromium.org
On 27 October 2014 19:12, Simon Glass sjg@chromium.org wrote:
On 24 October 2014 09:45, Przemyslaw Marczak p.marczak@samsung.com wrote:
There is no gaps in exynos gpio enum after rework, so the gpio numbers should be adjusted to the new numbering.
Signed-off-by: Przemyslaw Marczak p.marczak@samsung.com
Acked-by: Simon Glass sjg@chromium.org
Applied to u-boot-dm, thanks!
There is no gaps in exynos gpio enum after rework, so the gpio numbers should be adjusted to the new numbering.
Signed-off-by: Przemyslaw Marczak p.marczak@samsung.com --- arch/arm/dts/exynos4412-trats2.dts | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/dts/exynos4412-trats2.dts b/arch/arm/dts/exynos4412-trats2.dts index 3b1e458..60e4515 100644 --- a/arch/arm/dts/exynos4412-trats2.dts +++ b/arch/arm/dts/exynos4412-trats2.dts @@ -416,7 +416,7 @@ sdhci@12510000 { samsung,bus-width = <8>; samsung,timing = <1 3 3>; - pwr-gpios = <&gpio 0xB2 0>; + pwr-gpios = <&gpio 0x6a 0>; status = "disabled"; };
@@ -427,7 +427,7 @@ sdhci@12530000 { samsung,bus-width = <4>; samsung,timing = <1 2 3>; - cd-gpios = <&gpio 0x3BC 0>; + cd-gpios = <&gpio 0x7a 0>; };
sdhci@12540000 { @@ -437,7 +437,7 @@ dwmmc@12550000 { samsung,bus-width = <8>; samsung,timing = <2 1 0>; - pwr-gpios = <&gpio 0xB2 0>; + pwr-gpios = <&gpio 0x6a 0>; fifoth_val = <0x203f0040>; bus_hz = <400000000>; div = <0x3>;
On 24 October 2014 09:45, Przemyslaw Marczak p.marczak@samsung.com wrote:
There is no gaps in exynos gpio enum after rework, so the gpio numbers should be adjusted to the new numbering.
Signed-off-by: Przemyslaw Marczak p.marczak@samsung.com
Acked-by: Simon Glass sjg@chromium.org
On 27 October 2014 19:12, Simon Glass sjg@chromium.org wrote:
On 24 October 2014 09:45, Przemyslaw Marczak p.marczak@samsung.com wrote:
There is no gaps in exynos gpio enum after rework, so the gpio numbers should be adjusted to the new numbering.
Signed-off-by: Przemyslaw Marczak p.marczak@samsung.com
Acked-by: Simon Glass sjg@chromium.org
Applied to u-boot-dm, thanks!
There is no gaps in exynos gpio enum after rework, so the gpio numbers should be adjusted to the new numbering.
Signed-off-by: Przemyslaw Marczak p.marczak@samsung.com --- arch/arm/dts/exynos4412-odroid.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/dts/exynos4412-odroid.dts b/arch/arm/dts/exynos4412-odroid.dts index 4c5e2b3..aea012c 100644 --- a/arch/arm/dts/exynos4412-odroid.dts +++ b/arch/arm/dts/exynos4412-odroid.dts @@ -51,7 +51,7 @@ sdhci@12530000 { samsung,bus-width = <4>; samsung,timing = <1 2 3>; - cd-gpios = <&gpio 0xC2 0>; + cd-gpios = <&gpio 122 0>; };
sdhci@12540000 {
On 24 October 2014 09:45, Przemyslaw Marczak p.marczak@samsung.com wrote:
There is no gaps in exynos gpio enum after rework, so the gpio numbers should be adjusted to the new numbering.
Signed-off-by: Przemyslaw Marczak p.marczak@samsung.com
Acked-by: Simon Glass sjg@chromium.org
On 27 October 2014 19:12, Simon Glass sjg@chromium.org wrote:
On 24 October 2014 09:45, Przemyslaw Marczak p.marczak@samsung.com wrote:
There is no gaps in exynos gpio enum after rework, so the gpio numbers should be adjusted to the new numbering.
Signed-off-by: Przemyslaw Marczak p.marczak@samsung.com
Acked-by: Simon Glass sjg@chromium.org
Applied to u-boot-dm, thanks!
Odroid is based on Exynos4412.
Signed-off-by: Przemyslaw Marczak p.marczak@samsung.com --- arch/arm/dts/exynos4412-odroid.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/dts/exynos4412-odroid.dts b/arch/arm/dts/exynos4412-odroid.dts index aea012c..2a1f1dd 100644 --- a/arch/arm/dts/exynos4412-odroid.dts +++ b/arch/arm/dts/exynos4412-odroid.dts @@ -8,7 +8,7 @@ */
/dts-v1/; -#include "exynos4.dtsi" +#include "exynos4412.dtsi"
/ { model = "Odroid based on Exynos4412";
On 24 October 2014 09:45, Przemyslaw Marczak p.marczak@samsung.com wrote:
Odroid is based on Exynos4412.
Signed-off-by: Przemyslaw Marczak p.marczak@samsung.com
Acked-by: Simon Glass sjg@chromium.org
On 27 October 2014 19:12, Simon Glass sjg@chromium.org wrote:
On 24 October 2014 09:45, Przemyslaw Marczak p.marczak@samsung.com wrote:
Odroid is based on Exynos4412.
Signed-off-by: Przemyslaw Marczak p.marczak@samsung.com
Acked-by: Simon Glass sjg@chromium.org
Applied to u-boot-dm, thanks!
Setting gpio value before dm gpio init has no effect, so now, odroid gpio settings are moved after the gpio uclass init.
Using non-requested gpio pin cases printing error messages. To avoid this, gpio_request() is added for those gpios.
Signed-off-by: Przemyslaw Marczak p.marczak@samsung.com --- board/samsung/odroid/odroid.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/board/samsung/odroid/odroid.c b/board/samsung/odroid/odroid.c index 5edb250..5ce8e9f 100644 --- a/board/samsung/odroid/odroid.c +++ b/board/samsung/odroid/odroid.c @@ -355,22 +355,36 @@ static void board_clock_init(void)
static void board_gpio_init(void) { + char buf[16]; + /* eMMC Reset Pin */ + sprintf(buf, "eMMC Reset"); + gpio_request(EXYNOS4X12_GPIO_K12, buf); + gpio_cfg_pin(EXYNOS4X12_GPIO_K12, S5P_GPIO_FUNC(0x1)); gpio_set_pull(EXYNOS4X12_GPIO_K12, S5P_GPIO_PULL_NONE); gpio_set_drv(EXYNOS4X12_GPIO_K12, S5P_GPIO_DRV_4X);
/* Enable FAN (Odroid U3) */ + sprintf(buf, "FAN Control"); + gpio_request(EXYNOS4X12_GPIO_D00, buf); + gpio_set_pull(EXYNOS4X12_GPIO_D00, S5P_GPIO_PULL_UP); gpio_set_drv(EXYNOS4X12_GPIO_D00, S5P_GPIO_DRV_4X); gpio_direction_output(EXYNOS4X12_GPIO_D00, 1);
/* OTG Vbus output (Odroid U3+) */ + sprintf(buf, "OTG Vbus"); + gpio_request(EXYNOS4X12_GPIO_L20, buf); + gpio_set_pull(EXYNOS4X12_GPIO_L20, S5P_GPIO_PULL_NONE); gpio_set_drv(EXYNOS4X12_GPIO_L20, S5P_GPIO_DRV_4X); gpio_direction_output(EXYNOS4X12_GPIO_L20, 0);
/* OTG INT (Odroid U3+) */ + sprintf(buf, "OTG INT"); + gpio_request(EXYNOS4X12_GPIO_X31, buf); + gpio_set_pull(EXYNOS4X12_GPIO_X31, S5P_GPIO_PULL_UP); gpio_set_drv(EXYNOS4X12_GPIO_X31, S5P_GPIO_DRV_4X); gpio_direction_input(EXYNOS4X12_GPIO_X31); @@ -403,7 +417,6 @@ static void board_init_i2c(void) int exynos_early_init_f(void) { board_clock_init(); - board_gpio_init();
return 0; } @@ -414,6 +427,8 @@ int exynos_init(void) gd->ram_size -= SZ_1M; gd->bd->bi_dram[CONFIG_NR_DRAM_BANKS - 1].size -= SZ_1M;
+ board_gpio_init(); + return 0; }
Hi,
On 24 October 2014 09:45, Przemyslaw Marczak p.marczak@samsung.com wrote:
Setting gpio value before dm gpio init has no effect, so now, odroid gpio settings are moved after the gpio uclass init.
Using non-requested gpio pin cases printing error messages. To avoid this, gpio_request() is added for those gpios.
Signed-off-by: Przemyslaw Marczak p.marczak@samsung.com
board/samsung/odroid/odroid.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/board/samsung/odroid/odroid.c b/board/samsung/odroid/odroid.c index 5edb250..5ce8e9f 100644 --- a/board/samsung/odroid/odroid.c +++ b/board/samsung/odroid/odroid.c @@ -355,22 +355,36 @@ static void board_clock_init(void)
static void board_gpio_init(void) {
char buf[16];/* eMMC Reset Pin */sprintf(buf, "eMMC Reset");gpio_request(EXYNOS4X12_GPIO_K12, buf);
You can use:
gpio_request(EXYNOS4X12_GPIO_K12, "eMMC Reset");
Same below.
gpio_cfg_pin(EXYNOS4X12_GPIO_K12, S5P_GPIO_FUNC(0x1)); gpio_set_pull(EXYNOS4X12_GPIO_K12, S5P_GPIO_PULL_NONE); gpio_set_drv(EXYNOS4X12_GPIO_K12, S5P_GPIO_DRV_4X); /* Enable FAN (Odroid U3) */sprintf(buf, "FAN Control");gpio_request(EXYNOS4X12_GPIO_D00, buf);gpio_set_pull(EXYNOS4X12_GPIO_D00, S5P_GPIO_PULL_UP); gpio_set_drv(EXYNOS4X12_GPIO_D00, S5P_GPIO_DRV_4X); gpio_direction_output(EXYNOS4X12_GPIO_D00, 1); /* OTG Vbus output (Odroid U3+) */sprintf(buf, "OTG Vbus");gpio_request(EXYNOS4X12_GPIO_L20, buf);gpio_set_pull(EXYNOS4X12_GPIO_L20, S5P_GPIO_PULL_NONE); gpio_set_drv(EXYNOS4X12_GPIO_L20, S5P_GPIO_DRV_4X); gpio_direction_output(EXYNOS4X12_GPIO_L20, 0); /* OTG INT (Odroid U3+) */sprintf(buf, "OTG INT");gpio_request(EXYNOS4X12_GPIO_X31, buf);gpio_set_pull(EXYNOS4X12_GPIO_X31, S5P_GPIO_PULL_UP); gpio_set_drv(EXYNOS4X12_GPIO_X31, S5P_GPIO_DRV_4X); gpio_direction_input(EXYNOS4X12_GPIO_X31);@@ -403,7 +417,6 @@ static void board_init_i2c(void) int exynos_early_init_f(void) { board_clock_init();
board_gpio_init(); return 0;} @@ -414,6 +427,8 @@ int exynos_init(void) gd->ram_size -= SZ_1M; gd->bd->bi_dram[CONFIG_NR_DRAM_BANKS - 1].size -= SZ_1M;
board_gpio_init();return 0;}
-- 1.9.1
Regards, Simon
Hello,
On 10/28/2014 02:13 AM, Simon Glass wrote:
Hi,
On 24 October 2014 09:45, Przemyslaw Marczak p.marczak@samsung.com wrote:
Setting gpio value before dm gpio init has no effect, so now, odroid gpio settings are moved after the gpio uclass init.
Using non-requested gpio pin cases printing error messages. To avoid this, gpio_request() is added for those gpios.
Signed-off-by: Przemyslaw Marczak p.marczak@samsung.com
board/samsung/odroid/odroid.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/board/samsung/odroid/odroid.c b/board/samsung/odroid/odroid.c index 5edb250..5ce8e9f 100644 --- a/board/samsung/odroid/odroid.c +++ b/board/samsung/odroid/odroid.c @@ -355,22 +355,36 @@ static void board_clock_init(void)
static void board_gpio_init(void) {
char buf[16];/* eMMC Reset Pin */sprintf(buf, "eMMC Reset");gpio_request(EXYNOS4X12_GPIO_K12, buf);You can use:
gpio_request(EXYNOS4X12_GPIO_K12, "eMMC Reset");
Same below.
Ops, right! This was to easy:)
gpio_cfg_pin(EXYNOS4X12_GPIO_K12, S5P_GPIO_FUNC(0x1)); gpio_set_pull(EXYNOS4X12_GPIO_K12, S5P_GPIO_PULL_NONE); gpio_set_drv(EXYNOS4X12_GPIO_K12, S5P_GPIO_DRV_4X); /* Enable FAN (Odroid U3) */sprintf(buf, "FAN Control");gpio_request(EXYNOS4X12_GPIO_D00, buf);gpio_set_pull(EXYNOS4X12_GPIO_D00, S5P_GPIO_PULL_UP); gpio_set_drv(EXYNOS4X12_GPIO_D00, S5P_GPIO_DRV_4X); gpio_direction_output(EXYNOS4X12_GPIO_D00, 1); /* OTG Vbus output (Odroid U3+) */sprintf(buf, "OTG Vbus");gpio_request(EXYNOS4X12_GPIO_L20, buf);gpio_set_pull(EXYNOS4X12_GPIO_L20, S5P_GPIO_PULL_NONE); gpio_set_drv(EXYNOS4X12_GPIO_L20, S5P_GPIO_DRV_4X); gpio_direction_output(EXYNOS4X12_GPIO_L20, 0); /* OTG INT (Odroid U3+) */sprintf(buf, "OTG INT");gpio_request(EXYNOS4X12_GPIO_X31, buf);gpio_set_pull(EXYNOS4X12_GPIO_X31, S5P_GPIO_PULL_UP); gpio_set_drv(EXYNOS4X12_GPIO_X31, S5P_GPIO_DRV_4X); gpio_direction_input(EXYNOS4X12_GPIO_X31);@@ -403,7 +417,6 @@ static void board_init_i2c(void) int exynos_early_init_f(void) { board_clock_init();
board_gpio_init(); return 0;}
@@ -414,6 +427,8 @@ int exynos_init(void) gd->ram_size -= SZ_1M; gd->bd->bi_dram[CONFIG_NR_DRAM_BANKS - 1].size -= SZ_1M;
board_gpio_init();return 0;-- 1.9.1
Regards, Simon
Best regards,
Hello,
On 10/24/2014 05:44 PM, Przemyslaw Marczak wrote:
Hello Simon, Tom,
The last driver-model changes was merged too fast and I was not able to test it well on all my boards. It was worked well for the first look, but after deep testing - it required some additional work to do.
So this is a set of fixes required for Exynos4xxx boards. I am not sure what about the Origen.
The patchset was rebased on the top of u-boot-dm/master, which is now: c2ded96 serial: remove uniphier_serial_initialize() call
Tested on:
- Trats (E4210)
- UniversalC210 (E4210)
- Trats2 (E4412)
- Odroid U3 (E4412)
- Odroid X2 (E4412)
Best Regards, Przemyslaw Marczak
Przemyslaw Marczak (14): mmc: s5p: set SD detection pin as input exynos: common: enable generic fs operations exynos4/4x12: cpu: add extra gpio base addresses exynos4/4x12: gpio: use gpio extra base addresses exynos4412: dts: fix bad gpio order in pinctrl exynos4412: dts: adjust pinctrl-uboot to changed gpio order exynos4210: dts: fix gpio offset in pinctrl-uboot universal: request soft i2c gpio universal: dts: adjust gpio numbers to new api trats: dts: adjust gpio numbers to new api trats2: dts: adjust gpio numbers after gpio rework odroid: dts: adjust sd cd-gpios for SD Card odroid: dts: fix name of included dtsi odroid: adjust gpio calls to dm gpio api
arch/arm/dts/exynos4210-pinctrl-uboot.dtsi | 2 +- arch/arm/dts/exynos4210-trats.dts | 4 +- arch/arm/dts/exynos4210-universal_c210.dts | 4 +- arch/arm/dts/exynos4412-odroid.dts | 4 +- arch/arm/dts/exynos4412-trats2.dts | 6 +-- arch/arm/dts/exynos4x12-pinctrl-uboot.dtsi | 5 +-- arch/arm/dts/exynos4x12-pinctrl.dtsi | 54 +++++++++++++-------------- arch/arm/include/asm/arch-exynos/cpu.h | 9 +++++ arch/arm/include/asm/arch-exynos/gpio.h | 59 ++++++++++++++++++++---------- board/samsung/odroid/odroid.c | 17 ++++++++- board/samsung/universal_c210/universal.c | 9 +++++ drivers/mmc/s5p_sdhci.c | 2 +- include/configs/exynos-common.h | 1 + 13 files changed, 113 insertions(+), 63 deletions(-)
The patchset is also available on github:
https://github.com/bobenstein/u-boot.git branch: dm_exynos_gpio_fix
Best regards,
Hi Przemyslaw,
On 24 October 2014 09:44, Przemyslaw Marczak p.marczak@samsung.com wrote:
Hello Simon, Tom,
The last driver-model changes was merged too fast and I was not able to test it well on all my boards. It was worked well for the first look, but after deep testing - it required some additional work to do.
So this is a set of fixes required for Exynos4xxx boards. I am not sure what about the Origen.
The patchset was rebased on the top of u-boot-dm/master, which is now: c2ded96 serial: remove uniphier_serial_initialize() call
Tested on:
- Trats (E4210)
- UniversalC210 (E4210)
- Trats2 (E4412)
- Odroid U3 (E4412)
- Odroid X2 (E4412)
Actually I never did update the device tree numbering so I suspect this series has been incorrect since version 1! Since exynos5 was always sequential I somehow missing thinking about it. This is great, thanks for straightening it all out and testing. Particularly I am pleased about Universal since the soft SPI was a bit of a poke in the dark.
I'll go through this soon. I was also planning to send a patch to clean up some of the gpio_name_num_table stuff since it shouldn't be needed any more.
Regards, Simon
Hi Prezemyslaw,
On 27 October 2014 12:48, Simon Glass sjg@chromium.org wrote:
Hi Przemyslaw,
On 24 October 2014 09:44, Przemyslaw Marczak p.marczak@samsung.com wrote:
Hello Simon, Tom,
The last driver-model changes was merged too fast and I was not able to test it well on all my boards. It was worked well for the first look, but after deep testing - it required some additional work to do.
So this is a set of fixes required for Exynos4xxx boards. I am not sure what about the Origen.
The patchset was rebased on the top of u-boot-dm/master, which is now: c2ded96 serial: remove uniphier_serial_initialize() call
Tested on:
- Trats (E4210)
- UniversalC210 (E4210)
- Trats2 (E4412)
- Odroid U3 (E4412)
- Odroid X2 (E4412)
Actually I never did update the device tree numbering so I suspect this series has been incorrect since version 1! Since exynos5 was always sequential I somehow missing thinking about it. This is great, thanks for straightening it all out and testing. Particularly I am pleased about Universal since the soft SPI was a bit of a poke in the dark.
I'll go through this soon. I was also planning to send a patch to clean up some of the gpio_name_num_table stuff since it shouldn't be needed any more.
I have applied all but 3, 4 and 14 to dm/master. Please take a look at my comments.
Regards, Simon
Hello,
On 10/27/2014 07:48 PM, Simon Glass wrote:
Hi Przemyslaw,
On 24 October 2014 09:44, Przemyslaw Marczak p.marczak@samsung.com wrote:
Hello Simon, Tom,
The last driver-model changes was merged too fast and I was not able to test it well on all my boards. It was worked well for the first look, but after deep testing - it required some additional work to do.
So this is a set of fixes required for Exynos4xxx boards. I am not sure what about the Origen.
The patchset was rebased on the top of u-boot-dm/master, which is now: c2ded96 serial: remove uniphier_serial_initialize() call
Tested on:
- Trats (E4210)
- UniversalC210 (E4210)
- Trats2 (E4412)
- Odroid U3 (E4412)
- Odroid X2 (E4412)
Actually I never did update the device tree numbering so I suspect this series has been incorrect since version 1! Since exynos5 was always sequential I somehow missing thinking about it. This is great, thanks for straightening it all out and testing. Particularly I am pleased about Universal since the soft SPI was a bit of a poke in the dark.
I'll go through this soon. I was also planning to send a patch to clean up some of the gpio_name_num_table stuff since it shouldn't be needed any more.
Regards, Simon
Yes, probably some bugs, was there before the last changes. But the main issue was, that after remove the gaps in gpio enums, the pinmux and the spl(if used) configured some wrong registers. Now this should works. I have some other task now, so the rest of unmerged patches I will resend today evening. Thank you for the review, and I hope that I didn't break any Exynos5 board?
Best regards,
After remove the offsets in Exynos4/4x12 gpio enums, an additional gpio base addresses are required.
Signed-off-by: Przemyslaw Marczak p.marczak@samsung.com --- arch/arm/include/asm/arch-exynos/cpu.h | 9 +++++++++ 1 file changed, 9 insertions(+)
diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h index ba71714..78aceef 100644 --- a/arch/arm/include/asm/arch-exynos/cpu.h +++ b/arch/arm/include/asm/arch-exynos/cpu.h @@ -29,6 +29,8 @@ #define EXYNOS4_MIU_BASE 0x10600000 #define EXYNOS4_ACE_SFR_BASE 0x10830000 #define EXYNOS4_GPIO_PART2_BASE 0x11000000 +#define EXYNOS4_GPIO_PART2_0 0x11000000 /* GPJ0 */ +#define EXYNOS4_GPIO_PART2_1 0x11000c00 /* GPX0 */ #define EXYNOS4_GPIO_PART1_BASE 0x11400000 #define EXYNOS4_FIMD_BASE 0x11C00000 #define EXYNOS4_MIPI_DSIM_BASE 0x11C80000 @@ -70,7 +72,14 @@ #define EXYNOS4X12_GPIO_PART4_BASE 0x106E0000 #define EXYNOS4X12_ACE_SFR_BASE 0x10830000 #define EXYNOS4X12_GPIO_PART2_BASE 0x11000000 +#define EXYNOS4X12_GPIO_PART2_0 0x11000000 +#define EXYNOS4X12_GPIO_PART2_1 0x11000040 /* GPK0 */ +#define EXYNOS4X12_GPIO_PART2_2 0x11000260 /* GPM0 */ +#define EXYNOS4X12_GPIO_PART2_3 0x11000c00 /* GPX0 */ #define EXYNOS4X12_GPIO_PART1_BASE 0x11400000 +#define EXYNOS4X12_GPIO_PART1_0 0x11400000 /* GPA0 */ +#define EXYNOS4X12_GPIO_PART1_1 0x11400180 /* GPF0 */ +#define EXYNOS4X12_GPIO_PART1_2 0x11400240 /* GPJ0 */ #define EXYNOS4X12_FIMD_BASE 0x11C00000 #define EXYNOS4X12_MIPI_DSIM_BASE 0x11C80000 #define EXYNOS4X12_USBOTG_BASE 0x12480000
This patch adds extra gpio part addresses to exynos4 and exynos4x12_gpio_data arrays, which are required since the gpio enum lists are linear
Signed-off-by: Przemyslaw Marczak p.marczak@samsung.com --- arch/arm/include/asm/arch-exynos/gpio.h | 59 ++++++++++++++++++++++----------- 1 file changed, 39 insertions(+), 20 deletions(-)
diff --git a/arch/arm/include/asm/arch-exynos/gpio.h b/arch/arm/include/asm/arch-exynos/gpio.h index ad2ece6..02287de 100644 --- a/arch/arm/include/asm/arch-exynos/gpio.h +++ b/arch/arm/include/asm/arch-exynos/gpio.h @@ -284,7 +284,10 @@ enum exynos4_gpio_pin { EXYNOS4_GPIO_Y65, EXYNOS4_GPIO_Y66, EXYNOS4_GPIO_Y67, - EXYNOS4_GPIO_X00, /* 256 0x100 */ + + /* GPIO_PART2_1 STARTS */ + EXYNOS4_GPIO_MAX_PORT_PART_2_0, /* 256 0x100 */ + EXYNOS4_GPIO_X00 = EXYNOS4_GPIO_MAX_PORT_PART_2_0, EXYNOS4_GPIO_X01, EXYNOS4_GPIO_X02, EXYNOS4_GPIO_X03, @@ -318,8 +321,8 @@ enum exynos4_gpio_pin { EXYNOS4_GPIO_X37,
/* GPIO_PART3_STARTS */ - EXYNOS4_GPIO_MAX_PORT_PART_2, /* 288 0x120 */ - EXYNOS4_GPIO_Z0 = EXYNOS4_GPIO_MAX_PORT_PART_2, + EXYNOS4_GPIO_MAX_PORT_PART_2_1, /* 288 0x120 */ + EXYNOS4_GPIO_Z0 = EXYNOS4_GPIO_MAX_PORT_PART_2_1, EXYNOS4_GPIO_Z1, EXYNOS4_GPIO_Z2, EXYNOS4_GPIO_Z3, @@ -332,7 +335,7 @@ enum exynos4_gpio_pin { };
enum exynos4X12_gpio_pin { - /* GPIO_PART1_STARTS */ + /* EXYNOS4X12_GPIO_PART1_0 starts here */ EXYNOS4X12_GPIO_A00, /* 0 */ EXYNOS4X12_GPIO_A01, EXYNOS4X12_GPIO_A02, @@ -389,7 +392,9 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_D15, EXYNOS4X12_GPIO_D16, EXYNOS4X12_GPIO_D17, - EXYNOS4X12_GPIO_F00, /* 56 0x38 */ + EXYNOS4X12_GPIO_MAX_PORT_PART_1_0, /* 56 0x38 */ + /* EXYNOS4X12_GPIO_PART1_1 starts here */ + EXYNOS4X12_GPIO_F00 = EXYNOS4X12_GPIO_MAX_PORT_PART_1_0, EXYNOS4X12_GPIO_F01, EXYNOS4X12_GPIO_F02, EXYNOS4X12_GPIO_F03, @@ -421,7 +426,9 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_F35, EXYNOS4X12_GPIO_F36, EXYNOS4X12_GPIO_F37, - EXYNOS4X12_GPIO_J00, /* 88 0x58 */ + EXYNOS4X12_GPIO_MAX_PORT_PART_1_1, /* 88 0x58 */ + /* EXYNOS4X12_GPIO_PART1_2 starts here */ + EXYNOS4X12_GPIO_J00 = EXYNOS4X12_GPIO_MAX_PORT_PART_1_1, EXYNOS4X12_GPIO_J01, EXYNOS4X12_GPIO_J02, EXYNOS4X12_GPIO_J03, @@ -438,9 +445,12 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_J16, EXYNOS4X12_GPIO_J17,
- /* GPIO_PART2_STARTS */ - EXYNOS4X12_GPIO_MAX_PORT_PART_1,/* 104 0x66 */ - EXYNOS4X12_GPIO_K00 = EXYNOS4X12_GPIO_MAX_PORT_PART_1, + /** + * EXYNOS4X12_GPIO_PART2_0 is not used + * EXYNOS4X12_GPIO_PART2_1 starts here + */ + EXYNOS4X12_GPIO_MAX_PORT_PART_1_2, /* 104 0x66 */ + EXYNOS4X12_GPIO_K00 = EXYNOS4X12_GPIO_MAX_PORT_PART_1_2, EXYNOS4X12_GPIO_K01, EXYNOS4X12_GPIO_K02, EXYNOS4X12_GPIO_K03, @@ -552,7 +562,9 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_Y65, EXYNOS4X12_GPIO_Y66, EXYNOS4X12_GPIO_Y67, - EXYNOS4X12_GPIO_M00, /* 216 0xd8 */ + EXYNOS4X12_GPIO_MAX_PORT_PART_2_1, /* 216 0xd8 */ + /* EXYNOS4X12_GPIO_PART2_2 starts here */ + EXYNOS4X12_GPIO_M00 = EXYNOS4X12_GPIO_MAX_PORT_PART_2_1, EXYNOS4X12_GPIO_M01, EXYNOS4X12_GPIO_M02, EXYNOS4X12_GPIO_M03, @@ -592,7 +604,9 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_M45, EXYNOS4X12_GPIO_M46, EXYNOS4X12_GPIO_M47, - EXYNOS4X12_GPIO_X00, /* 256 0x100 */ + EXYNOS4X12_GPIO_MAX_PORT_PART_2_2, /* 256 0x100 */ + /* EXYNOS4X12_GPIO_PART2_3 starts here */ + EXYNOS4X12_GPIO_X00 = EXYNOS4X12_GPIO_MAX_PORT_PART_2_2, EXYNOS4X12_GPIO_X01, EXYNOS4X12_GPIO_X02, EXYNOS4X12_GPIO_X03, @@ -625,9 +639,9 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_X36, EXYNOS4X12_GPIO_X37,
- /* GPIO_PART3_STARTS */ - EXYNOS4X12_GPIO_MAX_PORT_PART_2,/* 288 0x120 */ - EXYNOS4X12_GPIO_Z0 = EXYNOS4X12_GPIO_MAX_PORT_PART_2, + /* EXYNOS4X12_GPIO_PART3 starts here */ + EXYNOS4X12_GPIO_MAX_PORT_PART_2_3, /* 288 0x120 */ + EXYNOS4X12_GPIO_Z0 = EXYNOS4X12_GPIO_MAX_PORT_PART_2_3, EXYNOS4X12_GPIO_Z1, EXYNOS4X12_GPIO_Z2, EXYNOS4X12_GPIO_Z3, @@ -636,7 +650,7 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_Z6, EXYNOS4X12_GPIO_Z7,
- /* GPIO_PART4_STARTS */ + /* EXYNOS4X12_GPIO_PART4 starts here */ EXYNOS4X12_GPIO_MAX_PORT_PART_3,/* 296 0x128 */ EXYNOS4X12_GPIO_V00 = EXYNOS4X12_GPIO_MAX_PORT_PART_3, EXYNOS4X12_GPIO_V01, @@ -1339,17 +1353,22 @@ struct gpio_info { unsigned int max_gpio; /* Maximum GPIO in this part */ };
-#define EXYNOS4_GPIO_NUM_PARTS 3 +#define EXYNOS4_GPIO_NUM_PARTS 4 static struct gpio_info exynos4_gpio_data[EXYNOS4_GPIO_NUM_PARTS] = { { EXYNOS4_GPIO_PART1_BASE, EXYNOS4_GPIO_MAX_PORT_PART_1 }, - { EXYNOS4_GPIO_PART2_BASE, EXYNOS4_GPIO_MAX_PORT_PART_2 }, + { EXYNOS4_GPIO_PART2_0, EXYNOS4_GPIO_MAX_PORT_PART_2_0 }, + { EXYNOS4_GPIO_PART2_1, EXYNOS4_GPIO_MAX_PORT_PART_2_1 }, { EXYNOS4_GPIO_PART3_BASE, EXYNOS4_GPIO_MAX_PORT }, };
-#define EXYNOS4X12_GPIO_NUM_PARTS 4 +#define EXYNOS4X12_GPIO_NUM_PARTS 8 static struct gpio_info exynos4x12_gpio_data[EXYNOS4X12_GPIO_NUM_PARTS] = { - { EXYNOS4X12_GPIO_PART1_BASE, EXYNOS4X12_GPIO_MAX_PORT_PART_1 }, - { EXYNOS4X12_GPIO_PART2_BASE, EXYNOS4X12_GPIO_MAX_PORT_PART_2 }, + { EXYNOS4X12_GPIO_PART1_0, EXYNOS4X12_GPIO_MAX_PORT_PART_1_0 }, + { EXYNOS4X12_GPIO_PART1_1, EXYNOS4X12_GPIO_MAX_PORT_PART_1_1 }, + { EXYNOS4X12_GPIO_PART1_2, EXYNOS4X12_GPIO_MAX_PORT_PART_1_2 }, + { EXYNOS4X12_GPIO_PART2_1, EXYNOS4X12_GPIO_MAX_PORT_PART_2_1 }, + { EXYNOS4X12_GPIO_PART2_2, EXYNOS4X12_GPIO_MAX_PORT_PART_2_2 }, + { EXYNOS4X12_GPIO_PART2_3, EXYNOS4X12_GPIO_MAX_PORT_PART_2_3 }, { EXYNOS4X12_GPIO_PART3_BASE, EXYNOS4X12_GPIO_MAX_PORT_PART_3 }, { EXYNOS4X12_GPIO_PART4_BASE, EXYNOS4X12_GPIO_MAX_PORT }, };
On 28 October 2014 10:31, Przemyslaw Marczak p.marczak@samsung.com wrote:
This patch adds extra gpio part addresses to exynos4 and exynos4x12_gpio_data arrays, which are required since the gpio enum lists are linear
Signed-off-by: Przemyslaw Marczak p.marczak@samsung.com
Acked-by: Simon Glass sjg@chromium.org
On 29/10/14 01:31, Przemyslaw Marczak wrote:
This patch adds extra gpio part addresses to exynos4 and exynos4x12_gpio_data arrays, which are required since the gpio enum lists are linear
Signed-off-by: Przemyslaw Marczak p.marczak@samsung.com
arch/arm/include/asm/arch-exynos/gpio.h | 59 ++++++++++++++++++++++----------- 1 file changed, 39 insertions(+), 20 deletions(-)
applied to u-boot-samsung.
Thanks, Minkyu Kang.
Hello Minkyu,
On 10/30/2014 02:54 PM, Minkyu Kang wrote:
On 29/10/14 01:31, Przemyslaw Marczak wrote:
This patch adds extra gpio part addresses to exynos4 and exynos4x12_gpio_data arrays, which are required since the gpio enum lists are linear
Signed-off-by: Przemyslaw Marczak p.marczak@samsung.com
arch/arm/include/asm/arch-exynos/gpio.h | 59 ++++++++++++++++++++++----------- 1 file changed, 39 insertions(+), 20 deletions(-)
applied to u-boot-samsung.
Thanks, Minkyu Kang.
I thought that those patches will go through u-boot-dm, since it was a second version of some not merged V1 patches.
Now, the u-boot-dm/master and u-boot/master are broken for exynos4 because of missing those few patches.
Could you please make a pull request with those patches asap?
Best regards,
On 04/11/14 18:29, Przemyslaw Marczak wrote:
Hello Minkyu,
On 10/30/2014 02:54 PM, Minkyu Kang wrote:
On 29/10/14 01:31, Przemyslaw Marczak wrote:
This patch adds extra gpio part addresses to exynos4 and exynos4x12_gpio_data arrays, which are required since the gpio enum lists are linear
Signed-off-by: Przemyslaw Marczak p.marczak@samsung.com
arch/arm/include/asm/arch-exynos/gpio.h | 59 ++++++++++++++++++++++----------- 1 file changed, 39 insertions(+), 20 deletions(-)
applied to u-boot-samsung.
Thanks, Minkyu Kang.
I thought that those patches will go through u-boot-dm, since it was a second version of some not merged V1 patches.
Now, the u-boot-dm/master and u-boot/master are broken for exynos4 because of missing those few patches.
Could you please make a pull request with those patches asap?
Best regards,
ok.
Thanks, Minkyu Kang.
Setting gpio value before dm gpio init has no effect, so now, odroid gpio settings are moved after the gpio uclass init.
Using non-requested gpio pin cases printing error messages. To avoid this, gpio_request() is added for those gpios.
Signed-off-by: Przemyslaw Marczak p.marczak@samsung.com --- board/samsung/odroid/odroid.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/board/samsung/odroid/odroid.c b/board/samsung/odroid/odroid.c index 5edb250..33003ee 100644 --- a/board/samsung/odroid/odroid.c +++ b/board/samsung/odroid/odroid.c @@ -356,21 +356,29 @@ static void board_clock_init(void) static void board_gpio_init(void) { /* eMMC Reset Pin */ + gpio_request(EXYNOS4X12_GPIO_K12, "eMMC Reset"); + gpio_cfg_pin(EXYNOS4X12_GPIO_K12, S5P_GPIO_FUNC(0x1)); gpio_set_pull(EXYNOS4X12_GPIO_K12, S5P_GPIO_PULL_NONE); gpio_set_drv(EXYNOS4X12_GPIO_K12, S5P_GPIO_DRV_4X);
/* Enable FAN (Odroid U3) */ + gpio_request(EXYNOS4X12_GPIO_D00, "FAN Control"); + gpio_set_pull(EXYNOS4X12_GPIO_D00, S5P_GPIO_PULL_UP); gpio_set_drv(EXYNOS4X12_GPIO_D00, S5P_GPIO_DRV_4X); gpio_direction_output(EXYNOS4X12_GPIO_D00, 1);
/* OTG Vbus output (Odroid U3+) */ + gpio_request(EXYNOS4X12_GPIO_L20, "OTG Vbus"); + gpio_set_pull(EXYNOS4X12_GPIO_L20, S5P_GPIO_PULL_NONE); gpio_set_drv(EXYNOS4X12_GPIO_L20, S5P_GPIO_DRV_4X); gpio_direction_output(EXYNOS4X12_GPIO_L20, 0);
/* OTG INT (Odroid U3+) */ + gpio_request(EXYNOS4X12_GPIO_X31, "OTG INT"); + gpio_set_pull(EXYNOS4X12_GPIO_X31, S5P_GPIO_PULL_UP); gpio_set_drv(EXYNOS4X12_GPIO_X31, S5P_GPIO_DRV_4X); gpio_direction_input(EXYNOS4X12_GPIO_X31); @@ -403,7 +411,6 @@ static void board_init_i2c(void) int exynos_early_init_f(void) { board_clock_init(); - board_gpio_init();
return 0; } @@ -414,6 +421,8 @@ int exynos_init(void) gd->ram_size -= SZ_1M; gd->bd->bi_dram[CONFIG_NR_DRAM_BANKS - 1].size -= SZ_1M;
+ board_gpio_init(); + return 0; }
Hi,
On 28 October 2014 10:31, Przemyslaw Marczak p.marczak@samsung.com wrote:
Setting gpio value before dm gpio init has no effect, so now, odroid gpio settings are moved after the gpio uclass init.
Using non-requested gpio pin cases printing error messages. To avoid this, gpio_request() is added for those gpios.
Signed-off-by: Przemyslaw Marczak p.marczak@samsung.com
board/samsung/odroid/odroid.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/board/samsung/odroid/odroid.c b/board/samsung/odroid/odroid.c index 5edb250..33003ee 100644 --- a/board/samsung/odroid/odroid.c +++ b/board/samsung/odroid/odroid.c @@ -356,21 +356,29 @@ static void board_clock_init(void) static void board_gpio_init(void) { /* eMMC Reset Pin */
gpio_request(EXYNOS4X12_GPIO_K12, "eMMC Reset");
It occurred to me that we should perhaps avoid spaces in the label since Stephen Warren is talking about enhancing the gpio command to handle these labels. But I think we can always address this later if needed.
Acked-by: Simon Glass sjg@chromium.org
gpio_cfg_pin(EXYNOS4X12_GPIO_K12, S5P_GPIO_FUNC(0x1)); gpio_set_pull(EXYNOS4X12_GPIO_K12, S5P_GPIO_PULL_NONE); gpio_set_drv(EXYNOS4X12_GPIO_K12, S5P_GPIO_DRV_4X); /* Enable FAN (Odroid U3) */gpio_request(EXYNOS4X12_GPIO_D00, "FAN Control");gpio_set_pull(EXYNOS4X12_GPIO_D00, S5P_GPIO_PULL_UP); gpio_set_drv(EXYNOS4X12_GPIO_D00, S5P_GPIO_DRV_4X); gpio_direction_output(EXYNOS4X12_GPIO_D00, 1); /* OTG Vbus output (Odroid U3+) */gpio_request(EXYNOS4X12_GPIO_L20, "OTG Vbus");gpio_set_pull(EXYNOS4X12_GPIO_L20, S5P_GPIO_PULL_NONE); gpio_set_drv(EXYNOS4X12_GPIO_L20, S5P_GPIO_DRV_4X); gpio_direction_output(EXYNOS4X12_GPIO_L20, 0); /* OTG INT (Odroid U3+) */gpio_request(EXYNOS4X12_GPIO_X31, "OTG INT");gpio_set_pull(EXYNOS4X12_GPIO_X31, S5P_GPIO_PULL_UP); gpio_set_drv(EXYNOS4X12_GPIO_X31, S5P_GPIO_DRV_4X); gpio_direction_input(EXYNOS4X12_GPIO_X31);@@ -403,7 +411,6 @@ static void board_init_i2c(void) int exynos_early_init_f(void) { board_clock_init();
board_gpio_init(); return 0;} @@ -414,6 +421,8 @@ int exynos_init(void) gd->ram_size -= SZ_1M; gd->bd->bi_dram[CONFIG_NR_DRAM_BANKS - 1].size -= SZ_1M;
board_gpio_init();return 0;}
-- 1.9.1
Regards, Simon
On 29/10/14 01:31, Przemyslaw Marczak wrote:
Setting gpio value before dm gpio init has no effect, so now, odroid gpio settings are moved after the gpio uclass init.
Using non-requested gpio pin cases printing error messages. To avoid this, gpio_request() is added for those gpios.
Signed-off-by: Przemyslaw Marczak p.marczak@samsung.com
board/samsung/odroid/odroid.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-)
applied to u-boot-samsung.
Thanks, Minkyu Kang.
Hello Simon,
On 10/28/2014 05:31 PM, Przemyslaw Marczak wrote:
After remove the offsets in Exynos4/4x12 gpio enums, an additional gpio base addresses are required.
Signed-off-by: Przemyslaw Marczak p.marczak@samsung.com
arch/arm/include/asm/arch-exynos/cpu.h | 9 +++++++++ 1 file changed, 9 insertions(+)
diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h index ba71714..78aceef 100644 --- a/arch/arm/include/asm/arch-exynos/cpu.h +++ b/arch/arm/include/asm/arch-exynos/cpu.h @@ -29,6 +29,8 @@ #define EXYNOS4_MIU_BASE 0x10600000 #define EXYNOS4_ACE_SFR_BASE 0x10830000 #define EXYNOS4_GPIO_PART2_BASE 0x11000000 +#define EXYNOS4_GPIO_PART2_0 0x11000000 /* GPJ0 */ +#define EXYNOS4_GPIO_PART2_1 0x11000c00 /* GPX0 */ #define EXYNOS4_GPIO_PART1_BASE 0x11400000 #define EXYNOS4_FIMD_BASE 0x11C00000 #define EXYNOS4_MIPI_DSIM_BASE 0x11C80000 @@ -70,7 +72,14 @@ #define EXYNOS4X12_GPIO_PART4_BASE 0x106E0000 #define EXYNOS4X12_ACE_SFR_BASE 0x10830000 #define EXYNOS4X12_GPIO_PART2_BASE 0x11000000 +#define EXYNOS4X12_GPIO_PART2_0 0x11000000 +#define EXYNOS4X12_GPIO_PART2_1 0x11000040 /* GPK0 */ +#define EXYNOS4X12_GPIO_PART2_2 0x11000260 /* GPM0 */ +#define EXYNOS4X12_GPIO_PART2_3 0x11000c00 /* GPX0 */ #define EXYNOS4X12_GPIO_PART1_BASE 0x11400000 +#define EXYNOS4X12_GPIO_PART1_0 0x11400000 /* GPA0 */ +#define EXYNOS4X12_GPIO_PART1_1 0x11400180 /* GPF0 */ +#define EXYNOS4X12_GPIO_PART1_2 0x11400240 /* GPJ0 */ #define EXYNOS4X12_FIMD_BASE 0x11C00000 #define EXYNOS4X12_MIPI_DSIM_BASE 0x11C80000 #define EXYNOS4X12_USBOTG_BASE 0x12480000
Please check the fixed patches. I missed the changelog, so: - [PATCH 1/3] exynos4/4x12: cpu: add extra gpio base addresses Commit message cleanup
- [PATCH 2/3] exynos4/4x12: gpio: use gpio extra base addresses Commit message cleanup
- [PATCH 3/3] odroid: adjust gpio calls to dm gpio api Remove the redundant sprintf calls and put the strings directly into the gpio_request() calls.
The gpio parts sub base addresses stays unchanged. I think that breaking the "pretty" names is reasonable here.
Best regards,
On 28 October 2014 10:31, Przemyslaw Marczak p.marczak@samsung.com wrote:
After remove the offsets in Exynos4/4x12 gpio enums, an additional gpio base addresses are required.
Signed-off-by: Przemyslaw Marczak p.marczak@samsung.com
Acked-by: Simon Glass sjg@chromium.org
On 29/10/14 01:31, Przemyslaw Marczak wrote:
After remove the offsets in Exynos4/4x12 gpio enums, an additional gpio base addresses are required.
Signed-off-by: Przemyslaw Marczak p.marczak@samsung.com
arch/arm/include/asm/arch-exynos/cpu.h | 9 +++++++++ 1 file changed, 9 insertions(+)
applied to u-boot-samsung.
Thanks, Minkyu Kang.
participants (4)
-
Jaehoon Chung -
Minkyu Kang -
Przemyslaw Marczak -
Simon Glass