The SPL implementation for SPEAr600 is older than the common SPL infrastructure. This patch now moves the SPEAr600 SPL over to the common SPL code.

Tested on the only SPEAr board that currently uses SPL in mainline U-Boot, the x600.

Signed-off-by: Stefan Roese sr@denx.de Cc: Viresh Kumar viresh.kumar@linaro.org Cc: Vipin Kumar vk.vipin@gmail.com --- arch/arm/cpu/arm926ejs/spear/Makefile | 2 +- arch/arm/cpu/arm926ejs/spear/spear600.c | 23 ++-- arch/arm/cpu/arm926ejs/spear/spl.c | 74 ++++++------ arch/arm/cpu/arm926ejs/spear/spl_boot.c | 181 ---------------------------- arch/arm/cpu/arm926ejs/spear/start.S | 3 +- arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds | 54 +++------ arch/arm/include/asm/arch-spear/spr_defs.h | 2 - include/configs/x600.h | 17 ++- 8 files changed, 85 insertions(+), 271 deletions(-) delete mode 100644 arch/arm/cpu/arm926ejs/spear/spl_boot.c

diff --git a/arch/arm/cpu/arm926ejs/spear/Makefile b/arch/arm/cpu/arm926ejs/spear/Makefile index 3f190bc..7b15d4e 100644 --- a/arch/arm/cpu/arm926ejs/spear/Makefile +++ b/arch/arm/cpu/arm926ejs/spear/Makefile @@ -10,7 +10,7 @@ obj-y := cpu.o \ timer.o

ifdef CONFIG_SPL_BUILD -obj-y += spl.o spl_boot.o +obj-y += spl.o obj-$(CONFIG_SPEAR600) += spear600.o obj-$(CONFIG_DDR_MT47H64M16) += spr600_mt47h64m16_3_333_cl5_psync.o obj-$(CONFIG_DDR_MT47H32M16) += spr600_mt47h32m16_333_cl5_psync.o diff --git a/arch/arm/cpu/arm926ejs/spear/spear600.c b/arch/arm/cpu/arm926ejs/spear/spear600.c index 6474e9d..1fdf715 100644 --- a/arch/arm/cpu/arm926ejs/spear/spear600.c +++ b/arch/arm/cpu/arm926ejs/spear/spear600.c @@ -12,6 +12,21 @@ #include <asm/arch/spr_misc.h> #include <asm/arch/spr_defs.h>

+void spear_late_init(void) +{ + struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE; + + writel(0x80000007, &misc_p->arb_icm_ml1); + writel(0x80000007, &misc_p->arb_icm_ml2); + writel(0x80000007, &misc_p->arb_icm_ml3); + writel(0x80000007, &misc_p->arb_icm_ml4); + writel(0x80000007, &misc_p->arb_icm_ml5); + writel(0x80000007, &misc_p->arb_icm_ml6); + writel(0x80000007, &misc_p->arb_icm_ml7); + writel(0x80000007, &misc_p->arb_icm_ml8); + writel(0x80000007, &misc_p->arb_icm_ml9); +} + static void sel_1v8(void) { struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE; @@ -104,14 +119,6 @@ void plat_ddr_init(void) }

/* - * soc_init: - */ -void soc_init(void) -{ - /* Nothing to be done for SPEAr600 */ -} - -/* * xxx_boot_selected: * * return true if the particular booting option is selected diff --git a/arch/arm/cpu/arm926ejs/spear/spl.c b/arch/arm/cpu/arm926ejs/spear/spl.c index b550404..a60f583 100644 --- a/arch/arm/cpu/arm926ejs/spear/spl.c +++ b/arch/arm/cpu/arm926ejs/spear/spl.c @@ -8,12 +8,14 @@ */

#include <common.h> +#include <spl.h> #include <version.h> #include <asm/io.h> #include <asm/arch/hardware.h> #include <asm/arch/spr_defs.h> #include <asm/arch/spr_misc.h> #include <asm/arch/spr_syscntl.h> +#include <linux/mtd/st_smi.h>

static void ddr_clock_init(void) { @@ -205,55 +207,51 @@ int get_socrev(void) #endif }

-void lowlevel_init(void) +/* + * SNOR (Serial NOR flash) related functions + */ +static void snor_init(void) +{ + struct smi_regs *const smicntl = + (struct smi_regs * const)CONFIG_SYS_SMI_BASE; + + /* Setting the fast mode values. SMI working at 166/4 = 41.5 MHz */ + writel(HOLD1 | FAST_MODE | BANK_EN | DSEL_TIME | PRESCAL4, + &smicntl->smi_cr1); +} + +u32 spl_boot_device(void) +{ + u32 mode; + + /* Currently only SNOR is supported as the only */ + if (snor_boot_selected()) { + /* SNOR-SMI initialization */ + snor_init(); + + mode = BOOT_DEVICE_NOR; + } + + return mode; +} + +void board_init_f(ulong dummy) { struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE; - const char *u_boot_rev = U_BOOT_VERSION;

/* Initialize PLLs */ sys_init();

- /* Initialize UART */ - serial_init(); - - /* Print U-Boot SPL version string */ - serial_puts("\nU-Boot SPL "); - /* Avoid a second "U-Boot" coming from this string */ - u_boot_rev = &u_boot_rev[7]; - serial_puts(u_boot_rev); - serial_puts(" ("); - serial_puts(U_BOOT_DATE); - serial_puts(" - "); - serial_puts(U_BOOT_TIME); - serial_puts(")\n"); - -#if defined(CONFIG_OS_BOOT) - writel(readl(&misc_p->periph1_clken) | PERIPH_UART1, - &misc_p->periph1_clken); -#endif + preloader_console_init(); + arch_cpu_init();

/* Enable IPs (release reset) */ writel(PERIPH_RST_ALL, &misc_p->periph1_rst);

/* Initialize MPMC */ - serial_puts("Configure DDR\n"); + puts("Configure DDR\n"); mpmc_init(); + spear_late_init();

- /* SoC specific initialization */ - soc_init(); -} - -void spear_late_init(void) -{ - struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE; - - writel(0x80000007, &misc_p->arb_icm_ml1); - writel(0x80000007, &misc_p->arb_icm_ml2); - writel(0x80000007, &misc_p->arb_icm_ml3); - writel(0x80000007, &misc_p->arb_icm_ml4); - writel(0x80000007, &misc_p->arb_icm_ml5); - writel(0x80000007, &misc_p->arb_icm_ml6); - writel(0x80000007, &misc_p->arb_icm_ml7); - writel(0x80000007, &misc_p->arb_icm_ml8); - writel(0x80000007, &misc_p->arb_icm_ml9); + board_init_r(NULL, 0); } diff --git a/arch/arm/cpu/arm926ejs/spear/spl_boot.c b/arch/arm/cpu/arm926ejs/spear/spl_boot.c deleted file mode 100644 index c846d75..0000000 --- a/arch/arm/cpu/arm926ejs/spear/spl_boot.c +++ /dev/null @@ -1,181 +0,0 @@ -/* - * (C) Copyright 2000-2009 - * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com - * - * Copyright (C) 2012 Stefan Roese sr@denx.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <image.h> -#include <linux/compiler.h> -#include <asm/io.h> -#include <asm/arch/spr_defs.h> -#include <linux/mtd/st_smi.h> - -static const char kernel_name[] = "Linux"; -static const char loader_name[] = "U-Boot"; - -int image_check_header(image_header_t *hdr, const char *name) -{ - if (image_check_magic(hdr) && - (!strncmp(image_get_name(hdr), name, strlen(name))) && - image_check_hcrc(hdr)) { - return 1; - } - return 0; -} - -int image_check_data(image_header_t *hdr) -{ - if (image_check_dcrc(hdr)) - return 1; - - return 0; -} - -/* - * SNOR (Serial NOR flash) related functions - */ -void snor_init(void) -{ - struct smi_regs *const smicntl = - (struct smi_regs * const)CONFIG_SYS_SMI_BASE; - - /* Setting the fast mode values. SMI working at 166/4 = 41.5 MHz */ - writel(HOLD1 | FAST_MODE | BANK_EN | DSEL_TIME | PRESCAL4, - &smicntl->smi_cr1); -} - -static int snor_image_load(u8 *load_addr, void (**image_p)(void), - const char *image_name) -{ - image_header_t *header; - - /* - * Since calculating the crc in the SNOR flash does not - * work, we copy the image to the destination address - * minus the header size. And point the header to this - * new destination. This will not work for address 0 - * of course. - */ - header = (image_header_t *)load_addr; - memcpy((ulong *)(image_get_load(header) - sizeof(image_header_t)), - (const ulong *)load_addr, - image_get_data_size(header) + sizeof(image_header_t)); - header = (image_header_t *)(image_get_load(header) - - sizeof(image_header_t)); - - if (image_check_header(header, image_name)) { - if (image_check_data(header)) { - /* Jump to boot image */ - *image_p = (void *)image_get_load(header); - return 1; - } - } - - return 0; -} - -static void boot_image(void (*image)(void)) -{ - void (*funcp)(void) __noreturn = (void *)image; - - (*funcp)(); -} - -/* - * spl_boot: - * - * All supported booting types of all supported SoCs are listed here. - * Generic readback APIs are provided for each supported booting type - * eg. nand_read_skip_bad - */ -u32 spl_boot(void) -{ - void (*image)(void); - -#ifdef CONFIG_SPEAR_USBTTY - plat_late_init(); - return 1; -#endif - - /* - * All the supported booting devices are listed here. Each of - * the booting type supported by the platform would define the - * macro xxx_BOOT_SUPPORTED to true. - */ - - if (SNOR_BOOT_SUPPORTED && snor_boot_selected()) { - /* SNOR-SMI initialization */ - snor_init(); - - serial_puts("Booting via SNOR\n"); - /* Serial NOR booting */ - if (1 == snor_image_load((u8 *)CONFIG_SYS_UBOOT_BASE, - &image, loader_name)) { - /* Platform related late initialasations */ - plat_late_init(); - - /* Jump to boot image */ - serial_puts("Jumping to U-Boot\n"); - boot_image(image); - return 1; - } - } - - if (NAND_BOOT_SUPPORTED && nand_boot_selected()) { - /* NAND booting */ - /* Not ported from XLoader to SPL yet */ - return 0; - } - - if (PNOR_BOOT_SUPPORTED && pnor_boot_selected()) { - /* PNOR booting */ - /* Not ported from XLoader to SPL yet */ - return 0; - } - - if (MMC_BOOT_SUPPORTED && mmc_boot_selected()) { - /* MMC booting */ - /* Not ported from XLoader to SPL yet */ - return 0; - } - - if (SPI_BOOT_SUPPORTED && spi_boot_selected()) { - /* SPI booting */ - /* Not supported for any platform as of now */ - return 0; - } - - if (I2C_BOOT_SUPPORTED && i2c_boot_selected()) { - /* I2C booting */ - /* Not supported for any platform as of now */ - return 0; - } - - /* - * All booting types without memory are listed as below - * Control has to be returned to BootROM in case of all - * the following booting scenarios - */ - - if (USB_BOOT_SUPPORTED && usb_boot_selected()) { - plat_late_init(); - return 1; - } - - if (TFTP_BOOT_SUPPORTED && tftp_boot_selected()) { - plat_late_init(); - return 1; - } - - if (UART_BOOT_SUPPORTED && uart_boot_selected()) { - plat_late_init(); - return 1; - } - - /* Ideally, the control should not reach here. */ - hang(); -} diff --git a/arch/arm/cpu/arm926ejs/spear/start.S b/arch/arm/cpu/arm926ejs/spear/start.S index 290ac2e..f392e7b 100644 --- a/arch/arm/cpu/arm926ejs/spear/start.S +++ b/arch/arm/cpu/arm926ejs/spear/start.S @@ -45,7 +45,6 @@ reset: * BSS area lies in the DDR location which is not yet initialized * bss is assumed to be uninitialized. */ - bl spl_boot ldmia sp!, {r0-r12,pc}

/* @@ -77,5 +76,5 @@ cpu_init_crit: * Go setup Memory and board specific bits prior to relocation. */ stmdb sp!, {lr} - bl lowlevel_init /* go setup pll,mux,memory */ + bl _main /* _main will call board_init_f */ ldmia sp!, {pc} diff --git a/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds b/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds index c7ee199..47910d3 100644 --- a/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds +++ b/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds @@ -1,4 +1,6 @@ /* + * Copyright (C) 2015 Stefan Roese sr@denx.de + * * Copyright (C) 2011 Marek Vasut marek.vasut@gmail.com * on behalf of DENX Software Engineering GmbH * @@ -11,59 +13,43 @@ * SPDX-License-Identifier: GPL-2.0+ */

+MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\ + LENGTH = CONFIG_SPL_MAX_SIZE } + OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") OUTPUT_ARCH(arm) ENTRY(_start) SECTIONS { - . = 0x00000000; - - . = ALIGN(4); - .text : + .text : { + __start = .; *(.vectors) - arch/arm/cpu/arm926ejs/spear/start.o (.text*) + CPUDIR/spear/start.o (.text*) *(.text*) - } + } > .sram

. = ALIGN(4); - .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram

. = ALIGN(4); - .data : { - *(.data*) - } + .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram

. = ALIGN(4); + .u_boot_list : { + KEEP(*(SORT(.u_boot_list*))); + } > .sram

- .rel.dyn : { - __rel_dyn_start = .; - *(.rel*) - __rel_dyn_end = .; - } + . = ALIGN(4); + __image_copy_end = .; + _end = .;

- .bss : { + .bss : + { . = ALIGN(4); __bss_start = .; *(.bss*) . = ALIGN(4); __bss_end = .; - } - - .end : - { - *(.__end) - } - - _image_binary_end = .; - - .dynsym _image_binary_end : { *(.dynsym) } - .dynbss : { *(.dynbss) } - .dynstr : { *(.dynstr*) } - .dynamic : { *(.dynamic*) } - .hash : { *(.hash*) } - .plt : { *(.plt*) } - .interp : { *(.interp*) } - .gnu : { *(.gnu*) } - .ARM.exidx : { *(.ARM.exidx*) } + } > .sram } diff --git a/arch/arm/include/asm/arch-spear/spr_defs.h b/arch/arm/include/asm/arch-spear/spr_defs.h index 7e77a30..bece2d6 100644 --- a/arch/arm/include/asm/arch-spear/spr_defs.h +++ b/arch/arm/include/asm/arch-spear/spr_defs.h @@ -13,9 +13,7 @@ extern void setfreq(unsigned int, unsigned int); extern unsigned int setfreq_sz;

void plat_ddr_init(void); -void soc_init(void); void spear_late_init(void); -void plat_late_init(void);

int snor_boot_selected(void); int nand_boot_selected(void); diff --git a/include/configs/x600.h b/include/configs/x600.h index edb16b1..70e633c 100644 --- a/include/configs/x600.h +++ b/include/configs/x600.h @@ -2,7 +2,7 @@ * (C) Copyright 2009 * Vipin Kumar, STMicroelectronics, vipin.kumar@st.com * - * Copyright (C) 2012 Stefan Roese sr@denx.de + * Copyright (C) 2012, 2015 Stefan Roese sr@denx.de * * SPDX-License-Identifier: GPL-2.0+ */ @@ -162,7 +162,8 @@

/* Use last 2 lwords in internal SRAM for bootcounter */ #define CONFIG_BOOTCOUNT_LIMIT -#define CONFIG_SYS_BOOTCOUNT_ADDR 0xd2801ff8 +#define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SRAM_BASE + \ + CONFIG_SRAM_SIZE)

#define CONFIG_HOSTNAME x600 #define CONFIG_UBI_PART ubi0 @@ -248,8 +249,11 @@ #define PHYS_SDRAM_1_MAXSIZE 0x40000000

#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_ADDR 0xD2800000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 +#define CONFIG_SRAM_BASE 0xd2800000 +/* Preserve the last 2 lwords for the boot-counter */ +#define CONFIG_SRAM_SIZE ((8 << 10) - 0x8) +#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SRAM_BASE +#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SRAM_SIZE

#define CONFIG_SYS_INIT_SP_OFFSET \ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) @@ -260,10 +264,13 @@ /* * SPL related defines */ -#define CONFIG_SPL_TEXT_BASE 0xd2800b00 +#define CONFIG_SPL_TEXT_BASE 0xd2800b00 +#define CONFIG_SPL_MAX_SIZE (CONFIG_SRAM_SIZE - 0xb00) #define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/spear" #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds"

+#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_NOR_SUPPORT #define CONFIG_SPL_SERIAL_SUPPORT #define CONFIG_SPL_LIBCOMMON_SUPPORT /* image.c */ #define CONFIG_SPL_LIBGENERIC_SUPPORT /* string.c */

USB EHCI on SPEAr600 has not been tested for a while. The base controller addresses are missing. This patch adds the defines to the header. And adds the missing code.

Signed-off-by: Stefan Roese sr@denx.de Cc: Viresh Kumar viresh.kumar@linaro.org Cc: Vipin Kumar vk.vipin@gmail.com Cc: Marek Vasut marex@denx.de --- arch/arm/cpu/arm926ejs/spear/cpu.c | 4 ++++ arch/arm/include/asm/arch-spear/hardware.h | 2 ++ drivers/usb/host/ehci-spear.c | 38 +++++++++++++++++++++++++++--- 3 files changed, 41 insertions(+), 3 deletions(-)

diff --git a/arch/arm/cpu/arm926ejs/spear/cpu.c b/arch/arm/cpu/arm926ejs/spear/cpu.c index 1ce9db7..3037084 100644 --- a/arch/arm/cpu/arm926ejs/spear/cpu.c +++ b/arch/arm/cpu/arm926ejs/spear/cpu.c @@ -47,8 +47,12 @@ int arch_cpu_init(void) #if defined(CONFIG_NAND_FSMC) periph1_clken |= MISC_FSMCENB; #endif +#if defined(CONFIG_USB_EHCI_SPEAR) + periph1_clken |= PERIPH_USBH1 | PERIPH_USBH2; +#endif

writel(periph1_clken, &misc_p->periph1_clken); + return 0; }

diff --git a/arch/arm/include/asm/arch-spear/hardware.h b/arch/arm/include/asm/arch-spear/hardware.h index c6da405..065360a 100644 --- a/arch/arm/include/asm/arch-spear/hardware.h +++ b/arch/arm/include/asm/arch-spear/hardware.h @@ -11,6 +11,8 @@ #define CONFIG_SYS_USBD_BASE 0xE1100000 #define CONFIG_SYS_PLUG_BASE 0xE1200000 #define CONFIG_SYS_FIFO_BASE 0xE1000800 +#define CONFIG_SYS_UHC0_EHCI_BASE 0xE1800000 +#define CONFIG_SYS_UHC1_EHCI_BASE 0xE2000000 #define CONFIG_SYS_SMI_BASE 0xFC000000 #define CONFIG_SPEAR_SYSCNTLBASE 0xFCA00000 #define CONFIG_SPEAR_TIMERBASE 0xFC800000 diff --git a/drivers/usb/host/ehci-spear.c b/drivers/usb/host/ehci-spear.c index 210ee9e..9e90e18 100644 --- a/drivers/usb/host/ehci-spear.c +++ b/drivers/usb/host/ehci-spear.c @@ -14,7 +14,21 @@ #include <usb.h> #include "ehci.h" #include <asm/arch/hardware.h> +#include <asm/arch/spr_misc.h>

+static void spear6xx_usbh_stop(void) +{ + struct misc_regs *const misc_p = + (struct misc_regs *)CONFIG_SPEAR_MISCBASE; + u32 periph1_rst = readl(misc_p->periph1_rst); + + periph1_rst |= PERIPH_USBH1 | PERIPH_USBH2; + writel(periph1_rst, misc_p->periph1_rst); + + udelay(1000); + periph1_rst &= ~(PERIPH_USBH1 | PERIPH_USBH2); + writel(periph1_rst, misc_p->periph1_rst); +}

/* * Create the appropriate control structures to manage @@ -23,9 +37,23 @@ int ehci_hcd_init(int index, enum usb_init_type init, struct ehci_hccr **hccr, struct ehci_hcor **hcor) { - *hccr = (struct ehci_hccr *)(CONFIG_SYS_UHC0_EHCI_BASE + 0x100); - *hcor = (struct ehci_hcor *)((uint32_t)*hccr - + HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); + u32 ehci = 0; + + switch (index) { + case 0: + ehci = CONFIG_SYS_UHC0_EHCI_BASE; + break; + case 1: + ehci = CONFIG_SYS_UHC1_EHCI_BASE; + break; + default: + printf("ERROR: wrong controller index!\n"); + break; + }; + + *hccr = (struct ehci_hccr *)(ehci + 0x100); + *hcor = (struct ehci_hcor *)((uint32_t) *hccr + + HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));

debug("SPEAr-ehci: init hccr %x and hcor %x hc_length %d\n", (uint32_t)*hccr, (uint32_t)*hcor, @@ -40,5 +68,9 @@ int ehci_hcd_init(int index, enum usb_init_type init, */ int ehci_hcd_stop(int index) { +#if defined(CONFIG_SPEAR600) + spear6xx_usbh_stop(); +#endif + return 0; }

The designware ethernet driver supports d-cache now. So there is nothing stopping us now to enable the caches completely on SPEAr.

Tested on SPEAr600 x600 board.

Signed-off-by: Stefan Roese sr@denx.de Cc: Viresh Kumar viresh.kumar@linaro.org Cc: Vipin Kumar vk.vipin@gmail.com --- arch/arm/cpu/arm926ejs/spear/cpu.c | 10 ++++++++++ 1 file changed, 10 insertions(+)

diff --git a/arch/arm/cpu/arm926ejs/spear/cpu.c b/arch/arm/cpu/arm926ejs/spear/cpu.c index 3037084..e39cdba 100644 --- a/arch/arm/cpu/arm926ejs/spear/cpu.c +++ b/arch/arm/cpu/arm926ejs/spear/cpu.c @@ -56,6 +56,16 @@ int arch_cpu_init(void) return 0; }

+void enable_caches(void) +{ +#ifndef CONFIG_SYS_ICACHE_OFF + icache_enable(); +#endif +#ifndef CONFIG_SYS_DCACHE_OFF + dcache_enable(); +#endif +} + #ifdef CONFIG_DISPLAY_CPUINFO int print_cpuinfo(void) {

This patch brings the following changes to the x600 board support:

- Add USB EHCI support - Add VFAT support for USB key file access - Increase malloc size (for UBI / UBIFS usage) - Enable Thumb mode to save some image space - Remove unreferenced CONFIG_STACKSIZE - Remove unreferenced CONFIG_SPL_NO_PRINTF

Signed-off-by: Stefan Roese sr@denx.de Cc: Viresh Kumar viresh.kumar@linaro.org Cc: Vipin Kumar vk.vipin@gmail.com --- include/configs/x600.h | 21 ++++++++++++++++----- 1 file changed, 16 insertions(+), 5 deletions(-)

diff --git a/include/configs/x600.h b/include/configs/x600.h index 70e633c..6a57388 100644 --- a/include/configs/x600.h +++ b/include/configs/x600.h @@ -30,6 +30,7 @@ #define CONFIG_SYS_SPL_LEN CONFIG_SPL_PAD_TO #define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_FLASH_BASE + \ CONFIG_SYS_SPL_LEN) +#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_MONITOR_LEN 0x60000

@@ -98,6 +99,12 @@ #define CONFIG_FPGA_SPARTAN3 #define CONFIG_FPGA_COUNT 1

+/* USB EHCI options */ +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_SPEAR +#define CONFIG_USB_STORAGE +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 + /* * Command support defines */ @@ -105,7 +112,9 @@ #define CONFIG_CMD_DATE #define CONFIG_CMD_DHCP #define CONFIG_CMD_ENV +#define CONFIG_CMD_FAT #define CONFIG_CMD_FPGA_LOADMK +#define CONFIG_CMD_FS_GENERIC #define CONFIG_CMD_GPIO #define CONFIG_CMD_I2C #define CONFIG_CMD_MII @@ -115,8 +124,13 @@ #define CONFIG_CMD_SAVES #define CONFIG_CMD_UBI #define CONFIG_CMD_UBIFS +#define CONFIG_CMD_USB #define CONFIG_LZO

+/* Filesystem support (for USB key) */ +#define CONFIG_SUPPORT_VFAT +#define CONFIG_DOS_PARTITION + #define CONFIG_BOOTDELAY 3

#define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */ @@ -148,10 +162,11 @@

#define CONFIG_SYS_MEMTEST_START 0x00800000 #define CONFIG_SYS_MEMTEST_END 0x04000000 -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) +#define CONFIG_SYS_MALLOC_LEN (8 << 20) #define CONFIG_IDENT_STRING "-SPEAr" #define CONFIG_SYS_LONGHELP #define CONFIG_CMDLINE_EDITING +#define CONFIG_AUTO_COMPLETE #define CONFIG_SYS_CBSIZE 256 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ sizeof(CONFIG_SYS_PROMPT) + 16) @@ -240,9 +255,6 @@ "bootcmd=run nand_ubifs\0" \ "\0"

-/* Stack sizes */ -#define CONFIG_STACKSIZE (512 * 1024) - /* Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM_1 0x00000000 @@ -274,7 +286,6 @@ #define CONFIG_SPL_SERIAL_SUPPORT #define CONFIG_SPL_LIBCOMMON_SUPPORT /* image.c */ #define CONFIG_SPL_LIBGENERIC_SUPPORT /* string.c */ -#define CONFIG_SPL_NO_PRINTF

/* * Please select/define only one of the following

On 18-08-15, 09:27, Stefan Roese wrote:

Booting SPEAr600 eval board doesn't work with current mainline U-Boot. With this patch the low-vector bit is left to '0'. Resulting in the common relocation of the vectors to 0 (SDRAM) to work correctly.

Tested on the SPEAr600 EVB.

Signed-off-by: Stefan Roese sr@denx.de Cc: Viresh Kumar viresh.kumar@linaro.org Cc: Vipin Kumar vk.vipin@gmail.com

---

board/spear/common/spr_lowlevel_init.S | 5 ----- 1 file changed, 5 deletions(-)

diff --git a/board/spear/common/spr_lowlevel_init.S b/board/spear/common/spr_lowlevel_init.S index 23a0369..6494883 100644 --- a/board/spear/common/spr_lowlevel_init.S +++ b/board/spear/common/spr_lowlevel_init.S @@ -14,11 +14,6 @@ */ .globl lowlevel_init lowlevel_init:

• /* By default, U-Boot switches CPU to low-vector */
• /* Revert this as we work in high vector even in U-Boot */
• mrc p15, 0, r0, c1, c0, 0
• orr r0, r0, #0x00002000
• mcr p15, 0, r0, c1, c0, 0 mov pc, lr

/* void setfreq(unsigned int device, unsigned int frequency) */

For the complete series:

Acked-by: Viresh Kumar viresh.kumar@linaro.org