From: Chin Liang See chin.liang.see@intel.com

Add the base address map for Statix10 SoC

Signed-off-by: Chin Liang See chin.liang.see@intel.com --- arch/arm/mach-socfpga/include/mach/base_addr_s10.h | 58 ++++++++++++++++++++++ 1 file changed, 58 insertions(+) create mode 100644 arch/arm/mach-socfpga/include/mach/base_addr_s10.h

diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_s10.h b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h new file mode 100644 index 0000000..feb1881 --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h @@ -0,0 +1,58 @@ +/* + * Copyright (C) 2016-2017 Intel Corporation <www.intel.com> + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _SOCFPGA_S10_BASE_HARDWARE_H_ +#define _SOCFPGA_S10_BASE_HARDWARE_H_ + +#define SOCFPGA_SDR_SCHEDULER_ADDRESS 0xf8000400 +#define SOCFPGA_HMC_MMR_IO48_ADDRESS 0xf8010000 +#define SOCFPGA_SDR_ADDRESS 0xf8011000 +#define SOCFPGA_SMMU_ADDRESS 0xfa000000 +#define SOCFPGA_EMAC0_ADDRESS 0xff800000 +#define SOCFPGA_EMAC1_ADDRESS 0xff802000 +#define SOCFPGA_EMAC2_ADDRESS 0xff804000 +#define SOCFPGA_SDMMC_ADDRESS 0xff808000 +#define SOCFPGA_QSPIREGS_ADDRESS 0xff8d2000 +#define SOCFPGA_QSPIDATA_ADDRESS 0xff900000 +#define SOCFPGA_MAILBOX_ADDRESS 0xffA30000 +#define SOCFPGA_USB0_ADDRESS 0xffb00000 +#define SOCFPGA_USB1_ADDRESS 0xffb40000 +#define SOCFPGA_NANDREGS_ADDRESS 0xffb80000 +#define SOCFPGA_NANDDATA_ADDRESS 0xffb90000 +#define SOCFPGA_UART0_ADDRESS 0xffc02000 +#define SOCFPGA_UART1_ADDRESS 0xffc02100 +#define SOCFPGA_I2C0_ADDRESS 0xffc02800 +#define SOCFPGA_I2C1_ADDRESS 0xffc02900 +#define SOCFPGA_I2C2_ADDRESS 0xffc02a00 +#define SOCFPGA_I2C3_ADDRESS 0xffc02b00 +#define SOCFPGA_I2C4_ADDRESS 0xffc02c00 +#define SOCFPGA_SPTIMER0_ADDRESS 0xffc03000 +#define SOCFPGA_SPTIMER1_ADDRESS 0xffc03100 +#define SOCFPGA_GPIO0_ADDRESS 0xffc03200 +#define SOCFPGA_GPIO1_ADDRESS 0xffc03300 +#define SOCFPGA_SYSTIMER0_ADDRESS 0xffd00000 +#define SOCFPGA_SYSTIMER1_ADDRESS 0xffd00100 +#define SOCFPGA_L4WD0_ADDRESS 0xffd00200 +#define SOCFPGA_L4WD1_ADDRESS 0xffd00300 +#define SOCFPGA_L4WD2_ADDRESS 0xffd00400 +#define SOCFPGA_L4WD3_ADDRESS 0xffd00500 +#define SOCFPGA_GTIMER_SEC_ADDRESS 0xffd01000 +#define SOCFPGA_GTIMER_NSEC_ADDRESS 0xffd02000 +#define SOCFPGA_CLKMGR_ADDRESS 0xffd10000 +#define SOCFPGA_RSTMGR_ADDRESS 0xffd11000 +#define SOCFPGA_SYSMGR_ADDRESS 0xffd12000 +#define SOCFPGA_PINMUX_DEDICATED_IO_ADDRESS 0xffd13000 +#define SOCFPGA_DMANONSECURE_ADDRESS 0xffda0000 +#define SOCFPGA_DMASECURE_ADDRESS 0xffda1000 +#define SOCFPGA_SPIS0_ADDRESS 0xffda2000 +#define SOCFPGA_SPIS1_ADDRESS 0xffda3000 +#define SOCFPGA_SPIM0_ADDRESS 0xffda4000 +#define SOCFPGA_SPIM1_ADDRESS 0xffda5000 +#define SOCFPGA_OCRAM_ADDRESS 0xffe00000 +#define GICD_BASE 0xfffc1000 +#define GICC_BASE 0xfffc2000 + +#endif /* _SOCFPGA_S10_BASE_HARDWARE_H_ */

From: Chin Liang See chin.liang.see@intel.com

Add Clock Manager driver support for Stratix SoC

Signed-off-by: Chin Liang See chin.liang.see@intel.com --- arch/arm/mach-socfpga/Makefile | 4 + arch/arm/mach-socfpga/clock_manager.c | 4 +- arch/arm/mach-socfpga/clock_manager_s10.c | 359 +++++++++++++++++++++ arch/arm/mach-socfpga/include/mach/clock_manager.h | 2 + .../mach-socfpga/include/mach/clock_manager_s10.h | 202 ++++++++++++ arch/arm/mach-socfpga/include/mach/handoff_s10.h | 29 ++ arch/arm/mach-socfpga/wrap_pll_config_s10.c | 46 +++ 7 files changed, 644 insertions(+), 2 deletions(-) create mode 100644 arch/arm/mach-socfpga/clock_manager_s10.c create mode 100644 arch/arm/mach-socfpga/include/mach/clock_manager_s10.h create mode 100644 arch/arm/mach-socfpga/include/mach/handoff_s10.h create mode 100644 arch/arm/mach-socfpga/wrap_pll_config_s10.c

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index 286bfef..e5f9dd7 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -30,6 +30,10 @@ obj-y += pinmux_arria10.o obj-y += reset_manager_arria10.o endif

+ifdef CONFIG_TARGET_SOCFPGA_STRATIX10 +obj-y += clock_manager_s10.o +obj-y += wrap_pll_config_s10.o +endif ifdef CONFIG_SPL_BUILD obj-y += spl.o ifdef CONFIG_TARGET_SOCFPGA_GEN5 diff --git a/arch/arm/mach-socfpga/clock_manager.c b/arch/arm/mach-socfpga/clock_manager.c index cb6ae03..f9450a4 100644 --- a/arch/arm/mach-socfpga/clock_manager.c +++ b/arch/arm/mach-socfpga/clock_manager.c @@ -21,7 +21,7 @@ void cm_wait_for_lock(u32 mask) do { #if defined(CONFIG_TARGET_SOCFPGA_GEN5) inter_val = readl(&clock_manager_base->inter) & mask; -#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) +#else inter_val = readl(&clock_manager_base->stat) & mask; #endif /* Wait for stable lock */ @@ -52,7 +52,7 @@ int set_cpu_clk_info(void)

#if defined(CONFIG_TARGET_SOCFPGA_GEN5) gd->bd->bi_ddr_freq = cm_get_sdram_clk_hz() / 1000000; -#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) +#else gd->bd->bi_ddr_freq = 0; #endif

diff --git a/arch/arm/mach-socfpga/clock_manager_s10.c b/arch/arm/mach-socfpga/clock_manager_s10.c new file mode 100644 index 0000000..a9f9b07 --- /dev/null +++ b/arch/arm/mach-socfpga/clock_manager_s10.c @@ -0,0 +1,359 @@ +/* + * Copyright (C) 2016-2017 Intel Corporation <www.intel.com> + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/clock_manager.h> +#include <asm/arch/handoff_s10.h> + +DECLARE_GLOBAL_DATA_PTR; + +static const struct socfpga_clock_manager *clock_manager_base = + (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS; + +/* + * function to write the bypass register which requires a poll of the + * busy bit + */ +static void cm_write_bypass_mainpll(uint32_t val) +{ + writel(val, &clock_manager_base->main_pll.bypass); + cm_wait_for_fsm(); +} +static void cm_write_bypass_perpll(uint32_t val) +{ + writel(val, &clock_manager_base->per_pll.bypass); + cm_wait_for_fsm(); +} + +/* function to write the ctrl register which requires a poll of the busy bit */ +static void cm_write_ctrl(uint32_t val) +{ + writel(val, &clock_manager_base->ctrl); + cm_wait_for_fsm(); +} + +/* + * Setup clocks while making no assumptions about previous state of the clocks. + * + */ +void cm_basic_init(const struct cm_config * const cfg) +{ + uint32_t mdiv, refclkdiv, mscnt, hscnt, vcocalib; + + if (cfg == 0) + return; + + /* Put all plls in bypass */ + cm_write_bypass_mainpll(CLKMGR_BYPASS_MAINPLL_ALL); + cm_write_bypass_perpll(CLKMGR_BYPASS_PERPLL_ALL); + + /* setup main PLL dividers */ + /* calculate the vcocalib value */ + mdiv = (cfg->main_pll_fdbck >> CLKMGR_FDBCK_MDIV_OFFSET) & + CLKMGR_FDBCK_MDIV_MASK; + refclkdiv = (cfg->main_pll_pllglob >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) & + CLKMGR_PLLGLOB_REFCLKDIV_MASK; + mscnt = 200 / (6 + mdiv) / refclkdiv; + hscnt = (mdiv + 6) * mscnt / refclkdiv - 9; + vcocalib = (hscnt & CLKMGR_VCOCALIB_HSCNT_MASK) | + ((mscnt & CLKMGR_VCOCALIB_MSCNT_MASK) << + CLKMGR_VCOCALIB_MSCNT_OFFSET); + + writel((cfg->main_pll_pllglob & ~CLKMGR_PLLGLOB_PD_MASK & + ~CLKMGR_PLLGLOB_RST_MASK), + &clock_manager_base->main_pll.pllglob); + writel(cfg->main_pll_fdbck, &clock_manager_base->main_pll.fdbck); + writel(vcocalib, &clock_manager_base->main_pll.vcocalib); + writel(cfg->main_pll_pllc0, &clock_manager_base->main_pll.pllc0); + writel(cfg->main_pll_pllc1, &clock_manager_base->main_pll.pllc1); + writel(cfg->main_pll_nocdiv, &clock_manager_base->main_pll.nocdiv); + + /* setup peripheral PLL dividers */ + /* calculate the vcocalib value */ + mdiv = (cfg->per_pll_fdbck >> CLKMGR_FDBCK_MDIV_OFFSET) & + CLKMGR_FDBCK_MDIV_MASK; + refclkdiv = (cfg->per_pll_pllglob >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) & + CLKMGR_PLLGLOB_REFCLKDIV_MASK; + mscnt = 200 / (6 + mdiv) / refclkdiv; + hscnt = (mdiv + 6) * mscnt / refclkdiv - 9; + vcocalib = (hscnt & CLKMGR_VCOCALIB_HSCNT_MASK) | + ((mscnt & CLKMGR_VCOCALIB_MSCNT_MASK) << + CLKMGR_VCOCALIB_MSCNT_OFFSET); + + writel((cfg->per_pll_pllglob & ~CLKMGR_PLLGLOB_PD_MASK & + ~CLKMGR_PLLGLOB_RST_MASK), + &clock_manager_base->per_pll.pllglob); + writel(cfg->per_pll_fdbck, &clock_manager_base->per_pll.fdbck); + writel(vcocalib, &clock_manager_base->per_pll.vcocalib); + writel(cfg->per_pll_pllc0, &clock_manager_base->per_pll.pllc0); + writel(cfg->per_pll_pllc1, &clock_manager_base->per_pll.pllc1); + writel(cfg->per_pll_emacctl, &clock_manager_base->per_pll.emacctl); + writel(cfg->per_pll_gpiodiv, &clock_manager_base->per_pll.gpiodiv); + + /* Take both PLL out of reset and power up */ + setbits_le32(&clock_manager_base->main_pll.pllglob, + CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK); + setbits_le32(&clock_manager_base->per_pll.pllglob, + CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK); + +#define LOCKED_MASK \ + (CLKMGR_STAT_MAINPLL_LOCKED | \ + CLKMGR_STAT_PERPLL_LOCKED) + + cm_wait_for_lock(LOCKED_MASK); + + /* + * Dividers for C2 to C9 only init after PLLs are lock. We will a large + * dividers value then final value as requested by hardware behaviour + */ + writel(0xff, &clock_manager_base->main_pll.mpuclk); + writel(0xff, &clock_manager_base->main_pll.nocclk); + writel(0xff, &clock_manager_base->main_pll.cntr2clk); + writel(0xff, &clock_manager_base->main_pll.cntr3clk); + writel(0xff, &clock_manager_base->main_pll.cntr4clk); + writel(0xff, &clock_manager_base->main_pll.cntr5clk); + writel(0xff, &clock_manager_base->main_pll.cntr6clk); + writel(0xff, &clock_manager_base->main_pll.cntr7clk); + writel(0xff, &clock_manager_base->main_pll.cntr8clk); + writel(0xff, &clock_manager_base->main_pll.cntr9clk); + writel(0xff, &clock_manager_base->per_pll.cntr2clk); + writel(0xff, &clock_manager_base->per_pll.cntr3clk); + writel(0xff, &clock_manager_base->per_pll.cntr4clk); + writel(0xff, &clock_manager_base->per_pll.cntr5clk); + writel(0xff, &clock_manager_base->per_pll.cntr6clk); + writel(0xff, &clock_manager_base->per_pll.cntr7clk); + writel(0xff, &clock_manager_base->per_pll.cntr8clk); + writel(0xff, &clock_manager_base->per_pll.cntr9clk); + + writel(cfg->main_pll_mpuclk, &clock_manager_base->main_pll.mpuclk); + writel(cfg->main_pll_nocclk, &clock_manager_base->main_pll.nocclk); + writel(cfg->main_pll_cntr2clk, &clock_manager_base->main_pll.cntr2clk); + writel(cfg->main_pll_cntr3clk, &clock_manager_base->main_pll.cntr3clk); + writel(cfg->main_pll_cntr4clk, &clock_manager_base->main_pll.cntr4clk); + writel(cfg->main_pll_cntr5clk, &clock_manager_base->main_pll.cntr5clk); + writel(cfg->main_pll_cntr6clk, &clock_manager_base->main_pll.cntr6clk); + writel(cfg->main_pll_cntr7clk, &clock_manager_base->main_pll.cntr7clk); + writel(cfg->main_pll_cntr8clk, &clock_manager_base->main_pll.cntr8clk); + writel(cfg->main_pll_cntr9clk, &clock_manager_base->main_pll.cntr9clk); + writel(cfg->per_pll_cntr2clk, &clock_manager_base->per_pll.cntr2clk); + writel(cfg->per_pll_cntr3clk, &clock_manager_base->per_pll.cntr3clk); + writel(cfg->per_pll_cntr4clk, &clock_manager_base->per_pll.cntr4clk); + writel(cfg->per_pll_cntr5clk, &clock_manager_base->per_pll.cntr5clk); + writel(cfg->per_pll_cntr6clk, &clock_manager_base->per_pll.cntr6clk); + writel(cfg->per_pll_cntr7clk, &clock_manager_base->per_pll.cntr7clk); + writel(cfg->per_pll_cntr8clk, &clock_manager_base->per_pll.cntr8clk); + writel(cfg->per_pll_cntr9clk, &clock_manager_base->per_pll.cntr9clk); + + /* Take all PLLs out of bypass */ + cm_write_bypass_mainpll(0); + cm_write_bypass_perpll(0); + + /* clear safe mode / out of boot mode */ + cm_write_ctrl(readl(&clock_manager_base->ctrl) + & ~(CLKMGR_CTRL_SAFEMODE)); + + /* Now ungate non-hw-managed clocks */ + writel(~0, &clock_manager_base->main_pll.en); + writel(~0, &clock_manager_base->per_pll.en); + + /* Clear the loss of lock bits (write 1 to clear) */ + writel(CLKMGR_INTER_PERPLLLOST_MASK | CLKMGR_INTER_MAINPLLLOST_MASK, + &clock_manager_base->intrclr); +} + +static unsigned long cm_get_main_vco_clk_hz(void) +{ + unsigned long fref, refdiv, mdiv, reg, vco; + + reg = readl(&clock_manager_base->main_pll.pllglob); + + /* get the fref */ + fref = (reg >> CLKMGR_PLLGLOB_VCO_PSRC_OFFSET) & + CLKMGR_PLLGLOB_VCO_PSRC_MASK; + switch (fref) { + case CLKMGR_VCO_PSRC_EOSC1: + fref = cm_get_osc_clk_hz(0); + break; + case CLKMGR_VCO_PSRC_INTOSC: + fref = cm_get_intosc_clk_hz(); + break; + case CLKMGR_VCO_PSRC_F2S: + fref = cm_get_fpga_clk_hz(); + break; + } + + /* get the refdiv */ + refdiv = (reg >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) & + CLKMGR_PLLGLOB_REFCLKDIV_MASK; + + /* get the mdiv */ + reg = readl(&clock_manager_base->main_pll.fdbck); + mdiv = (reg >> CLKMGR_FDBCK_MDIV_OFFSET) & CLKMGR_FDBCK_MDIV_MASK; + + vco = fref / refdiv; + vco = vco * (6 + mdiv); + return vco; +} + +static unsigned long cm_get_per_vco_clk_hz(void) +{ + unsigned long fref, refdiv, mdiv, reg, vco; + + reg = readl(&clock_manager_base->per_pll.pllglob); + + /* get the fref */ + fref = (reg >> CLKMGR_PLLGLOB_VCO_PSRC_OFFSET) & + CLKMGR_PLLGLOB_VCO_PSRC_MASK; + switch (fref) { + case CLKMGR_VCO_PSRC_EOSC1: + fref = cm_get_osc_clk_hz(0); + break; + case CLKMGR_VCO_PSRC_INTOSC: + fref = cm_get_intosc_clk_hz(); + break; + case CLKMGR_VCO_PSRC_F2S: + fref = cm_get_fpga_clk_hz(); + break; + } + + /* get the refdiv */ + refdiv = (reg >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) & + CLKMGR_PLLGLOB_REFCLKDIV_MASK; + + /* get the mdiv */ + reg = readl(&clock_manager_base->per_pll.fdbck); + mdiv = (reg >> CLKMGR_FDBCK_MDIV_OFFSET) & CLKMGR_FDBCK_MDIV_MASK; + + vco = fref / refdiv; + vco = vco * (6 + mdiv); + return vco; +} + +unsigned long cm_get_mpu_clk_hz(void) +{ + unsigned long clock = readl(&clock_manager_base->main_pll.mpuclk); + clock = (clock >> CLKMGR_CLKSRC_OFFSET) & CLKMGR_CLKSRC_MASK; + + switch (clock) { + case CLKMGR_CLKSRC_MAIN: + clock = cm_get_main_vco_clk_hz(); + clock /= (readl(&clock_manager_base->main_pll.pllc0) & + CLKMGR_PLLC0_DIV_MASK); + break; + + case CLKMGR_CLKSRC_PER: + clock = cm_get_per_vco_clk_hz(); + clock /= (readl(&clock_manager_base->per_pll.pllc0) & + CLKMGR_CLKCNT_MSK); + break; + + case CLKMGR_CLKSRC_OSC1: + clock = cm_get_osc_clk_hz(0); + break; + + case CLKMGR_CLKSRC_INTOSC: + clock = cm_get_intosc_clk_hz(); + break; + + case CLKMGR_CLKSRC_FPGA: + clock = cm_get_fpga_clk_hz(); + break; + } + + clock /= 1 + (readl(&clock_manager_base->main_pll.mpuclk) & + CLKMGR_CLKCNT_MSK); + return clock; +} + +unsigned int cm_get_l3_main_clk_hz(void) +{ + uint32_t clock = readl(&clock_manager_base->main_pll.nocclk); + clock = (clock >> CLKMGR_CLKSRC_OFFSET) & CLKMGR_CLKSRC_MASK; + + switch (clock) { + case CLKMGR_CLKSRC_MAIN: + clock = cm_get_main_vco_clk_hz(); + clock /= (readl(&clock_manager_base->main_pll.pllc1) & + CLKMGR_PLLC0_DIV_MASK); + break; + + case CLKMGR_CLKSRC_PER: + clock = cm_get_per_vco_clk_hz(); + clock /= (readl(&clock_manager_base->per_pll.pllc1) & + CLKMGR_CLKCNT_MSK); + break; + + case CLKMGR_CLKSRC_OSC1: + clock = cm_get_osc_clk_hz(0); + break; + + case CLKMGR_CLKSRC_INTOSC: + clock = cm_get_intosc_clk_hz(); + break; + + case CLKMGR_CLKSRC_FPGA: + clock = cm_get_fpga_clk_hz(); + break; + } + + clock /= 1 + (readl(&clock_manager_base->main_pll.nocclk) & + CLKMGR_CLKCNT_MSK); + return clock; +} + +unsigned int cm_get_mmc_controller_clk_hz(void) +{ + uint32_t clock = readl(&clock_manager_base->per_pll.cntr6clk); + clock = (clock >> CLKMGR_CLKSRC_OFFSET) & CLKMGR_CLKSRC_MASK; + + switch (clock) { + case CLKMGR_CLKSRC_MAIN: + clock = cm_get_l3_main_clk_hz(); + clock /= 1 + (readl(&clock_manager_base->main_pll.cntr6clk) & + CLKMGR_CLKCNT_MSK); + break; + + case CLKMGR_CLKSRC_PER: + clock = cm_get_l3_main_clk_hz(); + clock /= 1 + (readl(&clock_manager_base->per_pll.cntr6clk) & + CLKMGR_CLKCNT_MSK); + break; + + case CLKMGR_CLKSRC_OSC1: + clock = cm_get_osc_clk_hz(0); + break; + + case CLKMGR_CLKSRC_INTOSC: + clock = cm_get_intosc_clk_hz(); + break; + + case CLKMGR_CLKSRC_FPGA: + clock = cm_get_fpga_clk_hz(); + break; + } + return clock/4; +} + +unsigned int cm_get_l4_sp_clk_hz(void) +{ + uint32_t clock = cm_get_l3_main_clk_hz(); + + clock /= (1 << ((readl(&clock_manager_base->main_pll.nocdiv) >> + CLKMGR_NOCDIV_L4SPCLK_OFFSET) & CLKMGR_CLKCNT_MSK)); + return clock; +} + +void cm_print_clock_quick_summary(void) +{ + printf("MPU %d kHz\n", (u32)(cm_get_mpu_clk_hz() / 1000)); + printf("L3 main %d kHz\n", cm_get_l3_main_clk_hz() / 1000); + printf("Main VCO %d kHz\n", (u32)(cm_get_main_vco_clk_hz() / 1000)); + printf("Per VCO %d kHz\n", (u32)(cm_get_per_vco_clk_hz() / 1000)); + printf("EOSC1 %d kHz\n", cm_get_osc_clk_hz(0) / 1000); + printf("HPS MMC %d kHz\n", cm_get_mmc_controller_clk_hz() / 1000); + printf("UART %d kHz\n", cm_get_l4_sp_clk_hz() / 1000); +} diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h b/arch/arm/mach-socfpga/include/mach/clock_manager.h index 4c6b1f8..ddf814f 100644 --- a/arch/arm/mach-socfpga/include/mach/clock_manager.h +++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h @@ -17,6 +17,8 @@ void cm_print_clock_quick_summary(void); #include <asm/arch/clock_manager_gen5.h> #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) #include <asm/arch/clock_manager_arria10.h> +#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10) +#include <asm/arch/clock_manager_s10.h> #endif

#endif /* _CLOCK_MANAGER_H_ */ diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h new file mode 100644 index 0000000..c99ad97 --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h @@ -0,0 +1,202 @@ +/* + * Copyright (C) 2016-2017 Intel Corporation <www.intel.com> + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _CLOCK_MANAGER_S10_ +#define _CLOCK_MANAGER_S10_ + +/* Clock speed accessors */ +unsigned long cm_get_mpu_clk_hz(void); +unsigned long cm_get_sdram_clk_hz(void); +unsigned int cm_get_l4_sp_clk_hz(void); +unsigned int cm_get_mmc_controller_clk_hz(void); +unsigned int cm_get_qspi_controller_clk_hz(void); +unsigned int cm_get_spi_controller_clk_hz(void); +const unsigned int cm_get_osc_clk_hz(const int osc); +const unsigned int cm_get_f2s_per_ref_clk_hz(void); +const unsigned int cm_get_f2s_sdr_ref_clk_hz(void); +const unsigned int cm_get_intosc_clk_hz(void); +const unsigned int cm_get_fpga_clk_hz(void); + +/* Clock configuration accessors */ +const struct cm_config * const cm_get_default_config(void); + +struct cm_config { + /* main group */ + uint32_t main_pll_mpuclk; + uint32_t main_pll_nocclk; + uint32_t main_pll_cntr2clk; + uint32_t main_pll_cntr3clk; + uint32_t main_pll_cntr4clk; + uint32_t main_pll_cntr5clk; + uint32_t main_pll_cntr6clk; + uint32_t main_pll_cntr7clk; + uint32_t main_pll_cntr8clk; + uint32_t main_pll_cntr9clk; + uint32_t main_pll_nocdiv; + uint32_t main_pll_pllglob; + uint32_t main_pll_fdbck; + uint32_t main_pll_pllc0; + uint32_t main_pll_pllc1; + uint32_t spare; + + /* peripheral group */ + uint32_t per_pll_cntr2clk; + uint32_t per_pll_cntr3clk; + uint32_t per_pll_cntr4clk; + uint32_t per_pll_cntr5clk; + uint32_t per_pll_cntr6clk; + uint32_t per_pll_cntr7clk; + uint32_t per_pll_cntr8clk; + uint32_t per_pll_cntr9clk; + uint32_t per_pll_emacctl; + uint32_t per_pll_gpiodiv; + uint32_t per_pll_pllglob; + uint32_t per_pll_fdbck; + uint32_t per_pll_pllc0; + uint32_t per_pll_pllc1; + + /* incoming clock */ + uint32_t hps_osc_clk_hz; + uint32_t fpga_clk_hz; +}; + +void cm_basic_init(const struct cm_config * const cfg); + +struct socfpga_clock_manager_main_pll { + u32 en; + u32 ens; + u32 enr; + u32 bypass; + u32 bypasss; + u32 bypassr; + u32 mpuclk; + u32 nocclk; + u32 cntr2clk; + u32 cntr3clk; + u32 cntr4clk; + u32 cntr5clk; + u32 cntr6clk; + u32 cntr7clk; + u32 cntr8clk; + u32 cntr9clk; + u32 nocdiv; + u32 pllglob; + u32 fdbck; + u32 mem; + u32 memstat; + u32 pllc0; + u32 pllc1; + u32 vcocalib; + u32 _pad_0x90_0xA0[5]; +}; + +struct socfpga_clock_manager_per_pll { + u32 en; + u32 ens; + u32 enr; + u32 bypass; + u32 bypasss; + u32 bypassr; + u32 cntr2clk; + u32 cntr3clk; + u32 cntr4clk; + u32 cntr5clk; + u32 cntr6clk; + u32 cntr7clk; + u32 cntr8clk; + u32 cntr9clk; + u32 emacctl; + u32 gpiodiv; + u32 pllglob; + u32 fdbck; + u32 mem; + u32 memstat; + u32 pllc0; + u32 pllc1; + u32 vcocalib; + u32 _pad_0x100_0x124[10]; +}; + +struct socfpga_clock_manager { + u32 ctrl; + u32 stat; + u32 testioctrl; + u32 intrgen; + u32 intrmsk; + u32 intrclr; + u32 intrsts; + u32 intrstk; + u32 intrraw; + u32 _pad_0x24_0x2c[3]; + struct socfpga_clock_manager_main_pll main_pll; + struct socfpga_clock_manager_per_pll per_pll; +}; + +#define CLKMGR_CTRL_SAFEMODE (1 << 0) +#define CLKMGR_BYPASS_MAINPLL_ALL 0x00000007 +#define CLKMGR_BYPASS_PERPLL_ALL 0x0000007f + +#define CLKMGR_INTER_MAINPLLLOCKED_MASK 0x00000001 +#define CLKMGR_INTER_PERPLLLOCKED_MASK 0x00000002 +#define CLKMGR_INTER_MAINPLLLOST_MASK 0x00000004 +#define CLKMGR_INTER_PERPLLLOST_MASK 0x00000008 +#define CLKMGR_STAT_BUSY (1 << 0) +#define CLKMGR_STAT_MAINPLL_LOCKED (1 << 8) +#define CLKMGR_STAT_PERPLL_LOCKED (1 << 9) + +#define CLKMGR_PLLGLOB_PD_MASK 0x00000001 +#define CLKMGR_PLLGLOB_RST_MASK 0x00000002 +#define CLKMGR_PLLGLOB_VCO_PSRC_MASK 0X3 +#define CLKMGR_PLLGLOB_VCO_PSRC_OFFSET 16 +#define CLKMGR_VCO_PSRC_EOSC1 0 +#define CLKMGR_VCO_PSRC_INTOSC 1 +#define CLKMGR_VCO_PSRC_F2S 2 +#define CLKMGR_PLLGLOB_REFCLKDIV_MASK 0X3f +#define CLKMGR_PLLGLOB_REFCLKDIV_OFFSET 8 + +#define CLKMGR_CLKSRC_MASK 0x7 +#define CLKMGR_CLKSRC_OFFSET 16 +#define CLKMGR_CLKSRC_MAIN 0 +#define CLKMGR_CLKSRC_PER 1 +#define CLKMGR_CLKSRC_OSC1 2 +#define CLKMGR_CLKSRC_INTOSC 3 +#define CLKMGR_CLKSRC_FPGA 4 +#define CLKMGR_CLKCNT_MSK 0x7ff + +#define CLKMGR_FDBCK_MDIV_MASK 0xff +#define CLKMGR_FDBCK_MDIV_OFFSET 24 + +#define CLKMGR_PLLC0_DIV_MASK 0xff +#define CLKMGR_PLLC1_DIV_MASK 0xff +#define CLKMGR_PLLC0_EN_OFFSET 27 +#define CLKMGR_PLLC1_EN_OFFSET 24 + +#define CLKMGR_NOCDIV_L4MAIN_OFFSET 0 +#define CLKMGR_NOCDIV_L4MPCLK_OFFSET 8 +#define CLKMGR_NOCDIV_L4SPCLK_OFFSET 16 +#define CLKMGR_NOCDIV_CSATCLK_OFFSET 24 +#define CLKMGR_NOCDIV_CSTRACECLK_OFFSET 26 +#define CLKMGR_NOCDIV_CSPDBGCLK_OFFSET 28 + +#define CLKMGR_NOCDIV_L4SPCLK_MASK 0X3 +#define CLKMGR_NOCDIV_DIV1 0 +#define CLKMGR_NOCDIV_DIV2 1 +#define CLKMGR_NOCDIV_DIV4 2 +#define CLKMGR_NOCDIV_DIV8 3 +#define CLKMGR_CSPDBGCLK_DIV1 0 +#define CLKMGR_CSPDBGCLK_DIV4 1 + +#define CLKMGR_VCOCALIB_MSCNT_MASK 0xff +#define CLKMGR_VCOCALIB_MSCNT_OFFSET 9 +#define CLKMGR_VCOCALIB_HSCNT_MASK 0xff + +#define CLKMGR_EMACCTL_EMAC0SEL_OFFSET 26 +#define CLKMGR_EMACCTL_EMAC1SEL_OFFSET 27 +#define CLKMGR_EMACCTL_EMAC2SEL_OFFSET 28 + +#define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK 0x00000020 + +#endif /* _CLOCK_MANAGER_S10_ */ diff --git a/arch/arm/mach-socfpga/include/mach/handoff_s10.h b/arch/arm/mach-socfpga/include/mach/handoff_s10.h new file mode 100644 index 0000000..d4b89ac --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/handoff_s10.h @@ -0,0 +1,29 @@ +/* + * Copyright (C) 2017 Intel Corporation <www.intel.com> + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _HANDOFF_S10_H_ +#define _HANDOFF_S10_H_ + +/* + * Offset for HW handoff from Quartus tools + */ +#define CONFIG_HANDOFF_BASE 0xFFE3F000 +#define CONFIG_HANDOFF_MUX (CONFIG_HANDOFF_BASE + 0x10) +#define CONFIG_HANDOFF_IOCTL (CONFIG_HANDOFF_BASE + 0x1A0) +#define CONFIG_HANDOFF_FPGA (CONFIG_HANDOFF_BASE + 0x330) +#define CONFIG_HANODFF_DELAY (CONFIG_HANDOFF_BASE + 0x3F0) +#define CONFIG_HANDOFF_CLOCK (CONFIG_HANDOFF_BASE + 0x580) +#define CONFIG_HANDOFF_MISC (CONFIG_HANDOFF_BASE + 0x610) +#define CONFIG_HANDOFF_MAGIC_MUX 0x504D5558 +#define CONFIG_HANDOFF_MAGIC_IOCTL 0x494F4354 +#define CONFIG_HANDOFF_MAGIC_FPGA 0x46504741 +#define CONFIG_HANDOFF_MAGIC_DELAY 0x444C4159 +#define CONFIG_HANDOFF_MAGIC_CLOCK 0x434C4B53 +#define CONFIG_HANDOFF_MAGIC_MISC 0x4D495343 +#define CONFIG_HANDOFF_OFFSET_LENGTH 0x4 +#define CONFIG_HANDOFF_OFFSET_DATA 0x10 + +#endif /* _HANDOFF_S10_H_ */ diff --git a/arch/arm/mach-socfpga/wrap_pll_config_s10.c b/arch/arm/mach-socfpga/wrap_pll_config_s10.c new file mode 100644 index 0000000..2a624d5 --- /dev/null +++ b/arch/arm/mach-socfpga/wrap_pll_config_s10.c @@ -0,0 +1,46 @@ +/* + * Copyright (C) 2016-2017 Intel Corporation <www.intel.com> + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <asm/arch/clock_manager.h> +#include <asm/io.h> +#include <asm/arch/handoff_s10.h> + +const struct cm_config * const cm_get_default_config(void) +{ + struct cm_config *cm_handoff_cfg = (struct cm_config *) + (CONFIG_HANDOFF_CLOCK + CONFIG_HANDOFF_OFFSET_DATA); + u32 *conversion = (u32 *)cm_handoff_cfg; + u32 i; + + if (swab32(readl(CONFIG_HANDOFF_CLOCK)) == CONFIG_HANDOFF_MAGIC_CLOCK) { + writel(swab32(readl(CONFIG_HANDOFF_CLOCK)), + CONFIG_HANDOFF_CLOCK); + for (i = 0; i < (sizeof(*cm_handoff_cfg) / sizeof(u32)); i++) + conversion[i] = swab32(conversion[i]); + return cm_handoff_cfg; + } else if (readl(CONFIG_HANDOFF_CLOCK) == CONFIG_HANDOFF_MAGIC_CLOCK) { + return cm_handoff_cfg; + } else + return 0; +} + +const unsigned int cm_get_osc_clk_hz(const int osc) +{ + return 25000000; +} + +const unsigned int cm_get_intosc_clk_hz(void) +{ + /* theory maximum internal osc clock */ + return 460000000; +} + +const unsigned int cm_get_fpga_clk_hz(void) +{ + /* assuming 50MHz */ + return 50000000; +}

From: Chin Liang See chin.liang.see@intel.com

Add misc support for Stratix SoC

Signed-off-by: Chin Liang See chin.liang.see@intel.com --- arch/arm/mach-socfpga/Makefile | 1 + arch/arm/mach-socfpga/misc.c | 4 + arch/arm/mach-socfpga/misc_s10.c | 165 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 170 insertions(+) create mode 100644 arch/arm/mach-socfpga/misc_s10.c

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index 910eb6f..b253914 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -32,6 +32,7 @@ endif

ifdef CONFIG_TARGET_SOCFPGA_STRATIX10 obj-y += clock_manager_s10.o +obj-y += misc_s10.o obj-y += reset_manager_s10.o obj-y += system_manager_s10.o obj-y += wrap_pinmux_config_s10.o diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index 00eff90..2ea94bc 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -23,8 +23,10 @@

DECLARE_GLOBAL_DATA_PTR;

+#ifdef CONFIG_SYS_L2_PL310 static const struct pl310_regs *const pl310 = (struct pl310_regs *)CONFIG_SYS_PL310_BASE; +#endif

struct bsel bsel_str[] = { { "rsvd", "Reserved", }, @@ -53,6 +55,7 @@ void enable_caches(void) #endif }

+#ifdef CONFIG_SYS_L2_PL310 void v7_outer_cache_enable(void) { /* Disable the L2 cache */ @@ -73,6 +76,7 @@ void v7_outer_cache_disable(void) /* Disable the L2 cache */ clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); } +#endif

#if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \ defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE) diff --git a/arch/arm/mach-socfpga/misc_s10.c b/arch/arm/mach-socfpga/misc_s10.c new file mode 100644 index 0000000..b84f055 --- /dev/null +++ b/arch/arm/mach-socfpga/misc_s10.c @@ -0,0 +1,165 @@ +/* + * Copyright (C) 2016-2017 Intel Corporation <www.intel.com> + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <asm/io.h> +#include <errno.h> +#include <fdtdec.h> +#include <libfdt.h> +#include <altera.h> +#include <miiphy.h> +#include <netdev.h> +#include <watchdog.h> +#include <asm/arch/reset_manager.h> +#include <asm/arch/system_manager.h> +#include <asm/pl310.h> + +#include <dt-bindings/reset/altr,rst-mgr-s10.h> + +DECLARE_GLOBAL_DATA_PTR; + +static struct socfpga_system_manager *sysmgr_regs = + (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; + +/* + * DesignWare Ethernet initialization + */ +#ifdef CONFIG_ETH_DESIGNWARE +void dwmac_deassert_reset(const unsigned int of_reset_id, + const u32 phymode) +{ + /* Put the emac we're using into reset. + * This is required before configuring the PHY interface + */ + socfpga_emac_manage_reset(of_reset_id, 1); + + clrsetbits_le32(&sysmgr_regs->emac0 + (of_reset_id - EMAC0_RESET), + SYSMGR_EMACGRP_CTRL_PHYSEL_MASK, + phymode); + + socfpga_emac_manage_reset(of_reset_id, 0); +} + +static u32 dwmac_phymode_to_modereg(const char *phymode, u32 *modereg) +{ + if (!phymode) + return -EINVAL; + + if (!strcmp(phymode, "mii") || !strcmp(phymode, "gmii")) { + *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII; + return 0; + } + + if (!strcmp(phymode, "rgmii")) { + *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII; + return 0; + } + + if (!strcmp(phymode, "rmii")) { + *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII; + return 0; + } + + return -EINVAL; +} + +static int socfpga_eth_reset(void) +{ + const void *fdt = gd->fdt_blob; + struct fdtdec_phandle_args args; + const char *phy_mode; + u32 phy_modereg; + int nodes[2]; /* Max. 3 GMACs */ + int ret, count; + int i, node; + + count = fdtdec_find_aliases_for_id(fdt, "ethernet", + COMPAT_ALTERA_SOCFPGA_DWMAC, + nodes, ARRAY_SIZE(nodes)); + for (i = 0; i < count; i++) { + node = nodes[i]; + if (node <= 0) + continue; + + ret = fdtdec_parse_phandle_with_args(fdt, node, "resets", + "#reset-cells", 1, 0, + &args); + if (ret || (args.args_count != 1)) { + debug("GMAC%i: Failed to parse DT 'resets'!\n", i); + continue; + } + + phy_mode = fdt_getprop(fdt, node, "phy-mode", NULL); + ret = dwmac_phymode_to_modereg(phy_mode, &phy_modereg); + if (ret) { + debug("GMAC%i: Failed to parse DT 'phy-mode'!\n", i); + continue; + } + + dwmac_deassert_reset(args.args[0], phy_modereg); + } + + return 0; +} +#else +static int socfpga_eth_reset(void) +{ + return 0; +}; +#endif + +/* + * Print CPU information + */ +#if defined(CONFIG_DISPLAY_CPUINFO) +int print_cpuinfo(void) +{ + puts("CPU: Intel FPGA SoCFPGA Platform\n"); + puts("FPGA: Intel FPGA Stratix 10\n"); + return 0; +} +#endif + +#ifdef CONFIG_ARCH_MISC_INIT +int arch_misc_init(void) +{ + return socfpga_eth_reset(); +} +#endif + +int arch_early_init_r(void) +{ + return 0; +} + +int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + if (argc != 2) + return CMD_RET_USAGE; + + argv++; + + switch (*argv[0]) { + case 'e': /* Enable */ + socfpga_bridges_reset(1); + break; + case 'd': /* Disable */ + socfpga_bridges_reset(0); + break; + default: + return CMD_RET_USAGE; + } + + return 0; +} + +U_BOOT_CMD( + bridge, 2, 1, do_bridge, + "SoCFPGA HPS FPGA bridge control", + "enable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n" + "bridge disable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n" + "" +);

From: Chin Liang See chin.liang.see@intel.com

Add MMU support for Stratix SoC

Signed-off-by: Chin Liang See chin.liang.see@intel.com --- arch/arm/mach-socfpga/Makefile | 1 + arch/arm/mach-socfpga/mmu-arm64_s10.c | 71 +++++++++++++++++++++++++++++++++++ 2 files changed, 72 insertions(+) create mode 100644 arch/arm/mach-socfpga/mmu-arm64_s10.c

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index 43e18d2..098e5e9 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -34,6 +34,7 @@ ifdef CONFIG_TARGET_SOCFPGA_STRATIX10 obj-y += clock_manager_s10.o obj-y += mailbox_s10.o obj-y += misc_s10.o +obj-y += mmu-arm64_s10.o obj-y += reset_manager_s10.o obj-y += system_manager_s10.o obj-y += wrap_pinmux_config_s10.o diff --git a/arch/arm/mach-socfpga/mmu-arm64_s10.c b/arch/arm/mach-socfpga/mmu-arm64_s10.c new file mode 100644 index 0000000..91c7f2e --- /dev/null +++ b/arch/arm/mach-socfpga/mmu-arm64_s10.c @@ -0,0 +1,71 @@ +/* + * Copyright (C) 2016-2017 Intel Corporation <www.intel.com> + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <asm/armv8/mmu.h> + +DECLARE_GLOBAL_DATA_PTR; + +static struct mm_region socfpga_stratix10_mem_map[] = { + { + /* MEM 2GB*/ + .virt = 0x0UL, + .phys = 0x0UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE, + }, { + /* FPGA 1.5GB */ + .virt = 0x80000000UL, + .phys = 0x80000000UL, + .size = 0x60000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN, + }, { + /* DEVICE 142MB */ + .virt = 0xF7000000UL, + .phys = 0xF7000000UL, + .size = 0x08E00000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN, + }, { + /* OCRAM 1MB but available 256KB */ + .virt = 0xFFE00000UL, + .phys = 0xFFE00000UL, + .size = 0x00100000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE, + }, { + /* DEVICE 32KB */ + .virt = 0xFFFC0000UL, + .phys = 0xFFFC0000UL, + .size = 0x00008000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN, + }, { + /* MEM 124GB */ + .virt = 0x0100000000UL, + .phys = 0x0100000000UL, + .size = 0x1F00000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE, + }, { + /* DEVICE 4GB */ + .virt = 0x2000000000UL, + .phys = 0x2000000000UL, + .size = 0x0100000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN, + }, { + /* List terminator */ + }, +}; + +struct mm_region *mem_map = socfpga_stratix10_mem_map;

From: Chin Liang See chin.liang.see@intel.com

Add SPL driver support for Stratix SoC

Signed-off-by: Chin Liang See chin.liang.see@intel.com --- arch/arm/mach-socfpga/Makefile | 4 + arch/arm/mach-socfpga/include/mach/base_addr_s10.h | 4 + arch/arm/mach-socfpga/include/mach/firewall_s10.h | 84 +++++++++++++ arch/arm/mach-socfpga/spl_s10.c | 138 +++++++++++++++++++++ 4 files changed, 230 insertions(+) create mode 100644 arch/arm/mach-socfpga/include/mach/firewall_s10.h create mode 100644 arch/arm/mach-socfpga/spl_s10.c

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index b669d43..35b124a 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -40,6 +40,7 @@ obj-y += system_manager_s10.o obj-y += wrap_pinmux_config_s10.o obj-y += wrap_pll_config_s10.o endif + ifdef CONFIG_SPL_BUILD ifdef CONFIG_TARGET_SOCFPGA_GEN5 obj-y += spl_gen5.o @@ -51,6 +52,9 @@ endif ifdef CONFIG_TARGET_SOCFPGA_ARRIA10 obj-y += spl_a10.o endif +ifdef CONFIG_TARGET_SOCFPGA_STRATIX10 +obj-y += spl_s10.o +endif endif

ifdef CONFIG_TARGET_SOCFPGA_GEN5 diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_s10.h b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h index feb1881..d79b9cd 100644 --- a/arch/arm/mach-socfpga/include/mach/base_addr_s10.h +++ b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h @@ -45,6 +45,10 @@ #define SOCFPGA_RSTMGR_ADDRESS 0xffd11000 #define SOCFPGA_SYSMGR_ADDRESS 0xffd12000 #define SOCFPGA_PINMUX_DEDICATED_IO_ADDRESS 0xffd13000 +#define SOCFPGA_FIREWALL_L4_PER 0xffd21000 +#define SOCFPGA_FIREWALL_L4_SYS 0xffd21100 +#define SOCFPGA_FIREWALL_SOC2FPGA 0xffd21200 +#define SOCFPGA_FIREWALL_LWSOC2FPGA 0xffd21300 #define SOCFPGA_DMANONSECURE_ADDRESS 0xffda0000 #define SOCFPGA_DMASECURE_ADDRESS 0xffda1000 #define SOCFPGA_SPIS0_ADDRESS 0xffda2000 diff --git a/arch/arm/mach-socfpga/include/mach/firewall_s10.h b/arch/arm/mach-socfpga/include/mach/firewall_s10.h new file mode 100644 index 0000000..6894bb9 --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/firewall_s10.h @@ -0,0 +1,84 @@ +/* + * Copyright (C) 2017 Intel Corporation <www.intel.com> + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _FIREWALL_S10_ +#define _FIREWALL_S10_ + +struct socfpga_firwall_l4_per { + u32 nand; /* 0x00 */ + u32 nand_data; + u32 _pad_0x8; + u32 usb0; + u32 usb1; /* 0x10 */ + u32 _pad_0x14; + u32 _pad_0x18; + u32 spim0; + u32 spim1; /* 0x20 */ + u32 spis0; + u32 spis1; + u32 emac0; + u32 emac1; /* 0x30 */ + u32 emac2; + u32 _pad_0x38; + u32 _pad_0x3c; + u32 sdmmc; /* 0x40 */ + u32 gpio0; + u32 gpio1; + u32 _pad_0x4c; + u32 i2c0; /* 0x50 */ + u32 i2c1; + u32 i2c2; + u32 i2c3; + u32 i2c4; /* 0x60 */ + u32 timer0; + u32 timer1; + u32 uart0; + u32 uart1; /* 0x70 */ +}; + +struct socfpga_firwall_l4_sys { + u32 _pad_0x00; /* 0x00 */ + u32 _pad_0x04; + u32 dma_ecc; + u32 emac0rx_ecc; + u32 emac0tx_ecc; /* 0x10 */ + u32 emac1rx_ecc; + u32 emac1tx_ecc; + u32 emac2rx_ecc; + u32 emac2tx_ecc; /* 0x20 */ + u32 _pad_0x24; + u32 _pad_0x28; + u32 nand_ecc; + u32 nand_read_ecc; /* 0x30 */ + u32 nand_write_ecc; + u32 ocram_ecc; + u32 _pad_0x3c; + u32 sdmmc_ecc; /* 0x40 */ + u32 usb0_ecc; + u32 usb1_ecc; + u32 clock_manager; + u32 _pad_0x50; /* 0x50 */ + u32 io_manager; + u32 reset_manager; + u32 system_manager; + u32 osc0_timer; /* 0x60 */ + u32 osc1_timer; + u32 watchdog0; + u32 watchdog1; + u32 watchdog2; /* 0x70 */ + u32 watchdog3; +}; + +#define FIREWALL_L4_DISABLE_ALL (BIT(0) | BIT(24) | BIT(16)) +#define FIREWALL_BRIDGE_DISABLE_ALL (~0) + +#define CCU_CPU0_MPRT_ADMASK_MEM_RAM0_ADDR 0xf7004688 +#define CCU_IOM_MPRT_ADMASK_MEM_RAM0_ADDR 0xf7018628 + +#define CCU_ADMASK_P_MASK (BIT(0)) +#define CCU_ADMASK_NS_MASK (BIT(1)) + +#endif /* _FIREWALL_S10_ */ diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/spl_s10.c new file mode 100644 index 0000000..12cafe6 --- /dev/null +++ b/arch/arm/mach-socfpga/spl_s10.c @@ -0,0 +1,138 @@ +/* + * Copyright (C) 2016-2017 Intel Corporation <www.intel.com> + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/u-boot.h> +#include <asm/utils.h> +#include <image.h> +#include <asm/arch/reset_manager.h> +#include <spl.h> +#include <asm/arch/system_manager.h> +#include <asm/arch/clock_manager.h> +#include <asm/arch/sdram_s10.h> +#include <asm/arch/mailbox_s10.h> +#include <asm/arch/firewall_s10.h> + +DECLARE_GLOBAL_DATA_PTR; + +static const struct socfpga_firwall_l4_per *firwall_l4_per_base = + (struct socfpga_firwall_l4_per *)SOCFPGA_FIREWALL_L4_PER; +static const struct socfpga_firwall_l4_sys *firwall_l4_sys_base = + (struct socfpga_firwall_l4_sys *)SOCFPGA_FIREWALL_L4_SYS; + +u32 spl_boot_device(void) +{ + /* TODO: Get from SDM or handoff */ +/* #ifdef CONFIG_CADENCE_QSPI*/ +#if 0 + return BOOT_DEVICE_SPI; +#else + return BOOT_DEVICE_MMC1; +#endif +} + +#ifdef CONFIG_SPL_MMC_SUPPORT +u32 spl_boot_mode(const u32 boot_device) +{ +#if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT) + return MMCSD_MODE_FS; +#else + return MMCSD_MODE_RAW; +#endif +} +#endif + +void board_init_f(ulong dummy) +{ + const struct cm_config *cm_default_cfg = cm_get_default_config(); + + socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0); + timer_init(); + + populate_sysmgr_pinmux(); + + /* configuring the HPS clocks */ + cm_basic_init(cm_default_cfg); + + /* enable console uart printing */ +#if (CONFIG_SYS_NS16550_COM1 == SOCFPGA_UART0_ADDRESS) + socfpga_per_reset(SOCFPGA_RESET(UART0), 0); + /* enables nonsecure access to UART0 */ + writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->uart0); +#elif (CONFIG_SYS_NS16550_COM1 == SOCFPGA_UART1_ADDRESS) + socfpga_per_reset(SOCFPGA_RESET(UART1), 0); + /* enables nonsecure access to UART1 */ + writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->uart1); +#endif + + preloader_console_init(); + cm_print_clock_quick_summary(); + + /* enable all EMACs */ + writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->emac0); + writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->emac1); + writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->emac2); + /* enables nonsecure access to all the emacs */ + writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->emac0rx_ecc); + writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->emac0tx_ecc); + writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->emac1rx_ecc); + writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->emac1tx_ecc); + writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->emac2rx_ecc); + writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->emac2tx_ecc); + + /* enables SDMMC */ + socfpga_per_reset(SOCFPGA_RESET(SDMMC_OCP), 0); + socfpga_per_reset(SOCFPGA_RESET(SDMMC), 0); + /* Enables nonsecure access to SDMMC */ + writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->sdmmc); + writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->sdmmc_ecc); + + /* enable i2c0 and i2c1 */ + socfpga_per_reset(SOCFPGA_RESET(I2C0), 0); + socfpga_per_reset(SOCFPGA_RESET(I2C1), 0); + /* enables nonsecure access to i2c0 and i2c1 */ + writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->i2c0); + writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_per_base->i2c1); + + /* disable lwsocf2fpga and soc2fpga bridge security */ + writel(FIREWALL_BRIDGE_DISABLE_ALL, SOCFPGA_FIREWALL_SOC2FPGA); + writel(FIREWALL_BRIDGE_DISABLE_ALL, SOCFPGA_FIREWALL_LWSOC2FPGA); + + /* enables nonsecure access to clock mgr */ + writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->clock_manager); + + /* enables nonsecure access to OCRAM */ + writel(FIREWALL_L4_DISABLE_ALL, &firwall_l4_sys_base->ocram_ecc); + + /* disable ocram security at CCU for non secure access */ + clrbits_le32(CCU_CPU0_MPRT_ADMASK_MEM_RAM0_ADDR, + CCU_ADMASK_P_MASK | CCU_ADMASK_NS_MASK); + clrbits_le32(CCU_IOM_MPRT_ADMASK_MEM_RAM0_ADDR, + CCU_ADMASK_P_MASK | CCU_ADMASK_NS_MASK); + + puts("DDR: Initializing Hard Memory Controller\n"); + if (sdram_mmr_init_full(0)) { + puts("DDR: Initialization failed.\n"); + hang(); + } + + gd->ram_size = sdram_calculate_size(); + printf("DDR: %d MiB\n", (int)(gd->ram_size >> 20)); + + /* Sanity check ensure correct SDRAM size specified */ + puts("DDR: Running SDRAM size sanity check\n"); + if (get_ram_size(0, gd->ram_size) != gd->ram_size) { + puts("DDR: SDRAM size check failed!\n"); + hang(); + } + puts("DDR: SDRAM size check passed!\n"); + +#ifdef CONFIG_CADENCE_QSPI + mbox_init(); + mbox_qspi_open(); +#endif +}

From: Chin Liang See chin.liang.see@intel.com

Add DDR support for Stratix SoC

Signed-off-by: Chin Liang See chin.liang.see@intel.com --- arch/arm/mach-socfpga/include/mach/sdram_s10.h | 333 +++++++++++++++++++++ drivers/ddr/altera/Makefile | 1 + drivers/ddr/altera/sdram_s10.c | 382 +++++++++++++++++++++++++ 3 files changed, 716 insertions(+) create mode 100644 arch/arm/mach-socfpga/include/mach/sdram_s10.h create mode 100644 drivers/ddr/altera/sdram_s10.c

diff --git a/arch/arm/mach-socfpga/include/mach/sdram_s10.h b/arch/arm/mach-socfpga/include/mach/sdram_s10.h new file mode 100644 index 0000000..d0fd958 --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/sdram_s10.h @@ -0,0 +1,333 @@ +/* + * Copyright (C) 2016-2017 Intel Corporation <www.intel.com> + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _SDRAM_S10_H_ +#define _SDRAM_S10_H_ + +unsigned long sdram_calculate_size(void); +int sdram_mmr_init_full(unsigned int sdr_phy_reg); +int sdram_calibration_full(void); + +#define DDR_TWR 15 +#define DDR_READ_LATENCY_DELAY 40 +#define DDR_ACTIVATE_FAWBANK 0x1 + + +struct socfpga_ecc_hmc { + uint32_t ip_rev_id; + uint32_t _pad_0x4_0x7; + uint32_t ddrioctrl; + uint32_t ddrcalstat; + uint32_t mpr_0beat1; + uint32_t mpr_1beat1; + uint32_t mpr_2beat1; + uint32_t mpr_3beat1; + uint32_t mpr_4beat1; + uint32_t mpr_5beat1; + uint32_t mpr_6beat1; + uint32_t mpr_7beat1; + uint32_t mpr_8beat1; + uint32_t mpr_0beat2; + uint32_t mpr_1beat2; + uint32_t mpr_2beat2; + uint32_t mpr_3beat2; + uint32_t mpr_4beat2; + uint32_t mpr_5beat2; + uint32_t mpr_6beat2; + uint32_t mpr_7beat2; + uint32_t mpr_8beat2; + uint32_t _pad_0x58_0x5f[2]; + uint32_t auto_precharge; + uint32_t _pad_0x64_0xdf[31]; + uint32_t dramaddrwidth; + uint32_t _pad_0xe4_0xff[7]; + uint32_t eccctrl; + uint32_t eccctrl2; + uint32_t _pad_0x108_0x10f[2]; + uint32_t errinten; + uint32_t errintens; + uint32_t errintenr; + uint32_t intmode; + uint32_t intstat; + uint32_t diaginttest; + uint32_t modstat; + uint32_t derraddra; + uint32_t serraddra; + uint32_t _pad_0x134_0x137; + uint32_t autowb_corraddr; + uint32_t serrcntreg; + uint32_t autowb_drop_cntreg; + uint32_t ecc_reg2wreccdatabus; + uint32_t ecc_rdeccdata2regbus; + uint32_t ecc_reg2rdeccdatabus; + uint32_t ecc_diagon; + uint32_t ecc_decstat; + uint32_t _pad_0x158_0x15f[2]; + uint32_t ecc_errgenaddr_0; + uint32_t ecc_errgenaddr_1; + uint32_t ecc_errgenaddr_2; + uint32_t ecc_errgenaddr_3; + uint32_t ecc_ref2rddatabus_beat0; + uint32_t ecc_ref2rddatabus_beat1; + uint32_t ecc_ref2rddatabus_beat2; + uint32_t ecc_ref2rddatabus_beat3; + uint32_t ecc_errgenhaddr_0; + uint32_t ecc_errgenhaddr_1; + uint32_t ecc_errgenhaddr_2; + uint32_t ecc_errgenhaddr_3; + uint32_t ecc_rdeccdata2regbus_beat0; + uint32_t ecc_rdeccdata2regbus_beat1; + uint32_t ecc_rdeccdata2regbus_beat2; + uint32_t ecc_rdeccdata2regbus_beat3; + uint32_t _pad_0x1a0_0x1af[4]; + uint32_t derrhaddr; + uint32_t serrhaddr; + uint32_t _pad_0x1b8_0x1bb; + uint32_t autowb_corrhaddr; + uint32_t _pad_0x1c0_0x20f[20]; + uint32_t hpsintfcsel; + uint32_t rsthandshakectrl; + uint32_t rsthandshakestat; +}; + +struct socfpga_noc_ddr_scheduler { + uint32_t main_scheduler_id_coreid; + uint32_t main_scheduler_id_revisionid; + uint32_t main_scheduler_ddrconf; + uint32_t main_scheduler_ddrtiming; + uint32_t main_scheduler_ddrmode; + uint32_t main_scheduler_readlatency; + uint32_t _pad_0x18_0x37[8]; + uint32_t main_scheduler_activate; + uint32_t main_scheduler_devtodev; + uint32_t main_scheduler_ddr4timing; +}; + +struct socfpga_io48_mmr { + uint32_t dbgcfg0; + uint32_t dbgcfg1; + uint32_t dbgcfg2; + uint32_t dbgcfg3; + uint32_t dbgcfg4; + uint32_t dbgcfg5; + uint32_t dbgcfg6; + uint32_t reserve0; + uint32_t reserve1; + uint32_t reserve2; + uint32_t ctrlcfg0; + uint32_t ctrlcfg1; + uint32_t ctrlcfg2; + uint32_t ctrlcfg3; + uint32_t ctrlcfg4; + uint32_t ctrlcfg5; + uint32_t ctrlcfg6; + uint32_t ctrlcfg7; + uint32_t ctrlcfg8; + uint32_t ctrlcfg9; + uint32_t dramtiming0; + uint32_t dramodt0; + uint32_t dramodt1; + uint32_t sbcfg0; + uint32_t sbcfg1; + uint32_t sbcfg2; + uint32_t sbcfg3; + uint32_t sbcfg4; + uint32_t sbcfg5; + uint32_t sbcfg6; + uint32_t sbcfg7; + uint32_t caltiming0; + uint32_t caltiming1; + uint32_t caltiming2; + uint32_t caltiming3; + uint32_t caltiming4; + uint32_t caltiming5; + uint32_t caltiming6; + uint32_t caltiming7; + uint32_t caltiming8; + uint32_t caltiming9; + uint32_t caltiming10; + uint32_t dramaddrw; + uint32_t sideband0; + uint32_t sideband1; + uint32_t sideband2; + uint32_t sideband3; + uint32_t sideband4; + uint32_t sideband5; + uint32_t sideband6; + uint32_t sideband7; + uint32_t sideband8; + uint32_t sideband9; + uint32_t sideband10; + uint32_t sideband11; + uint32_t sideband12; + uint32_t sideband13; + uint32_t sideband14; + uint32_t sideband15; + uint32_t dramsts; + uint32_t dbgdone; + uint32_t dbgsignals; + uint32_t dbgreset; + uint32_t dbgmatch; + uint32_t counter0mask; + uint32_t counter1mask; + uint32_t counter0match; + uint32_t counter1match; + uint32_t niosreserve0; + uint32_t niosreserve1; + uint32_t niosreserve2; +}; + +union dramaddrw_reg { + struct { + u32 cfg_col_addr_width:5; + u32 cfg_row_addr_width:5; + u32 cfg_bank_addr_width:4; + u32 cfg_bank_group_addr_width:2; + u32 cfg_cs_addr_width:3; + u32 reserved:13; + }; + u32 word; +}; + +union ctrlcfg0_reg { + struct { + u32 cfg_mem_type:4; + u32 cfg_dimm_type:3; + u32 cfg_ac_pos:2; + u32 cfg_ctrl_burst_len:5; + u32 reserved:18; /* Other fields unused */ + }; + u32 word; +}; + +union ctrlcfg1_reg { + struct { + u32 cfg_dbc3_burst_len:5; + u32 cfg_addr_order:2; + u32 cfg_ctrl_enable_ecc:1; + u32 reserved:24; /* Other fields unused */ + }; + u32 word; +}; + +union dramtiming0_reg { + struct { + u32 cfg_tcl:6; + u32 reserved:8; /* Other fields unused */ + }; + u32 word; +}; + +union caltiming0_reg { + struct { + u32 cfg_act_to_rdwr:6; + u32 cfg_act_to_pch:6; + u32 cfg_act_to_act:6; + u32 cfg_act_to_act_db:6; + u32 reserved:8; /* Other fields unused */ + }; + u32 word; +}; + +union caltiming1_reg { + struct { + u32 cfg_rd_to_rd:6; + u32 cfg_rd_to_rd_dc:6; + u32 cfg_rd_to_rd_db:6; + u32 cfg_rd_to_wr:6; + u32 cfg_rd_to_wr_dc:6; + u32 reserved:2; + }; + u32 word; +}; + +union caltiming2_reg { + struct { + u32 cfg_rd_to_wr_db:6; + u32 cfg_rd_to_pch:6; + u32 cfg_rd_ap_to_valid:6; + u32 cfg_wr_to_wr:6; + u32 cfg_wr_to_wr_dc:6; + u32 reserved:2; + }; + u32 word; +}; + +union caltiming3_reg { + struct { + u32 cfg_wr_to_wr_db:6; + u32 cfg_wr_to_rd:6; + u32 cfg_wr_to_rd_dc:6; + u32 cfg_wr_to_rd_db:6; + u32 cfg_wr_to_pch:6; + u32 reserved:2; + }; + u32 word; +}; + +union caltiming4_reg { + struct { + u32 cfg_wr_ap_to_valid:6; + u32 cfg_pch_to_valid:6; + u32 cfg_pch_all_to_valid:6; + u32 cfg_arf_to_valid:8; + u32 cfg_pdn_to_valid:6; + }; + u32 word; +}; + +union caltiming9_reg { + struct { + u32 cfg_4_act_to_act:8; + u32 reserved:24; + }; + u32 word; +}; + +#define DDR_SCHED_DDRTIMING_ACTTOACT_OFFSET 0 +#define DDR_SCHED_DDRTIMING_RDTOMISS_OFFSET 6 +#define DDR_SCHED_DDRTIMING_WRTOMISS_OFFSET 12 +#define DDR_SCHED_DDRTIMING_BURSTLEN_OFFSET 18 +#define DDR_SCHED_DDRTIMING_RDTOWR_OFFSET 21 +#define DDR_SCHED_DDRTIMING_WRTORD_OFFSET 26 +#define DDR_SCHED_DDRTIMING_BWRATIO_OFFSET 31 +#define DDR_SCHED_DDRMOD_BWRATIOEXTENDED_OFFSET 1 +#define DDR_SCHED_ACTIVATE_RRD_OFFSET 0 +#define DDR_SCHED_ACTIVATE_FAW_OFFSET 4 +#define DDR_SCHED_ACTIVATE_FAWBANK_OFFSET 10 +#define DDR_SCHED_DEVTODEV_BUSRDTORD_OFFSET 0 +#define DDR_SCHED_DEVTODEV_BUSRDTOWR_OFFSET 2 +#define DDR_SCHED_DEVTODEV_BUSWRTORD_OFFSET 4 +#define DDR_HMC_DDRIOCTRL_IOSIZE_MSK 0x00000003 +#define DDR_HMC_DDRCALSTAT_CAL_MSK 0x00000001 +#define DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK 0x00010000 +#define DDR_HMC_ECCCTL_CNT_RST_SET_MSK 0x00000100 +#define DDR_HMC_ECCCTL_ECC_EN_SET_MSK 0x00000001 +#define DDR_HMC_ECCCTL2_RMW_EN_SET_MSK 0x00000100 +#define DDR_HMC_ECCCTL2_AWB_EN_SET_MSK 0x00000001 +#define DDR_HMC_RSTHANDSHAKE_MASK 0x000000ff +#define DDR_HMC_CORE2SEQ_INT_REQ 0xF +#define DDR_HMC_SEQ2CORE_INT_RESP_MASK 0x8 +#define DDR_HMC_HPSINTFCSEL_ENABLE_MASK 0x001f1f1f + +#define CCU_CPU0_MPRT_ADBASE_DDRREG_ADDR 0xf7004400 +#define CCU_CPU0_MPRT_ADBASE_MEMSPACE0_ADDR 0xf70045c0 +#define CCU_CPU0_MPRT_ADBASE_MEMSPACE1A_ADDR 0xf70045e0 +#define CCU_CPU0_MPRT_ADBASE_MEMSPACE1B_ADDR 0xf7004600 +#define CCU_CPU0_MPRT_ADBASE_MEMSPACE1C_ADDR 0xf7004620 +#define CCU_CPU0_MPRT_ADBASE_MEMSPACE1D_ADDR 0xf7004640 +#define CCU_CPU0_MPRT_ADBASE_MEMSPACE1E_ADDR 0xf7004660 + +#define CCU_IOM_MPRT_ADBASE_MEMSPACE0_ADDR 0xf7018560 +#define CCU_IOM_MPRT_ADBASE_MEMSPACE1A_ADDR 0xf7018580 +#define CCU_IOM_MPRT_ADBASE_MEMSPACE1B_ADDR 0xf70185a0 +#define CCU_IOM_MPRT_ADBASE_MEMSPACE1C_ADDR 0xf70185c0 +#define CCU_IOM_MPRT_ADBASE_MEMSPACE1D_ADDR 0xf70185e0 +#define CCU_IOM_MPRT_ADBASE_MEMSPACE1E_ADDR 0xf7018600 + +#define CCU_ADBASE_DI_MASK 0x00000010 + +#endif /* _SDRAM_S10_H_ */ diff --git a/drivers/ddr/altera/Makefile b/drivers/ddr/altera/Makefile index bdd2872..943b6cd 100644 --- a/drivers/ddr/altera/Makefile +++ b/drivers/ddr/altera/Makefile @@ -10,4 +10,5 @@

ifdef CONFIG_ALTERA_SDRAM obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram.o sequencer.o +obj-$(CONFIG_TARGET_SOCFPGA_STRATIX10) += sdram_s10.o endif diff --git a/drivers/ddr/altera/sdram_s10.c b/drivers/ddr/altera/sdram_s10.c new file mode 100644 index 0000000..c488caf --- /dev/null +++ b/drivers/ddr/altera/sdram_s10.c @@ -0,0 +1,382 @@ +/* + * Copyright (C) 2016-2017 Intel Corporation <www.intel.com> + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <errno.h> +#include <div64.h> +#include <asm/io.h> +#include <watchdog.h> +#include <asm/arch/sdram_s10.h> +#include <asm/arch/system_manager.h> +#include <asm/arch/reset_manager.h> + +DECLARE_GLOBAL_DATA_PTR; + +static const struct socfpga_ecc_hmc *socfpga_ecc_hmc_base = + (void *)SOCFPGA_SDR_ADDRESS; +static const struct socfpga_noc_ddr_scheduler *socfpga_noc_ddr_scheduler_base = + (void *)SOCFPGA_SDR_SCHEDULER_ADDRESS; +static const struct socfpga_io48_mmr *socfpga_io48_mmr_base = + (void *)SOCFPGA_HMC_MMR_IO48_ADDRESS; +static const struct socfpga_system_manager *sysmgr_regs = + (void *)SOCFPGA_SYSMGR_ADDRESS; + +#define DDR_CONFIG(A, B, C, R) ((A<<24)|(B<<16)|(C<<8)|R) + +/* The followring are the supported configurations */ +u32 ddr_config[] = { + /* DDR_CONFIG(Address order,Bank,Column,Row) */ + /* List for DDR3 or LPDDR3 (pinout order > chip, row, bank, column) */ + DDR_CONFIG(0, 3, 10, 12), + DDR_CONFIG(0, 3, 9, 13), + DDR_CONFIG(0, 3, 10, 13), + DDR_CONFIG(0, 3, 9, 14), + DDR_CONFIG(0, 3, 10, 14), + DDR_CONFIG(0, 3, 10, 15), + DDR_CONFIG(0, 3, 11, 14), + DDR_CONFIG(0, 3, 11, 15), + DDR_CONFIG(0, 3, 10, 16), + DDR_CONFIG(0, 3, 11, 16), + DDR_CONFIG(0, 3, 12, 15), /* 0xa */ + /* List for DDR4 only (pinout order > chip, bank, row, column) */ + DDR_CONFIG(1, 3, 10, 14), + DDR_CONFIG(1, 4, 10, 14), + DDR_CONFIG(1, 3, 10, 15), + DDR_CONFIG(1, 4, 10, 15), + DDR_CONFIG(1, 3, 10, 16), + DDR_CONFIG(1, 4, 10, 16), + DDR_CONFIG(1, 3, 10, 17), + DDR_CONFIG(1, 4, 10, 17), +}; + +#define DDR_CONFIG_ELEMENTS (sizeof(ddr_config)/sizeof(u32)) + +int match_ddr_conf(u32 ddr_conf) +{ + int i; + for (i = 0; i < DDR_CONFIG_ELEMENTS; i++) { + if (ddr_conf == ddr_config[i]) + return i; + } + return 0; +} + +static int emif_clear(void) +{ + u32 s2c, i; + + writel(0, &socfpga_ecc_hmc_base->rsthandshakectrl); + s2c = readl(&socfpga_ecc_hmc_base->rsthandshakestat) & + DDR_HMC_RSTHANDSHAKE_MASK; + + for (i = 1000; (i > 0) && s2c; i--) { + WATCHDOG_RESET(); + mdelay(1); + s2c = readl(&socfpga_ecc_hmc_base->rsthandshakestat) & + DDR_HMC_RSTHANDSHAKE_MASK; + } + return !s2c; +} + +static int emif_reset(void) +{ + u32 c2s, s2c, i; + + c2s = readl(&socfpga_ecc_hmc_base->rsthandshakectrl) & + DDR_HMC_RSTHANDSHAKE_MASK; + s2c = readl(&socfpga_ecc_hmc_base->rsthandshakestat) & + DDR_HMC_RSTHANDSHAKE_MASK; + + debug("DDR: c2s=%08x s2c=%08x nr0=%08x nr1=%08x nr2=%08x dst=%08x\n", + c2s, s2c, readl(&socfpga_io48_mmr_base->niosreserve0), + readl(&socfpga_io48_mmr_base->niosreserve1), + readl(&socfpga_io48_mmr_base->niosreserve2), + readl(&socfpga_io48_mmr_base->dramsts)); + + if (s2c && emif_clear()) { + printf("DDR: emif_clear() failed\n"); + return -1; + } + + puts("DDR: Triggerring emif_reset\n"); + writel(DDR_HMC_CORE2SEQ_INT_REQ, + &socfpga_ecc_hmc_base->rsthandshakectrl); + + for (i = 1000; i > 0; i--) { + /* if seq2core[3] = 0, we are good */ + if (!(readl(&socfpga_ecc_hmc_base->rsthandshakestat) & + DDR_HMC_SEQ2CORE_INT_RESP_MASK)) + break; + WATCHDOG_RESET(); + mdelay(1); + } + + if (!i) { + printf("DDR: failed to get ack from EMIF\n"); + return -2; + } + + if (emif_clear()) { + printf("DDR: emif_clear() failed\n"); + return -3; + } + + printf("DDR: emif_reset triggered successly\n"); + return 0; +} + +static int poll_hmc_clock_status(void) +{ + u32 status, i; + + for (i = 1000; i > 0; i--) { + status = readl(&sysmgr_regs->hmc_clk) & + SYSMGR_HMC_CLK_STATUS_MSK; + udelay(1); + if (status) + break; + WATCHDOG_RESET(); + } + return status; +} + +/** + * sdram_mmr_init_full() - Function to initialize SDRAM MMR + * + * Initialize the SDRAM MMR. + */ +int sdram_mmr_init_full(unsigned int unused) +{ + u32 update_value, io48_value, ddrioctl; + u32 i, j, cal_success; + + /* Enable access to DDR from CPU master */ + clrbits_le32(CCU_CPU0_MPRT_ADBASE_DDRREG_ADDR, CCU_ADBASE_DI_MASK); + clrbits_le32(CCU_CPU0_MPRT_ADBASE_MEMSPACE0_ADDR, CCU_ADBASE_DI_MASK); + clrbits_le32(CCU_CPU0_MPRT_ADBASE_MEMSPACE1A_ADDR, CCU_ADBASE_DI_MASK); + clrbits_le32(CCU_CPU0_MPRT_ADBASE_MEMSPACE1B_ADDR, CCU_ADBASE_DI_MASK); + clrbits_le32(CCU_CPU0_MPRT_ADBASE_MEMSPACE1C_ADDR, CCU_ADBASE_DI_MASK); + clrbits_le32(CCU_CPU0_MPRT_ADBASE_MEMSPACE1D_ADDR, CCU_ADBASE_DI_MASK); + clrbits_le32(CCU_CPU0_MPRT_ADBASE_MEMSPACE1E_ADDR, CCU_ADBASE_DI_MASK); + + /* Enable access to DDR from IO master */ + clrbits_le32(CCU_IOM_MPRT_ADBASE_MEMSPACE0_ADDR, CCU_ADBASE_DI_MASK); + clrbits_le32(CCU_IOM_MPRT_ADBASE_MEMSPACE1A_ADDR, CCU_ADBASE_DI_MASK); + clrbits_le32(CCU_IOM_MPRT_ADBASE_MEMSPACE1B_ADDR, CCU_ADBASE_DI_MASK); + clrbits_le32(CCU_IOM_MPRT_ADBASE_MEMSPACE1C_ADDR, CCU_ADBASE_DI_MASK); + clrbits_le32(CCU_IOM_MPRT_ADBASE_MEMSPACE1D_ADDR, CCU_ADBASE_DI_MASK); + clrbits_le32(CCU_IOM_MPRT_ADBASE_MEMSPACE1E_ADDR, CCU_ADBASE_DI_MASK); + + /* this enables nonsecure access to DDR */ + /* mpuregion0addr_limit */ + writel(0xFFFF0000, 0xF8020118); + writel(0x1F, 0xF802011c); + + /* nonmpuregion0addr_limit */ + writel(0xFFFF0000, 0xF8020198); + writel(0x1F, 0xF802019C); + + /* Enable mpuregion0enable and nonmpuregion0enable */ + writel(BIT(0) | BIT(8), 0xF8020100); + + /* Ensure HMC clock is running */ + if (!poll_hmc_clock_status()) { + puts("DDR: Error as HMC clock not running\n"); + return -1; + } + + /* release DDR scheduler from reset */ + socfpga_per_reset(SOCFPGA_RESET(SDR), 0); + + /* Try 3 times to do a calibration */ + for (i = 0; i < 3; i++) { + cal_success = readl(&socfpga_ecc_hmc_base->ddrcalstat) & + DDR_HMC_DDRCALSTAT_CAL_MSK; + /* A delay to wait for calibration bit to set */ + for (j = 0; (j < 1000) && !cal_success; j++) { + WATCHDOG_RESET(); + mdelay(1); + cal_success = readl(&socfpga_ecc_hmc_base->ddrcalstat) + & DDR_HMC_DDRCALSTAT_CAL_MSK; + } + + if (cal_success) + break; + else + emif_reset(); + } + + if (!cal_success) { + puts("DDR: Error as SDRAM calibration failed\n"); + return -1; + } + puts("DDR: Calibration success\n"); + + union ctrlcfg0_reg ctrlcfg0 = (union ctrlcfg0_reg) + readl(&socfpga_io48_mmr_base->ctrlcfg0); + union ctrlcfg1_reg ctrlcfg1 = (union ctrlcfg1_reg) + readl(&socfpga_io48_mmr_base->ctrlcfg1); + union dramaddrw_reg dramaddrw = (union dramaddrw_reg) + readl(&socfpga_io48_mmr_base->dramaddrw); + union dramtiming0_reg dramtim0 = (union dramtiming0_reg) + readl(&socfpga_io48_mmr_base->dramtiming0); + union caltiming0_reg caltim0 = (union caltiming0_reg) + readl(&socfpga_io48_mmr_base->caltiming0); + union caltiming1_reg caltim1 = (union caltiming1_reg) + readl(&socfpga_io48_mmr_base->caltiming1); + union caltiming2_reg caltim2 = (union caltiming2_reg) + readl(&socfpga_io48_mmr_base->caltiming2); + union caltiming3_reg caltim3 = (union caltiming3_reg) + readl(&socfpga_io48_mmr_base->caltiming3); + union caltiming4_reg caltim4 = (union caltiming4_reg) + readl(&socfpga_io48_mmr_base->caltiming4); + union caltiming9_reg caltim9 = (union caltiming9_reg) + readl(&socfpga_io48_mmr_base->caltiming9); + + /* + * Configure the DDR IO size [0xFFCFB008] + * niosreserve0: Used to indicate DDR width & + * bit[7:0] = Number of data bits (bit[6:5] 0x01=32bit, 0x10=64bit) + * bit[8] = 1 if user-mode OCT is present + * bit[9] = 1 if warm reset compiled into EMIF Cal Code + * bit[10] = 1 if warm reset is on during generation in EMIF Cal + * niosreserve1: IP ADCDS version encoded as 16 bit value + * bit[2:0] = Variant (0=not special,1=FAE beta, 2=Customer beta, + * 3=EAP, 4-6 are reserved) + * bit[5:3] = Service Pack # (e.g. 1) + * bit[9:6] = Minor Release # + * bit[14:10] = Major Release # + */ + update_value = readl(&socfpga_io48_mmr_base->niosreserve0); + writel(((update_value & 0xFF) >> 5), &socfpga_ecc_hmc_base->ddrioctrl); + ddrioctl = readl(&socfpga_ecc_hmc_base->ddrioctrl); + + /* enable HPS interface to HMC */ + writel(DDR_HMC_HPSINTFCSEL_ENABLE_MASK, + &socfpga_ecc_hmc_base->hpsintfcsel); + + /* Set the DDR Configuration */ + io48_value = DDR_CONFIG(ctrlcfg1.cfg_addr_order, + (dramaddrw.cfg_bank_addr_width + + dramaddrw.cfg_bank_group_addr_width), + dramaddrw.cfg_col_addr_width, + dramaddrw.cfg_row_addr_width); + + update_value = match_ddr_conf(io48_value); + if (update_value) + writel(update_value, + &socfpga_noc_ddr_scheduler_base->main_scheduler_ddrconf); + + /* Configure HMC dramaddrw */ + writel(readl(&socfpga_io48_mmr_base->dramaddrw), + &socfpga_ecc_hmc_base->dramaddrwidth); + + /* + * Configure DDR timing + * RDTOMISS = tRTP + tRP + tRCD - BL/2 + * WRTOMISS = WL + tWR + tRP + tRCD and + * WL = RL + BL/2 + 2 - rd-to-wr ; tWR = 15ns so... + * First part of equation is in memory clock units so divide by 2 + * for HMC clock units. 1066MHz is close to 1ns so use 15 directly. + * WRTOMISS = ((RL + BL/2 + 2 + tWR) >> 1)- rd-to-wr + tRP + tRCD + */ + update_value = caltim2.cfg_rd_to_pch + caltim4.cfg_pch_to_valid + + caltim0.cfg_act_to_rdwr - + (ctrlcfg0.cfg_ctrl_burst_len >> 2); + io48_value = (((dramtim0.cfg_tcl + 2 + DDR_TWR + + (ctrlcfg0.cfg_ctrl_burst_len >> 1)) >> 1) - + /* Up to here was in memory cycles so divide by 2 */ + caltim1.cfg_rd_to_wr + caltim0.cfg_act_to_rdwr + + caltim4.cfg_pch_to_valid); + + writel(((caltim0.cfg_act_to_act << DDR_SCHED_DDRTIMING_ACTTOACT_OFFSET) | + (update_value << DDR_SCHED_DDRTIMING_RDTOMISS_OFFSET) | + (io48_value << DDR_SCHED_DDRTIMING_WRTOMISS_OFFSET) | + ((ctrlcfg0.cfg_ctrl_burst_len >> 2) << + DDR_SCHED_DDRTIMING_BURSTLEN_OFFSET) | + (caltim1.cfg_rd_to_wr << DDR_SCHED_DDRTIMING_RDTOWR_OFFSET) | + (caltim3.cfg_wr_to_rd << DDR_SCHED_DDRTIMING_WRTORD_OFFSET) | + (((ddrioctl == 1) ? 1 : 0) << + DDR_SCHED_DDRTIMING_BWRATIO_OFFSET)), + &socfpga_noc_ddr_scheduler_base->main_scheduler_ddrtiming); + + /* Configure DDR mode [precharge = 0] */ + writel(((ddrioctl ? 0 : 1) << DDR_SCHED_DDRMOD_BWRATIOEXTENDED_OFFSET), + &socfpga_noc_ddr_scheduler_base->main_scheduler_ddrmode); + + /* Configure the read latency */ + writel((dramtim0.cfg_tcl >> 1) + DDR_READ_LATENCY_DELAY, + &socfpga_noc_ddr_scheduler_base->main_scheduler_readlatency); + + /* + * Configuring timing values concerning activate commands + * [FAWBANK alway 1 because always 4 bank DDR] + */ + writel(((caltim0.cfg_act_to_act_db << DDR_SCHED_ACTIVATE_RRD_OFFSET) | + (caltim9.cfg_4_act_to_act << DDR_SCHED_ACTIVATE_FAW_OFFSET) | + (DDR_ACTIVATE_FAWBANK << DDR_SCHED_ACTIVATE_FAWBANK_OFFSET)), + &socfpga_noc_ddr_scheduler_base->main_scheduler_activate); + + /* + * Configuring timing values concerning device to device data bus + * ownership change + */ + writel(((caltim1.cfg_rd_to_rd_dc << + DDR_SCHED_DEVTODEV_BUSRDTORD_OFFSET) | + (caltim1.cfg_rd_to_wr_dc << + DDR_SCHED_DEVTODEV_BUSRDTOWR_OFFSET) | + (caltim3.cfg_wr_to_rd_dc << + DDR_SCHED_DEVTODEV_BUSWRTORD_OFFSET)), + &socfpga_noc_ddr_scheduler_base->main_scheduler_devtodev); + + /* Enable or disable the SDRAM ECC */ + if (ctrlcfg1.cfg_ctrl_enable_ecc) { + setbits_le32(&socfpga_ecc_hmc_base->eccctrl, + (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK | + DDR_HMC_ECCCTL_CNT_RST_SET_MSK | + DDR_HMC_ECCCTL_ECC_EN_SET_MSK)); + clrbits_le32(&socfpga_ecc_hmc_base->eccctrl, + (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK | + DDR_HMC_ECCCTL_CNT_RST_SET_MSK)); + setbits_le32(&socfpga_ecc_hmc_base->eccctrl2, + (DDR_HMC_ECCCTL2_RMW_EN_SET_MSK | + DDR_HMC_ECCCTL2_AWB_EN_SET_MSK)); + } else { + clrbits_le32(&socfpga_ecc_hmc_base->eccctrl, + (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK | + DDR_HMC_ECCCTL_CNT_RST_SET_MSK | + DDR_HMC_ECCCTL_ECC_EN_SET_MSK)); + clrbits_le32(&socfpga_ecc_hmc_base->eccctrl2, + (DDR_HMC_ECCCTL2_RMW_EN_SET_MSK | + DDR_HMC_ECCCTL2_AWB_EN_SET_MSK)); + } + + puts("DDR: HMC init success\n"); + return 0; +} + +/** + * sdram_calculate_size() - Calculate SDRAM size + * + * Calculate SDRAM device size based on SDRAM controller parameters. + * Size is specified in bytes. + */ +unsigned long sdram_calculate_size(void) +{ + union dramaddrw_reg dramaddrw = + (union dramaddrw_reg)readl(&socfpga_io48_mmr_base->dramaddrw); + + u32 size = (1 << (dramaddrw.cfg_cs_addr_width + + dramaddrw.cfg_bank_group_addr_width + + dramaddrw.cfg_bank_addr_width + + dramaddrw.cfg_row_addr_width + + dramaddrw.cfg_col_addr_width)); + + size *= (2 << (readl(&socfpga_ecc_hmc_base->ddrioctrl) & + DDR_HMC_DDRIOCTRL_IOSIZE_MSK)); + + return size; +}

From: Chin Liang See chin.liang.see@intel.com

Add build support for Stratix SoC

Signed-off-by: Chin Liang See chin.liang.see@intel.com --- arch/arm/Kconfig | 8 +- arch/arm/mach-socfpga/Kconfig | 13 ++ configs/socfpga_stratix10_defconfig | 39 ++++++ include/configs/socfpga_stratix10_socdk.h | 216 ++++++++++++++++++++++++++++++ 4 files changed, 273 insertions(+), 3 deletions(-) create mode 100644 configs/socfpga_stratix10_defconfig create mode 100644 include/configs/socfpga_stratix10_socdk.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index bb64b9c..13dd144 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -655,21 +655,23 @@ config ARCH_SNAPDRAGON

config ARCH_SOCFPGA bool "Altera SOCFPGA family" - select CPU_V7 + select CPU_V7 if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 + select ARM64 if TARGET_SOCFPGA_STRATIX10 select SUPPORT_SPL select OF_CONTROL select SPL_OF_CONTROL select DM select DM_SPI_FLASH select DM_SPI - select ENABLE_ARM_SOC_BOOT0_HOOK + select ENABLE_ARM_SOC_BOOT0_HOOK if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 select ARCH_EARLY_INIT_R select ARCH_MISC_INIT select SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION - select SYS_THUMB_BUILD + select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 imply CMD_MTDPARTS imply CRC32_VERIFY imply FAT_WRITE + select SPL_SEPARATE_BSS if TARGET_SOCFPGA_STRATIX10

config ARCH_SUNXI bool "Support sunxi (Allwinner) SoCs" diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 45e5379..03ab956 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -49,6 +49,12 @@ config TARGET_SOCFPGA_GEN5 bool select ALTERA_SDRAM

+config TARGET_SOCFPGA_STRATIX10 + bool + select ARMV8_MULTIENTRY + select ARMV8_SPIN_TABLE + select ARMV8_SET_SMPEN + choice prompt "Altera SOCFPGA board select" optional @@ -86,6 +92,10 @@ config TARGET_SOCFPGA_SR1500 bool "SR1500 (Cyclone V)" select TARGET_SOCFPGA_CYCLONE5

+config TARGET_SOCFPGA_STRATIX10_SOCDK + bool "Intel SOCFPGA SoCDK (Stratix 10)" + select TARGET_SOCFPGA_STRATIX10 + config TARGET_SOCFPGA_TERASIC_DE0_NANO bool "Terasic DE0-Nano-Atlas (Cyclone V)" select TARGET_SOCFPGA_CYCLONE5 @@ -116,12 +126,14 @@ config SYS_BOARD default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES default "sr1500" if TARGET_SOCFPGA_SR1500 + default "stratix10-socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA

config SYS_VENDOR default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK + default "altera" if TARGET_SOCFPGA_STRATIX10_SOCDK default "aries" if TARGET_SOCFPGA_ARIES_MCVEVK default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA @@ -145,6 +157,7 @@ config SYS_CONFIG_NAME default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500 + default "socfpga_stratix10_socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA

endif diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig new file mode 100644 index 0000000..e5a7a69 --- /dev/null +++ b/configs/socfpga_stratix10_defconfig @@ -0,0 +1,39 @@ +CONFIG_ARM=y +CONFIG_ARCH_SOCFPGA=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SPL_FAT_SUPPORT=y +CONFIG_TARGET_SOCFPGA_STRATIX10_SOCDK=y +CONFIG_IDENT_STRING="socfpga_stratix10" +CONFIG_DEFAULT_DEVICE_TREE="socfpga_stratix10_socdk" +CONFIG_BOOTDELAY=5 +CONFIG_SYS_PROMPT="SOCFPGA_STRATIX10 # " +CONFIG_CMD_CACHE=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_FS_GENERIC=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MII=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PING=y +CONFIG_CMD_SF=y +CONFIG_SPL=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_DM_MMC=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_DFU_MMC=y +CONFIG_MMC_DW=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_CADENCE_QSPI=y +CONFIG_DM_ETH=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_SYS_NS16550=y +CONFIG_USE_TINY_PRINTF=y diff --git a/include/configs/socfpga_stratix10_socdk.h b/include/configs/socfpga_stratix10_socdk.h new file mode 100644 index 0000000..0d955f8 --- /dev/null +++ b/include/configs/socfpga_stratix10_socdk.h @@ -0,0 +1,216 @@ +/* + * Copyright (C) 2016-2017 Intel Corporation <www.intel.com> + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef __CONFIG_SOCFGPA_STRATIX10_H__ +#define __CONFIG_SOCFGPA_STRATIX10_H__ + +#include <asm/arch/base_addr_s10.h> + +/* + * U-Boot general configurations + */ +#define CONFIG_SYS_TEXT_BASE 0x1000 +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE +#define CONFIG_LOADADDR 0x80000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_REMAKE_ELF +#define CPU_RELEASE_ADDR 0x80 +#define CONFIG_SYS_CACHELINE_SIZE 64 + +/* + * U-Boot console configurations + */ +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_CBSIZE 2048 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_LONGHELP +#define CONFIG_AUTO_COMPLETE /* Command auto complete */ +#define CONFIG_CMDLINE_EDITING /* Command history etc */ + +/* Extend size of kernel image for uncompression */ +#define CONFIG_SYS_BOOTM_LEN (32 * 1024 * 1024) + +/* + * U-Boot run time memory configurations + */ +#define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x40000 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR \ + + CONFIG_SYS_INIT_RAM_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_SP_ADDR) +#define CONFIG_SYS_MALLOC_LEN (5 * 1024 * 1024) + +/* + * U-Boot display configurations + */ +#define CONFIG_DISPLAY_BOARDINFO_LATE + +/* + * U-Boot environment configurations + */ +#define CONFIG_ENV_SIZE 0x1000 +#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */ +#define CONFIG_ENV_OFFSET 512 /* just after the MBR */ + +/* + * QSPI support + */ + #ifdef CONFIG_CADENCE_QSPI +/* Enable it if you want to use dual-stacked mode */ +#undef CONFIG_SF_DUAL_FLASH +/*#define CONFIG_QSPI_RBF_ADDR 0x720000*/ + +/* Flash device info */ +#define CONFIG_SF_DEFAULT_SPEED (50000000) +#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_3 | SPI_RX_QUAD) +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_CS 0 + +/*#define CONFIG_ENV_IS_IN_SPI_FLASH*/ +#ifdef CONFIG_ENV_IS_IN_SPI_FLASH +#undef CONFIG_ENV_OFFSET +#undef CONFIG_ENV_SIZE +#define CONFIG_ENV_OFFSET 0x710000 +#define CONFIG_ENV_SIZE (4 * 1024) +#define CONFIG_ENV_SECT_SIZE (4 * 1024) +#endif /* CONFIG_ENV_IS_IN_SPI_FLASH */ + +/*#define CONFIG_BOOT_FLASH_TYPE "qspi"*/ +#define CONFIG_CQSPI_DECODER 0 + +#ifndef CONFIG_SPL_BUILD +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#define MTDIDS_DEFAULT "nor0=ff705000.spi.0" +#endif /* CONFIG_SPL_BUILD */ + +/* 533MHz, TODO: Get from SDM */ +#define CONFIG_CQSPI_REF_CLK 400000000 + +#endif /* CONFIG_CADENCE_QSPI */ + +/* + * Boot arguments passed to the boot command. The value of + * CONFIG_BOOTARGS goes into the environment value "bootargs". + * Do note the value will overide also the chosen node in FDT blob. + */ +#define CONFIG_BOOTARGS "earlycon" +#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "bootfile=Image\0" \ + "fdt_addr=8000000\0" \ + "fdtimage=socfpga_stratix10_socdk.dtb\0" \ + "mmcroot=/dev/mmcblk0p2\0" \ + "mmcboot=setenv bootargs " CONFIG_BOOTARGS \ + " root=${mmcroot} rw rootwait;" \ + "booti ${loadaddr} - ${fdt_addr}\0" \ + "mmcload=mmc rescan;" \ + "load mmc 0:1 ${loadaddr} ${bootfile};" \ + "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" + +/* + * Generic Interrupt Controller Definitions + */ +#define CONFIG_GICV2 + +/* + * External memory configurations + */ +#define PHYS_SDRAM_1 0x0 +#define PHYS_SDRAM_1_SIZE (1 * 1024 * 1024 * 1024) +#define CONFIG_SYS_SDRAM_BASE 0 +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_MEMTEST_START 0 +#define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE - 0x200000 + +/* + * SDRAM controller + */ +#define CONFIG_ALTERA_SDRAM + +/* + * Serial / UART configurations + */ +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE -4 +#define CONFIG_SYS_NS16550_COM1 SOCFPGA_UART0_ADDRESS +#define CONFIG_SYS_NS16550_CLK 100000000 +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 +/* always write in 32 bit manner */ +#define CONFIG_SYS_NS16550_MEM32 +#define CONFIG_SYS_NS16550_REG_SIZE -4 + +/* + * Timer & watchdog configurations + */ +#define COUNTER_FREQUENCY 400000000 + + +/* + * SDMMC configurations + */ +#ifdef CONFIG_CMD_MMC +#define CONFIG_BOUNCE_BUFFER +#define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 +#endif +/* + * Flash configurations + */ +#define CONFIG_SYS_MAX_FLASH_BANKS 1 + +/* Ethernet on SoC (EMAC) */ +#if defined(CONFIG_CMD_NET) +#define CONFIG_PHY_MICREL +#define CONFIG_PHY_MICREL_KSZ9031 +#define CONFIG_DW_ALTDESCRIPTOR +#define CONFIG_MII +#define CONFIG_AUTONEG_TIMEOUT (15 * CONFIG_SYS_HZ) +#define CONFIG_PHY_GIGE +#endif /* CONFIG_CMD_NET */ + + +/* + * SPL memory layout + * + * On chip RAM + * 0xFFE0_0000 ...... Start of OCRAM + * SPL code, rwdata + * 0xFFEx_xxxx ...... Top of stack (grows down) + * 0xFFEy_yyyy ...... Global Data + * 0xFFEz_zzzz ...... Malloc prior relocation (size CONFIG_SYS_MALLOC_F_LEN) + * 0xFFE3_FFFF ...... End of OCRAM + * + * SDRAM + * 0x0000_0000 ...... Start of SDRAM_1 + * unused / empty space for image loading + * Size 64MB ...... MALLOC (size CONFIG_SYS_SPL_MALLOC_SIZE) + * Size 1MB ...... BSS (size CONFIG_SPL_BSS_MAX_SIZE) + * 0x8000_0000 ...... End of SDRAM_1 (assume 2GB) + * + */ +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR +#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE +#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR +#define CONFIG_SPL_BSS_MAX_SIZE 0x100000 /* 1 MB */ +#define CONFIG_SPL_BSS_START_ADDR (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE \ + - CONFIG_SPL_BSS_MAX_SIZE) +#define CONFIG_SYS_SPL_MALLOC_SIZE (CONFIG_SYS_MALLOC_LEN) +#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR \ + - CONFIG_SYS_SPL_MALLOC_SIZE) +#define CONFIG_SPL_SPI_LOAD +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x400000 + +/* SPL SDMMC boot support */ +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img" + +#endif /* __CONFIG_H */