This command uses AMP boot mode to boot the omap5 device. it is used to run two different software on each dedicated core without using hypervisor. A typical example is: Core0 uses Linux or Android and Core1 uses QNX or baremetal app. It is also used for benchmarking the hypervisor performance where hypervisor is run in the SMP mode and runs two different operating systems or baremetal app on top of it.

Signed-off-by: Bharat Gohil ghl.bhrt@gmail.com Cc: Tom Rini trini@konsulko.com --- arch/arm/include/asm/arch-omap5/hardware.h | 5 +++ common/Kconfig | 6 +++ common/Makefile | 1 + common/cmd_omap5_ampboot.c | 59 ++++++++++++++++++++++++++++++ configs/dra7xx_evm_defconfig | 3 ++ 5 files changed, 74 insertions(+) create mode 100644 common/cmd_omap5_ampboot.c

diff --git a/arch/arm/include/asm/arch-omap5/hardware.h b/arch/arm/include/asm/arch-omap5/hardware.h index f7011b4..540d9c3 100644 --- a/arch/arm/include/asm/arch-omap5/hardware.h +++ b/arch/arm/include/asm/arch-omap5/hardware.h @@ -23,4 +23,9 @@ /* GPMC Base address */ #define GPMC_BASE 0x50000000

+/* Secondary core control registers */ +#define AUXCORE_BOOT1 0x48281804 +#define AUXCORE_BOOT0 0x48281800 + + #endif diff --git a/common/Kconfig b/common/Kconfig index 40cd69e..fbb0353 100644 --- a/common/Kconfig +++ b/common/Kconfig @@ -474,6 +474,12 @@ config CMD_SOUND sound init - set up sound system sound play - play a sound

+config CMD_OMAP5_AMPBOOT + bool "omap5 ampboot" + depends on OMAP54XX + help + This command start secondary core1 from dual CoretexA15 omap5. + endmenu

menu "Boot timing" diff --git a/common/Makefile b/common/Makefile index d6c1d48..0734dd9 100644 --- a/common/Makefile +++ b/common/Makefile @@ -264,6 +264,7 @@ obj-$(CONFIG_FIT_SIGNATURE) += image-sig.o obj-$(CONFIG_IO_TRACE) += iotrace.o obj-y += memsize.o obj-y += stdio.o +obj-$(CONFIG_CMD_OMAP5_AMPBOOT) += cmd_omap5_ampboot.o

# This option is not just y/n - it can have a numeric value ifdef CONFIG_FASTBOOT_FLASH_MMC_DEV diff --git a/common/cmd_omap5_ampboot.c b/common/cmd_omap5_ampboot.c new file mode 100644 index 0000000..212a815 --- /dev/null +++ b/common/cmd_omap5_ampboot.c @@ -0,0 +1,59 @@ +/* + * cmd_omap5_ampboot.c + * + * Copyright (c) 2015 Bharat Gohil (ghl.bhrt@gmail.com). + * + * Licensed under the GPL-2 or later. + */ + +/* This command uses AMP boot mode to boot the omap5 device. it is used to run +* two different software on each dedicated core without using hypervisor. +* A typical example is: Core0 uses Linux or Android and Core1 uses QNX or + baremetal app. +* It is also used for benchmarking the hypervisor performance where +* hypervisor is run in the SMP mode and runs two different operating systems +* or baremetal app on top of it. +*/ + +#include <common.h> +#include <command.h> +#include <asm/io.h> +#include <asm/hardware.h> + +static inline void dsb_sev(void) +{ + __asm__ __volatile__("dsb\n" + "sev\n" + "nop"); +} + +int ampboot(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) +{ + unsigned long addr; + char *endp; + + if (argc < 2) + return -1; + + addr = simple_strtoul(argv[1], &endp, 16); + if (*argv[1] == 0 || *endp != 0) + return -1; + + /* 'addr' is starting address of core1 in the dual ARM A15 sub-system */ + writel(addr, AUXCORE_BOOT1); + + /* 'AUXCORE_BOOT0' is a status register for core1. Writing a non-zero value + * to this register indicates that, AUXCORE_BOOT1 register has valid start + * address for core1 + */ + writel(0x20, AUXCORE_BOOT0); + + /* Kick secondary core1 */ + dsb_sev(); + + return 0; +} + +U_BOOT_CMD(ampboot, 2, 1, ampboot, + "ampboot <image address>", + "Start Core1 at specified address where binary image is stored"); + diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig index 463a7e2..af6f69d 100644 --- a/configs/dra7xx_evm_defconfig +++ b/configs/dra7xx_evm_defconfig @@ -7,5 +7,8 @@ CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1" # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NFS is not set +CONFIG_CMD_MISC=y +# CONFIG_CMD_TIMER is not set +CONFIG_CMD_OMAP5_AMPBOOT=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y