On 2023/4/22 09:23, Jonas Karlman wrote:

Add bootph-all prop to xin24m clock node, it is referenced by cru node.

Signed-off-by: Jonas Karlman jonas@kwiboo.se

Reviewed-by: Kever Yang kever.yang@rock-chips.com

Thanks, - Kever

---

arch/arm/dts/rk356x-u-boot.dtsi | 5 +++++ 1 file changed, 5 insertions(+)

diff --git a/arch/arm/dts/rk356x-u-boot.dtsi b/arch/arm/dts/rk356x-u-boot.dtsi index 0a764ce5119c..a1c2d03c52f0 100644 --- a/arch/arm/dts/rk356x-u-boot.dtsi +++ b/arch/arm/dts/rk356x-u-boot.dtsi @@ -34,6 +34,11 @@ }; };

+&xin24m {

• bootph-all;
• status = "okay";

+};

• &cru { bootph-all; status = "okay";

On 2023/4/22 09:23, Jonas Karlman wrote:

Use the same prop as linux to control the use of fifo or dma mode. Also add a u-boot,spl-sfc-no-dma prop to control the same in SPL.

Signed-off-by: Jonas Karlman jonas@kwiboo.se

Reviewed-by: Kever Yang kever.yang@rock-chips.com

Thanks, - Kever

---

drivers/spi/rockchip_sfc.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/drivers/spi/rockchip_sfc.c b/drivers/spi/rockchip_sfc.c index 851a6482985b..1c26802c618e 100644 --- a/drivers/spi/rockchip_sfc.c +++ b/drivers/spi/rockchip_sfc.c @@ -227,10 +227,12 @@ static int rockchip_sfc_ofdata_to_platdata(struct udevice *bus) struct rockchip_sfc *sfc = dev_get_plat(bus);

sfc->regbase = dev_read_addr_ptr(bus);

• if (ofnode_read_bool(dev_ofnode(bus), "sfc-no-dma"))

• sfc->use_dma = false;
  

• else

• sfc->use_dma = true;
  

• sfc->use_dma = !dev_read_bool(bus, "rockchip,sfc-no-dma");

+#ifdef CONFIG_SPL_BUILD

• if (sfc->use_dma)

• sfc->use_dma = !dev_read_bool(bus, "u-boot,spl-sfc-no-dma");
  

+#endif

#if CONFIG_IS_ENABLED(CLK) int ret;

On 2023/4/22 09:23, Jonas Karlman wrote:

Update defconfig for rk3566-radxa-cm3-io with new defaults. Also add missing supported mmc modes to sdhci node.

Remove the SPL_ROCKCHIP_BACK_TO_BROM=y option, SPL is expected to load next stage from a FIT image and then jump to next stage not back to BootRom.

Add CONFIG_SPL_FIT_SIGNATURE=y to let SPL verify an auto generated hash of FIT images. This help indicate if there is an issue loading any of the images to DRAM or SRAM.

Extend SPL_MAX_SIZE to 0x40000, SPL is loaded to 0x0 and TF-A is loaded to 0x40000, use the space in between as SPL_MAX_SIZE.

Add config option to include useful gpio cmd.

Remove the CONFIG_NET_RANDOM_ETHADDR=y option, ethaddr and eth1addr is set based on cpuid read from OTP.

Filter out assigned-clock props with CONFIG_OF_SPL_REMOVE_PROPS, U-Boot proper will read and configure assigned-clock props.

Add CONFIG_SYS_NS16550_MEM32=y to use 32bit access of serial register.

Signed-off-by: Jonas Karlman jonas@kwiboo.se

Reviewed-by: Kever Yang kever.yang@rock-chips.com

Thanks, - Kever

---

arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi | 5 +++++ configs/radxa-cm3-io-rk3566_defconfig | 9 +++++---- 2 files changed, 10 insertions(+), 4 deletions(-)

diff --git a/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi b/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi index d183e935754d..a8c31fecafd8 100644 --- a/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi +++ b/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi @@ -11,6 +11,11 @@ }; };

+&sdhci {

• cap-mmc-highspeed;
• mmc-ddr-1_8v;

+};

• &uart2 { clock-frequency = <24000000>; bootph-all;

diff --git a/configs/radxa-cm3-io-rk3566_defconfig b/configs/radxa-cm3-io-rk3566_defconfig index 1df9cab79d51..dfaacbc8839e 100644 --- a/configs/radxa-cm3-io-rk3566_defconfig +++ b/configs/radxa-cm3-io-rk3566_defconfig @@ -10,9 +10,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 CONFIG_DEFAULT_DEVICE_TREE="rk3566-radxa-cm3-io" CONFIG_ROCKCHIP_RK3568=y -CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y -CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_STACK_R_ADDR=0x600000 CONFIG_TARGET_EVB_RK3568=y @@ -23,11 +21,12 @@ CONFIG_SYS_LOAD_ADDR=0xc00800 CONFIG_DEBUG_UART=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y CONFIG_SPL_LOAD_FIT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-radxa-cm3-io.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_MAX_SIZE=0x20000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x4000000 @@ -36,6 +35,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x4000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_ATF=y +CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -46,7 +46,7 @@ CONFIG_CMD_REGULATOR=y # CONFIG_SPL_DOS_PARTITION is not set CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIVE=y -CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_SPL_REGMAP=y CONFIG_SPL_SYSCON=y CONFIG_SPL_CLK=y @@ -70,6 +70,7 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_SPL_RAM=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y

On 2023/4/22 09:23, Jonas Karlman wrote:

Enable pinctrl for sdmmc and sdhci in SPL to support loading of FIT image from SD and eMMC storage when booting from SPI NOR flash.

Signed-off-by: Jonas Karlman jonas@kwiboo.se

Reviewed-by: Kever Yang kever.yang@rock-chips.com

Thanks, - Kever

---

arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi | 56 ++++++++++++++++++++ configs/radxa-cm3-io-rk3566_defconfig | 3 +- 2 files changed, 58 insertions(+), 1 deletion(-)

diff --git a/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi b/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi index a8c31fecafd8..d2ee19aaa8d5 100644 --- a/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi +++ b/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi @@ -11,6 +11,62 @@ }; };

+&pinctrl {

• bootph-pre-ram;

+};

+&pcfg_pull_up {

• bootph-pre-ram;

+};

+&pcfg_pull_none {

• bootph-pre-ram;

+};

+&pcfg_pull_up_drv_level_2 {

• bootph-pre-ram;

+};

+&uart2m0_xfer {

• bootph-pre-ram;

+};

+&sdmmc0_bus4 {

• bootph-pre-ram;

+};

+&sdmmc0_clk {

• bootph-pre-ram;

+};

+&sdmmc0_cmd {

• bootph-pre-ram;

+};

+&sdmmc0_det {

• bootph-pre-ram;

+};

+&sdmmc0_pwren {

• bootph-pre-ram;

+};

+&emmc_bus8 {

• bootph-pre-ram;

+};

+&emmc_clk {

• bootph-pre-ram;

+};

+&emmc_cmd {

• bootph-pre-ram;

+};

+&emmc_datastrobe {

• bootph-pre-ram;

+};

• &sdhci { cap-mmc-highspeed; mmc-ddr-1_8v;

diff --git a/configs/radxa-cm3-io-rk3566_defconfig b/configs/radxa-cm3-io-rk3566_defconfig index dfaacbc8839e..dd1dd36a59b7 100644 --- a/configs/radxa-cm3-io-rk3566_defconfig +++ b/configs/radxa-cm3-io-rk3566_defconfig @@ -46,7 +46,7 @@ CONFIG_CMD_REGULATOR=y # CONFIG_SPL_DOS_PARTITION is not set CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIVE=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_SPL_REGMAP=y CONFIG_SPL_SYSCON=y CONFIG_SPL_CLK=y @@ -63,6 +63,7 @@ CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_SPL_PINCTRL=y CONFIG_DM_PMIC=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_RK8XX=y

On 2023/4/22 09:23, Jonas Karlman wrote:

Update defconfig for rk3568-evb with new defaults.

Remove the SPL_ROCKCHIP_BACK_TO_BROM=y option, SPL is expected to load next stage from a FIT image and then jump to next stage not back to BootRom.

Add CONFIG_SPL_FIT_SIGNATURE=y to let SPL verify an auto generated hash of FIT images. This help indicate if there is an issue loading any of the images to DRAM or SRAM.

Extend SPL_MAX_SIZE to 0x40000, SPL is loaded to 0x0 and TF-A is loaded to 0x40000, use the space in between as SPL_MAX_SIZE.

Add config options to include useful gpio, i2c, pmic and regulator cmd.

Remove the CONFIG_NET_RANDOM_ETHADDR=y option, ethaddr and eth1addr is set based on cpuid read from OTP.

Filter out assigned-clock props with CONFIG_OF_SPL_REMOVE_PROPS, U-Boot proper will read and configure assigned-clock props.

Add config options to enable support for the RK809 PMIC.

Signed-off-by: Jonas Karlman jonas@kwiboo.se

Reviewed-by: Kever Yang kever.yang@rock-chips.com

Thanks, - Kever

---

configs/evb-rk3568_defconfig | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-)

diff --git a/configs/evb-rk3568_defconfig b/configs/evb-rk3568_defconfig index c929bac509c0..0b4fc52e263d 100644 --- a/configs/evb-rk3568_defconfig +++ b/configs/evb-rk3568_defconfig @@ -10,9 +10,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 CONFIG_DEFAULT_DEVICE_TREE="rk3568-evb" CONFIG_ROCKCHIP_RK3568=y -CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y -CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_STACK_R_ADDR=0x600000 CONFIG_TARGET_EVB_RK3568=y @@ -23,11 +21,12 @@ CONFIG_SYS_LOAD_ADDR=0xc00800 CONFIG_DEBUG_UART=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y CONFIG_SPL_LOAD_FIT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-evb.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_MAX_SIZE=0x20000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x4000000 @@ -36,13 +35,17 @@ CONFIG_SPL_BSS_MAX_SIZE=0x4000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_ATF=y +CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y # CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y # CONFIG_SPL_DOS_PARTITION is not set CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIVE=y -CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_SPL_REGMAP=y CONFIG_SPL_SYSCON=y CONFIG_SPL_CLK=y @@ -57,7 +60,9 @@ CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y -CONFIG_REGULATOR_PWM=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_SPL_RAM=y CONFIG_BAUDRATE=1500000

On 2023/4/22 09:23, Jonas Karlman wrote:

Update defconfig for rk3568-rock-3a with new defaults.

Remove the SPL_ROCKCHIP_BACK_TO_BROM=y option, SPL is expected to load next stage from a FIT image and then jump to next stage not back to BootRom.

Add CONFIG_SPL_FIT_SIGNATURE=y to let SPL verify an auto generated hash of FIT images. This help indicate if there is an issue loading any of the images to DRAM or SRAM.

Extend SPL_MAX_SIZE to 0x40000, SPL is loaded to 0x0 and TF-A is loaded to 0x40000, use the space in between as SPL_MAX_SIZE.

Add config option to include useful gpio cmd.

Remove the CONFIG_NET_RANDOM_ETHADDR=y option, ethaddr and eth1addr is set based on cpuid read from OTP.

Filter out assigned-clock props with CONFIG_OF_SPL_REMOVE_PROPS, U-Boot proper will read and configure assigned-clock props.

Remove the CONFIG_SPL_PMIC_RK8XX=y option, the pmic is not used in SPL.

Signed-off-by: Jonas Karlman jonas@kwiboo.se

Reviewed-by: Kever Yang kever.yang@rock-chips.com

Thanks, - Kever

---

configs/rock-3a-rk3568_defconfig | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/configs/rock-3a-rk3568_defconfig b/configs/rock-3a-rk3568_defconfig index f0db15baa30e..5126feb6b11d 100644 --- a/configs/rock-3a-rk3568_defconfig +++ b/configs/rock-3a-rk3568_defconfig @@ -10,9 +10,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 CONFIG_DEFAULT_DEVICE_TREE="rk3568-rock-3a" CONFIG_ROCKCHIP_RK3568=y -CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y -CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_STACK_R_ADDR=0x600000 CONFIG_TARGET_EVB_RK3568=y @@ -23,11 +21,12 @@ CONFIG_SYS_LOAD_ADDR=0xc00800 CONFIG_DEBUG_UART=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y CONFIG_SPL_LOAD_FIT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-rock-3a.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_MAX_SIZE=0x20000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x4000000 @@ -36,6 +35,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x4000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_ATF=y +CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -46,7 +46,7 @@ CONFIG_CMD_REGULATOR=y # CONFIG_SPL_DOS_PARTITION is not set CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIVE=y -CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_SPL_REGMAP=y CONFIG_SPL_SYSCON=y CONFIG_SPL_CLK=y @@ -65,7 +65,6 @@ CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y CONFIG_DM_PMIC=y CONFIG_PMIC_RK8XX=y -CONFIG_SPL_PMIC_RK8XX=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_SPL_RAM=y

On 2023/4/22 09:23, Jonas Karlman wrote:

Enable pinctrl for sdmmc and sdhci in SPL to support loading of FIT image from SD and eMMC storage when booting from SPI NOR flash.

Signed-off-by: Jonas Karlman jonas@kwiboo.se

Reviewed-by: Kever Yang kever.yang@rock-chips.com

Thanks, - Kever

---

arch/arm/dts/rk3568-rock-3a-u-boot.dtsi | 52 +++++++++++++++++++++++++ configs/rock-3a-rk3568_defconfig | 3 +- 2 files changed, 54 insertions(+), 1 deletion(-)

diff --git a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi index 801c91af5b41..b2af3b1dbed6 100644 --- a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi +++ b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi @@ -13,6 +13,58 @@ }; };

+&pinctrl {

• bootph-pre-ram;

+};

+&pcfg_pull_up {

• bootph-pre-ram;

+};

+&pcfg_pull_none {

• bootph-pre-ram;

+};

+&pcfg_pull_up_drv_level_2 {

• bootph-pre-ram;

+};

+&uart2m0_xfer {

• bootph-pre-ram;

+};

+&sdmmc0_bus4 {

• bootph-pre-ram;

+};

+&sdmmc0_clk {

• bootph-pre-ram;

+};

+&sdmmc0_cmd {

• bootph-pre-ram;

+};

+&sdmmc0_det {

• bootph-pre-ram;

+};

+&emmc_bus8 {

• bootph-pre-ram;

+};

+&emmc_clk {

• bootph-pre-ram;

+};

+&emmc_cmd {

• bootph-pre-ram;

+};

+&emmc_datastrobe {

• bootph-pre-ram;

+};

• &sdhci { cap-mmc-highspeed; mmc-ddr-1_8v;

diff --git a/configs/rock-3a-rk3568_defconfig b/configs/rock-3a-rk3568_defconfig index 5126feb6b11d..2e556dc2c1a2 100644 --- a/configs/rock-3a-rk3568_defconfig +++ b/configs/rock-3a-rk3568_defconfig @@ -46,7 +46,7 @@ CONFIG_CMD_REGULATOR=y # CONFIG_SPL_DOS_PARTITION is not set CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIVE=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_SPL_REGMAP=y CONFIG_SPL_SYSCON=y CONFIG_SPL_CLK=y @@ -63,6 +63,7 @@ CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_SPL_PINCTRL=y CONFIG_DM_PMIC=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_RK8XX=y

On 2023/4/22 09:23, Jonas Karlman wrote:

Add sfc and flash node to device tree and config options to enable support for booting from SPI NOR flash on Radxa ROCK 3 Model A.

Unlike prior generation SoCs the BootRom in RK3568 can read all data and look for idbloader at 0x8000, same as on SD and eMMC.

Use the rksd format and modify the mkimage offset to generate a bootable u-boot-rockchip-spi.bin that can be written to 0x0 of SPI NOR flash. The FIT image is loaded from 0x60000.

=> sf probe SF: Detected mx25u12835f with page size 256 Bytes, erase size 4 KiB, total 16 MiB

=> load mmc 1:1 10000000 u-boot-rockchip-spi.bin 1384448 bytes read in 119 ms (11.1 MiB/s)

=> sf update $fileaddr 0 $filesize device 0 offset 0x0, size 0x152000 1179648 bytes written, 204800 bytes skipped in 9.901s, speed 143185 B/s

Signed-off-by: Jonas Karlman jonas@kwiboo.se

Reviewed-by: Kever Yang kever.yang@rock-chips.com

Thanks, - Kever

---

arch/arm/dts/rk3568-rock-3a-u-boot.dtsi | 25 +++++++++++++++++++++++++ arch/arm/dts/rk356x-u-boot.dtsi | 11 +++++++++++ configs/rock-3a-rk3568_defconfig | 10 ++++++++++ 3 files changed, 46 insertions(+)

diff --git a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi index b2af3b1dbed6..7cd2dc80c317 100644 --- a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi +++ b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi @@ -7,6 +7,10 @@ #include "rk356x-u-boot.dtsi"

/ {

• aliases {

• spi0 = &sfc;
  

• };
• chosen { stdout-path = &uart2; u-boot,spl-boot-order = "same-as-spl", &sdmmc0, &sdhci;

@@ -33,6 +37,10 @@ bootph-pre-ram; };

+&fspi_pins {

• bootph-pre-ram;

+};

• &sdmmc0_bus4 { bootph-pre-ram; };

@@ -65,6 +73,23 @@ bootph-pre-ram; };

+&sfc {

• bootph-pre-ram;
• u-boot,spl-sfc-no-dma;
• #address-cells = <1>;
• #size-cells = <0>;
• status = "okay";
• flash@0 {

• bootph-pre-ram;
  

• compatible = "jedec,spi-nor";
  

• reg = <0>;
  

• spi-max-frequency = <24000000>;
  

• spi-rx-bus-width = <4>;
  

• spi-tx-bus-width = <1>;
  

• };

+};

• &sdhci { cap-mmc-highspeed; mmc-ddr-1_8v;

diff --git a/arch/arm/dts/rk356x-u-boot.dtsi b/arch/arm/dts/rk356x-u-boot.dtsi index a1c2d03c52f0..c340c2bba6ff 100644 --- a/arch/arm/dts/rk356x-u-boot.dtsi +++ b/arch/arm/dts/rk356x-u-boot.dtsi @@ -68,3 +68,14 @@ bootph-pre-ram; status = "okay"; };

+#ifdef CONFIG_ROCKCHIP_SPI_IMAGE +&binman {

• simple-bin-spi {

• mkimage {
  

• 	args = "-n", CONFIG_SYS_SOC, "-T", "rksd";
  

• 	offset = <0x8000>;
  

• };
  

• };

+}; +#endif diff --git a/configs/rock-3a-rk3568_defconfig b/configs/rock-3a-rk3568_defconfig index 2e556dc2c1a2..64864a300153 100644 --- a/configs/rock-3a-rk3568_defconfig +++ b/configs/rock-3a-rk3568_defconfig @@ -8,15 +8,20 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 +CONFIG_SF_DEFAULT_SPEED=24000000 +CONFIG_SF_DEFAULT_MODE=0x2000 CONFIG_DEFAULT_DEVICE_TREE="rk3568-rock-3a" CONFIG_ROCKCHIP_RK3568=y CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y +CONFIG_ROCKCHIP_SPI_IMAGE=y CONFIG_SPL_SERIAL=y CONFIG_SPL_STACK_R_ADDR=0x600000 CONFIG_TARGET_EVB_RK3568=y CONFIG_SPL_STACK=0x400000 CONFIG_DEBUG_UART_BASE=0xFE660000 CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0xc00800 CONFIG_DEBUG_UART=y CONFIG_FIT=y @@ -34,6 +39,8 @@ CONFIG_SPL_BSS_MAX_SIZE=0x4000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_STACK_R=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000 CONFIG_SPL_ATF=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y @@ -59,6 +66,8 @@ CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_XTX=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y @@ -72,6 +81,7 @@ CONFIG_SPL_RAM=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y +CONFIG_ROCKCHIP_SFC=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y

On 2023/4/22 09:23, Jonas Karlman wrote:

Like other Rockchip SoCs, DM_RESET and DM_REGULATOR_FIXED is useful across RK3588 platform. Select them from arch Kconfig.

Signed-off-by: Jonas Karlman jonas@kwiboo.se

Reviewed-by: Kever Yang kever.yang@rock-chips.com

Thanks, - Kever

---

arch/arm/mach-rockchip/Kconfig | 2 ++ configs/evb-rk3588_defconfig | 2 -- configs/neu6a-io-rk3588_defconfig | 1 - configs/rock5b-rk3588_defconfig | 2 -- 4 files changed, 2 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 327779a79818..9d6d20bf8ed6 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -311,6 +311,8 @@ config ROCKCHIP_RK3588 select REGMAP select SYSCON select BOARD_LATE_INIT

• select DM_REGULATOR_FIXED
• select DM_RESET imply SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF imply ROCKCHIP_COMMON_BOARD imply OF_LIBFDT_OVERLAY

diff --git a/configs/evb-rk3588_defconfig b/configs/evb-rk3588_defconfig index ddeadb8a760f..8760671a1772 100644 --- a/configs/evb-rk3588_defconfig +++ b/configs/evb-rk3588_defconfig @@ -9,10 +9,8 @@ CONFIG_NR_DRAM_BANKS=2 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 CONFIG_DEFAULT_DEVICE_TREE="rk3588-evb1-v10" -CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3588=y CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y -CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_STACK_R_ADDR=0x600000 CONFIG_TARGET_EVB_RK3588=y diff --git a/configs/neu6a-io-rk3588_defconfig b/configs/neu6a-io-rk3588_defconfig index fb1ce4c1746f..09729a0ea429 100644 --- a/configs/neu6a-io-rk3588_defconfig +++ b/configs/neu6a-io-rk3588_defconfig @@ -9,7 +9,6 @@ CONFIG_NR_DRAM_BANKS=2 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 CONFIG_DEFAULT_DEVICE_TREE="rk3588-edgeble-neu6a-io" -CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3588=y CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y CONFIG_SPL_SERIAL=y diff --git a/configs/rock5b-rk3588_defconfig b/configs/rock5b-rk3588_defconfig index c57de5a5be02..2e034b724cc9 100644 --- a/configs/rock5b-rk3588_defconfig +++ b/configs/rock5b-rk3588_defconfig @@ -9,7 +9,6 @@ CONFIG_NR_DRAM_BANKS=2 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 CONFIG_DEFAULT_DEVICE_TREE="rk3588-rock-5b" -CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3588=y CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y @@ -67,7 +66,6 @@ CONFIG_GMAC_ROCKCHIP=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_SPL_PINCTRL=y CONFIG_REGULATOR_PWM=y -CONFIG_DM_REGULATOR_FIXED=y CONFIG_PWM_ROCKCHIP=y CONFIG_SPL_RAM=y CONFIG_BAUDRATE=1500000

On 2023/4/22 09:23, Jonas Karlman wrote:

Update defconfig for rk3588-evb with new defaults.

Add CONFIG_SPL_FIT_SIGNATURE=y to let SPL verify an auto generated hash of FIT images. This help indicate if there is an issue loading any of the images to DRAM or SRAM.

Extend SPL_MAX_SIZE to 0x40000, SPL is loaded to 0x0 and TF-A is loaded to 0x40000, use the space in between as SPL_MAX_SIZE.

Add config options to include useful gpio and regulator cmd.

Remove the CONFIG_NET_RANDOM_ETHADDR=y option, ethaddr and eth1addr is set based on cpuid read from OTP.

Disable CONFIG_SPL_MMC_SDHCI_SDMA option to use PIO to load TF-A into DRAM and SRAM.

Remove CONFIG_DEBUG_UART_ANNOUNCE=y to remove debug messages.

Add CONFIG_SYS_NS16550_MEM32=y to use 32bit access of serial register.

Signed-off-by: Jonas Karlman jonas@kwiboo.se

Reviewed-by: Kever Yang kever.yang@rock-chips.com

Thanks, - Kever

---

configs/evb-rk3588_defconfig | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/configs/evb-rk3588_defconfig b/configs/evb-rk3588_defconfig index 8760671a1772..70e435b1f745 100644 --- a/configs/evb-rk3588_defconfig +++ b/configs/evb-rk3588_defconfig @@ -21,12 +21,13 @@ CONFIG_SYS_LOAD_ADDR=0xc00800 CONFIG_DEBUG_UART=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y CONFIG_SPL_LOAD_FIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-evb1-v10.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_MAX_SIZE=0x20000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x4000000 @@ -35,14 +36,15 @@ CONFIG_SPL_BSS_MAX_SIZE=0x4000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_ATF=y +CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y # CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_REGULATOR=y # CONFIG_SPL_DOS_PARTITION is not set CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIVE=y CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_REGMAP=y CONFIG_SPL_SYSCON=y CONFIG_SPL_CLK=y @@ -54,6 +56,7 @@ CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SDMA=y +# CONFIG_SPL_MMC_SDHCI_SDMA is not set CONFIG_MMC_SDHCI_ROCKCHIP=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y @@ -62,6 +65,6 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_SPL_RAM=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 -CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_ERRNO_STR=y

On 2023/4/22 09:23, Jonas Karlman wrote:

Update defconfig for rk3588-rock-5b with new defaults.

Remove the SPL_ROCKCHIP_BACK_TO_BROM=y option, SPL is expected to load next stage from a FIT image and then jump to next stage not back to BootRom.

Extend SPL_MAX_SIZE to 0x40000, SPL is loaded to 0x0 and TF-A is loaded to 0x40000, use the space in between as SPL_MAX_SIZE.

Add config option to include useful gpio cmd.

Remove the CONFIG_NET_RANDOM_ETHADDR=y option, ethaddr and eth1addr is set based on cpuid read from OTP.

Add CONFIG_SYS_NS16550_MEM32=y to use 32bit access of serial register.

Signed-off-by: Jonas Karlman jonas@kwiboo.se

Reviewed-by: Kever Yang kever.yang@rock-chips.com

Thanks, - Kever

---

configs/rock5b-rk3588_defconfig | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/configs/rock5b-rk3588_defconfig b/configs/rock5b-rk3588_defconfig index 2e034b724cc9..2f0a74ee5559 100644 --- a/configs/rock5b-rk3588_defconfig +++ b/configs/rock5b-rk3588_defconfig @@ -10,9 +10,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 CONFIG_DEFAULT_DEVICE_TREE="rk3588-rock-5b" CONFIG_ROCKCHIP_RK3588=y -CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y -CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_STACK_R_ADDR=0x600000 CONFIG_TARGET_ROCK5B_RK3588=y @@ -29,7 +27,7 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-rock-5b.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_MAX_SIZE=0x20000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x4000000 @@ -38,6 +36,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x4000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_ATF=y +CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y @@ -47,7 +46,6 @@ CONFIG_CMD_REGULATOR=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIVE=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_REGMAP=y CONFIG_SPL_SYSCON=y CONFIG_SPL_CLK=y @@ -70,6 +68,7 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_SPL_RAM=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y

On 2023/4/22 09:23, Jonas Karlman wrote:

Enable pinctrl for sdhci in SPL to support loading of FIT image from SD and eMMC storage when booting from SPI NOR flash.

Signed-off-by: Jonas Karlman jonas@kwiboo.se

Reviewed-by: Kever Yang kever.yang@rock-chips.com

Thanks, - Kever

---

arch/arm/dts/rk3588-rock-5b-u-boot.dtsi | 28 +++++++++++++++++++++++++ 1 file changed, 28 insertions(+)

diff --git a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi index 715328d204c2..4bbc19058c90 100644 --- a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi +++ b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi @@ -61,6 +61,14 @@ bootph-all; };

+&pcfg_pull_none {

• bootph-all;

+};

+&uart2m0_xfer {

• bootph-all;

+};

• &sdmmc_bus4 { bootph-all; };

@@ -77,6 +85,26 @@ bootph-all; };

+&emmc_bus8 {

• bootph-all;

+};

+&emmc_clk {

• bootph-all;

+};

+&emmc_cmd {

• bootph-all;

+};

+&emmc_data_strobe {

• bootph-all;

+};

+&emmc_rstnout {

• bootph-all;

+};

• &usb_host0_ehci { companion = <&usb_host0_ohci>; phys = <&u2phy2_host>;

On 2023/4/22 09:23, Jonas Karlman wrote:

Add sfc and flash node to device tree and config options to enable support for booting from SPI NOR flash on Radxa ROCK 5 Model B.

Signed-off-by: Jonas Karlman jonas@kwiboo.se

Reviewed-by: Kever Yang kever.yang@rock-chips.com

Thanks, - Kever

---

arch/arm/dts/rk3588-rock-5b-u-boot.dtsi | 24 ++++++++++++++++++++++++ arch/arm/dts/rk3588s-u-boot.dtsi | 20 ++++++++++++++++++++ arch/arm/mach-rockchip/rk3588/rk3588.c | 1 + configs/rock5b-rk3588_defconfig | 10 ++++++++++ 4 files changed, 55 insertions(+)

diff --git a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi index 4bbc19058c90..b63dd40deb6d 100644 --- a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi +++ b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi @@ -11,6 +11,7 @@ / { aliases { mmc1 = &sdmmc;

• spi0 = &sfc;
  

  };

  chosen {

@@ -43,6 +44,25 @@ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_data_strobe &emmc_rstnout>; };

+&sfc {

• bootph-pre-ram;
• u-boot,spl-sfc-no-dma;
• pinctrl-names = "default";
• pinctrl-0 = <&fspim2_pins>;
• #address-cells = <1>;
• #size-cells = <0>;
• status = "okay";
• flash@0 {

• bootph-pre-ram;
  

• compatible = "jedec,spi-nor";
  

• reg = <0>;
  

• spi-max-frequency = <24000000>;
  

• spi-rx-bus-width = <4>;
  

• spi-tx-bus-width = <1>;
  

• };

+};

• &pinctrl { bootph-all;

@@ -69,6 +89,10 @@ bootph-all; };

+&fspim2_pins {

• bootph-all;

+};

• &sdmmc_bus4 { bootph-all; };

diff --git a/arch/arm/dts/rk3588s-u-boot.dtsi b/arch/arm/dts/rk3588s-u-boot.dtsi index cd7e6cb50ee2..d8a471a37fd1 100644 --- a/arch/arm/dts/rk3588s-u-boot.dtsi +++ b/arch/arm/dts/rk3588s-u-boot.dtsi @@ -104,6 +104,15 @@ }; };

• sfc: spi@fe2b0000 {

• compatible = "rockchip,sfc";
  

• reg = <0x0 0xfe2b0000 0x0 0x4000>;
  

• interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH 0>;
  

• clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
  

• clock-names = "clk_sfc", "hclk_sfc";
  

• status = "disabled";
  

• };
• otp: nvmem@fecc0000 { compatible = "rockchip,rk3588-otp"; reg = <0x0 0xfecc0000 0x0 0x400>;

@@ -164,3 +173,14 @@ &ioc { bootph-pre-ram; };

+#ifdef CONFIG_ROCKCHIP_SPI_IMAGE +&binman {

• simple-bin-spi {

• mkimage {
  

• 	args = "-n", CONFIG_SYS_SOC, "-T", "rksd";
  

• 	offset = <0x8000>;
  

• };
  

• };

+}; +#endif diff --git a/arch/arm/mach-rockchip/rk3588/rk3588.c b/arch/arm/mach-rockchip/rk3588/rk3588.c index 18e67b5ca9b2..0e85893e0096 100644 --- a/arch/arm/mach-rockchip/rk3588/rk3588.c +++ b/arch/arm/mach-rockchip/rk3588/rk3588.c @@ -41,6 +41,7 @@ const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { [BROM_BOOTSOURCE_EMMC] = "/mmc@fe2e0000", [BROM_BOOTSOURCE_SPINOR] = "/spi@fe2b0000/flash@0", [BROM_BOOTSOURCE_SD] = "/mmc@fe2c0000",

• [6] = "/spi@fe2b0000/flash@0", };

  static struct mm_region rk3588_mem_map[] = {

diff --git a/configs/rock5b-rk3588_defconfig b/configs/rock5b-rk3588_defconfig index 2f0a74ee5559..e6a903853fb7 100644 --- a/configs/rock5b-rk3588_defconfig +++ b/configs/rock5b-rk3588_defconfig @@ -8,15 +8,20 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 +CONFIG_SF_DEFAULT_SPEED=24000000 +CONFIG_SF_DEFAULT_MODE=0x2000 CONFIG_DEFAULT_DEVICE_TREE="rk3588-rock-5b" CONFIG_ROCKCHIP_RK3588=y CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y +CONFIG_ROCKCHIP_SPI_IMAGE=y CONFIG_SPL_SERIAL=y CONFIG_SPL_STACK_R_ADDR=0x600000 CONFIG_TARGET_ROCK5B_RK3588=y CONFIG_SPL_STACK=0x400000 CONFIG_DEBUG_UART_BASE=0xFEB50000 CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0xc00800 CONFIG_DEBUG_UART=y CONFIG_FIT=y @@ -35,6 +40,8 @@ CONFIG_SPL_BSS_MAX_SIZE=0x4000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_STACK_R=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000 CONFIG_SPL_ATF=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y @@ -59,6 +66,8 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SDMA=y # CONFIG_SPL_MMC_SDHCI_SDMA is not set CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_XTX=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y @@ -69,6 +78,7 @@ CONFIG_SPL_RAM=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y +CONFIG_ROCKCHIP_SFC=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y

Hi Eugen,

On 2023-05-16 17:06, Eugen Hristev wrote:

Hi Jonas,

On 5/9/23 14:16, Kever Yang wrote:

...

On 2023/4/22 09:23, Jonas Karlman wrote:

...

Add sfc and flash node to device tree and config options to enable support for booting from SPI NOR flash on Radxa ROCK 5 Model B.

Signed-off-by: Jonas Karlman jonas@kwiboo.se

Reviewed-by: Kever Yang kever.yang@rock-chips.com

Thanks,

• Kever

...

---

arch/arm/dts/rk3588-rock-5b-u-boot.dtsi | 24 ++++++++++++++++++++++++   arch/arm/dts/rk3588s-u-boot.dtsi        | 20 ++++++++++++++++++++   arch/arm/mach-rockchip/rk3588/rk3588.c  |  1 +   configs/rock5b-rk3588_defconfig         | 10 ++++++++++   4 files changed, 55 insertions(+)

diff --git a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi index 4bbc19058c90..b63dd40deb6d 100644 --- a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi +++ b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi @@ -11,6 +11,7 @@   / {       aliases {           mmc1 = &sdmmc; +        spi0 = &sfc;       };       chosen { @@ -43,6 +44,25 @@       pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_data_strobe &emmc_rstnout>;   }; +&sfc { +    bootph-pre-ram;

Any reason why the sfc and flash are pre-ram and the pins bootph-all ?

This used to be u-boot,dm-spl and was later replaced with bootph-pre-ram.

For fspim2_pins I used the same bootph as the other pins. Not sure why the pins use bootph-all to begin with, sdmmc and sdhci use bootph-pre-ram in rk3588s-u-boot.dtsi.

...

...

+    u-boot,spl-sfc-no-dma; +    pinctrl-names = "default"; +    pinctrl-0 = <&fspim2_pins>; +    #address-cells = <1>; +    #size-cells = <0>; +    status = "okay";

+    flash@0 { +        bootph-pre-ram; +        compatible = "jedec,spi-nor"; +        reg = <0>; +        spi-max-frequency = <24000000>; +        spi-rx-bus-width = <4>; +        spi-tx-bus-width = <1>; +    }; +};

&pinctrl {       bootph-all; @@ -69,6 +89,10 @@       bootph-all;   }; +&fspim2_pins { +    bootph-all; +};

&sdmmc_bus4 {       bootph-all;   }; diff --git a/arch/arm/dts/rk3588s-u-boot.dtsi b/arch/arm/dts/rk3588s-u-boot.dtsi index cd7e6cb50ee2..d8a471a37fd1 100644 --- a/arch/arm/dts/rk3588s-u-boot.dtsi +++ b/arch/arm/dts/rk3588s-u-boot.dtsi @@ -104,6 +104,15 @@           };       }; +    sfc: spi@fe2b0000 { +        compatible = "rockchip,sfc"; +        reg = <0x0 0xfe2b0000 0x0 0x4000>; +        interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH 0>; +        clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; +        clock-names = "clk_sfc", "hclk_sfc"; +        status = "disabled"; +    };

otp: nvmem@fecc0000 {           compatible = "rockchip,rk3588-otp";           reg = <0x0 0xfecc0000 0x0 0x400>; @@ -164,3 +173,14 @@   &ioc {       bootph-pre-ram;   };

+#ifdef CONFIG_ROCKCHIP_SPI_IMAGE +&binman { +    simple-bin-spi { +        mkimage { +            args = "-n", CONFIG_SYS_SOC, "-T", "rksd"; +            offset = <0x8000>;

What is this offset referring to ?

This offset is referring to the normal mmc 32 KiB offset that idbloader is normally written to. I used the offset prop so that the u-boot-rockchip-spi.bin can be written to offset 0 of spi similar as is currently done for rk3399.

...

...

+        }; +    }; +}; +#endif diff --git a/arch/arm/mach-rockchip/rk3588/rk3588.c b/arch/arm/mach-rockchip/rk3588/rk3588.c index 18e67b5ca9b2..0e85893e0096 100644 --- a/arch/arm/mach-rockchip/rk3588/rk3588.c +++ b/arch/arm/mach-rockchip/rk3588/rk3588.c @@ -41,6 +41,7 @@ const char * const boot_devices[BROM_LAST_BOOTSOURCE

• 1] = {

[BROM_BOOTSOURCE_EMMC] = "/mmc@fe2e0000",       [BROM_BOOTSOURCE_SPINOR] = "/spi@fe2b0000/flash@0",       [BROM_BOOTSOURCE_SD] = "/mmc@fe2c0000", +    [6] = "/spi@fe2b0000/flash@0",

Is this '6' meaning something in particular ? or just the next number in line ?

The bootrom on rk3588 use value 6 when booting from the spi flash on my ROCK 5B, normally bootrom have used value 3 (BROM_BOOTSOURCE_SPINOR) on rk356x and earlier socs.

I have no idea what we should call this BOOTSOURCE, could not find any define in vendor u-boot to help give this a proper name.

Kever: Any insights into what this value should be called?

...

...

};   static struct mm_region rk3588_mem_map[] = { diff --git a/configs/rock5b-rk3588_defconfig b/configs/rock5b-rk3588_defconfig index 2f0a74ee5559..e6a903853fb7 100644 --- a/configs/rock5b-rk3588_defconfig +++ b/configs/rock5b-rk3588_defconfig @@ -8,15 +8,20 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y   CONFIG_NR_DRAM_BANKS=2   CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y   CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 +CONFIG_SF_DEFAULT_SPEED=24000000 +CONFIG_SF_DEFAULT_MODE=0x2000

Any reason for changing the default mode ?

Default speed and mode is changed to match the speed and mode used in the device tree. SPL use these Kconfig instead of reading the speed and mode from fdt blob.

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CONFIG_DEFAULT_DEVICE_TREE="rk3588-rock-5b"   CONFIG_ROCKCHIP_RK3588=y   CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y +CONFIG_ROCKCHIP_SPI_IMAGE=y   CONFIG_SPL_SERIAL=y   CONFIG_SPL_STACK_R_ADDR=0x600000   CONFIG_TARGET_ROCK5B_RK3588=y   CONFIG_SPL_STACK=0x400000   CONFIG_DEBUG_UART_BASE=0xFEB50000   CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI=y   CONFIG_SYS_LOAD_ADDR=0xc00800   CONFIG_DEBUG_UART=y   CONFIG_FIT=y @@ -35,6 +40,8 @@ CONFIG_SPL_BSS_MAX_SIZE=0x4000   # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set   # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set   CONFIG_SPL_STACK_R=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000

I have a feeling the default is 0x80000, do you have any reason for the change to 0x60000 ?

The default is probably set for rk3399 that requires double space for idbloader because bootrom only read first 2 KiB of every 4 KiB page. To not waste usable space I used the same offset that was used by multiple rk3399 configs:

u-boot,spl-payload-offset = <0x60000>; /* @ 384KB */

SPI flash layout would look something like:

idbloader: @ 32 KiB - TPL: current ddr init blob use around 54 KiB - SPL: max 256 KiB FIT payload: @ 384 KiB

Should mean we have at least 96 KiB for TPL.

Regards, Jonas

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CONFIG_SPL_ATF=y   CONFIG_CMD_GPIO=y   CONFIG_CMD_GPT=y @@ -59,6 +66,8 @@ CONFIG_MMC_SDHCI=y   CONFIG_MMC_SDHCI_SDMA=y   # CONFIG_SPL_MMC_SDHCI_SDMA is not set   CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_XTX=y   CONFIG_ETH_DESIGNWARE=y   CONFIG_GMAC_ROCKCHIP=y   CONFIG_PHY_ROCKCHIP_INNO_USB2=y @@ -69,6 +78,7 @@ CONFIG_SPL_RAM=y   CONFIG_BAUDRATE=1500000   CONFIG_DEBUG_UART_SHIFT=2   CONFIG_SYS_NS16550_MEM32=y +CONFIG_ROCKCHIP_SFC=y   CONFIG_SYSRESET=y   CONFIG_USB=y   CONFIG_USB_EHCI_HCD=y

On 2023-05-16 21:13, Eugen Hristev wrote:

On 5/16/23 20:38, Jonas Karlman wrote:

...

Hi Eugen,

On 2023-05-16 17:06, Eugen Hristev wrote:

...

Hi Jonas,

On 5/9/23 14:16, Kever Yang wrote:

...

On 2023/4/22 09:23, Jonas Karlman wrote:

...

Add sfc and flash node to device tree and config options to enable support for booting from SPI NOR flash on Radxa ROCK 5 Model B.

Signed-off-by: Jonas Karlman jonas@kwiboo.se

Reviewed-by: Kever Yang kever.yang@rock-chips.com

Thanks,

• Kever

...

---

arch/arm/dts/rk3588-rock-5b-u-boot.dtsi | 24 ++++++++++++++++++++++++   arch/arm/dts/rk3588s-u-boot.dtsi        | 20 ++++++++++++++++++++   arch/arm/mach-rockchip/rk3588/rk3588.c  |  1 +   configs/rock5b-rk3588_defconfig         | 10 ++++++++++   4 files changed, 55 insertions(+)

diff --git a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi index 4bbc19058c90..b63dd40deb6d 100644 --- a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi +++ b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi @@ -11,6 +11,7 @@   / {       aliases {           mmc1 = &sdmmc; +        spi0 = &sfc;       };       chosen { @@ -43,6 +44,25 @@       pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_data_strobe &emmc_rstnout>;   }; +&sfc { +    bootph-pre-ram;

Any reason why the sfc and flash are pre-ram and the pins bootph-all ?

This used to be u-boot,dm-spl and was later replaced with bootph-pre-ram.

Right... but bootph-pre-ram means that the node is available in SPL right ? But it will not be available 'post-ram' ?

I was under the assumption that a node would be available at any later stage, re-reading the dt-schema and checking Makefile I can now see that nodes will only be available in:

TPL: nodes having bootph-all or bootph-pre-sram SPL: nodes having bootph-all or bootph-pre-ram U-Boot proper: all nodes regardless of any bootph prop

...

For fspim2_pins I used the same bootph as the other pins. Not sure why the pins use bootph-all to begin with, sdmmc and sdhci use bootph-pre-ram in rk3588s-u-boot.dtsi.

Because out of my understanding, the pins should be available in all bootstages, hence 'bootph-all' , they are needed all the time.

Fully agree and will have to change a few to bootph-all for RK3568 in a v2 series.

Please correct me if I am wrong, I am not very familiar with these new names yet.

But 'pre-ram' suggests (at least to me) availability only in the initial stage (SPL)

Otherwise what's the difference between bootph-all and bootph-pre-ram ? Maybe that difference would enlighten me

After reading up on the bootph props I think the following could be good use for the Rockchip platform, where TPL main purpose is to init DRAM and SPL main purpose is to load U-Boot proper/TF-A from storage:

- bootph-all for e.g. clock, ram, pinctrl and debug uart related nodes. - bootph-pre-ram for any remaining node related to where U-Boot proper/TF-A could be loaded from.

Sorry for the long noise

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+    u-boot,spl-sfc-no-dma; +    pinctrl-names = "default"; +    pinctrl-0 = <&fspim2_pins>; +    #address-cells = <1>; +    #size-cells = <0>; +    status = "okay";

+    flash@0 { +        bootph-pre-ram; +        compatible = "jedec,spi-nor"; +        reg = <0>; +        spi-max-frequency = <24000000>; +        spi-rx-bus-width = <4>; +        spi-tx-bus-width = <1>; +    }; +};

&pinctrl {       bootph-all; @@ -69,6 +89,10 @@       bootph-all;   }; +&fspim2_pins { +    bootph-all; +};

&sdmmc_bus4 {       bootph-all;   }; diff --git a/arch/arm/dts/rk3588s-u-boot.dtsi b/arch/arm/dts/rk3588s-u-boot.dtsi index cd7e6cb50ee2..d8a471a37fd1 100644 --- a/arch/arm/dts/rk3588s-u-boot.dtsi +++ b/arch/arm/dts/rk3588s-u-boot.dtsi @@ -104,6 +104,15 @@           };       }; +    sfc: spi@fe2b0000 { +        compatible = "rockchip,sfc"; +        reg = <0x0 0xfe2b0000 0x0 0x4000>; +        interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH 0>; +        clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; +        clock-names = "clk_sfc", "hclk_sfc"; +        status = "disabled"; +    };

otp: nvmem@fecc0000 {           compatible = "rockchip,rk3588-otp";           reg = <0x0 0xfecc0000 0x0 0x400>; @@ -164,3 +173,14 @@   &ioc {       bootph-pre-ram;   };

+#ifdef CONFIG_ROCKCHIP_SPI_IMAGE +&binman { +    simple-bin-spi { +        mkimage { +            args = "-n", CONFIG_SYS_SOC, "-T", "rksd"; +            offset = <0x8000>;

What is this offset referring to ?

This offset is referring to the normal mmc 32 KiB offset that idbloader is normally written to. I used the offset prop so that the u-boot-rockchip-spi.bin can be written to offset 0 of spi similar as is currently done for rk3399.

Oh. I get it. thanks ! So it's the offset of 64 sectors that the rockchip tool needs.

I tried to write the u-boot-rockchip-spi.bin at offset 64 sectors, and it boots into the SPL, but cannot read the FIT. I tried to write it at offset 0, and then it boots correctly. Interesting behavior.

Possible other offsets then 64 sectors could be used, having idbloader at sector 0 did not seem to work on RK3568 but matching the mmc offset seemed to get my rk3568 device booting :-)

I think bootrom look for the idbloader header at multiple different offsets. So with u-boot-rockchip-spi.bin written at 64 sector offset bootrom will find and load TPL+SPL but SPL will not find FIT at the configured offset, CONFIG_SYS_SPI_U_BOOT_OFFS.

Do you have to specify here the offset for the FIT, in binman ? Or is it taken from CONFIG_SYS_SPI_U_BOOT_OFFS automatically ?

Correct, binman fit/u-boot-img node is using CONFIG_SYS_SPI_U_BOOT_OFFS for the offset in u-boot-rockchip-spi.bin.

arch/arm/dts/rockchip-u-boot.dtsi: offset = <CONFIG_SYS_SPI_U_BOOT_OFFS>;

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...

...

...

+        }; +    }; +}; +#endif diff --git a/arch/arm/mach-rockchip/rk3588/rk3588.c b/arch/arm/mach-rockchip/rk3588/rk3588.c index 18e67b5ca9b2..0e85893e0096 100644 --- a/arch/arm/mach-rockchip/rk3588/rk3588.c +++ b/arch/arm/mach-rockchip/rk3588/rk3588.c @@ -41,6 +41,7 @@ const char * const boot_devices[BROM_LAST_BOOTSOURCE

• 1] = {

[BROM_BOOTSOURCE_EMMC] = "/mmc@fe2e0000",       [BROM_BOOTSOURCE_SPINOR] = "/spi@fe2b0000/flash@0",       [BROM_BOOTSOURCE_SD] = "/mmc@fe2c0000", +    [6] = "/spi@fe2b0000/flash@0",

Is this '6' meaning something in particular ? or just the next number in line ?

The bootrom on rk3588 use value 6 when booting from the spi flash on my ROCK 5B, normally bootrom have used value 3 (BROM_BOOTSOURCE_SPINOR) on rk356x and earlier socs.

I have no idea what we should call this BOOTSOURCE, could not find any define in vendor u-boot to help give this a proper name.

Either this is a BOOTSOURCE_SPINOR_RK3588 specific, or the RK3588 calls some other device SPINOR, and this one (the sfc) something else. I remember seeing some other flash controllers in the dtsi of the SoC, maybe those are also bootable ?

True, could be that there are some more bootable devices on RK3588, will add and use BROM_BOOTSOURCE_SPINOR_RK3588 for v2.

...

Kever: Any insights into what this value should be called?

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};   static struct mm_region rk3588_mem_map[] = { diff --git a/configs/rock5b-rk3588_defconfig b/configs/rock5b-rk3588_defconfig index 2f0a74ee5559..e6a903853fb7 100644 --- a/configs/rock5b-rk3588_defconfig +++ b/configs/rock5b-rk3588_defconfig @@ -8,15 +8,20 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y   CONFIG_NR_DRAM_BANKS=2   CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y   CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 +CONFIG_SF_DEFAULT_SPEED=24000000 +CONFIG_SF_DEFAULT_MODE=0x2000

Any reason for changing the default mode ?

Default speed and mode is changed to match the speed and mode used in the device tree. SPL use these Kconfig instead of reading the speed and mode from fdt blob.

SPL should have its own blob, is the read from fdt not yet implemented ?

I had an issue on RK3568 where clk driver need an exact clock rate to configure fspi clock. Noticed that fspi was probed with Kconfig values instead of the values used in device tree. With default speed configured booting from spi flash started working on RK3568. Setting the default mode that would be used by U-Boot proper also seem appropriate.

Did same for RK3588 even if it may not strictly be needed.

common/spl/spl_spi.c: spi_flash_probe(sf_bus, sf_cs, CONFIG_SF_DEFAULT_SPEED, CONFIG_SF_DEFAULT_MODE);

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CONFIG_DEFAULT_DEVICE_TREE="rk3588-rock-5b"   CONFIG_ROCKCHIP_RK3588=y   CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y +CONFIG_ROCKCHIP_SPI_IMAGE=y   CONFIG_SPL_SERIAL=y   CONFIG_SPL_STACK_R_ADDR=0x600000   CONFIG_TARGET_ROCK5B_RK3588=y   CONFIG_SPL_STACK=0x400000   CONFIG_DEBUG_UART_BASE=0xFEB50000   CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI=y   CONFIG_SYS_LOAD_ADDR=0xc00800   CONFIG_DEBUG_UART=y   CONFIG_FIT=y @@ -35,6 +40,8 @@ CONFIG_SPL_BSS_MAX_SIZE=0x4000   # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set   # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set   CONFIG_SPL_STACK_R=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000

I have a feeling the default is 0x80000, do you have any reason for the change to 0x60000 ?

The default is probably set for rk3399 that requires double space for idbloader because bootrom only read first 2 KiB of every 4 KiB page. To not waste usable space I used the same offset that was used by multiple rk3399 configs:

u-boot,spl-payload-offset = <0x60000>; /* @ 384KB */

SPI flash layout would look something like:

idbloader: @ 32 KiB

• TPL: current ddr init blob use around 54 KiB
• SPL: max 256 KiB

FIT payload: @ 384 KiB

Should mean we have at least 96 KiB for TPL.

Looks good. I am only interested if this is different than from other devices, such that we keep a similar layout, and not diverge.

From what I could tell this is matching at least some rk3399 devices,

it is also matching a few rk356x devices I have prepared in my tree.

Regards, Jonas

...

Regards, Jonas

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CONFIG_SPL_ATF=y   CONFIG_CMD_GPIO=y   CONFIG_CMD_GPT=y @@ -59,6 +66,8 @@ CONFIG_MMC_SDHCI=y   CONFIG_MMC_SDHCI_SDMA=y   # CONFIG_SPL_MMC_SDHCI_SDMA is not set   CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_XTX=y   CONFIG_ETH_DESIGNWARE=y   CONFIG_GMAC_ROCKCHIP=y   CONFIG_PHY_ROCKCHIP_INNO_USB2=y @@ -69,6 +78,7 @@ CONFIG_SPL_RAM=y   CONFIG_BAUDRATE=1500000   CONFIG_DEBUG_UART_SHIFT=2   CONFIG_SYS_NS16550_MEM32=y +CONFIG_ROCKCHIP_SFC=y   CONFIG_SYSRESET=y   CONFIG_USB=y   CONFIG_USB_EHCI_HCD=y

On 2023/4/22 09:23, Jonas Karlman wrote:

Remove regulator-boot-on prop from regulators now that the phy core has support for phy-supply after commit "phy: add support for phy-supply" and regulators support a basic reference counter after commit "regulator: implement basic reference counter".

This reverts commit 7911f409ff20dce5995cc1b703a6e30c94022f6b.

Signed-off-by: Jonas Karlman jonas@kwiboo.se

Reviewed-by: Kever Yang kever.yang@rock-chips.com

Thanks, - Kever

---

After [1] and [2] these regulator-boot-on props can be removed.

[1] https://patchwork.ozlabs.org/project/uboot/patch/20230419134014.128461-3-eug... [2] https://patchwork.ozlabs.org/project/uboot/patch/20230419134526.128800-1-eug...

arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi | 4 ---- arch/arm/dts/rk3568-rock-3a-u-boot.dtsi | 8 -------- 2 files changed, 12 deletions(-)

diff --git a/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi b/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi index d2ee19aaa8d5..332f81b3bc7e 100644 --- a/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi +++ b/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi @@ -77,7 +77,3 @@ bootph-all; status = "okay"; };

-&vcc5v0_usb30 {

• regulator-boot-on;

-}; diff --git a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi index 7cd2dc80c317..8abee24c02c3 100644 --- a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi +++ b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi @@ -111,11 +111,3 @@ bootph-all; status = "okay"; };

-&vcc5v0_usb_host {

• regulator-boot-on;

-};

-&vcc5v0_usb_hub {

• regulator-boot-on;

-};