[U-Boot] [PATCHv3 0/5] clean up omap3 configuration structs
Here are some (hopefully final) changes to the omap3 cleanup.
changes since v2: - split cs-config into 2 patches (patch 1/2) - remove (accidentally missed) typedefs (patch 3) - based on arm/next (zoom2 ok now)
not changed (see discussion on v2): - using a function for gpmc config - replacing config[1-7] by an array
compile-tested on beagle, evm, overo, pandora, zoom[12]
best regards, Matthias
Matthias Ludwig (5): OMAP3EVM: net_chip uses CS5 not CS6 omap3: embedd gpmc_cs into gpmc config struct omap3: remove typedefs for configuration structs omap3: replace all instances of gpmc config struct by one global omap3: use only fixed-size types inside ctrl_structs
board/omap3/beagle/beagle.c | 6 +- board/omap3/evm/evm.c | 19 +- board/omap3/pandora/pandora.c | 8 +- board/omap3/zoom2/zoom2.c | 13 +- cpu/arm_cortexa8/omap3/board.c | 16 +- cpu/arm_cortexa8/omap3/clock.c | 14 +- cpu/arm_cortexa8/omap3/mem.c | 56 ++--- cpu/arm_cortexa8/omap3/sys_info.c | 13 +- cpu/arm_cortexa8/omap3/timer.c | 2 +- drivers/mtd/nand/omap_gpmc.c | 41 ++-- include/asm-arm/arch-omap3/cpu.h | 476 +++++++++++++++++++----------------- include/asm-arm/arch-omap3/mem.h | 4 +- include/asm-arm/arch-omap3/omap3.h | 8 +- include/configs/omap3_beagle.h | 3 +- include/configs/omap3_evm.h | 3 +- include/configs/omap3_overo.h | 3 +- include/configs/omap3_pandora.h | 3 +- include/configs/omap3_zoom1.h | 3 +- include/configs/omap3_zoom2.h | 3 +- 19 files changed, 342 insertions(+), 352 deletions(-)
Signed-off-by: Matthias Ludwig mludwig@ultratronik.de --- board/omap3/evm/evm.c | 16 ++++++++-------- include/asm-arm/arch-omap3/cpu.h | 5 +++-- 2 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/board/omap3/evm/evm.c b/board/omap3/evm/evm.c index c008c2e..5fd5efa 100644 --- a/board/omap3/evm/evm.c +++ b/board/omap3/evm/evm.c @@ -92,17 +92,17 @@ void set_muxconf_regs(void) static void setup_net_chip(void) { gpio_t *gpio3_base = (gpio_t *)OMAP34XX_GPIO3_BASE; - gpmc_csx_t *gpmc_cs6_base = (gpmc_csx_t *)GPMC_CONFIG_CS6_BASE; + gpmc_csx_t *gpmc_cs5_base = (gpmc_csx_t *)GPMC_CONFIG_CS5_BASE; ctrl_t *ctrl_base = (ctrl_t *)OMAP34XX_CTRL_BASE;
/* Configure GPMC registers */ - writel(NET_GPMC_CONFIG1, &gpmc_cs6_base->config1); - writel(NET_GPMC_CONFIG2, &gpmc_cs6_base->config2); - writel(NET_GPMC_CONFIG3, &gpmc_cs6_base->config3); - writel(NET_GPMC_CONFIG4, &gpmc_cs6_base->config4); - writel(NET_GPMC_CONFIG5, &gpmc_cs6_base->config5); - writel(NET_GPMC_CONFIG6, &gpmc_cs6_base->config6); - writel(NET_GPMC_CONFIG7, &gpmc_cs6_base->config7); + writel(NET_GPMC_CONFIG1, &gpmc_cs5_base->config1); + writel(NET_GPMC_CONFIG2, &gpmc_cs5_base->config2); + writel(NET_GPMC_CONFIG3, &gpmc_cs5_base->config3); + writel(NET_GPMC_CONFIG4, &gpmc_cs5_base->config4); + writel(NET_GPMC_CONFIG5, &gpmc_cs5_base->config5); + writel(NET_GPMC_CONFIG6, &gpmc_cs5_base->config6); + writel(NET_GPMC_CONFIG7, &gpmc_cs5_base->config7);
/* Enable off mode for NWE in PADCONF_GPMC_NWE register */ writew(readw(&ctrl_base ->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); diff --git a/include/asm-arm/arch-omap3/cpu.h b/include/asm-arm/arch-omap3/cpu.h index c544e0c..a4ce45a 100644 --- a/include/asm-arm/arch-omap3/cpu.h +++ b/include/asm-arm/arch-omap3/cpu.h @@ -84,9 +84,10 @@ typedef struct ctrl_id { /* GPMC CS3/cs4/cs6 not avaliable */ #define GPMC_BASE (OMAP34XX_GPMC_BASE) #define GPMC_CONFIG_CS0 0x60 -#define GPMC_CONFIG_CS6 0x150 +#define GPMC_CONFIG_CS5 0x150 + #define GPMC_CONFIG_CS0_BASE (GPMC_BASE + GPMC_CONFIG_CS0) -#define GPMC_CONFIG_CS6_BASE (GPMC_BASE + GPMC_CONFIG_CS6) +#define GPMC_CONFIG_CS5_BASE (GPMC_BASE + GPMC_CONFIG_CS5) #define GPMC_CONFIG_WP 0x10
#define GPMC_CONFIG_WIDTH 0x30
Embedd chip select configuration into struct for gpmc config instead of having it completely separated as suggested by Wolfgang Denk on http://lists.denx.de/pipermail/u-boot/2009-May/052247.html
Signed-off-by: Matthias Ludwig mludwig@ultratronik.de --- board/omap3/evm/evm.c | 16 +++++++------- board/omap3/zoom2/zoom2.c | 14 ++++-------- cpu/arm_cortexa8/omap3/mem.c | 33 +++++++++++------------------ cpu/arm_cortexa8/omap3/sys_info.c | 4 +- drivers/mtd/nand/omap_gpmc.c | 22 ++++++------------- include/asm-arm/arch-omap3/cpu.h | 41 ++++++++++++++++-------------------- include/configs/omap3_beagle.h | 1 - include/configs/omap3_evm.h | 1 - include/configs/omap3_overo.h | 1 - include/configs/omap3_pandora.h | 1 - include/configs/omap3_zoom1.h | 1 - include/configs/omap3_zoom2.h | 1 - 12 files changed, 53 insertions(+), 83 deletions(-)
diff --git a/board/omap3/evm/evm.c b/board/omap3/evm/evm.c index 5fd5efa..032c93a 100644 --- a/board/omap3/evm/evm.c +++ b/board/omap3/evm/evm.c @@ -92,17 +92,17 @@ void set_muxconf_regs(void) static void setup_net_chip(void) { gpio_t *gpio3_base = (gpio_t *)OMAP34XX_GPIO3_BASE; - gpmc_csx_t *gpmc_cs5_base = (gpmc_csx_t *)GPMC_CONFIG_CS5_BASE; + gpmc_t *gpmc = (gpmc_t *)GPMC_BASE; ctrl_t *ctrl_base = (ctrl_t *)OMAP34XX_CTRL_BASE;
/* Configure GPMC registers */ - writel(NET_GPMC_CONFIG1, &gpmc_cs5_base->config1); - writel(NET_GPMC_CONFIG2, &gpmc_cs5_base->config2); - writel(NET_GPMC_CONFIG3, &gpmc_cs5_base->config3); - writel(NET_GPMC_CONFIG4, &gpmc_cs5_base->config4); - writel(NET_GPMC_CONFIG5, &gpmc_cs5_base->config5); - writel(NET_GPMC_CONFIG6, &gpmc_cs5_base->config6); - writel(NET_GPMC_CONFIG7, &gpmc_cs5_base->config7); + writel(NET_GPMC_CONFIG1, &gpmc->cs[5].config1); + writel(NET_GPMC_CONFIG2, &gpmc->cs[5].config2); + writel(NET_GPMC_CONFIG3, &gpmc->cs[5].config3); + writel(NET_GPMC_CONFIG4, &gpmc->cs[5].config4); + writel(NET_GPMC_CONFIG5, &gpmc->cs[5].config5); + writel(NET_GPMC_CONFIG6, &gpmc->cs[5].config6); + writel(NET_GPMC_CONFIG7, &gpmc->cs[5].config7);
/* Enable off mode for NWE in PADCONF_GPMC_NWE register */ writew(readw(&ctrl_base ->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); diff --git a/board/omap3/zoom2/zoom2.c b/board/omap3/zoom2/zoom2.c index e5c248d..b3bca4a 100644 --- a/board/omap3/zoom2/zoom2.c +++ b/board/omap3/zoom2/zoom2.c @@ -48,8 +48,8 @@ * The details of the setting of the serial gpmc setup are not available. * The values were provided by another party. */ -extern void enable_gpmc_config(u32 *gpmc_config, gpmc_csx_t *gpmc_cs_base, - u32 base, u32 size); +void enable_gpmc_cs_config(u32 *gpmc_config, struct gpmc_cs *cs, u32 base, + u32 size);
static u32 gpmc_serial_TL16CP754C[GPMC_MAX_REG] = { 0x00011000, @@ -67,19 +67,15 @@ static u32 gpmc_serial_TL16CP754C[GPMC_MAX_REG] = { int board_init (void) { DECLARE_GLOBAL_DATA_PTR; - gpmc_csx_t *serial_cs_base; + gpmc_t *gpmc = (gpmc_t *)GPMC_BASE; u32 *gpmc_config;
gpmc_init (); /* in SRAM or SDRAM, finish GPMC */
/* Configure console support on zoom2 */ gpmc_config = gpmc_serial_TL16CP754C; - serial_cs_base = (gpmc_csx_t *) (GPMC_CONFIG_CS0_BASE + - (3 * GPMC_CONFIG_WIDTH)); - enable_gpmc_config(gpmc_config, - serial_cs_base, - SERIAL_TL16CP754C_BASE, - GPMC_SIZE_16M); + enable_gpmc_cs_config(gpmc_config, &gpmc->cs[4], + SERIAL_TL16CP754C_BASE, GPMC_SIZE_16M);
/* board id for Linux */ gd->bd->bi_arch_number = MACH_TYPE_OMAP_ZOOM2; diff --git a/cpu/arm_cortexa8/omap3/mem.c b/cpu/arm_cortexa8/omap3/mem.c index 3cc22c4..965de3a 100644 --- a/cpu/arm_cortexa8/omap3/mem.c +++ b/cpu/arm_cortexa8/omap3/mem.c @@ -51,7 +51,6 @@ static u32 gpmc_m_nand[GPMC_MAX_REG] = { M_NAND_GPMC_CONFIG6, 0 };
-gpmc_csx_t *nand_cs_base; gpmc_t *gpmc_cfg_base;
#if defined(CONFIG_ENV_IS_IN_NAND) @@ -72,8 +71,6 @@ static u32 gpmc_onenand[GPMC_MAX_REG] = { ONENAND_GPMC_CONFIG6, 0 };
-gpmc_csx_t *onenand_cs_base; - #if defined(CONFIG_ENV_IS_IN_ONENAND) #define GPMC_CS 0 #else @@ -195,21 +192,21 @@ void do_sdrc_init(u32 cs, u32 early) writel(0, &sdrc_base->cs[cs].mcfg); }
-void enable_gpmc_config(u32 *gpmc_config, gpmc_csx_t *gpmc_cs_base, u32 base, +void enable_gpmc_cs_config(u32 *gpmc_config, struct gpmc_cs *cs, u32 base, u32 size) { - writel(0, &gpmc_cs_base->config7); + writel(0, &cs->config7); sdelay(1000); /* Delay for settling */ - writel(gpmc_config[0], &gpmc_cs_base->config1); - writel(gpmc_config[1], &gpmc_cs_base->config2); - writel(gpmc_config[2], &gpmc_cs_base->config3); - writel(gpmc_config[3], &gpmc_cs_base->config4); - writel(gpmc_config[4], &gpmc_cs_base->config5); - writel(gpmc_config[5], &gpmc_cs_base->config6); + writel(gpmc_config[0], &cs->config1); + writel(gpmc_config[1], &cs->config2); + writel(gpmc_config[2], &cs->config3); + writel(gpmc_config[3], &cs->config4); + writel(gpmc_config[4], &cs->config5); + writel(gpmc_config[5], &cs->config6); /* Enable the config */ writel((((size & 0xF) << 8) | ((base >> 24) & 0x3F) | - (1 << 6)), &gpmc_cs_base->config7); + (1 << 6)), &cs->config7); sdelay(2000); }
@@ -223,7 +220,6 @@ void gpmc_init(void) /* putting a blanket check on GPMC based on ZeBu for now */ u32 *gpmc_config = NULL; gpmc_t *gpmc_base = (gpmc_t *)GPMC_BASE; - gpmc_csx_t *gpmc_cs_base = (gpmc_csx_t *)GPMC_CONFIG_CS0_BASE; u32 base = 0; u32 size = 0; u32 f_off = CONFIG_SYS_MONITOR_LEN; @@ -242,17 +238,16 @@ void gpmc_init(void) * Disable the GPMC0 config set by ROM code * It conflicts with our MPDB (both at 0x08000000) */ - writel(0, &gpmc_cs_base->config7); + writel(0, &gpmc_base->cs[0].config7); sdelay(1000);
#if defined(CONFIG_CMD_NAND) /* CS 0 */ gpmc_config = gpmc_m_nand; gpmc_cfg_base = gpmc_base; - nand_cs_base = (gpmc_csx_t *)(GPMC_CONFIG_CS0_BASE + - (GPMC_CS * GPMC_CONFIG_WIDTH)); + base = PISMO1_NAND_BASE; size = PISMO1_NAND_SIZE; - enable_gpmc_config(gpmc_config, nand_cs_base, base, size); + enable_gpmc_cs_config(gpmc_config, &gpmc_base->cs[0], base, size); #if defined(CONFIG_ENV_IS_IN_NAND) f_off = SMNAND_ENV_OFFSET; f_sec = SZ_128K; @@ -266,11 +261,9 @@ void gpmc_init(void)
#if defined(CONFIG_CMD_ONENAND) gpmc_config = gpmc_onenand; - onenand_cs_base = (gpmc_csx_t *)(GPMC_CONFIG_CS0_BASE + - (GPMC_CS * GPMC_CONFIG_WIDTH)); base = PISMO1_ONEN_BASE; size = PISMO1_ONEN_SIZE; - enable_gpmc_config(gpmc_config, onenand_cs_base, base, size); + enable_gpmc_cs_config(gpmc_config, &gpmc_base->cs[0], base, size); #if defined(CONFIG_ENV_IS_IN_ONENAND) f_off = ONENAND_ENV_OFFSET; f_sec = SZ_128K; diff --git a/cpu/arm_cortexa8/omap3/sys_info.c b/cpu/arm_cortexa8/omap3/sys_info.c index 2f04cd6..91ee2ff 100644 --- a/cpu/arm_cortexa8/omap3/sys_info.c +++ b/cpu/arm_cortexa8/omap3/sys_info.c @@ -32,7 +32,7 @@ #include <i2c.h>
extern omap3_sysinfo sysinfo; -static gpmc_csx_t *gpmc_cs_base = (gpmc_csx_t *)GPMC_CONFIG_CS0_BASE; +static gpmc_t *gpmc_base = (gpmc_t *)GPMC_BASE; static sdrc_t *sdrc_base = (sdrc_t *)OMAP34XX_SDRC_BASE; static ctrl_t *ctrl_base = (ctrl_t *)OMAP34XX_CTRL_BASE; static char *rev_s[CPU_3XX_MAX_REV] = { @@ -160,7 +160,7 @@ u32 get_gpmc0_base(void) { u32 b;
- b = readl(&gpmc_cs_base->config7); + b = readl(&gpmc_base->cs[0].config7); b &= 0x1F; /* keep base [5:0] */ b = b << 24; /* ret 0x0b000000 */ return b; diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c index 5f8ed39..c2dee25 100644 --- a/drivers/mtd/nand/omap_gpmc.c +++ b/drivers/mtd/nand/omap_gpmc.c @@ -31,7 +31,6 @@
static uint8_t cs; static gpmc_t *gpmc_base = (gpmc_t *)GPMC_BASE; -static gpmc_csx_t *gpmc_cs_base; static struct nand_ecclayout hw_nand_oob = GPMC_NAND_HW_ECC_LAYOUT;
/* @@ -49,13 +48,13 @@ static void omap_nand_hwcontrol(struct mtd_info *mtd, int32_t cmd, */ switch (ctrl) { case NAND_CTRL_CHANGE | NAND_CTRL_CLE: - this->IO_ADDR_W = (void __iomem *)&gpmc_cs_base->nand_cmd; + this->IO_ADDR_W = (void __iomem *)&gpmc_base->cs[cs].nand_cmd; break; case NAND_CTRL_CHANGE | NAND_CTRL_ALE: - this->IO_ADDR_W = (void __iomem *)&gpmc_cs_base->nand_adr; + this->IO_ADDR_W = (void __iomem *)&gpmc_base->cs[cs].nand_adr; break; case NAND_CTRL_CHANGE | NAND_NCE: - this->IO_ADDR_W = (void __iomem *)&gpmc_cs_base->nand_dat; + this->IO_ADDR_W = (void __iomem *)&gpmc_base->cs[cs].nand_dat; break; }
@@ -311,15 +310,8 @@ int board_nand_init(struct nand_chip *nand) * devices. */ while (cs < GPMC_MAX_CS) { - /* - * Each GPMC set for a single CS is at offset 0x30 - * - already remapped for us - */ - gpmc_cs_base = (gpmc_csx_t *)(GPMC_CONFIG_CS0_BASE + - (cs * GPMC_CONFIG_WIDTH)); /* Check if NAND type is set */ - if ((readl(&gpmc_cs_base->config1) & 0xC00) == - 0x800) { + if ((readl(&gpmc_base->cs[cs].config1) & 0xC00) == 0x800) { /* Found it!! */ break; } @@ -336,13 +328,13 @@ int board_nand_init(struct nand_chip *nand) gpmc_config |= 0x10; writel(gpmc_config, &gpmc_base->config);
- nand->IO_ADDR_R = (void __iomem *)&gpmc_cs_base->nand_dat; - nand->IO_ADDR_W = (void __iomem *)&gpmc_cs_base->nand_cmd; + nand->IO_ADDR_R = (void __iomem *)&gpmc_base->cs[cs].nand_dat; + nand->IO_ADDR_W = (void __iomem *)&gpmc_base->cs[cs].nand_cmd;
nand->cmd_ctrl = omap_nand_hwcontrol; nand->options = NAND_NO_PADDING | NAND_CACHEPRG | NAND_NO_AUTOINCR; /* If we are 16 bit dev, our gpmc config tells us that */ - if ((readl(gpmc_cs_base) & 0x3000) == 0x1000) + if ((readl(&gpmc_base->cs[cs].config1) & 0x3000) == 0x1000) nand->options |= NAND_BUSWIDTH_16;
nand->chip_delay = 100; diff --git a/include/asm-arm/arch-omap3/cpu.h b/include/asm-arm/arch-omap3/cpu.h index a4ce45a..2d203d1 100644 --- a/include/asm-arm/arch-omap3/cpu.h +++ b/include/asm-arm/arch-omap3/cpu.h @@ -81,30 +81,38 @@ typedef struct ctrl_id { #define HS_DEVICE 0x2 #define GP_DEVICE 0x3
-/* GPMC CS3/cs4/cs6 not avaliable */ #define GPMC_BASE (OMAP34XX_GPMC_BASE) #define GPMC_CONFIG_CS0 0x60 -#define GPMC_CONFIG_CS5 0x150 - -#define GPMC_CONFIG_CS0_BASE (GPMC_BASE + GPMC_CONFIG_CS0) -#define GPMC_CONFIG_CS5_BASE (GPMC_BASE + GPMC_CONFIG_CS5) -#define GPMC_CONFIG_WP 0x10 - -#define GPMC_CONFIG_WIDTH 0x30
#ifndef __ASSEMBLY__ +struct gpmc_cs { + unsigned int config1; /* 0x00 */ + unsigned int config2; /* 0x04 */ + unsigned int config3; /* 0x08 */ + unsigned int config4; /* 0x0C */ + unsigned int config5; /* 0x10 */ + unsigned int config6; /* 0x14 */ + unsigned int config7; /* 0x18 */ + unsigned int nand_cmd; /* 0x1C */ + unsigned int nand_adr; /* 0x20 */ + unsigned int nand_dat; /* 0x24 */ + unsigned char res[8]; /* blow up to 0x30 byte */ +}; + typedef struct gpmc { unsigned char res1[0x10]; unsigned int sysconfig; /* 0x10 */ unsigned char res2[0x4]; unsigned int irqstatus; /* 0x18 */ - unsigned int irqenable; /* 0x1C */ + unsigned int irqenable; /* 0x1C */ unsigned char res3[0x20]; unsigned int timeout_control; /* 0x40 */ unsigned char res4[0xC]; unsigned int config; /* 0x50 */ unsigned int status; /* 0x54 */ - unsigned char res5[0x19C]; + unsigned char res5[0x8]; + struct gpmc_cs cs[8]; /* 0x60, 0x90, .. */ + unsigned char res6[0x18]; unsigned int ecc_config; /* 0x1F4 */ unsigned int ecc_control; /* 0x1F8 */ unsigned int ecc_size_config; /* 0x1FC */ @@ -118,19 +126,6 @@ typedef struct gpmc { unsigned int ecc8_result; /* 0x21C */ unsigned int ecc9_result; /* 0x220 */ } gpmc_t; - -typedef struct gpmc_csx { - unsigned int config1; /* 0x00 */ - unsigned int config2; /* 0x04 */ - unsigned int config3; /* 0x08 */ - unsigned int config4; /* 0x0C */ - unsigned int config5; /* 0x10 */ - unsigned int config6; /* 0x14 */ - unsigned int config7; /* 0x18 */ - unsigned int nand_cmd; /* 0x1C */ - unsigned int nand_adr; /* 0x20 */ - unsigned int nand_dat; /* 0x24 */ -} gpmc_csx_t; #else /* __ASSEMBLY__ */ #define GPMC_CONFIG1 0x00 #define GPMC_CONFIG2 0x04 diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index a3d9cf6..b3afe1d 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -292,7 +292,6 @@ #define CONFIG_SYS_JFFS2_NUM_BANKS 1
#ifndef __ASSEMBLY__ -extern gpmc_csx_t *nand_cs_base; extern gpmc_t *gpmc_cfg_base; extern unsigned int boot_flash_base; extern volatile unsigned int boot_flash_env_addr; diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h index e205c01..2b7fe15 100644 --- a/include/configs/omap3_evm.h +++ b/include/configs/omap3_evm.h @@ -286,7 +286,6 @@ #define CONFIG_SYS_JFFS2_NUM_BANKS 1
#ifndef __ASSEMBLY__ -extern gpmc_csx_t *nand_cs_base; extern gpmc_t *gpmc_cfg_base; extern unsigned int boot_flash_base; extern volatile unsigned int boot_flash_env_addr; diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h index 8902312..326e0a5 100644 --- a/include/configs/omap3_overo.h +++ b/include/configs/omap3_overo.h @@ -277,7 +277,6 @@ #define CONFIG_SYS_JFFS2_NUM_BANKS 1
#ifndef __ASSEMBLY__ -extern gpmc_csx_t *nand_cs_base; extern gpmc_t *gpmc_cfg_base; extern unsigned int boot_flash_base; extern volatile unsigned int boot_flash_env_addr; diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h index dbd4dcc..6fb63cd 100644 --- a/include/configs/omap3_pandora.h +++ b/include/configs/omap3_pandora.h @@ -281,7 +281,6 @@ #define CONFIG_SYS_JFFS2_NUM_BANKS 1
#ifndef __ASSEMBLY__ -extern gpmc_csx_t *nand_cs_base; extern gpmc_t *gpmc_cfg_base; extern unsigned int boot_flash_base; extern volatile unsigned int boot_flash_env_addr; diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h index 9e000ed..04a0c6b 100644 --- a/include/configs/omap3_zoom1.h +++ b/include/configs/omap3_zoom1.h @@ -288,7 +288,6 @@ #define CONFIG_SYS_JFFS2_NUM_BANKS 1
#ifndef __ASSEMBLY__ -extern gpmc_csx_t *nand_cs_base; extern gpmc_t *gpmc_cfg_base; extern unsigned int boot_flash_base; extern volatile unsigned int boot_flash_env_addr; diff --git a/include/configs/omap3_zoom2.h b/include/configs/omap3_zoom2.h index e257419..9ea053d 100644 --- a/include/configs/omap3_zoom2.h +++ b/include/configs/omap3_zoom2.h @@ -236,7 +236,6 @@ #define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
#ifndef __ASSEMBLY__ -extern gpmc_csx_t *nand_cs_base; extern gpmc_t *gpmc_cfg_base; extern unsigned int boot_flash_base; extern volatile unsigned int boot_flash_env_addr;
Signed-off-by: Matthias Ludwig mludwig@ultratronik.de --- board/omap3/beagle/beagle.c | 6 ++-- board/omap3/evm/evm.c | 6 ++-- board/omap3/pandora/pandora.c | 8 +++--- board/omap3/zoom2/zoom2.c | 2 +- cpu/arm_cortexa8/omap3/board.c | 16 ++++++------ cpu/arm_cortexa8/omap3/clock.c | 14 +++++----- cpu/arm_cortexa8/omap3/mem.c | 14 +++++----- cpu/arm_cortexa8/omap3/sys_info.c | 12 ++++---- cpu/arm_cortexa8/omap3/timer.c | 2 +- drivers/mtd/nand/omap_gpmc.c | 2 +- include/asm-arm/arch-omap3/cpu.h | 50 ++++++++++++++++++------------------ include/asm-arm/arch-omap3/mem.h | 4 +- include/asm-arm/arch-omap3/omap3.h | 8 +++--- include/configs/omap3_beagle.h | 2 +- include/configs/omap3_evm.h | 2 +- include/configs/omap3_overo.h | 2 +- include/configs/omap3_pandora.h | 2 +- include/configs/omap3_zoom1.h | 2 +- include/configs/omap3_zoom2.h | 2 +- 19 files changed, 78 insertions(+), 78 deletions(-)
diff --git a/board/omap3/beagle/beagle.c b/board/omap3/beagle/beagle.c index 7eb70ee..2dc11dd 100644 --- a/board/omap3/beagle/beagle.c +++ b/board/omap3/beagle/beagle.c @@ -74,7 +74,7 @@ int beagle_get_revision(void) */ void beagle_identify(void) { - gpio_t *gpio6_base = (gpio_t *)OMAP34XX_GPIO6_BASE; + struct gpio *gpio6_base = (struct gpio *)OMAP34XX_GPIO6_BASE;
/* Configure GPIO 171 as input */ writel(readl(&gpio6_base->oe) | GPIO11, &gpio6_base->oe); @@ -98,8 +98,8 @@ void beagle_identify(void) */ int misc_init_r(void) { - gpio_t *gpio5_base = (gpio_t *)OMAP34XX_GPIO5_BASE; - gpio_t *gpio6_base = (gpio_t *)OMAP34XX_GPIO6_BASE; + struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE; + struct gpio *gpio6_base = (struct gpio *)OMAP34XX_GPIO6_BASE;
power_init_r();
diff --git a/board/omap3/evm/evm.c b/board/omap3/evm/evm.c index 032c93a..7747986 100644 --- a/board/omap3/evm/evm.c +++ b/board/omap3/evm/evm.c @@ -91,9 +91,9 @@ void set_muxconf_regs(void) */ static void setup_net_chip(void) { - gpio_t *gpio3_base = (gpio_t *)OMAP34XX_GPIO3_BASE; - gpmc_t *gpmc = (gpmc_t *)GPMC_BASE; - ctrl_t *ctrl_base = (ctrl_t *)OMAP34XX_CTRL_BASE; + struct gpio *gpio3_base = (struct gpio *)OMAP34XX_GPIO3_BASE; + struct gpmc *gpmc = (struct gpmc *)GPMC_BASE; + struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
/* Configure GPMC registers */ writel(NET_GPMC_CONFIG1, &gpmc->cs[5].config1); diff --git a/board/omap3/pandora/pandora.c b/board/omap3/pandora/pandora.c index c2f98ea..e4b45f7 100644 --- a/board/omap3/pandora/pandora.c +++ b/board/omap3/pandora/pandora.c @@ -59,10 +59,10 @@ int board_init(void) */ int misc_init_r(void) { - gpio_t *gpio1_base = (gpio_t *)OMAP34XX_GPIO1_BASE; - gpio_t *gpio4_base = (gpio_t *)OMAP34XX_GPIO4_BASE; - gpio_t *gpio5_base = (gpio_t *)OMAP34XX_GPIO5_BASE; - gpio_t *gpio6_base = (gpio_t *)OMAP34XX_GPIO6_BASE; + struct gpio *gpio1_base = (struct gpio *)OMAP34XX_GPIO1_BASE; + struct gpio *gpio4_base = (struct gpio *)OMAP34XX_GPIO4_BASE; + struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE; + struct gpio *gpio6_base = (struct gpio *)OMAP34XX_GPIO6_BASE;
power_init_r();
diff --git a/board/omap3/zoom2/zoom2.c b/board/omap3/zoom2/zoom2.c index b3bca4a..0d766d1 100644 --- a/board/omap3/zoom2/zoom2.c +++ b/board/omap3/zoom2/zoom2.c @@ -67,7 +67,7 @@ static u32 gpmc_serial_TL16CP754C[GPMC_MAX_REG] = { int board_init (void) { DECLARE_GLOBAL_DATA_PTR; - gpmc_t *gpmc = (gpmc_t *)GPMC_BASE; + struct gpmc *gpmc = (struct gpmc *)GPMC_BASE; u32 *gpmc_config;
gpmc_init (); /* in SRAM or SDRAM, finish GPMC */ diff --git a/cpu/arm_cortexa8/omap3/board.c b/cpu/arm_cortexa8/omap3/board.c index 51d5cf6..8a79f53 100644 --- a/cpu/arm_cortexa8/omap3/board.c +++ b/cpu/arm_cortexa8/omap3/board.c @@ -58,11 +58,11 @@ static inline void delay(unsigned long loops) *****************************************************************************/ void secure_unlock_mem(void) { - pm_t *pm_rt_ape_base = (pm_t *)PM_RT_APE_BASE_ADDR_ARM; - pm_t *pm_gpmc_base = (pm_t *)PM_GPMC_BASE_ADDR_ARM; - pm_t *pm_ocm_ram_base = (pm_t *)PM_OCM_RAM_BASE_ADDR_ARM; - pm_t *pm_iva2_base = (pm_t *)PM_IVA2_BASE_ADDR_ARM; - sms_t *sms_base = (sms_t *)OMAP34XX_SMS_BASE; + struct pm *pm_rt_ape_base = (struct pm *)PM_RT_APE_BASE_ADDR_ARM; + struct pm *pm_gpmc_base = (struct pm *)PM_GPMC_BASE_ADDR_ARM; + struct pm *pm_ocm_ram_base = (struct pm *)PM_OCM_RAM_BASE_ADDR_ARM; + struct pm *pm_iva2_base = (struct pm *)PM_IVA2_BASE_ADDR_ARM; + struct sms *sms_base = (struct sms *)OMAP34XX_SMS_BASE;
/* Protection Module Register Target APE (PM_RT) */ writel(UNLOCK_1, &pm_rt_ape_base->req_info_permission_1); @@ -233,7 +233,7 @@ void s_init(void) * Routine: wait_for_command_complete * Description: Wait for posting to finish on watchdog *****************************************************************************/ -void wait_for_command_complete(watchdog_t *wd_base) +void wait_for_command_complete(struct watchdog *wd_base) { int pending = 1; do { @@ -247,8 +247,8 @@ void wait_for_command_complete(watchdog_t *wd_base) *****************************************************************************/ void watchdog_init(void) { - watchdog_t *wd2_base = (watchdog_t *)WD2_BASE; - prcm_t *prcm_base = (prcm_t *)PRCM_BASE; + struct watchdog *wd2_base = (struct watchdog *)WD2_BASE; + struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
/* * There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is diff --git a/cpu/arm_cortexa8/omap3/clock.c b/cpu/arm_cortexa8/omap3/clock.c index d035677..f03912d 100644 --- a/cpu/arm_cortexa8/omap3/clock.c +++ b/cpu/arm_cortexa8/omap3/clock.c @@ -41,10 +41,10 @@ u32 get_osc_clk_speed(void) { u32 start, cstart, cend, cdiff, val; - prcm_t *prcm_base = (prcm_t *)PRCM_BASE; - prm_t *prm_base = (prm_t *)PRM_BASE; - gptimer_t *gpt1_base = (gptimer_t *)OMAP34XX_GPT1; - s32ktimer_t *s32k_base = (s32ktimer_t *)SYNC_32KTIMER_BASE; + struct prcm *prcm_base = (struct prcm *)PRCM_BASE; + struct prm *prm_base = (struct prm *)PRM_BASE; + struct gptimer *gpt1_base = (struct gptimer *)OMAP34XX_GPT1; + struct s32ktimer *s32k_base = (struct s32ktimer *)SYNC_32KTIMER_BASE;
val = readl(&prm_base->clksrc_ctrl);
@@ -133,8 +133,8 @@ void prcm_init(void) int xip_safe, p0, p1, p2, p3; u32 osc_clk = 0, sys_clkin_sel; u32 clk_index, sil_index = 0; - prm_t *prm_base = (prm_t *)PRM_BASE; - prcm_t *prcm_base = (prcm_t *)PRCM_BASE; + struct prm *prm_base = (struct prm *)PRM_BASE; + struct prcm *prcm_base = (struct prcm *)PRCM_BASE; dpll_param *dpll_param_p;
f_lock_pll = (void *) ((u32) &_end_vect - (u32) &_start + @@ -341,7 +341,7 @@ void prcm_init(void) *****************************************************************************/ void per_clocks_enable(void) { - prcm_t *prcm_base = (prcm_t *)PRCM_BASE; + struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
/* Enable GP2 timer. */ sr32(&prcm_base->clksel_per, 0, 1, 0x1); /* GPT2 = sys clk */ diff --git a/cpu/arm_cortexa8/omap3/mem.c b/cpu/arm_cortexa8/omap3/mem.c index 965de3a..aa15f94 100644 --- a/cpu/arm_cortexa8/omap3/mem.c +++ b/cpu/arm_cortexa8/omap3/mem.c @@ -51,7 +51,7 @@ static u32 gpmc_m_nand[GPMC_MAX_REG] = { M_NAND_GPMC_CONFIG6, 0 };
-gpmc_t *gpmc_cfg_base; +struct gpmc *gpmc_cfg;
#if defined(CONFIG_ENV_IS_IN_NAND) #define GPMC_CS 0 @@ -79,7 +79,7 @@ static u32 gpmc_onenand[GPMC_MAX_REG] = {
#endif
-static sdrc_t *sdrc_base = (sdrc_t *)OMAP34XX_SDRC_BASE; +static struct sdrc *sdrc_base = (struct sdrc *)OMAP34XX_SDRC_BASE;
/************************************************************************** * make_cs1_contiguous() - for es2 and above remap cs1 behind cs0 to allow @@ -146,12 +146,12 @@ void sdrc_init(void)
void do_sdrc_init(u32 cs, u32 early) { - sdrc_actim_t *sdrc_actim_base; + struct sdrc_actim *sdrc_actim_base;
if(cs) - sdrc_actim_base = (sdrc_actim_t *)SDRC_ACTIM_CTRL1_BASE; + sdrc_actim_base = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE; else - sdrc_actim_base = (sdrc_actim_t *)SDRC_ACTIM_CTRL0_BASE; + sdrc_actim_base = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE;
if (early) { /* reset sdrc controller */ @@ -219,7 +219,7 @@ void gpmc_init(void) { /* putting a blanket check on GPMC based on ZeBu for now */ u32 *gpmc_config = NULL; - gpmc_t *gpmc_base = (gpmc_t *)GPMC_BASE; + struct gpmc *gpmc_base = (struct gpmc *)GPMC_BASE; u32 base = 0; u32 size = 0; u32 f_off = CONFIG_SYS_MONITOR_LEN; @@ -243,7 +243,7 @@ void gpmc_init(void)
#if defined(CONFIG_CMD_NAND) /* CS 0 */ gpmc_config = gpmc_m_nand; - gpmc_cfg_base = gpmc_base; + gpmc_cfg = gpmc_base;
base = PISMO1_NAND_BASE; size = PISMO1_NAND_SIZE; diff --git a/cpu/arm_cortexa8/omap3/sys_info.c b/cpu/arm_cortexa8/omap3/sys_info.c index 91ee2ff..e0e5153 100644 --- a/cpu/arm_cortexa8/omap3/sys_info.c +++ b/cpu/arm_cortexa8/omap3/sys_info.c @@ -32,9 +32,9 @@ #include <i2c.h>
extern omap3_sysinfo sysinfo; -static gpmc_t *gpmc_base = (gpmc_t *)GPMC_BASE; -static sdrc_t *sdrc_base = (sdrc_t *)OMAP34XX_SDRC_BASE; -static ctrl_t *ctrl_base = (ctrl_t *)OMAP34XX_CTRL_BASE; +static struct gpmc *gpmc_base = (struct gpmc *)GPMC_BASE; +static struct sdrc *sdrc_base = (struct sdrc *)OMAP34XX_SDRC_BASE; +static struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE; static char *rev_s[CPU_3XX_MAX_REV] = { "1.0", "2.0", @@ -47,7 +47,7 @@ static char *rev_s[CPU_3XX_MAX_REV] = { *****************************************************************/ void dieid_num_r(void) { - ctrl_id_t *id_base = (ctrl_id_t *)OMAP34XX_ID_L4_IO_BASE; + struct ctrl_id *id_base = (struct ctrl_id *)OMAP34XX_ID_L4_IO_BASE; char *uid_s, die_id[34]; u32 id[4];
@@ -82,7 +82,7 @@ u32 get_cpu_type(void) u32 get_cpu_rev(void) { u32 cpuid = 0; - ctrl_id_t *id_base; + struct ctrl_id *id_base;
/* * On ES1.0 the IDCODE register is not exposed on L4 @@ -93,7 +93,7 @@ u32 get_cpu_rev(void) return CPU_3XX_ES10; else { /* Decode the IDs on > ES1.0 */ - id_base = (ctrl_id_t *) OMAP34XX_ID_L4_IO_BASE; + id_base = (struct ctrl_id *) OMAP34XX_ID_L4_IO_BASE;
cpuid = (readl(&id_base->idcode) >> CPU_3XX_ID_SHIFT) & 0xf;
diff --git a/cpu/arm_cortexa8/omap3/timer.c b/cpu/arm_cortexa8/omap3/timer.c index 05cfe76..12a16b3 100644 --- a/cpu/arm_cortexa8/omap3/timer.c +++ b/cpu/arm_cortexa8/omap3/timer.c @@ -37,7 +37,7 @@
static ulong timestamp; static ulong lastinc; -static gptimer_t *timer_base = (gptimer_t *)CONFIG_SYS_TIMERBASE; +static struct gptimer *timer_base = (struct gptimer *)CONFIG_SYS_TIMERBASE;
/* * Nothing really to do with interrupts, just starts up a counter. diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c index c2dee25..89e8b1c 100644 --- a/drivers/mtd/nand/omap_gpmc.c +++ b/drivers/mtd/nand/omap_gpmc.c @@ -30,7 +30,7 @@ #include <nand.h>
static uint8_t cs; -static gpmc_t *gpmc_base = (gpmc_t *)GPMC_BASE; +static struct gpmc *gpmc_base = (struct gpmc *)GPMC_BASE; static struct nand_ecclayout hw_nand_oob = GPMC_NAND_HW_ECC_LAYOUT;
/* diff --git a/include/asm-arm/arch-omap3/cpu.h b/include/asm-arm/arch-omap3/cpu.h index 2d203d1..b66bd85 100644 --- a/include/asm-arm/arch-omap3/cpu.h +++ b/include/asm-arm/arch-omap3/cpu.h @@ -28,7 +28,7 @@ /* Register offsets of common modules */ /* Control */ #ifndef __ASSEMBLY__ -typedef struct ctrl { +struct ctrl { unsigned char res1[0xC0]; unsigned short gpmc_nadv_ale; /* 0xC0 */ unsigned short gpmc_noe; /* 0xC2 */ @@ -49,7 +49,7 @@ typedef struct ctrl { unsigned int randkey_3; /* 0x324 */ unsigned char res5[0x124]; unsigned int ctrl_omap_stat; /* 0x44C */ -} ctrl_t; +}; #else /* __ASSEMBLY__ */ #define CONTROL_STATUS 0x2F0 #endif /* __ASSEMBLY__ */ @@ -61,7 +61,7 @@ typedef struct ctrl { #define OMAP3530 0x0c00
#ifndef __ASSEMBLY__ -typedef struct ctrl_id { +struct ctrl_id { unsigned char res1[0x4]; unsigned int idcode; /* 0x04 */ unsigned int prod_id; /* 0x08 */ @@ -70,7 +70,7 @@ typedef struct ctrl_id { unsigned int die_id_1; /* 0x1C */ unsigned int die_id_2; /* 0x20 */ unsigned int die_id_3; /* 0x24 */ -} ctrl_id_t; +}; #endif /* __ASSEMBLY__ */
/* device type */ @@ -99,7 +99,7 @@ struct gpmc_cs { unsigned char res[8]; /* blow up to 0x30 byte */ };
-typedef struct gpmc { +struct gpmc { unsigned char res1[0x10]; unsigned int sysconfig; /* 0x10 */ unsigned char res2[0x4]; @@ -125,7 +125,7 @@ typedef struct gpmc { unsigned int ecc7_result; /* 0x218 */ unsigned int ecc8_result; /* 0x21C */ unsigned int ecc9_result; /* 0x220 */ -} gpmc_t; +}; #else /* __ASSEMBLY__ */ #define GPMC_CONFIG1 0x00 #define GPMC_CONFIG2 0x04 @@ -151,21 +151,21 @@ typedef struct gpmc { /* (actual size small port) */ /* SMS */ #ifndef __ASSEMBLY__ -typedef struct sms { +struct sms { unsigned char res1[0x10]; unsigned int sysconfig; /* 0x10 */ unsigned char res2[0x34]; unsigned int rg_att0; /* 0x48 */ unsigned char res3[0x84]; unsigned int class_arb0; /* 0xD0 */ -} sms_t; +}; #endif /* __ASSEMBLY__ */
#define BURSTCOMPLETE_GROUP7 (0x1 << 31)
/* SDRC */ #ifndef __ASSEMBLY__ -typedef struct sdrc_cs { +struct sdrc_cs { unsigned int mcfg; /* 0x80 || 0xB0 */ unsigned int mr; /* 0x84 || 0xB4 */ unsigned char res1[0x4]; @@ -174,14 +174,14 @@ typedef struct sdrc_cs { unsigned int rfr_ctrl; /* 0x84 || 0xD4 */ unsigned int manual; /* 0xA8 || 0xD8 */ unsigned char res3[0x4]; -} sdrc_cs_t; +};
-typedef struct sdrc_actim { +struct sdrc_actim { unsigned int ctrla; /* 0x9C || 0xC4 */ unsigned int ctrlb; /* 0xA0 || 0xC8 */ -} sdrc_actim_t; +};
-typedef struct sdrc { +struct sdrc { unsigned char res1[0x10]; unsigned int sysconfig; /* 0x10 */ unsigned int status; /* 0x14 */ @@ -195,8 +195,8 @@ typedef struct sdrc { unsigned int dllb_status; /* 0x6C */ unsigned int power; /* 0x70 */ unsigned char res4[0xC]; - sdrc_cs_t cs[2]; /* 0x80 || 0xB0 */ -} sdrc_t; + struct sdrc_cs cs[2]; /* 0x80 || 0xB0 */ +}; #endif /* __ASSEMBLY__ */
#define DLLPHASE_90 (0x1 << 1) @@ -240,7 +240,7 @@ typedef struct sdrc { /* timer regs offsets (32 bit regs) */
#ifndef __ASSEMBLY__ -typedef struct gptimer { +struct gptimer { unsigned int tidr; /* 0x00 r */ unsigned char res[0xc]; unsigned int tiocp_cfg; /* 0x10 rw */ @@ -257,7 +257,7 @@ typedef struct gptimer { unsigned int tcar1; /* 0x3c r */ unsigned int tcicr; /* 0x40 rw */ unsigned int tcar2; /* 0x44 r */ -} gptimer_t; +}; #endif /* __ASSEMBLY__ */
/* enable sys_clk NO-prescale /1 */ @@ -265,12 +265,12 @@ typedef struct gptimer {
/* Watchdog */ #ifndef __ASSEMBLY__ -typedef struct watchdog { +struct watchdog { unsigned char res1[0x34]; unsigned int wwps; /* 0x34 r */ unsigned char res2[0x10]; unsigned int wspr; /* 0x48 rw */ -} watchdog_t; +}; #endif /* __ASSEMBLY__ */
#define WD_UNLOCK1 0xAAAA @@ -280,7 +280,7 @@ typedef struct watchdog { #define PRCM_BASE 0x48004000
#ifndef __ASSEMBLY__ -typedef struct prcm { +struct prcm { unsigned int fclken_iva2; /* 0x00 */ unsigned int clken_pll_iva2; /* 0x04 */ unsigned char res1[0x1c]; @@ -344,7 +344,7 @@ typedef struct prcm { unsigned int clksel_per; /* 0x1040 */ unsigned char res28[0xfc]; unsigned int clksel1_emu; /* 0x1140 */ -} prcm_t; +}; #else /* __ASSEMBLY__ */ #define CM_CLKSEL_CORE 0x48004a40 #define CM_CLKSEL_GFX 0x48004b40 @@ -357,14 +357,14 @@ typedef struct prcm { #define PRM_BASE 0x48306000
#ifndef __ASSEMBLY__ -typedef struct prm { +struct prm { unsigned char res1[0xd40]; unsigned int clksel; /* 0xd40 */ unsigned char res2[0x50c]; unsigned int rstctrl; /* 0x1250 */ unsigned char res3[0x1c]; unsigned int clksrc_ctrl; /* 0x1270 */ -} prm_t; +}; #else /* __ASSEMBLY__ */ #define PRM_RSTCTRL 0x48307250 #endif /* __ASSEMBLY__ */ @@ -400,7 +400,7 @@ typedef struct prm { #define PM_IVA2_BASE_ADDR_ARM (SMX_APE_BASE + 0x14000)
#ifndef __ASSEMBLY__ -typedef struct pm { +struct pm { unsigned char res1[0x48]; unsigned int req_info_permission_0; /* 0x48 */ unsigned char res2[0x4]; @@ -413,7 +413,7 @@ typedef struct pm { unsigned int req_info_permission_1; /* 0x68 */ unsigned char res6[0x14]; unsigned int addr_match_2; /* 0x80 */ -} pm_t; +}; #endif /*__ASSEMBLY__ */
/* Permission values for registers -Full fledged permissions to all */ diff --git a/include/asm-arm/arch-omap3/mem.h b/include/asm-arm/arch-omap3/mem.h index 6f0f90b..5b9ac75 100644 --- a/include/asm-arm/arch-omap3/mem.h +++ b/include/asm-arm/arch-omap3/mem.h @@ -29,12 +29,12 @@ #define CS1 0x1 /* mirror CS1 regs appear offset 0x30 from CS0 */
#ifndef __ASSEMBLY__ -typedef enum { +enum { STACKED = 0, IP_DDR = 1, COMBO_DDR = 2, IP_SDR = 3, -} mem_t; +}; #endif /* __ASSEMBLY__ */
#define EARLY_INIT 1 diff --git a/include/asm-arm/arch-omap3/omap3.h b/include/asm-arm/arch-omap3/omap3.h index 7c11019..d9d243f 100644 --- a/include/asm-arm/arch-omap3/omap3.h +++ b/include/asm-arm/arch-omap3/omap3.h @@ -79,10 +79,10 @@
#ifndef __ASSEMBLY__
-typedef struct s32ktimer { +struct s32ktimer { unsigned char res[0x10]; unsigned int s32k_cr; /* 0x10 */ -} s32ktimer_t; +};
#endif /* __ASSEMBLY__ */
@@ -95,14 +95,14 @@ typedef struct s32ktimer { #define OMAP34XX_GPIO6_BASE 0x49058000
#ifndef __ASSEMBLY__ -typedef struct gpio { +struct gpio { unsigned char res1[0x34]; unsigned int oe; /* 0x34 */ unsigned int datain; /* 0x38 */ unsigned char res2[0x54]; unsigned int cleardataout; /* 0x90 */ unsigned int setdataout; /* 0x94 */ -} gpio_t; +}; #endif /* __ASSEMBLY__ */
#define GPIO0 (0x1 << 0) diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index b3afe1d..6ca2c68 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -292,7 +292,7 @@ #define CONFIG_SYS_JFFS2_NUM_BANKS 1
#ifndef __ASSEMBLY__ -extern gpmc_t *gpmc_cfg_base; +extern struct gpmc *gpmc_cfg; extern unsigned int boot_flash_base; extern volatile unsigned int boot_flash_env_addr; extern unsigned int boot_flash_off; diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h index 2b7fe15..7d26a21 100644 --- a/include/configs/omap3_evm.h +++ b/include/configs/omap3_evm.h @@ -286,7 +286,7 @@ #define CONFIG_SYS_JFFS2_NUM_BANKS 1
#ifndef __ASSEMBLY__ -extern gpmc_t *gpmc_cfg_base; +extern struct gpmc *gpmc_cfg; extern unsigned int boot_flash_base; extern volatile unsigned int boot_flash_env_addr; extern unsigned int boot_flash_off; diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h index 326e0a5..188c77c 100644 --- a/include/configs/omap3_overo.h +++ b/include/configs/omap3_overo.h @@ -277,7 +277,7 @@ #define CONFIG_SYS_JFFS2_NUM_BANKS 1
#ifndef __ASSEMBLY__ -extern gpmc_t *gpmc_cfg_base; +extern struct gpmc *gpmc_cfg; extern unsigned int boot_flash_base; extern volatile unsigned int boot_flash_env_addr; extern unsigned int boot_flash_off; diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h index 6fb63cd..e372728 100644 --- a/include/configs/omap3_pandora.h +++ b/include/configs/omap3_pandora.h @@ -281,7 +281,7 @@ #define CONFIG_SYS_JFFS2_NUM_BANKS 1
#ifndef __ASSEMBLY__ -extern gpmc_t *gpmc_cfg_base; +extern struct gpmc *gpmc_cfg; extern unsigned int boot_flash_base; extern volatile unsigned int boot_flash_env_addr; extern unsigned int boot_flash_off; diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h index 04a0c6b..c9bc3f9 100644 --- a/include/configs/omap3_zoom1.h +++ b/include/configs/omap3_zoom1.h @@ -288,7 +288,7 @@ #define CONFIG_SYS_JFFS2_NUM_BANKS 1
#ifndef __ASSEMBLY__ -extern gpmc_t *gpmc_cfg_base; +extern struct gpmc *gpmc_cfg; extern unsigned int boot_flash_base; extern volatile unsigned int boot_flash_env_addr; extern unsigned int boot_flash_off; diff --git a/include/configs/omap3_zoom2.h b/include/configs/omap3_zoom2.h index 9ea053d..4be5917 100644 --- a/include/configs/omap3_zoom2.h +++ b/include/configs/omap3_zoom2.h @@ -236,7 +236,7 @@ #define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
#ifndef __ASSEMBLY__ -extern gpmc_t *gpmc_cfg_base; +extern struct gpmc *gpmc_cfg; extern unsigned int boot_flash_base; extern volatile unsigned int boot_flash_env_addr; extern unsigned int boot_flash_off;
Signed-off-by: Matthias Ludwig mludwig@ultratronik.de --- board/omap3/evm/evm.c | 15 +++++++-------- board/omap3/zoom2/zoom2.c | 3 +-- cpu/arm_cortexa8/omap3/mem.c | 21 ++++++++++----------- cpu/arm_cortexa8/omap3/sys_info.c | 3 +-- drivers/mtd/nand/omap_gpmc.c | 33 ++++++++++++++++----------------- 5 files changed, 35 insertions(+), 40 deletions(-)
diff --git a/board/omap3/evm/evm.c b/board/omap3/evm/evm.c index 7747986..efbb405 100644 --- a/board/omap3/evm/evm.c +++ b/board/omap3/evm/evm.c @@ -92,17 +92,16 @@ void set_muxconf_regs(void) static void setup_net_chip(void) { struct gpio *gpio3_base = (struct gpio *)OMAP34XX_GPIO3_BASE; - struct gpmc *gpmc = (struct gpmc *)GPMC_BASE; struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
/* Configure GPMC registers */ - writel(NET_GPMC_CONFIG1, &gpmc->cs[5].config1); - writel(NET_GPMC_CONFIG2, &gpmc->cs[5].config2); - writel(NET_GPMC_CONFIG3, &gpmc->cs[5].config3); - writel(NET_GPMC_CONFIG4, &gpmc->cs[5].config4); - writel(NET_GPMC_CONFIG5, &gpmc->cs[5].config5); - writel(NET_GPMC_CONFIG6, &gpmc->cs[5].config6); - writel(NET_GPMC_CONFIG7, &gpmc->cs[5].config7); + writel(NET_GPMC_CONFIG1, &gpmc_cfg->cs[5].config1); + writel(NET_GPMC_CONFIG2, &gpmc_cfg->cs[5].config2); + writel(NET_GPMC_CONFIG3, &gpmc_cfg->cs[5].config3); + writel(NET_GPMC_CONFIG4, &gpmc_cfg->cs[5].config4); + writel(NET_GPMC_CONFIG5, &gpmc_cfg->cs[5].config5); + writel(NET_GPMC_CONFIG6, &gpmc_cfg->cs[5].config6); + writel(NET_GPMC_CONFIG7, &gpmc_cfg->cs[5].config7);
/* Enable off mode for NWE in PADCONF_GPMC_NWE register */ writew(readw(&ctrl_base ->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); diff --git a/board/omap3/zoom2/zoom2.c b/board/omap3/zoom2/zoom2.c index 0d766d1..fcc2f2c 100644 --- a/board/omap3/zoom2/zoom2.c +++ b/board/omap3/zoom2/zoom2.c @@ -67,14 +67,13 @@ static u32 gpmc_serial_TL16CP754C[GPMC_MAX_REG] = { int board_init (void) { DECLARE_GLOBAL_DATA_PTR; - struct gpmc *gpmc = (struct gpmc *)GPMC_BASE; u32 *gpmc_config;
gpmc_init (); /* in SRAM or SDRAM, finish GPMC */
/* Configure console support on zoom2 */ gpmc_config = gpmc_serial_TL16CP754C; - enable_gpmc_cs_config(gpmc_config, &gpmc->cs[4], + enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[4], SERIAL_TL16CP754C_BASE, GPMC_SIZE_16M);
/* board id for Linux */ diff --git a/cpu/arm_cortexa8/omap3/mem.c b/cpu/arm_cortexa8/omap3/mem.c index aa15f94..079c848 100644 --- a/cpu/arm_cortexa8/omap3/mem.c +++ b/cpu/arm_cortexa8/omap3/mem.c @@ -41,6 +41,8 @@ unsigned int boot_flash_sec; unsigned int boot_flash_type; volatile unsigned int boot_flash_env_addr;
+struct gpmc *gpmc_cfg; + #if defined(CONFIG_CMD_NAND) static u32 gpmc_m_nand[GPMC_MAX_REG] = { M_NAND_GPMC_CONFIG1, @@ -51,8 +53,6 @@ static u32 gpmc_m_nand[GPMC_MAX_REG] = { M_NAND_GPMC_CONFIG6, 0 };
-struct gpmc *gpmc_cfg; - #if defined(CONFIG_ENV_IS_IN_NAND) #define GPMC_CS 0 #else @@ -219,7 +219,7 @@ void gpmc_init(void) { /* putting a blanket check on GPMC based on ZeBu for now */ u32 *gpmc_config = NULL; - struct gpmc *gpmc_base = (struct gpmc *)GPMC_BASE; + gpmc_cfg = (struct gpmc *)GPMC_BASE; u32 base = 0; u32 size = 0; u32 f_off = CONFIG_SYS_MONITOR_LEN; @@ -227,27 +227,26 @@ void gpmc_init(void) u32 config = 0;
/* global settings */ - writel(0, &gpmc_base->irqenable); /* isr's sources masked */ - writel(0, &gpmc_base->timeout_control);/* timeout disable */ + writel(0, &gpmc_cfg->irqenable); /* isr's sources masked */ + writel(0, &gpmc_cfg->timeout_control);/* timeout disable */
- config = readl(&gpmc_base->config); + config = readl(&gpmc_cfg->config); config &= (~0xf00); - writel(config, &gpmc_base->config); + writel(config, &gpmc_cfg->config);
/* * Disable the GPMC0 config set by ROM code * It conflicts with our MPDB (both at 0x08000000) */ - writel(0, &gpmc_base->cs[0].config7); + writel(0, &gpmc_cfg->cs[0].config7); sdelay(1000);
#if defined(CONFIG_CMD_NAND) /* CS 0 */ gpmc_config = gpmc_m_nand; - gpmc_cfg = gpmc_base;
base = PISMO1_NAND_BASE; size = PISMO1_NAND_SIZE; - enable_gpmc_cs_config(gpmc_config, &gpmc_base->cs[0], base, size); + enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size); #if defined(CONFIG_ENV_IS_IN_NAND) f_off = SMNAND_ENV_OFFSET; f_sec = SZ_128K; @@ -263,7 +262,7 @@ void gpmc_init(void) gpmc_config = gpmc_onenand; base = PISMO1_ONEN_BASE; size = PISMO1_ONEN_SIZE; - enable_gpmc_cs_config(gpmc_config, &gpmc_base->cs[0], base, size); + enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size); #if defined(CONFIG_ENV_IS_IN_ONENAND) f_off = ONENAND_ENV_OFFSET; f_sec = SZ_128K; diff --git a/cpu/arm_cortexa8/omap3/sys_info.c b/cpu/arm_cortexa8/omap3/sys_info.c index e0e5153..765aaf2 100644 --- a/cpu/arm_cortexa8/omap3/sys_info.c +++ b/cpu/arm_cortexa8/omap3/sys_info.c @@ -32,7 +32,6 @@ #include <i2c.h>
extern omap3_sysinfo sysinfo; -static struct gpmc *gpmc_base = (struct gpmc *)GPMC_BASE; static struct sdrc *sdrc_base = (struct sdrc *)OMAP34XX_SDRC_BASE; static struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE; static char *rev_s[CPU_3XX_MAX_REV] = { @@ -160,7 +159,7 @@ u32 get_gpmc0_base(void) { u32 b;
- b = readl(&gpmc_base->cs[0].config7); + b = readl(&gpmc_cfg->cs[0].config7); b &= 0x1F; /* keep base [5:0] */ b = b << 24; /* ret 0x0b000000 */ return b; diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c index 89e8b1c..99b9cef 100644 --- a/drivers/mtd/nand/omap_gpmc.c +++ b/drivers/mtd/nand/omap_gpmc.c @@ -30,7 +30,6 @@ #include <nand.h>
static uint8_t cs; -static struct gpmc *gpmc_base = (struct gpmc *)GPMC_BASE; static struct nand_ecclayout hw_nand_oob = GPMC_NAND_HW_ECC_LAYOUT;
/* @@ -48,13 +47,13 @@ static void omap_nand_hwcontrol(struct mtd_info *mtd, int32_t cmd, */ switch (ctrl) { case NAND_CTRL_CHANGE | NAND_CTRL_CLE: - this->IO_ADDR_W = (void __iomem *)&gpmc_base->cs[cs].nand_cmd; + this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd; break; case NAND_CTRL_CHANGE | NAND_CTRL_ALE: - this->IO_ADDR_W = (void __iomem *)&gpmc_base->cs[cs].nand_adr; + this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_adr; break; case NAND_CTRL_CHANGE | NAND_NCE: - this->IO_ADDR_W = (void __iomem *)&gpmc_base->cs[cs].nand_dat; + this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat; break; }
@@ -74,8 +73,8 @@ static void omap_hwecc_init(struct nand_chip *chip) * Init ECC Control Register * Clear all ECC | Enable Reg1 */ - writel(ECCCLEAR | ECCRESULTREG1, &gpmc_base->ecc_control); - writel(ECCSIZE1 | ECCSIZE0 | ECCSIZE0SEL, &gpmc_base->ecc_size_config); + writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control); + writel(ECCSIZE1 | ECCSIZE0 | ECCSIZE0SEL, &gpmc_cfg->ecc_size_config); }
/* @@ -178,7 +177,7 @@ static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat, u_int32_t val;
/* Start Reading from HW ECC1_Result = 0x200 */ - val = readl(&gpmc_base->ecc1_result); + val = readl(&gpmc_cfg->ecc1_result);
ecc_code[0] = val & 0xFF; ecc_code[1] = (val >> 16) & 0xFF; @@ -188,7 +187,7 @@ static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat, * Stop reading anymore ECC vals and clear old results * enable will be called if more reads are required */ - writel(0x000, &gpmc_base->ecc_config); + writel(0x000, &gpmc_cfg->ecc_config);
return 0; } @@ -207,7 +206,7 @@ static void omap_enable_hwecc(struct mtd_info *mtd, int32_t mode) case NAND_ECC_READ: case NAND_ECC_WRITE: /* Clear the ecc result registers, select ecc reg as 1 */ - writel(ECCCLEAR | ECCRESULTREG1, &gpmc_base->ecc_control); + writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control);
/* * Size 0 = 0xFF, Size1 is 0xFF - both are 512 bytes @@ -215,9 +214,9 @@ static void omap_enable_hwecc(struct mtd_info *mtd, int32_t mode) * we just have a single ECC engine for all CS */ writel(ECCSIZE1 | ECCSIZE0 | ECCSIZE0SEL, - &gpmc_base->ecc_size_config); + &gpmc_cfg->ecc_size_config); val = (dev_width << 7) | (cs << 1) | (0x1); - writel(val, &gpmc_base->ecc_config); + writel(val, &gpmc_cfg->ecc_config); break; default: printf("Error: Unrecognized Mode[%d]!\n", mode); @@ -311,7 +310,7 @@ int board_nand_init(struct nand_chip *nand) */ while (cs < GPMC_MAX_CS) { /* Check if NAND type is set */ - if ((readl(&gpmc_base->cs[cs].config1) & 0xC00) == 0x800) { + if ((readl(&gpmc_cfg->cs[cs].config1) & 0xC00) == 0x800) { /* Found it!! */ break; } @@ -323,18 +322,18 @@ int board_nand_init(struct nand_chip *nand) return -ENODEV; }
- gpmc_config = readl(&gpmc_base->config); + gpmc_config = readl(&gpmc_cfg->config); /* Disable Write protect */ gpmc_config |= 0x10; - writel(gpmc_config, &gpmc_base->config); + writel(gpmc_config, &gpmc_cfg->config);
- nand->IO_ADDR_R = (void __iomem *)&gpmc_base->cs[cs].nand_dat; - nand->IO_ADDR_W = (void __iomem *)&gpmc_base->cs[cs].nand_cmd; + nand->IO_ADDR_R = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat; + nand->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd;
nand->cmd_ctrl = omap_nand_hwcontrol; nand->options = NAND_NO_PADDING | NAND_CACHEPRG | NAND_NO_AUTOINCR; /* If we are 16 bit dev, our gpmc config tells us that */ - if ((readl(&gpmc_base->cs[cs].config1) & 0x3000) == 0x1000) + if ((readl(&gpmc_cfg->cs[cs].config1) & 0x3000) == 0x1000) nand->options |= NAND_BUSWIDTH_16;
nand->chip_delay = 100;
replace variable types in ctrl_structs for omap3 by those with fixed size (u8, u16, u32). Additional ifndef-protection is needed by examples which do not compile when including asm/types.h
Signed-off-by: Matthias Ludwig mludwig@ultratronik.de --- include/asm-arm/arch-omap3/cpu.h | 412 ++++++++++++++++++++------------------ 1 files changed, 218 insertions(+), 194 deletions(-)
diff --git a/include/asm-arm/arch-omap3/cpu.h b/include/asm-arm/arch-omap3/cpu.h index b66bd85..b2c8498 100644 --- a/include/asm-arm/arch-omap3/cpu.h +++ b/include/asm-arm/arch-omap3/cpu.h @@ -25,34 +25,40 @@ #ifndef _CPU_H #define _CPU_H
+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) +#include <asm/types.h> +#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */ + /* Register offsets of common modules */ /* Control */ +#ifndef __KERNEL_STRICT_NAMES #ifndef __ASSEMBLY__ struct ctrl { - unsigned char res1[0xC0]; - unsigned short gpmc_nadv_ale; /* 0xC0 */ - unsigned short gpmc_noe; /* 0xC2 */ - unsigned short gpmc_nwe; /* 0xC4 */ - unsigned char res2[0x22A]; - unsigned int status; /* 0x2F0 */ - unsigned int gpstatus; /* 0x2F4 */ - unsigned char res3[0x08]; - unsigned int rpubkey_0; /* 0x300 */ - unsigned int rpubkey_1; /* 0x304 */ - unsigned int rpubkey_2; /* 0x308 */ - unsigned int rpubkey_3; /* 0x30C */ - unsigned int rpubkey_4; /* 0x310 */ - unsigned char res4[0x04]; - unsigned int randkey_0; /* 0x318 */ - unsigned int randkey_1; /* 0x31C */ - unsigned int randkey_2; /* 0x320 */ - unsigned int randkey_3; /* 0x324 */ - unsigned char res5[0x124]; - unsigned int ctrl_omap_stat; /* 0x44C */ + u8 res1[0xC0]; + u16 gpmc_nadv_ale; /* 0xC0 */ + u16 gpmc_noe; /* 0xC2 */ + u16 gpmc_nwe; /* 0xC4 */ + u8 res2[0x22A]; + u32 status; /* 0x2F0 */ + u32 gpstatus; /* 0x2F4 */ + u8 res3[0x08]; + u32 rpubkey_0; /* 0x300 */ + u32 rpubkey_1; /* 0x304 */ + u32 rpubkey_2; /* 0x308 */ + u32 rpubkey_3; /* 0x30C */ + u32 rpubkey_4; /* 0x310 */ + u8 res4[0x04]; + u32 randkey_0; /* 0x318 */ + u32 randkey_1; /* 0x31C */ + u32 randkey_2; /* 0x320 */ + u32 randkey_3; /* 0x324 */ + u8 res5[0x124]; + u32 ctrl_omap_stat; /* 0x44C */ }; #else /* __ASSEMBLY__ */ #define CONTROL_STATUS 0x2F0 #endif /* __ASSEMBLY__ */ +#endif /* __KERNEL_STRICT_NAMES */
/* cpu type */ #define OMAP3503 0x5c00 @@ -60,18 +66,20 @@ struct ctrl { #define OMAP3525 0x4c00 #define OMAP3530 0x0c00
+#ifndef __KERNEL_STRICT_NAMES #ifndef __ASSEMBLY__ struct ctrl_id { - unsigned char res1[0x4]; - unsigned int idcode; /* 0x04 */ - unsigned int prod_id; /* 0x08 */ - unsigned char res2[0x0C]; - unsigned int die_id_0; /* 0x18 */ - unsigned int die_id_1; /* 0x1C */ - unsigned int die_id_2; /* 0x20 */ - unsigned int die_id_3; /* 0x24 */ + u8 res1[0x4]; + u32 idcode; /* 0x04 */ + u32 prod_id; /* 0x08 */ + u8 res2[0x0C]; + u32 die_id_0; /* 0x18 */ + u32 die_id_1; /* 0x1C */ + u32 die_id_2; /* 0x20 */ + u32 die_id_3; /* 0x24 */ }; #endif /* __ASSEMBLY__ */ +#endif /* __KERNEL_STRICT_NAMES */
/* device type */ #define DEVICE_MASK (0x7 << 8) @@ -84,47 +92,48 @@ struct ctrl_id { #define GPMC_BASE (OMAP34XX_GPMC_BASE) #define GPMC_CONFIG_CS0 0x60
+#ifndef __KERNEL_STRICT_NAMES #ifndef __ASSEMBLY__ struct gpmc_cs { - unsigned int config1; /* 0x00 */ - unsigned int config2; /* 0x04 */ - unsigned int config3; /* 0x08 */ - unsigned int config4; /* 0x0C */ - unsigned int config5; /* 0x10 */ - unsigned int config6; /* 0x14 */ - unsigned int config7; /* 0x18 */ - unsigned int nand_cmd; /* 0x1C */ - unsigned int nand_adr; /* 0x20 */ - unsigned int nand_dat; /* 0x24 */ - unsigned char res[8]; /* blow up to 0x30 byte */ + u32 config1; /* 0x00 */ + u32 config2; /* 0x04 */ + u32 config3; /* 0x08 */ + u32 config4; /* 0x0C */ + u32 config5; /* 0x10 */ + u32 config6; /* 0x14 */ + u32 config7; /* 0x18 */ + u32 nand_cmd; /* 0x1C */ + u32 nand_adr; /* 0x20 */ + u32 nand_dat; /* 0x24 */ + u8 res[8]; /* blow up to 0x30 byte */ };
struct gpmc { - unsigned char res1[0x10]; - unsigned int sysconfig; /* 0x10 */ - unsigned char res2[0x4]; - unsigned int irqstatus; /* 0x18 */ - unsigned int irqenable; /* 0x1C */ - unsigned char res3[0x20]; - unsigned int timeout_control; /* 0x40 */ - unsigned char res4[0xC]; - unsigned int config; /* 0x50 */ - unsigned int status; /* 0x54 */ - unsigned char res5[0x8]; + u8 res1[0x10]; + u32 sysconfig; /* 0x10 */ + u8 res2[0x4]; + u32 irqstatus; /* 0x18 */ + u32 irqenable; /* 0x1C */ + u8 res3[0x20]; + u32 timeout_control; /* 0x40 */ + u8 res4[0xC]; + u32 config; /* 0x50 */ + u32 status; /* 0x54 */ + u8 res5[0x8]; struct gpmc_cs cs[8]; /* 0x60, 0x90, .. */ - unsigned char res6[0x18]; - unsigned int ecc_config; /* 0x1F4 */ - unsigned int ecc_control; /* 0x1F8 */ - unsigned int ecc_size_config; /* 0x1FC */ - unsigned int ecc1_result; /* 0x200 */ - unsigned int ecc2_result; /* 0x204 */ - unsigned int ecc3_result; /* 0x208 */ - unsigned int ecc4_result; /* 0x20C */ - unsigned int ecc5_result; /* 0x210 */ - unsigned int ecc6_result; /* 0x214 */ - unsigned int ecc7_result; /* 0x218 */ - unsigned int ecc8_result; /* 0x21C */ - unsigned int ecc9_result; /* 0x220 */ + u8 res6[0x18]; + u32 ecc_config; /* 0x1F4 */ + u32 ecc_control; /* 0x1F8 */ + u32 ecc_size_config; /* 0x1FC */ + u32 ecc1_result; /* 0x200 */ + u32 ecc2_result; /* 0x204 */ + u32 ecc3_result; /* 0x208 */ + u32 ecc4_result; /* 0x20C */ + u32 ecc5_result; /* 0x210 */ + u32 ecc6_result; /* 0x214 */ + u32 ecc7_result; /* 0x218 */ + u32 ecc8_result; /* 0x21C */ + u32 ecc9_result; /* 0x220 */ }; #else /* __ASSEMBLY__ */ #define GPMC_CONFIG1 0x00 @@ -135,6 +144,7 @@ struct gpmc { #define GPMC_CONFIG6 0x14 #define GPMC_CONFIG7 0x18 #endif /* __ASSEMBLY__ */ +#endif /* __KERNEL_STRICT_NAMES */
/* GPMC Mapping */ #define FLASH_BASE 0x10000000 /* NOR flash, */ @@ -150,54 +160,58 @@ struct gpmc { #define ONENAND_MAP 0x20000000 /* OneNand addr */ /* (actual size small port) */ /* SMS */ +#ifndef __KERNEL_STRICT_NAMES #ifndef __ASSEMBLY__ struct sms { - unsigned char res1[0x10]; - unsigned int sysconfig; /* 0x10 */ - unsigned char res2[0x34]; - unsigned int rg_att0; /* 0x48 */ - unsigned char res3[0x84]; - unsigned int class_arb0; /* 0xD0 */ + u8 res1[0x10]; + u32 sysconfig; /* 0x10 */ + u8 res2[0x34]; + u32 rg_att0; /* 0x48 */ + u8 res3[0x84]; + u32 class_arb0; /* 0xD0 */ }; #endif /* __ASSEMBLY__ */ +#endif /* __KERNEL_STRICT_NAMES */
#define BURSTCOMPLETE_GROUP7 (0x1 << 31)
/* SDRC */ +#ifndef __KERNEL_STRICT_NAMES #ifndef __ASSEMBLY__ struct sdrc_cs { - unsigned int mcfg; /* 0x80 || 0xB0 */ - unsigned int mr; /* 0x84 || 0xB4 */ - unsigned char res1[0x4]; - unsigned int emr2; /* 0x8C || 0xBC */ - unsigned char res2[0x14]; - unsigned int rfr_ctrl; /* 0x84 || 0xD4 */ - unsigned int manual; /* 0xA8 || 0xD8 */ - unsigned char res3[0x4]; + u32 mcfg; /* 0x80 || 0xB0 */ + u32 mr; /* 0x84 || 0xB4 */ + u8 res1[0x4]; + u32 emr2; /* 0x8C || 0xBC */ + u8 res2[0x14]; + u32 rfr_ctrl; /* 0x84 || 0xD4 */ + u32 manual; /* 0xA8 || 0xD8 */ + u8 res3[0x4]; };
struct sdrc_actim { - unsigned int ctrla; /* 0x9C || 0xC4 */ - unsigned int ctrlb; /* 0xA0 || 0xC8 */ + u32 ctrla; /* 0x9C || 0xC4 */ + u32 ctrlb; /* 0xA0 || 0xC8 */ };
struct sdrc { - unsigned char res1[0x10]; - unsigned int sysconfig; /* 0x10 */ - unsigned int status; /* 0x14 */ - unsigned char res2[0x28]; - unsigned int cs_cfg; /* 0x40 */ - unsigned int sharing; /* 0x44 */ - unsigned char res3[0x18]; - unsigned int dlla_ctrl; /* 0x60 */ - unsigned int dlla_status; /* 0x64 */ - unsigned int dllb_ctrl; /* 0x68 */ - unsigned int dllb_status; /* 0x6C */ - unsigned int power; /* 0x70 */ - unsigned char res4[0xC]; - struct sdrc_cs cs[2]; /* 0x80 || 0xB0 */ + u8 res1[0x10]; + u32 sysconfig; /* 0x10 */ + u32 status; /* 0x14 */ + u8 res2[0x28]; + u32 cs_cfg; /* 0x40 */ + u32 sharing; /* 0x44 */ + u8 res3[0x18]; + u32 dlla_ctrl; /* 0x60 */ + u32 dlla_status; /* 0x64 */ + u32 dllb_ctrl; /* 0x68 */ + u32 dllb_status; /* 0x6C */ + u32 power; /* 0x70 */ + u8 res4[0xC]; + struct sdrc_cs cs[2]; /* 0x80 || 0xB0 */ }; #endif /* __ASSEMBLY__ */ +#endif /* __KERNEL_STRICT_NAMES */
#define DLLPHASE_90 (0x1 << 1) #define LOADDLL (0x1 << 2) @@ -239,39 +253,43 @@ struct sdrc {
/* timer regs offsets (32 bit regs) */
+#ifndef __KERNEL_STRICT_NAMES #ifndef __ASSEMBLY__ struct gptimer { - unsigned int tidr; /* 0x00 r */ - unsigned char res[0xc]; - unsigned int tiocp_cfg; /* 0x10 rw */ - unsigned int tistat; /* 0x14 r */ - unsigned int tisr; /* 0x18 rw */ - unsigned int tier; /* 0x1c rw */ - unsigned int twer; /* 0x20 rw */ - unsigned int tclr; /* 0x24 rw */ - unsigned int tcrr; /* 0x28 rw */ - unsigned int tldr; /* 0x2c rw */ - unsigned int ttgr; /* 0x30 rw */ - unsigned int twpc; /* 0x34 r*/ - unsigned int tmar; /* 0x38 rw*/ - unsigned int tcar1; /* 0x3c r */ - unsigned int tcicr; /* 0x40 rw */ - unsigned int tcar2; /* 0x44 r */ + u32 tidr; /* 0x00 r */ + u8 res[0xc]; + u32 tiocp_cfg; /* 0x10 rw */ + u32 tistat; /* 0x14 r */ + u32 tisr; /* 0x18 rw */ + u32 tier; /* 0x1c rw */ + u32 twer; /* 0x20 rw */ + u32 tclr; /* 0x24 rw */ + u32 tcrr; /* 0x28 rw */ + u32 tldr; /* 0x2c rw */ + u32 ttgr; /* 0x30 rw */ + u32 twpc; /* 0x34 r*/ + u32 tmar; /* 0x38 rw*/ + u32 tcar1; /* 0x3c r */ + u32 tcicr; /* 0x40 rw */ + u32 tcar2; /* 0x44 r */ }; #endif /* __ASSEMBLY__ */ +#endif /* __KERNEL_STRICT_NAMES */
/* enable sys_clk NO-prescale /1 */ #define GPT_EN ((0x0 << 2) | (0x1 << 1) | (0x1 << 0))
/* Watchdog */ +#ifndef __KERNEL_STRICT_NAMES #ifndef __ASSEMBLY__ struct watchdog { - unsigned char res1[0x34]; - unsigned int wwps; /* 0x34 r */ - unsigned char res2[0x10]; - unsigned int wspr; /* 0x48 rw */ + u8 res1[0x34]; + u32 wwps; /* 0x34 r */ + u8 res2[0x10]; + u32 wspr; /* 0x48 rw */ }; #endif /* __ASSEMBLY__ */ +#endif /* __KERNEL_STRICT_NAMES */
#define WD_UNLOCK1 0xAAAA #define WD_UNLOCK2 0x5555 @@ -279,71 +297,72 @@ struct watchdog { /* PRCM */ #define PRCM_BASE 0x48004000
+#ifndef __KERNEL_STRICT_NAMES #ifndef __ASSEMBLY__ struct prcm { - unsigned int fclken_iva2; /* 0x00 */ - unsigned int clken_pll_iva2; /* 0x04 */ - unsigned char res1[0x1c]; - unsigned int idlest_pll_iva2; /* 0x24 */ - unsigned char res2[0x18]; - unsigned int clksel1_pll_iva2 ; /* 0x40 */ - unsigned int clksel2_pll_iva2; /* 0x44 */ - unsigned char res3[0x8bc]; - unsigned int clken_pll_mpu; /* 0x904 */ - unsigned char res4[0x1c]; - unsigned int idlest_pll_mpu; /* 0x924 */ - unsigned char res5[0x18]; - unsigned int clksel1_pll_mpu; /* 0x940 */ - unsigned int clksel2_pll_mpu; /* 0x944 */ - unsigned char res6[0xb8]; - unsigned int fclken1_core; /* 0xa00 */ - unsigned char res7[0xc]; - unsigned int iclken1_core; /* 0xa10 */ - unsigned int iclken2_core; /* 0xa14 */ - unsigned char res8[0x28]; - unsigned int clksel_core; /* 0xa40 */ - unsigned char res9[0xbc]; - unsigned int fclken_gfx; /* 0xb00 */ - unsigned char res10[0xc]; - unsigned int iclken_gfx; /* 0xb10 */ - unsigned char res11[0x2c]; - unsigned int clksel_gfx; /* 0xb40 */ - unsigned char res12[0xbc]; - unsigned int fclken_wkup; /* 0xc00 */ - unsigned char res13[0xc]; - unsigned int iclken_wkup; /* 0xc10 */ - unsigned char res14[0xc]; - unsigned int idlest_wkup; /* 0xc20 */ - unsigned char res15[0x1c]; - unsigned int clksel_wkup; /* 0xc40 */ - unsigned char res16[0xbc]; - unsigned int clken_pll; /* 0xd00 */ - unsigned char res17[0x1c]; - unsigned int idlest_ckgen; /* 0xd20 */ - unsigned char res18[0x1c]; - unsigned int clksel1_pll; /* 0xd40 */ - unsigned int clksel2_pll; /* 0xd44 */ - unsigned int clksel3_pll; /* 0xd48 */ - unsigned char res19[0xb4]; - unsigned int fclken_dss; /* 0xe00 */ - unsigned char res20[0xc]; - unsigned int iclken_dss; /* 0xe10 */ - unsigned char res21[0x2c]; - unsigned int clksel_dss; /* 0xe40 */ - unsigned char res22[0xbc]; - unsigned int fclken_cam; /* 0xf00 */ - unsigned char res23[0xc]; - unsigned int iclken_cam; /* 0xf10 */ - unsigned char res24[0x2c]; - unsigned int clksel_cam; /* 0xf40 */ - unsigned char res25[0xbc]; - unsigned int fclken_per; /* 0x1000 */ - unsigned char res26[0xc]; - unsigned int iclken_per; /* 0x1010 */ - unsigned char res27[0x2c]; - unsigned int clksel_per; /* 0x1040 */ - unsigned char res28[0xfc]; - unsigned int clksel1_emu; /* 0x1140 */ + u32 fclken_iva2; /* 0x00 */ + u32 clken_pll_iva2; /* 0x04 */ + u8 res1[0x1c]; + u32 idlest_pll_iva2; /* 0x24 */ + u8 res2[0x18]; + u32 clksel1_pll_iva2 ; /* 0x40 */ + u32 clksel2_pll_iva2; /* 0x44 */ + u8 res3[0x8bc]; + u32 clken_pll_mpu; /* 0x904 */ + u8 res4[0x1c]; + u32 idlest_pll_mpu; /* 0x924 */ + u8 res5[0x18]; + u32 clksel1_pll_mpu; /* 0x940 */ + u32 clksel2_pll_mpu; /* 0x944 */ + u8 res6[0xb8]; + u32 fclken1_core; /* 0xa00 */ + u8 res7[0xc]; + u32 iclken1_core; /* 0xa10 */ + u32 iclken2_core; /* 0xa14 */ + u8 res8[0x28]; + u32 clksel_core; /* 0xa40 */ + u8 res9[0xbc]; + u32 fclken_gfx; /* 0xb00 */ + u8 res10[0xc]; + u32 iclken_gfx; /* 0xb10 */ + u8 res11[0x2c]; + u32 clksel_gfx; /* 0xb40 */ + u8 res12[0xbc]; + u32 fclken_wkup; /* 0xc00 */ + u8 res13[0xc]; + u32 iclken_wkup; /* 0xc10 */ + u8 res14[0xc]; + u32 idlest_wkup; /* 0xc20 */ + u8 res15[0x1c]; + u32 clksel_wkup; /* 0xc40 */ + u8 res16[0xbc]; + u32 clken_pll; /* 0xd00 */ + u8 res17[0x1c]; + u32 idlest_ckgen; /* 0xd20 */ + u8 res18[0x1c]; + u32 clksel1_pll; /* 0xd40 */ + u32 clksel2_pll; /* 0xd44 */ + u32 clksel3_pll; /* 0xd48 */ + u8 res19[0xb4]; + u32 fclken_dss; /* 0xe00 */ + u8 res20[0xc]; + u32 iclken_dss; /* 0xe10 */ + u8 res21[0x2c]; + u32 clksel_dss; /* 0xe40 */ + u8 res22[0xbc]; + u32 fclken_cam; /* 0xf00 */ + u8 res23[0xc]; + u32 iclken_cam; /* 0xf10 */ + u8 res24[0x2c]; + u32 clksel_cam; /* 0xf40 */ + u8 res25[0xbc]; + u32 fclken_per; /* 0x1000 */ + u8 res26[0xc]; + u32 iclken_per; /* 0x1010 */ + u8 res27[0x2c]; + u32 clksel_per; /* 0x1040 */ + u8 res28[0xfc]; + u32 clksel1_emu; /* 0x1140 */ }; #else /* __ASSEMBLY__ */ #define CM_CLKSEL_CORE 0x48004a40 @@ -353,21 +372,24 @@ struct prcm { #define CM_CLKSEL1_PLL 0x48004d40 #define CM_CLKSEL1_EMU 0x48005140 #endif /* __ASSEMBLY__ */ +#endif /* __KERNEL_STRICT_NAMES */
#define PRM_BASE 0x48306000
+#ifndef __KERNEL_STRICT_NAMES #ifndef __ASSEMBLY__ struct prm { - unsigned char res1[0xd40]; - unsigned int clksel; /* 0xd40 */ - unsigned char res2[0x50c]; - unsigned int rstctrl; /* 0x1250 */ - unsigned char res3[0x1c]; - unsigned int clksrc_ctrl; /* 0x1270 */ + u8 res1[0xd40]; + u32 clksel; /* 0xd40 */ + u8 res2[0x50c]; + u32 rstctrl; /* 0x1250 */ + u8 res3[0x1c]; + u32 clksrc_ctrl; /* 0x1270 */ }; #else /* __ASSEMBLY__ */ #define PRM_RSTCTRL 0x48307250 #endif /* __ASSEMBLY__ */ +#endif /* __KERNEL_STRICT_NAMES */
#define SYSCLKDIV_1 (0x1 << 6) #define SYSCLKDIV_2 (0x1 << 7) @@ -399,22 +421,24 @@ struct prm { #define PM_OCM_RAM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12800) #define PM_IVA2_BASE_ADDR_ARM (SMX_APE_BASE + 0x14000)
+#ifndef __KERNEL_STRICT_NAMES #ifndef __ASSEMBLY__ struct pm { - unsigned char res1[0x48]; - unsigned int req_info_permission_0; /* 0x48 */ - unsigned char res2[0x4]; - unsigned int read_permission_0; /* 0x50 */ - unsigned char res3[0x4]; - unsigned int wirte_permission_0; /* 0x58 */ - unsigned char res4[0x4]; - unsigned int addr_match_1; /* 0x58 */ - unsigned char res5[0x4]; - unsigned int req_info_permission_1; /* 0x68 */ - unsigned char res6[0x14]; - unsigned int addr_match_2; /* 0x80 */ + u8 res1[0x48]; + u32 req_info_permission_0; /* 0x48 */ + u8 res2[0x4]; + u32 read_permission_0; /* 0x50 */ + u8 res3[0x4]; + u32 wirte_permission_0; /* 0x58 */ + u8 res4[0x4]; + u32 addr_match_1; /* 0x58 */ + u8 res5[0x4]; + u32 req_info_permission_1; /* 0x68 */ + u8 res6[0x14]; + u32 addr_match_2; /* 0x80 */ }; #endif /*__ASSEMBLY__ */ +#endif /* __KERNEL_STRICT_NAMES */
/* Permission values for registers -Full fledged permissions to all */ #define UNLOCK_1 0xFFFFFFFF
On 09:09 Tue 19 May , Matthias Ludwig wrote:
Signed-off-by: Matthias Ludwig mludwig@ultratronik.de
board/omap3/beagle/beagle.c | 6 ++-- board/omap3/evm/evm.c | 6 ++-- board/omap3/pandora/pandora.c | 8 +++--- board/omap3/zoom2/zoom2.c | 2 +- cpu/arm_cortexa8/omap3/board.c | 16 ++++++------ cpu/arm_cortexa8/omap3/clock.c | 14 +++++----- cpu/arm_cortexa8/omap3/mem.c | 14 +++++----- cpu/arm_cortexa8/omap3/sys_info.c | 12 ++++---- cpu/arm_cortexa8/omap3/timer.c | 2 +- drivers/mtd/nand/omap_gpmc.c | 2 +- include/asm-arm/arch-omap3/cpu.h | 50 ++++++++++++++++++------------------ include/asm-arm/arch-omap3/mem.h | 4 +- include/asm-arm/arch-omap3/omap3.h | 8 +++--- include/configs/omap3_beagle.h | 2 +- include/configs/omap3_evm.h | 2 +- include/configs/omap3_overo.h | 2 +- include/configs/omap3_pandora.h | 2 +- include/configs/omap3_zoom1.h | 2 +- include/configs/omap3_zoom2.h | 2 +- 19 files changed, 78 insertions(+), 78 deletions(-)
diff --git a/board/omap3/beagle/beagle.c b/board/omap3/beagle/beagle.c index 7eb70ee..2dc11dd 100644 --- a/board/omap3/beagle/beagle.c +++ b/board/omap3/beagle/beagle.c @@ -74,7 +74,7 @@ int beagle_get_revision(void) */ void beagle_identify(void) {
- gpio_t *gpio6_base = (gpio_t *)OMAP34XX_GPIO6_BASE;
- struct gpio *gpio6_base = (struct gpio *)OMAP34XX_GPIO6_BASE;
please use a namespace name gpio is too much generic and it's the same for the other struct sms, pm etc... omap_ will be better as the omap4 will certanly use the same or near IP
Best Regards, J.
Dear Jean-Christophe,
Jean-Christophe PLAGNIOL-VILLARD wrote:
On 09:09 Tue 19 May , Matthias Ludwig wrote:
Signed-off-by: Matthias Ludwig mludwig@ultratronik.de
board/omap3/beagle/beagle.c | 6 ++-- board/omap3/evm/evm.c | 6 ++-- board/omap3/pandora/pandora.c | 8 +++--- board/omap3/zoom2/zoom2.c | 2 +- cpu/arm_cortexa8/omap3/board.c | 16 ++++++------ cpu/arm_cortexa8/omap3/clock.c | 14 +++++----- cpu/arm_cortexa8/omap3/mem.c | 14 +++++----- cpu/arm_cortexa8/omap3/sys_info.c | 12 ++++---- cpu/arm_cortexa8/omap3/timer.c | 2 +- drivers/mtd/nand/omap_gpmc.c | 2 +- include/asm-arm/arch-omap3/cpu.h | 50 ++++++++++++++++++------------------ include/asm-arm/arch-omap3/mem.h | 4 +- include/asm-arm/arch-omap3/omap3.h | 8 +++--- include/configs/omap3_beagle.h | 2 +- include/configs/omap3_evm.h | 2 +- include/configs/omap3_overo.h | 2 +- include/configs/omap3_pandora.h | 2 +- include/configs/omap3_zoom1.h | 2 +- include/configs/omap3_zoom2.h | 2 +- 19 files changed, 78 insertions(+), 78 deletions(-)
diff --git a/board/omap3/beagle/beagle.c b/board/omap3/beagle/beagle.c index 7eb70ee..2dc11dd 100644 --- a/board/omap3/beagle/beagle.c +++ b/board/omap3/beagle/beagle.c @@ -74,7 +74,7 @@ int beagle_get_revision(void) */ void beagle_identify(void) {
- gpio_t *gpio6_base = (gpio_t *)OMAP34XX_GPIO6_BASE;
- struct gpio *gpio6_base = (struct gpio *)OMAP34XX_GPIO6_BASE;
please use a namespace name gpio is too much generic and it's the same for the other struct sms, pm etc... omap_ will be better as the omap4 will certanly use the same or near IP
But OMAP4 most probably will not use a file board/omap3/beagle/beagle.c.
And using "omap_" would be wrong if your argument is OMAP4. Then it needs at least to be "omap3_".
And I can't see how a local variable could pollute the namespace, if this is what you mean.
And if I remember correctly, you are against global variables (at least you mentioned it in some reviews), so a global variable called "gpio6_base" would be the issue, not the naming of this local variable.
I.e. we are in omap3 directory and have a local variable, so it's fine to use no omap_ here and do it as it is in Matthias' patch.
Best regards
Dirk
void beagle_identify(void) {
- gpio_t *gpio6_base = (gpio_t *)OMAP34XX_GPIO6_BASE;
- struct gpio *gpio6_base = (struct gpio *)OMAP34XX_GPIO6_BASE;
please use a namespace name gpio is too much generic and it's the same for the other struct sms, pm etc... omap_ will be better as the omap4 will certanly use the same or near IP
But OMAP4 most probably will not use a file board/omap3/beagle/beagle.c.
And using "omap_" would be wrong if your argument is OMAP4. Then it needs at least to be "omap3_".
And I can't see how a local variable could pollute the namespace, if this is what you mean.
where did I speak about var name? the stuct name need to be less generic
Best Regards, J.
Dear Jean-Christophe,
Jean-Christophe PLAGNIOL-VILLARD wrote:
void beagle_identify(void) {
- gpio_t *gpio6_base = (gpio_t *)OMAP34XX_GPIO6_BASE;
- struct gpio *gpio6_base = (struct gpio *)OMAP34XX_GPIO6_BASE;
please use a namespace name gpio is too much generic and it's the same for the other struct sms, pm etc... omap_ will be better as the omap4 will certanly use the same or near IP
But OMAP4 most probably will not use a file board/omap3/beagle/beagle.c.
And using "omap_" would be wrong if your argument is OMAP4. Then it needs at least to be "omap3_".
And I can't see how a local variable could pollute the namespace, if this is what you mean.
where did I speak about var name?
Nowhere, sorry. I talk about it. Please replace string 'local variable' by 'local struct' above if you think it fits better.
the stuct name need to be less generic
Why? Please see my arguments why I think it's fine as done in Matthias' patch.
Best regards
Dirk
On 18:30 Sun 24 May , Dirk Behme wrote:
Dear Jean-Christophe,
Jean-Christophe PLAGNIOL-VILLARD wrote:
void beagle_identify(void) {
- gpio_t *gpio6_base = (gpio_t *)OMAP34XX_GPIO6_BASE;
- struct gpio *gpio6_base = (struct gpio *)OMAP34XX_GPIO6_BASE;
please use a namespace name gpio is too much generic and it's the same for the other struct sms, pm etc... omap_ will be better as the omap4 will certanly use the same or near IP
But OMAP4 most probably will not use a file board/omap3/beagle/beagle.c.
And using "omap_" would be wrong if your argument is OMAP4. Then it needs at least to be "omap3_".
And I can't see how a local variable could pollute the namespace, if this is what you mean.
where did I speak about var name?
Nowhere, sorry. I talk about it. Please replace string 'local variable' by 'local struct' above if you think it fits better.
the stuct name need to be less generic
Why? Please see my arguments why I think it's fine as done in Matthias' patch.
No as If we implemenent any generic API we will have the conflict as I've to fix for the stdio
so NAK
Best Regards, J.
Dear Jean-Christophe PLAGNIOL-VILLARD,
In message 20090524195826.GB29662@game.jcrosoft.org you wrote:
the stuct name need to be less generic
Why? Please see my arguments why I think it's fine as done in Matthias' patch.
No as If we implemenent any generic API we will have the conflict as I've to fix for the stdio
so NAK
Please revert this NAK. I do not see any Coding Style or other stylistic violation in that name. It is well localized and does not hurt anybody.
Best regards,
Wolfgang Denk
Dear Matthias Ludwig,
In message 042680c935ee2a71d7cd006d3fd5c01e7893b2db.1242716287.git.mludwig@ultratronik.de you wrote:
Signed-off-by: Matthias Ludwig mludwig@ultratronik.de
board/omap3/beagle/beagle.c | 6 ++-- board/omap3/evm/evm.c | 6 ++-- board/omap3/pandora/pandora.c | 8 +++--- board/omap3/zoom2/zoom2.c | 2 +- cpu/arm_cortexa8/omap3/board.c | 16 ++++++------ cpu/arm_cortexa8/omap3/clock.c | 14 +++++----- cpu/arm_cortexa8/omap3/mem.c | 14 +++++----- cpu/arm_cortexa8/omap3/sys_info.c | 12 ++++---- cpu/arm_cortexa8/omap3/timer.c | 2 +- drivers/mtd/nand/omap_gpmc.c | 2 +- include/asm-arm/arch-omap3/cpu.h | 50 ++++++++++++++++++------------------ include/asm-arm/arch-omap3/mem.h | 4 +- include/asm-arm/arch-omap3/omap3.h | 8 +++--- include/configs/omap3_beagle.h | 2 +- include/configs/omap3_evm.h | 2 +- include/configs/omap3_overo.h | 2 +- include/configs/omap3_pandora.h | 2 +- include/configs/omap3_zoom1.h | 2 +- include/configs/omap3_zoom2.h | 2 +- 19 files changed, 78 insertions(+), 78 deletions(-)
Sorry, this does not apply, and the required changes may be small, but are non-trivial for me:
Applying: omap3: remove typedefs for configuration structs error: patch failed: board/omap3/beagle/beagle.c:74 error: board/omap3/beagle/beagle.c: patch does not apply error: patch failed: board/omap3/pandora/pandora.c:59 error: board/omap3/pandora/pandora.c: patch does not apply fatal: sha1 information is lacking or useless (board/omap3/evm/evm.c). Repository lacks necessary blobs to fall back on 3-way merge. Cannot fall back to three-way merge. Patch failed at 0001.
Please rebase and resubmit.
Best regards,
Wolfgang Denk
Dear Matthias Ludwig,
In message 4a7b8b5de50ee2b17fba444c8816c35d1fda1477.1242716287.git.mludwig@ultratronik.de you wrote:
Embedd chip select configuration into struct for gpmc config instead of having it completely separated as suggested by Wolfgang Denk on http://lists.denx.de/pipermail/u-boot/2009-May/052247.html
Signed-off-by: Matthias Ludwig mludwig@ultratronik.de
board/omap3/evm/evm.c | 16 +++++++------- board/omap3/zoom2/zoom2.c | 14 ++++-------- cpu/arm_cortexa8/omap3/mem.c | 33 +++++++++++------------------ cpu/arm_cortexa8/omap3/sys_info.c | 4 +- drivers/mtd/nand/omap_gpmc.c | 22 ++++++------------- include/asm-arm/arch-omap3/cpu.h | 41 ++++++++++++++++-------------------- include/configs/omap3_beagle.h | 1 - include/configs/omap3_evm.h | 1 - include/configs/omap3_overo.h | 1 - include/configs/omap3_pandora.h | 1 - include/configs/omap3_zoom1.h | 1 - include/configs/omap3_zoom2.h | 1 - 12 files changed, 53 insertions(+), 83 deletions(-)
Applied, thanks.
Best regards,
Wolfgang Denk
On 09:09 Tue 19 May , Matthias Ludwig wrote: as predently the commit message does not correspond with the code
it's a typo fix not, the current code work it does use the CS5 in reality
Best Regards, J.
Signed-off-by: Matthias Ludwig mludwig@ultratronik.de ---
as predently the commit message does not correspond with the code
it's a typo fix not, the current code work it does use the CS5 in reality
You are right, it's only a "typo fix". Sorry for delayed fixing...
btw: i hope this kind of inline-commenting of a patch-mail is correct?!
best regards, Matthias
board/omap3/evm/evm.c | 16 ++++++++-------- include/asm-arm/arch-omap3/cpu.h | 5 +++-- 2 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/board/omap3/evm/evm.c b/board/omap3/evm/evm.c index c008c2e..5fd5efa 100644 --- a/board/omap3/evm/evm.c +++ b/board/omap3/evm/evm.c @@ -92,17 +92,17 @@ void set_muxconf_regs(void) static void setup_net_chip(void) { gpio_t *gpio3_base = (gpio_t *)OMAP34XX_GPIO3_BASE; - gpmc_csx_t *gpmc_cs6_base = (gpmc_csx_t *)GPMC_CONFIG_CS6_BASE; + gpmc_csx_t *gpmc_cs5_base = (gpmc_csx_t *)GPMC_CONFIG_CS5_BASE; ctrl_t *ctrl_base = (ctrl_t *)OMAP34XX_CTRL_BASE;
/* Configure GPMC registers */ - writel(NET_GPMC_CONFIG1, &gpmc_cs6_base->config1); - writel(NET_GPMC_CONFIG2, &gpmc_cs6_base->config2); - writel(NET_GPMC_CONFIG3, &gpmc_cs6_base->config3); - writel(NET_GPMC_CONFIG4, &gpmc_cs6_base->config4); - writel(NET_GPMC_CONFIG5, &gpmc_cs6_base->config5); - writel(NET_GPMC_CONFIG6, &gpmc_cs6_base->config6); - writel(NET_GPMC_CONFIG7, &gpmc_cs6_base->config7); + writel(NET_GPMC_CONFIG1, &gpmc_cs5_base->config1); + writel(NET_GPMC_CONFIG2, &gpmc_cs5_base->config2); + writel(NET_GPMC_CONFIG3, &gpmc_cs5_base->config3); + writel(NET_GPMC_CONFIG4, &gpmc_cs5_base->config4); + writel(NET_GPMC_CONFIG5, &gpmc_cs5_base->config5); + writel(NET_GPMC_CONFIG6, &gpmc_cs5_base->config6); + writel(NET_GPMC_CONFIG7, &gpmc_cs5_base->config7);
/* Enable off mode for NWE in PADCONF_GPMC_NWE register */ writew(readw(&ctrl_base ->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); diff --git a/include/asm-arm/arch-omap3/cpu.h b/include/asm-arm/arch-omap3/cpu.h index c544e0c..a4ce45a 100644 --- a/include/asm-arm/arch-omap3/cpu.h +++ b/include/asm-arm/arch-omap3/cpu.h @@ -84,9 +84,10 @@ typedef struct ctrl_id { /* GPMC CS3/cs4/cs6 not avaliable */ #define GPMC_BASE (OMAP34XX_GPMC_BASE) #define GPMC_CONFIG_CS0 0x60 -#define GPMC_CONFIG_CS6 0x150 +#define GPMC_CONFIG_CS5 0x150 + #define GPMC_CONFIG_CS0_BASE (GPMC_BASE + GPMC_CONFIG_CS0) -#define GPMC_CONFIG_CS6_BASE (GPMC_BASE + GPMC_CONFIG_CS6) +#define GPMC_CONFIG_CS5_BASE (GPMC_BASE + GPMC_CONFIG_CS5) #define GPMC_CONFIG_WP 0x10
#define GPMC_CONFIG_WIDTH 0x30
On 12:31 Tue 02 Jun , Matthias Ludwig wrote:
Signed-off-by: Matthias Ludwig mludwig@ultratronik.de
as predently the commit message does not correspond with the code
it's a typo fix not, the current code work it does use the CS5 in reality
You are right, it's only a "typo fix". Sorry for delayed fixing...
btw: i hope this kind of inline-commenting of a patch-mail is correct?!
yes it's the good way
best regards, Matthias
board/omap3/evm/evm.c | 16 ++++++++-------- include/asm-arm/arch-omap3/cpu.h | 5 +++-- 2 files changed, 11 insertions(+), 10 deletions(-)
applied to arm/next
Best Regards, J.
Hi
applied to arm/next
thanks! But what about rest of the patchset?
best regards, Matthias
Matthias Ludwig wrote:
Here are some (hopefully final) changes to the omap3 cleanup.
changes since v2:
- split cs-config into 2 patches (patch 1/2)
- remove (accidentally missed) typedefs (patch 3)
- based on arm/next (zoom2 ok now)
not changed (see discussion on v2):
- using a function for gpmc config
- replacing config[1-7] by an array
compile-tested on beagle, evm, overo, pandora, zoom[12]
Whole patch series applied to u-boot next, compile tested with ./MAKEALL ARM_CORTEX_A8 (except zoom2, not all zoom2 arm/next patches are in main/next yet), boot tested on BeagleBoard: All ok.
Acked-by: Dirk Behme dirk.behme@googlemail.com
Matthias Ludwig (5): OMAP3EVM: net_chip uses CS5 not CS6 omap3: embedd gpmc_cs into gpmc config struct omap3: remove typedefs for configuration structs omap3: replace all instances of gpmc config struct by one global omap3: use only fixed-size types inside ctrl_structs
board/omap3/beagle/beagle.c | 6 +- board/omap3/evm/evm.c | 19 +- board/omap3/pandora/pandora.c | 8 +- board/omap3/zoom2/zoom2.c | 13 +- cpu/arm_cortexa8/omap3/board.c | 16 +- cpu/arm_cortexa8/omap3/clock.c | 14 +- cpu/arm_cortexa8/omap3/mem.c | 56 ++--- cpu/arm_cortexa8/omap3/sys_info.c | 13 +- cpu/arm_cortexa8/omap3/timer.c | 2 +- drivers/mtd/nand/omap_gpmc.c | 41 ++-- include/asm-arm/arch-omap3/cpu.h | 476 +++++++++++++++++++----------------- include/asm-arm/arch-omap3/mem.h | 4 +- include/asm-arm/arch-omap3/omap3.h | 8 +- include/configs/omap3_beagle.h | 3 +- include/configs/omap3_evm.h | 3 +- include/configs/omap3_overo.h | 3 +- include/configs/omap3_pandora.h | 3 +- include/configs/omap3_zoom1.h | 3 +- include/configs/omap3_zoom2.h | 3 +- 19 files changed, 342 insertions(+), 352 deletions(-)
participants (4)
-
Dirk Behme -
Jean-Christophe PLAGNIOL-VILLARD -
Matthias Ludwig -
Wolfgang Denk