[U-Boot] [PATCH u-boot-arm/next v2 1/1] OMAP3: igep00x0: add SPL support for IGEP-based boards
This patch adds SPL support for IGEP-based boards.
Tested on an IGEPv2 Rev.C board with Micron NAND Flash memory.
Signed-off-by: Javier Martinez Canillas javier@dowhile0.org ---
Changes since v1: - CONFIG_SPL_MAX_SIZE should be 54 * 1024 instead of 45 * 1024 as suggested by Tom Rini
board/isee/igep0020/config.mk | 33 -------------------- board/isee/igep0020/igep0020.c | 34 ++++++++++++++++++++- board/isee/igep0030/config.mk | 33 -------------------- board/isee/igep0030/igep0030.c | 34 ++++++++++++++++++++- include/configs/igep00x0.h | 65 ++++++++++++++++++++++++++++++++++++++++ 5 files changed, 131 insertions(+), 68 deletions(-) delete mode 100644 board/isee/igep0020/config.mk delete mode 100644 board/isee/igep0030/config.mk
diff --git a/board/isee/igep0020/config.mk b/board/isee/igep0020/config.mk deleted file mode 100644 index 7964621..0000000 --- a/board/isee/igep0020/config.mk +++ /dev/null @@ -1,33 +0,0 @@ -# -# (C) Copyright 2009 -# ISEE 2007 SL, <www.iseebcn.com> -# -# IGEP0020 uses OMAP3 (ARM-CortexA8) cpu -# see http://www.ti.com/ for more information on Texas Instruments -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# -# Physical Address: -# 8000'0000 (bank0) -# A000/0000 (bank1) -# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 -# (mem base + reserved) - -# For use with external or internal boots. -CONFIG_SYS_TEXT_BASE = 0x80008000 diff --git a/board/isee/igep0020/igep0020.c b/board/isee/igep0020/igep0020.c index 971e31b..40436d6 100644 --- a/board/isee/igep0020/igep0020.c +++ b/board/isee/igep0020/igep0020.c @@ -58,6 +58,38 @@ int board_init(void) return 0; }
+#ifdef CONFIG_SPL_BUILD +/* + * Routine: omap_rev_string + * Description: For SPL builds output board rev + */ +void omap_rev_string(void) +{ +} + +/* + * Routine: get_board_mem_timings + * Description: If we use SPL then there is no x-loader nor config header + * so we have to setup the DDR timings ourself on both banks. + */ +void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, + u32 *mr) +{ + *mr = MICRON_V_MR_165; +#ifdef CONFIG_BOOT_NAND + *mcfg = MICRON_V_MCFG_165(512 << 20); + *ctrla = MICRON_V_ACTIMA_165; + *ctrlb = MICRON_V_ACTIMB_165; + *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; +#else + *mcfg = NUMONYX_V_MCFG_165(512 << 20); + *ctrla = NUMONYX_V_ACTIMA_165; + *ctrlb = NUMONYX_V_ACTIMB_165; + *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; +#endif +} +#endif + /* * Routine: setup_net_chip * Description: Setting up the configuration GPMC registers specific to the @@ -91,7 +123,7 @@ static void setup_net_chip(void) } #endif
-#ifdef CONFIG_GENERIC_MMC +#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) int board_mmc_init(bd_t *bis) { omap_mmc_init(0, 0, 0); diff --git a/board/isee/igep0030/config.mk b/board/isee/igep0030/config.mk deleted file mode 100644 index 059a878..0000000 --- a/board/isee/igep0030/config.mk +++ /dev/null @@ -1,33 +0,0 @@ -# -# (C) Copyright 2009 -# ISEE 2007 SL, <www.iseebcn.com> -# -# IGEP0030 uses OMAP3 (ARM-CortexA8) cpu -# see http://www.ti.com/ for more information on Texas Instruments -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# -# Physical Address: -# 8000'0000 (bank0) -# A000/0000 (bank1) -# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 -# (mem base + reserved) - -# For use with external or internal boots. -CONFIG_SYS_TEXT_BASE = 0x80008000 diff --git a/board/isee/igep0030/igep0030.c b/board/isee/igep0030/igep0030.c index 653c1b5..41a7548 100644 --- a/board/isee/igep0030/igep0030.c +++ b/board/isee/igep0030/igep0030.c @@ -45,7 +45,39 @@ int board_init(void) return 0; }
-#ifdef CONFIG_GENERIC_MMC +#ifdef CONFIG_SPL_BUILD +/* + * Routine: omap_rev_string + * Description: For SPL builds output board rev + */ +void omap_rev_string(void) +{ +} + +/* + * Routine: get_board_mem_timings + * Description: If we use SPL then there is no x-loader nor config header + * so we have to setup the DDR timings ourself on both banks. + */ +void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, + u32 *mr) +{ + *mr = MICRON_V_MR_165; +#ifdef CONFIG_BOOT_NAND + *mcfg = MICRON_V_MCFG_165(512 << 20); + *ctrla = MICRON_V_ACTIMA_165; + *ctrlb = MICRON_V_ACTIMB_165; + *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; +#else + *mcfg = NUMONYX_V_MCFG_165(512 << 20); + *ctrla = NUMONYX_V_ACTIMA_165; + *ctrlb = NUMONYX_V_ACTIMB_165; + *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; +#endif +} +#endif + +#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) int board_mmc_init(bd_t *bis) { omap_mmc_init(0, 0, 0); diff --git a/include/configs/igep00x0.h b/include/configs/igep00x0.h index d8e87c3..91e5de6 100644 --- a/include/configs/igep00x0.h +++ b/include/configs/igep00x0.h @@ -287,6 +287,11 @@ #define CONFIG_SMC911X_BASE 0x2C000000 #endif /* (CONFIG_CMD_NET) */
+/* + * Leave it at 0x80008000 to allow booting new u-boot.bin with X-loader + * and older u-boot.bin with the new U-Boot SPL. + */ +#define CONFIG_SYS_TEXT_BASE 0x80008000 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 @@ -294,4 +299,64 @@ CONFIG_SYS_INIT_RAM_SIZE - \ GENERATED_GBL_DATA_SIZE)
+/* SPL */ +#define CONFIG_SPL +#define CONFIG_SPL_NAND_SIMPLE +#define CONFIG_SPL_TEXT_BASE 0x40200800 +#define CONFIG_SPL_MAX_SIZE (54 * 1024) +#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK + +/* move malloc and bss high to prevent clashing with the main image */ +#define CONFIG_SYS_SPL_MALLOC_START 0x87000000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 +#define CONFIG_SPL_BSS_START_ADDR 0x87080000 /* end of minimum RAM */ +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ + +/* MMC boot config */ +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ +#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 +#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" + +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBDISK_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_FAT_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT + +#define CONFIG_SPL_POWER_SUPPORT +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" + +#ifdef CONFIG_BOOT_ONENAND +#define CONFIG_SPL_ONENAND_SUPPORT + +/* OneNAND boot config */ +#define CONFIG_SYS_ONENAND_U_BOOT_OFFS 0x80000 +#define CONFIG_SYS_ONENAND_PAGE_SIZE 2048 +#define CONFIG_SPL_ONENAND_LOAD_ADDR 0x80000 +#define CONFIG_SPL_ONENAND_LOAD_SIZE \ + (512 * 1024 - CONFIG_SPL_ONENAND_LOAD_ADDR) + +#endif + +#ifdef CONFIG_BOOT_NAND +#define CONFIG_SPL_NAND_SUPPORT + +/* NAND boot config */ +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 +#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ + 10, 11, 12, 13} +#define CONFIG_SYS_NAND_ECCSIZE 512 +#define CONFIG_SYS_NAND_ECCBYTES 3 +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 +#endif + #endif /* __IGEP00X0_H */
2012/7/17 Javier Martinez Canillas javier@dowhile0.org:
This patch adds SPL support for IGEP-based boards.
Tested on an IGEPv2 Rev.C board with Micron NAND Flash memory.
Signed-off-by: Javier Martinez Canillas javier@dowhile0.org
Changes since v1:
- CONFIG_SPL_MAX_SIZE should be 54 * 1024 instead of 45 * 1024 as suggested by Tom Rini
board/isee/igep0020/config.mk | 33 -------------------- board/isee/igep0020/igep0020.c | 34 ++++++++++++++++++++- board/isee/igep0030/config.mk | 33 -------------------- board/isee/igep0030/igep0030.c | 34 ++++++++++++++++++++- include/configs/igep00x0.h | 65 ++++++++++++++++++++++++++++++++++++++++ 5 files changed, 131 insertions(+), 68 deletions(-) delete mode 100644 board/isee/igep0020/config.mk delete mode 100644 board/isee/igep0030/config.mk
diff --git a/board/isee/igep0020/config.mk b/board/isee/igep0020/config.mk deleted file mode 100644 index 7964621..0000000 --- a/board/isee/igep0020/config.mk +++ /dev/null @@ -1,33 +0,0 @@ -# -# (C) Copyright 2009 -# ISEE 2007 SL, <www.iseebcn.com> -# -# IGEP0020 uses OMAP3 (ARM-CortexA8) cpu -# see http://www.ti.com/ for more information on Texas Instruments -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# -# Physical Address: -# 8000'0000 (bank0) -# A000/0000 (bank1) -# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 -# (mem base + reserved)
-# For use with external or internal boots. -CONFIG_SYS_TEXT_BASE = 0x80008000 diff --git a/board/isee/igep0020/igep0020.c b/board/isee/igep0020/igep0020.c index 971e31b..40436d6 100644 --- a/board/isee/igep0020/igep0020.c +++ b/board/isee/igep0020/igep0020.c @@ -58,6 +58,38 @@ int board_init(void) return 0; }
+#ifdef CONFIG_SPL_BUILD +/*
- Routine: omap_rev_string
- Description: For SPL builds output board rev
- */
+void omap_rev_string(void) +{ +}
+/*
- Routine: get_board_mem_timings
- Description: If we use SPL then there is no x-loader nor config header
- so we have to setup the DDR timings ourself on both banks.
- */
+void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
u32 *mr)+{
*mr = MICRON_V_MR_165;+#ifdef CONFIG_BOOT_NAND
*mcfg = MICRON_V_MCFG_165(512 << 20);*ctrla = MICRON_V_ACTIMA_165;*ctrlb = MICRON_V_ACTIMB_165;*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;+#else
*mcfg = NUMONYX_V_MCFG_165(512 << 20);*ctrla = NUMONYX_V_ACTIMA_165;*ctrlb = NUMONYX_V_ACTIMB_165;*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;+#endif +} +#endif
/*
- Routine: setup_net_chip
- Description: Setting up the configuration GPMC registers specific to the
@@ -91,7 +123,7 @@ static void setup_net_chip(void) } #endif
-#ifdef CONFIG_GENERIC_MMC +#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) int board_mmc_init(bd_t *bis) { omap_mmc_init(0, 0, 0); diff --git a/board/isee/igep0030/config.mk b/board/isee/igep0030/config.mk deleted file mode 100644 index 059a878..0000000 --- a/board/isee/igep0030/config.mk +++ /dev/null @@ -1,33 +0,0 @@ -# -# (C) Copyright 2009 -# ISEE 2007 SL, <www.iseebcn.com> -# -# IGEP0030 uses OMAP3 (ARM-CortexA8) cpu -# see http://www.ti.com/ for more information on Texas Instruments -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# -# Physical Address: -# 8000'0000 (bank0) -# A000/0000 (bank1) -# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 -# (mem base + reserved)
-# For use with external or internal boots. -CONFIG_SYS_TEXT_BASE = 0x80008000 diff --git a/board/isee/igep0030/igep0030.c b/board/isee/igep0030/igep0030.c index 653c1b5..41a7548 100644 --- a/board/isee/igep0030/igep0030.c +++ b/board/isee/igep0030/igep0030.c @@ -45,7 +45,39 @@ int board_init(void) return 0; }
-#ifdef CONFIG_GENERIC_MMC +#ifdef CONFIG_SPL_BUILD +/*
- Routine: omap_rev_string
- Description: For SPL builds output board rev
- */
+void omap_rev_string(void) +{ +}
+/*
- Routine: get_board_mem_timings
- Description: If we use SPL then there is no x-loader nor config header
- so we have to setup the DDR timings ourself on both banks.
- */
+void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
u32 *mr)+{
*mr = MICRON_V_MR_165;+#ifdef CONFIG_BOOT_NAND
*mcfg = MICRON_V_MCFG_165(512 << 20);*ctrla = MICRON_V_ACTIMA_165;*ctrlb = MICRON_V_ACTIMB_165;*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;+#else
*mcfg = NUMONYX_V_MCFG_165(512 << 20);*ctrla = NUMONYX_V_ACTIMA_165;*ctrlb = NUMONYX_V_ACTIMB_165;*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;+#endif +} +#endif
+#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) int board_mmc_init(bd_t *bis) { omap_mmc_init(0, 0, 0); diff --git a/include/configs/igep00x0.h b/include/configs/igep00x0.h index d8e87c3..91e5de6 100644 --- a/include/configs/igep00x0.h +++ b/include/configs/igep00x0.h @@ -287,6 +287,11 @@ #define CONFIG_SMC911X_BASE 0x2C000000 #endif /* (CONFIG_CMD_NET) */
+/*
- Leave it at 0x80008000 to allow booting new u-boot.bin with X-loader
- and older u-boot.bin with the new U-Boot SPL.
- */
+#define CONFIG_SYS_TEXT_BASE 0x80008000 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 @@ -294,4 +299,64 @@ CONFIG_SYS_INIT_RAM_SIZE - \ GENERATED_GBL_DATA_SIZE)
+/* SPL */ +#define CONFIG_SPL +#define CONFIG_SPL_NAND_SIMPLE +#define CONFIG_SPL_TEXT_BASE 0x40200800 +#define CONFIG_SPL_MAX_SIZE (54 * 1024) +#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
+/* move malloc and bss high to prevent clashing with the main image */ +#define CONFIG_SYS_SPL_MALLOC_START 0x87000000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 +#define CONFIG_SPL_BSS_START_ADDR 0x87080000 /* end of minimum RAM */ +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
+/* MMC boot config */ +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ +#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 +#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
+#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBDISK_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_FAT_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_POWER_SUPPORT +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
+#ifdef CONFIG_BOOT_ONENAND +#define CONFIG_SPL_ONENAND_SUPPORT
+/* OneNAND boot config */ +#define CONFIG_SYS_ONENAND_U_BOOT_OFFS 0x80000 +#define CONFIG_SYS_ONENAND_PAGE_SIZE 2048 +#define CONFIG_SPL_ONENAND_LOAD_ADDR 0x80000 +#define CONFIG_SPL_ONENAND_LOAD_SIZE \
(512 * 1024 - CONFIG_SPL_ONENAND_LOAD_ADDR)+#endif
+#ifdef CONFIG_BOOT_NAND +#define CONFIG_SPL_NAND_SUPPORT
+/* NAND boot config */ +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 +#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
10, 11, 12, 13}+#define CONFIG_SYS_NAND_ECCSIZE 512 +#define CONFIG_SYS_NAND_ECCBYTES 3 +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 +#endif
#endif /* __IGEP00X0_H */
1.7.7.6
Acked-by: Enric Balletbo i Serra eballetbo@gmail.com
Le Tue, 17 Jul 2012 02:15:17 +0200, Javier Martinez Canillas javier@dowhile0.org a écrit :
+void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
u32 *mr)+{
- *mr = MICRON_V_MR_165;
+#ifdef CONFIG_BOOT_NAND
- *mcfg = MICRON_V_MCFG_165(512 << 20);
- *ctrla = MICRON_V_ACTIMA_165;
- *ctrlb = MICRON_V_ACTIMB_165;
- *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
I thought the NAND version of the IGEPv2 was capable of using the 200 Mhz timings. At least, from the limited testing I had done, it seemed to work.
Best regards,
Thomas
On Wed, Jul 18, 2012 at 5:49 PM, Thomas Petazzoni thomas.petazzoni@free-electrons.com wrote:
Le Tue, 17 Jul 2012 02:15:17 +0200, Javier Martinez Canillas javier@dowhile0.org a écrit :
+void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
u32 *mr)+{
*mr = MICRON_V_MR_165;+#ifdef CONFIG_BOOT_NAND
*mcfg = MICRON_V_MCFG_165(512 << 20);*ctrla = MICRON_V_ACTIMA_165;*ctrlb = MICRON_V_ACTIMB_165;*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;I thought the NAND version of the IGEPv2 was capable of using the 200 Mhz timings. At least, from the limited testing I had done, it seemed to work.
Best regards,
Thomas
Hi Thomas,
Yes, you are right. I just tested the following patch on my NAND version IGEPv2 and it seems to work just fine.
Do you know if the OneNAND version also supports 200 MHz timings? If I remember correctly the OMAP3730 version did but the OMAP3530 didn't.
I guess Enric knows the answer :-)
I can re-send a v2 with these modifications or send an incremental patch once this get merged, whatever you guys think is better.
Thomas, Enric and Tom,
Sorry if you got this mail twice but my first mail got bounced from the list since I sent from a another non-registered account, so I'm resending to the list again.
Best regards, Javier
diff --git a/board/isee/igep0020/igep0020.c b/board/isee/igep0020/igep0020.c index 40436d6..9035af7 100644 --- a/board/isee/igep0020/igep0020.c +++ b/board/isee/igep0020/igep0020.c @@ -77,10 +77,10 @@ void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, { *mr = MICRON_V_MR_165; #ifdef CONFIG_BOOT_NAND - *mcfg = MICRON_V_MCFG_165(512 << 20); - *ctrla = MICRON_V_ACTIMA_165; - *ctrlb = MICRON_V_ACTIMB_165; - *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + *mcfg = MICRON_V_MCFG_200(512 << 20); + *ctrla = MICRON_V_ACTIMA_200; + *ctrlb = MICRON_V_ACTIMB_200; + *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; #else *mcfg = NUMONYX_V_MCFG_165(512 << 20); *ctrla = NUMONYX_V_ACTIMA_165; diff --git a/board/isee/igep0030/igep0030.c b/board/isee/igep0030/igep0030.c index 41a7548..5c87f2d 100644 --- a/board/isee/igep0030/igep0030.c +++ b/board/isee/igep0030/igep0030.c @@ -64,10 +64,10 @@ void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, { *mr = MICRON_V_MR_165; #ifdef CONFIG_BOOT_NAND - *mcfg = MICRON_V_MCFG_165(512 << 20); - *ctrla = MICRON_V_ACTIMA_165; - *ctrlb = MICRON_V_ACTIMB_165; - *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + *mcfg = MICRON_V_MCFG_200(512 << 20); + *ctrla = MICRON_V_ACTIMA_200; + *ctrlb = MICRON_V_ACTIMB_200; + *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; #else *mcfg = NUMONYX_V_MCFG_165(512 << 20); *ctrla = NUMONYX_V_ACTIMA_165;
2012/7/19 Javier Martinez Canillas javier@dowhile0.org:
On Wed, Jul 18, 2012 at 5:49 PM, Thomas Petazzoni thomas.petazzoni@free-electrons.com wrote:
Le Tue, 17 Jul 2012 02:15:17 +0200, Javier Martinez Canillas javier@dowhile0.org a écrit :
+void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
u32 *mr)+{
*mr = MICRON_V_MR_165;+#ifdef CONFIG_BOOT_NAND
*mcfg = MICRON_V_MCFG_165(512 << 20);*ctrla = MICRON_V_ACTIMA_165;*ctrlb = MICRON_V_ACTIMB_165;*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;I thought the NAND version of the IGEPv2 was capable of using the 200 Mhz timings. At least, from the limited testing I had done, it seemed to work.
Best regards,
Thomas
Hi Thomas,
Yes, you are right. I just tested the following patch on my NAND version IGEPv2 and it seems to work just fine.
Do you know if the OneNAND version also supports 200 MHz timings? If I remember correctly the OMAP3730 version did but the OMAP3530 didn't.
I guess Enric knows the answer :-)
I can re-send a v2 with these modifications or send an incremental patch once this get merged, whatever you guys think is better.
Thomas, Enric and Tom,
Sorry if you got this mail twice but my first mail got bounced from the list since I sent from a another non-registered account, so I'm resending to the list again.
Best regards, Javier
diff --git a/board/isee/igep0020/igep0020.c b/board/isee/igep0020/igep0020.c index 40436d6..9035af7 100644 --- a/board/isee/igep0020/igep0020.c +++ b/board/isee/igep0020/igep0020.c @@ -77,10 +77,10 @@ void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, { *mr = MICRON_V_MR_165; #ifdef CONFIG_BOOT_NAND
*mcfg = MICRON_V_MCFG_165(512 << 20);*ctrla = MICRON_V_ACTIMA_165;*ctrlb = MICRON_V_ACTIMB_165;*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
*mcfg = MICRON_V_MCFG_200(512 << 20);*ctrla = MICRON_V_ACTIMA_200;*ctrlb = MICRON_V_ACTIMB_200;*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;#else *mcfg = NUMONYX_V_MCFG_165(512 << 20); *ctrla = NUMONYX_V_ACTIMA_165; diff --git a/board/isee/igep0030/igep0030.c b/board/isee/igep0030/igep0030.c index 41a7548..5c87f2d 100644 --- a/board/isee/igep0030/igep0030.c +++ b/board/isee/igep0030/igep0030.c @@ -64,10 +64,10 @@ void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, { *mr = MICRON_V_MR_165; #ifdef CONFIG_BOOT_NAND
*mcfg = MICRON_V_MCFG_165(512 << 20);*ctrla = MICRON_V_ACTIMA_165;*ctrlb = MICRON_V_ACTIMB_165;*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
*mcfg = MICRON_V_MCFG_200(512 << 20);*ctrla = MICRON_V_ACTIMA_200;*ctrlb = MICRON_V_ACTIMB_200;*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;#else *mcfg = NUMONYX_V_MCFG_165(512 << 20); *ctrla = NUMONYX_V_ACTIMA_165; _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Both memories can work at 200MHz, I guess the limitation is on the processor that is populated on the board. If the IGEP board comes with OMAP3530 should work at 166MHz, if comes with DM3730 can work at 200MHz.
Cheers, Enric
On Thu, Jul 19, 2012 at 8:56 AM, Enric Balletbò i Serra eballetbo@gmail.com wrote:
2012/7/19 Javier Martinez Canillas javier@dowhile0.org:
On Wed, Jul 18, 2012 at 5:49 PM, Thomas Petazzoni thomas.petazzoni@free-electrons.com wrote:
Le Tue, 17 Jul 2012 02:15:17 +0200, Javier Martinez Canillas javier@dowhile0.org a écrit :
+void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
u32 *mr)+{
*mr = MICRON_V_MR_165;+#ifdef CONFIG_BOOT_NAND
*mcfg = MICRON_V_MCFG_165(512 << 20);*ctrla = MICRON_V_ACTIMA_165;*ctrlb = MICRON_V_ACTIMB_165;*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;I thought the NAND version of the IGEPv2 was capable of using the 200 Mhz timings. At least, from the limited testing I had done, it seemed to work.
Best regards,
Thomas
Hi Thomas,
Yes, you are right. I just tested the following patch on my NAND version IGEPv2 and it seems to work just fine.
Do you know if the OneNAND version also supports 200 MHz timings? If I remember correctly the OMAP3730 version did but the OMAP3530 didn't.
I guess Enric knows the answer :-)
Both memories can work at 200MHz, I guess the limitation is on the processor that is populated on the board. If the IGEP board comes with OMAP3530 should work at 166MHz, if comes with DM3730 can work at 200MHz.
Cheers, Enric
Hi Enric,
That's what I remembered but I wasn't sure about it, thanks for the clarification.
What do you think about this patch then?
diff --git a/board/isee/igep0020/igep0020.c b/board/isee/igep0020/igep0020.c index 40436d6..a4d099a 100644 --- a/board/isee/igep0020/igep0020.c +++ b/board/isee/igep0020/igep0020.c @@ -77,15 +77,23 @@ void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, { *mr = MICRON_V_MR_165; #ifdef CONFIG_BOOT_NAND - *mcfg = MICRON_V_MCFG_165(512 << 20); - *ctrla = MICRON_V_ACTIMA_165; - *ctrlb = MICRON_V_ACTIMB_165; - *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + *mcfg = MICRON_V_MCFG_200(512 << 20); + *ctrla = MICRON_V_ACTIMA_200; + *ctrlb = MICRON_V_ACTIMB_200; + *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; #else - *mcfg = NUMONYX_V_MCFG_165(512 << 20); - *ctrla = NUMONYX_V_ACTIMA_165; - *ctrlb = NUMONYX_V_ACTIMB_165; - *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + if (get_cpu_family() == CPU_OMAP34XX) { + *mcfg = NUMONYX_V_MCFG_165(512 << 20); + *ctrla = NUMONYX_V_ACTIMA_165; + *ctrlb = NUMONYX_V_ACTIMB_165; + *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + + } else { + *mcfg = NUMONYX_V_MCFG_200(512 << 20); + *ctrla = NUMONYX_V_ACTIMA_200; + *ctrlb = NUMONYX_V_ACTIMB_200; + *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; + } #endif } #endif diff --git a/board/isee/igep0030/igep0030.c b/board/isee/igep0030/igep0030.c index 41a7548..4f8b645 100644 --- a/board/isee/igep0030/igep0030.c +++ b/board/isee/igep0030/igep0030.c @@ -64,15 +64,23 @@ void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, { *mr = MICRON_V_MR_165; #ifdef CONFIG_BOOT_NAND - *mcfg = MICRON_V_MCFG_165(512 << 20); - *ctrla = MICRON_V_ACTIMA_165; - *ctrlb = MICRON_V_ACTIMB_165; - *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + *mcfg = MICRON_V_MCFG_200(512 << 20); + *ctrla = MICRON_V_ACTIMA_200; + *ctrlb = MICRON_V_ACTIMB_200; + *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; #else - *mcfg = NUMONYX_V_MCFG_165(512 << 20); - *ctrla = NUMONYX_V_ACTIMA_165; - *ctrlb = NUMONYX_V_ACTIMB_165; - *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + if (get_cpu_family() == CPU_OMAP34XX) { + *mcfg = NUMONYX_V_MCFG_165(512 << 20); + *ctrla = NUMONYX_V_ACTIMA_165; + *ctrlb = NUMONYX_V_ACTIMB_165; + *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + + } else { + *mcfg = NUMONYX_V_MCFG_200(512 << 20); + *ctrla = NUMONYX_V_ACTIMA_200; + *ctrlb = NUMONYX_V_ACTIMB_200; + *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; + } #endif } #endif
2012/7/19 Javier Martinez Canillas javier@dowhile0.org:
On Thu, Jul 19, 2012 at 8:56 AM, Enric Balletbò i Serra eballetbo@gmail.com wrote:
2012/7/19 Javier Martinez Canillas javier@dowhile0.org:
On Wed, Jul 18, 2012 at 5:49 PM, Thomas Petazzoni thomas.petazzoni@free-electrons.com wrote:
Le Tue, 17 Jul 2012 02:15:17 +0200, Javier Martinez Canillas javier@dowhile0.org a écrit :
+void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
u32 *mr)+{
*mr = MICRON_V_MR_165;+#ifdef CONFIG_BOOT_NAND
*mcfg = MICRON_V_MCFG_165(512 << 20);*ctrla = MICRON_V_ACTIMA_165;*ctrlb = MICRON_V_ACTIMB_165;*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;I thought the NAND version of the IGEPv2 was capable of using the 200 Mhz timings. At least, from the limited testing I had done, it seemed to work.
Best regards,
Thomas
Hi Thomas,
Yes, you are right. I just tested the following patch on my NAND version IGEPv2 and it seems to work just fine.
Do you know if the OneNAND version also supports 200 MHz timings? If I remember correctly the OMAP3730 version did but the OMAP3530 didn't.
I guess Enric knows the answer :-)
Both memories can work at 200MHz, I guess the limitation is on the processor that is populated on the board. If the IGEP board comes with OMAP3530 should work at 166MHz, if comes with DM3730 can work at 200MHz.
Cheers, Enric
Hi Enric,
That's what I remembered but I wasn't sure about it, thanks for the clarification.
What do you think about this patch then?
diff --git a/board/isee/igep0020/igep0020.c b/board/isee/igep0020/igep0020.c index 40436d6..a4d099a 100644 --- a/board/isee/igep0020/igep0020.c +++ b/board/isee/igep0020/igep0020.c @@ -77,15 +77,23 @@ void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, { *mr = MICRON_V_MR_165; #ifdef CONFIG_BOOT_NAND
*mcfg = MICRON_V_MCFG_165(512 << 20);*ctrla = MICRON_V_ACTIMA_165;*ctrlb = MICRON_V_ACTIMB_165;*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
*mcfg = MICRON_V_MCFG_200(512 << 20);*ctrla = MICRON_V_ACTIMA_200;*ctrlb = MICRON_V_ACTIMB_200;*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;#else
*mcfg = NUMONYX_V_MCFG_165(512 << 20);*ctrla = NUMONYX_V_ACTIMA_165;*ctrlb = NUMONYX_V_ACTIMB_165;*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
if (get_cpu_family() == CPU_OMAP34XX) {*mcfg = NUMONYX_V_MCFG_165(512 << 20);*ctrla = NUMONYX_V_ACTIMA_165;*ctrlb = NUMONYX_V_ACTIMB_165;*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;} else {*mcfg = NUMONYX_V_MCFG_200(512 << 20);*ctrla = NUMONYX_V_ACTIMA_200;*ctrlb = NUMONYX_V_ACTIMB_200;*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;}#endif } #endif diff --git a/board/isee/igep0030/igep0030.c b/board/isee/igep0030/igep0030.c index 41a7548..4f8b645 100644 --- a/board/isee/igep0030/igep0030.c +++ b/board/isee/igep0030/igep0030.c @@ -64,15 +64,23 @@ void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, { *mr = MICRON_V_MR_165; #ifdef CONFIG_BOOT_NAND
*mcfg = MICRON_V_MCFG_165(512 << 20);*ctrla = MICRON_V_ACTIMA_165;*ctrlb = MICRON_V_ACTIMB_165;*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
*mcfg = MICRON_V_MCFG_200(512 << 20);*ctrla = MICRON_V_ACTIMA_200;*ctrlb = MICRON_V_ACTIMB_200;*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;#else
*mcfg = NUMONYX_V_MCFG_165(512 << 20);*ctrla = NUMONYX_V_ACTIMA_165;*ctrlb = NUMONYX_V_ACTIMB_165;*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
if (get_cpu_family() == CPU_OMAP34XX) {*mcfg = NUMONYX_V_MCFG_165(512 << 20);*ctrla = NUMONYX_V_ACTIMA_165;*ctrlb = NUMONYX_V_ACTIMB_165;*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;} else {*mcfg = NUMONYX_V_MCFG_200(512 << 20);*ctrla = NUMONYX_V_ACTIMA_200;*ctrlb = NUMONYX_V_ACTIMB_200;*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;}#endif } #endif
Thanks Thomas for making this observation.
Javier, the patch looks good for me. If we have the Numonyx OneNAND we should check if the processor is OMAP3530 or DM3730 and apply the correct timings. If we have the Micron NAND memory this check is not necessary because all boards with this memory uses DM3730.
Cheers, Enric
On Thu, Jul 19, 2012 at 9:44 AM, Enric Balletbò i Serra eballetbo@gmail.com wrote:
2012/7/19 Javier Martinez Canillas javier@dowhile0.org:
On Thu, Jul 19, 2012 at 8:56 AM, Enric Balletbò i Serra eballetbo@gmail.com wrote:
2012/7/19 Javier Martinez Canillas javier@dowhile0.org:
On Wed, Jul 18, 2012 at 5:49 PM, Thomas Petazzoni thomas.petazzoni@free-electrons.com wrote:
Le Tue, 17 Jul 2012 02:15:17 +0200, Javier Martinez Canillas javier@dowhile0.org a écrit :
+void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
u32 *mr)+{
*mr = MICRON_V_MR_165;+#ifdef CONFIG_BOOT_NAND
*mcfg = MICRON_V_MCFG_165(512 << 20);*ctrla = MICRON_V_ACTIMA_165;*ctrlb = MICRON_V_ACTIMB_165;*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;I thought the NAND version of the IGEPv2 was capable of using the 200 Mhz timings. At least, from the limited testing I had done, it seemed to work.
Best regards,
Thomas
Hi Thomas,
Yes, you are right. I just tested the following patch on my NAND version IGEPv2 and it seems to work just fine.
Do you know if the OneNAND version also supports 200 MHz timings? If I remember correctly the OMAP3730 version did but the OMAP3530 didn't.
I guess Enric knows the answer :-)
Both memories can work at 200MHz, I guess the limitation is on the processor that is populated on the board. If the IGEP board comes with OMAP3530 should work at 166MHz, if comes with DM3730 can work at 200MHz.
Cheers, Enric
Hi Enric,
That's what I remembered but I wasn't sure about it, thanks for the clarification.
What do you think about this patch then?
diff --git a/board/isee/igep0020/igep0020.c b/board/isee/igep0020/igep0020.c index 40436d6..a4d099a 100644 --- a/board/isee/igep0020/igep0020.c +++ b/board/isee/igep0020/igep0020.c @@ -77,15 +77,23 @@ void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, { *mr = MICRON_V_MR_165; #ifdef CONFIG_BOOT_NAND
*mcfg = MICRON_V_MCFG_165(512 << 20);*ctrla = MICRON_V_ACTIMA_165;*ctrlb = MICRON_V_ACTIMB_165;*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
*mcfg = MICRON_V_MCFG_200(512 << 20);*ctrla = MICRON_V_ACTIMA_200;*ctrlb = MICRON_V_ACTIMB_200;*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;#else
*mcfg = NUMONYX_V_MCFG_165(512 << 20);*ctrla = NUMONYX_V_ACTIMA_165;*ctrlb = NUMONYX_V_ACTIMB_165;*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
if (get_cpu_family() == CPU_OMAP34XX) {*mcfg = NUMONYX_V_MCFG_165(512 << 20);*ctrla = NUMONYX_V_ACTIMA_165;*ctrlb = NUMONYX_V_ACTIMB_165;*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;} else {*mcfg = NUMONYX_V_MCFG_200(512 << 20);*ctrla = NUMONYX_V_ACTIMA_200;*ctrlb = NUMONYX_V_ACTIMB_200;*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;}#endif } #endif diff --git a/board/isee/igep0030/igep0030.c b/board/isee/igep0030/igep0030.c index 41a7548..4f8b645 100644 --- a/board/isee/igep0030/igep0030.c +++ b/board/isee/igep0030/igep0030.c @@ -64,15 +64,23 @@ void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, { *mr = MICRON_V_MR_165; #ifdef CONFIG_BOOT_NAND
*mcfg = MICRON_V_MCFG_165(512 << 20);*ctrla = MICRON_V_ACTIMA_165;*ctrlb = MICRON_V_ACTIMB_165;*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
*mcfg = MICRON_V_MCFG_200(512 << 20);*ctrla = MICRON_V_ACTIMA_200;*ctrlb = MICRON_V_ACTIMB_200;*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;#else
*mcfg = NUMONYX_V_MCFG_165(512 << 20);*ctrla = NUMONYX_V_ACTIMA_165;*ctrlb = NUMONYX_V_ACTIMB_165;*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
if (get_cpu_family() == CPU_OMAP34XX) {*mcfg = NUMONYX_V_MCFG_165(512 << 20);*ctrla = NUMONYX_V_ACTIMA_165;*ctrlb = NUMONYX_V_ACTIMB_165;*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;} else {*mcfg = NUMONYX_V_MCFG_200(512 << 20);*ctrla = NUMONYX_V_ACTIMA_200;*ctrlb = NUMONYX_V_ACTIMB_200;*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;}#endif } #endif
Thanks Thomas for making this observation.
Javier, the patch looks good for me. If we have the Numonyx OneNAND we should check if the processor is OMAP3530 or DM3730 and apply the correct timings. If we have the Micron NAND memory this check is not necessary because all boards with this memory uses DM3730.
Cheers, Enric
Hi Enric,
Great, I'll send a v2 with this modification to set the correct timings then.
Do you want me to preserve your Acked-by?
Best regards, Javier
participants (3)
-
Enric Balletbò i Serra -
Javier Martinez Canillas -
Thomas Petazzoni