[U-Boot-Users] [PATCH 3/4] Modify MPC85xx CPU files for MPC8544DS board port.
Recognize new SVR values, add a few register definitions, and add a few new sysclk cases. Make some DDR biasing configurations apply only to 8548. Allow for skipping DDR initialization if it is already done.
Signed-off-by: Ed Swarthout Ed.Swarthout@freescale.com Signed-off-by: Jon Loeliger jdl@freescale.com --- cpu/mpc85xx/cpu.c | 33 ++++++++++++++++------ cpu/mpc85xx/spd_sdram.c | 68 +++++++++++++++++++++++++++++++++++++++++----- cpu/mpc85xx/speed.c | 27 +++++++++++++++--- 3 files changed, 106 insertions(+), 22 deletions(-)
diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index 0507c47..660379c 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -1,5 +1,5 @@ /* - * Copyright 2004 Freescale Semiconductor. + * Copyright 2004,2007 Freescale Semiconductor, Inc. * (C) Copyright 2002, 2003 Motorola Inc. * Xianghua Xiao (X.Xiao@motorola.com) * @@ -70,6 +70,12 @@ int checkcpu (void) case SVR_8548_E: puts("8548_E"); break; + case SVR_8544: + puts("8544"); + break; + case SVR_8544_E: + puts("8544_E"); + break; default: puts("Unknown"); break; @@ -112,7 +118,7 @@ int checkcpu (void) #endif clkdiv = lcrr & 0x0f; if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) { -#ifdef CONFIG_MPC8548 +#if defined(CONFIG_MPC8548) || defined(CONFIG_MPC8544) /* * Yes, the entire PQ38 family use the same * bit-representation for twice the clock divider values. @@ -183,9 +189,9 @@ reset_85xx_watchdog(void) * Clear TSR(WIS) bit by writing 1 */ unsigned long val; - val = mfspr(tsr); - val |= 0x40000000; - mtspr(tsr, val); + val = mfspr(SPRN_TSR); + val |= TSR_WIS; + mtspr(SPRN_TSR, val); } #endif /* CONFIG_WATCHDOG */
@@ -196,6 +202,7 @@ void dma_init(void) {
dma->satr0 = 0x02c40000; dma->datr0 = 0x02c40000; + dma->sr0 = 0xfffffff; /* clear any errors */ asm("sync; isync; msync"); return; } @@ -210,6 +217,10 @@ uint dma_check(void) { status = dma->sr0; }
+ /* clear MR0[CS] channel start bit */ + dma->mr0 &= 0x00000001; + asm("sync;isync;msync"); + if (status != 0) { printf ("DMA Error: status = %x\n", status); } @@ -254,22 +265,26 @@ ft_cpu_setup(void *blob, bd_t *bd) *p = cpu_to_be32(clock);
#if defined(CONFIG_MPC85XX_TSEC1) - p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/mac-address", &len); + p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/local-mac-address", &len); + if (p != NULL) memcpy(p, bd->bi_enetaddr, 6); #endif
#if defined(CONFIG_HAS_ETH1) - p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/mac-address", &len); + p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/local-mac-address", &len); + if (p != NULL) memcpy(p, bd->bi_enet1addr, 6); #endif
#if defined(CONFIG_HAS_ETH2) - p = ft_get_prop(blob, "/" OF_SOC "/ethernet@26000/mac-address", &len); + p = ft_get_prop(blob, "/" OF_SOC "/ethernet@26000/local-mac-address", &len); + if (p != NULL) memcpy(p, bd->bi_enet2addr, 6); #endif
#if defined(CONFIG_HAS_ETH3) - p = ft_get_prop(blob, "/" OF_SOC "/ethernet@27000/mac-address", &len); + p = ft_get_prop(blob, "/" OF_SOC "/ethernet@27000/local-mac-address", &len); + if (p != NULL) memcpy(p, bd->bi_enet3addr, 6); #endif
diff --git a/cpu/mpc85xx/spd_sdram.c b/cpu/mpc85xx/spd_sdram.c index 6da5367..45e7879 100644 --- a/cpu/mpc85xx/spd_sdram.c +++ b/cpu/mpc85xx/spd_sdram.c @@ -1,5 +1,5 @@ /* - * Copyright 2004 Freescale Semiconductor. + * Copyright 2004, 2007 Freescale Semiconductor, Inc. * (C) Copyright 2003 Motorola Inc. * Xianghua Xiao (X.Xiao@motorola.com) * @@ -173,7 +173,6 @@ spd_sdram(void) { volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile ccsr_ddr_t *ddr = &immap->im_ddr; - volatile ccsr_gur_t *gur = &immap->im_gur; spd_eeprom_t spd; unsigned int n_ranks; unsigned int rank_density; @@ -189,7 +188,7 @@ spd_sdram(void) unsigned int max_data_rate, effective_data_rate; unsigned int busfreq; unsigned sdram_cfg; - unsigned int memsize; + unsigned int memsize=0; unsigned char caslat, caslat_ctrl; unsigned int trfc, trfc_clk, trfc_low, trfc_high; unsigned int trcd_clk; @@ -204,6 +203,46 @@ spd_sdram(void) unsigned int mode_caslat; unsigned char sdram_type; unsigned char d_init; + unsigned int bnds; + + /* + * Skip configuration if already configured. + * memsize is determined from last configured chip select. + */ + if (ddr->cs0_config & 0x80000000) { + debug(" cs0 already configured, bnds=%x\n",ddr->cs0_bnds); + bnds = 0xfff & ddr->cs0_bnds; + if (bnds < 0xff) { /* do not add if at top of 4G */ + memsize = (bnds + 1) << 4; + } + } + if (ddr->cs1_config & 0x80000000) { + debug(" cs1 already configured, bnds=%x\n",ddr->cs1_bnds); + bnds = 0xfff & ddr->cs1_bnds; + if (bnds < 0xff) { /* do not add if at top of 4G */ + memsize = (bnds + 1) << 4; /* assume ordered bnds */ + } + } + if (ddr->cs2_config & 0x80000000) { + debug(" cs2 already configured, bnds=%x\n",ddr->cs2_bnds); + bnds = 0xfff & ddr->cs2_bnds; + if (bnds < 0xff) { /* do not add if at top of 4G */ + memsize = (bnds + 1) << 4; + } + } + if (ddr->cs3_config & 0x80000000) { + debug(" cs3 already configured, bnds=%x\n",ddr->cs3_bnds); + bnds = 0xfff & ddr->cs3_bnds; + if (bnds < 0xff) { /* do not add if at top of 4G */ + memsize = (bnds + 1) << 4; + } + } + + if (memsize) { + printf(" Reusing current %dMB configuration\n",memsize); + memsize = setup_laws_and_tlbs(memsize); + return memsize << 20; + }
/* * Read SPD information. @@ -262,15 +301,19 @@ spd_sdram(void) return 0; }
+#ifdef CONFIG_MPC8548 /* - * Adjust DDR II IO voltage biasing. It just makes it work. + * Adjust DDR II IO voltage biasing - fix only 8548 rev 1. */ - if (spd.mem_type == SPD_MEMTYPE_DDR2) { + if (((get_svr() & 0xffff00f0) == ((SVR_8548_E << 16) | 0x10)) + && spd.mem_type == SPD_MEMTYPE_DDR2) { + volatile ccsr_gur_t *gur = &immap->im_gur; gur->ddrioovcr = (0 | 0x80000000 /* Enable */ | 0x10000000 /* VSEL to 1.8V */ ); } +#endif
/* * Determine the size of each Rank in bytes. @@ -786,9 +829,11 @@ spd_sdram(void) * Is this an ECC DDR chip? * But don't mess with it if the DDR controller will init mem. */ -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) +#if defined(CONFIG_DDR_ECC) if (spd.config == 0x02) { +#if !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) ddr->err_disable = 0x0000000d; +#endif ddr->err_sbe = 0x00ff0000; } debug("DDR: err_disable = 0x%08x\n", ddr->err_disable); @@ -991,17 +1036,24 @@ setup_laws_and_tlbs(unsigned int memsize) break; case 256: case 512: + tlb_size = BOOKE_PAGESZ_256M; + break; case 1024: case 2048: - tlb_size = BOOKE_PAGESZ_256M; + if (PVR_VER(get_pvr()) > PVR_85xx>>16) + tlb_size = BOOKE_PAGESZ_1G; + else + tlb_size = BOOKE_PAGESZ_256M; break; default: puts("DDR: only 16M,32M,64M,128M,256M,512M,1G and 2G are supported.\n");
/* * The memory was not able to be mapped. + * Default to a small size. */ - return 0; + tlb_size = BOOKE_PAGESZ_64M; + memsize = 64; break; }
diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c index ca81ee7..3c87926 100644 --- a/cpu/mpc85xx/speed.c +++ b/cpu/mpc85xx/speed.c @@ -1,5 +1,5 @@ /* - * Copyright 2004 Freescale Semiconductor. + * Copyright 2004, 2007 Freescale Semiconductor, Inc. * (C) Copyright 2003 Motorola Inc. * Xianghua Xiao, (X.Xiao@motorola.com) * @@ -31,27 +31,32 @@
DECLARE_GLOBAL_DATA_PTR;
-/* --------------------------------------------------------------- */
-void get_sys_info (sys_info_t * sysInfo) +void get_sys_info (sys_info_t *sysInfo) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile ccsr_gur_t *gur = &immap->im_gur; uint plat_ratio,e500_ratio;
plat_ratio = (gur->porpllsr) & 0x0000003e; plat_ratio >>= 1; - switch(plat_ratio) { + + switch (plat_ratio) { case 0x02: case 0x03: case 0x04: case 0x05: case 0x06: + case 0x07: case 0x08: case 0x09: case 0x0a: + case 0x0b: case 0x0c: + case 0x0e: + case 0x0f: case 0x10: + case 0x14: sysInfo->freqSystemBus = plat_ratio * CONFIG_SYS_CLK_FREQ; break; default: @@ -62,6 +67,12 @@ void get_sys_info (sys_info_t * sysInfo) e500_ratio = (gur->porpllsr) & 0x003f0000; e500_ratio >>= 16; switch(e500_ratio) { + case 0x02: + sysInfo->freqProcessor = sysInfo->freqSystemBus; + break; + case 0x03: + sysInfo->freqProcessor = 3*sysInfo->freqSystemBus/2; + break; case 0x04: sysInfo->freqProcessor = 2*sysInfo->freqSystemBus; break; @@ -74,6 +85,12 @@ void get_sys_info (sys_info_t * sysInfo) case 0x07: sysInfo->freqProcessor = 7*sysInfo->freqSystemBus/2; break; + case 0x08: + sysInfo->freqProcessor = 4*sysInfo->freqSystemBus; + break; + case 0x09: + sysInfo->freqProcessor = 9*sysInfo->freqSystemBus/2; + break; default: sysInfo->freqProcessor = 0; break;
participants (1)
-
Jon Loeliger