Hello,

I guess you are using 10MB ethernet. In the 440 is between EMAC and PHY inserted so called ZMII bridge, which can operate in several modes. If is in the RMII mode then is necessary to set correct speed in the ZMII Speed Select Register. The following patch will fix this problem.

Pavel Bartusek Sysgo AG

--- u-boot-1.0.0/cpu/ppc4xx/405gp_enet.c.ori 2003-09-10 20:20:30.000000000 +0200 +++ u-boot-1.0.0/cpu/ppc4xx/405gp_enet.c 2003-11-21 18:08:34.000000000 +0100 @@ -67,6 +67,9 @@ * 17-Jun-02 stefan.roese@esd-electronics.com * - MAL error debug printf 'M' removed (rx de interrupt may * occur upon many incoming packets with only 4 rx buffers). + * 21-Nov-03 pavel.bartusek@sysgo.com + * - set ZMII bridge speed on 440 + * *-----------------------------------------------------------------------------*/

#include <common.h> @@ -414,6 +417,14 @@

out32 (EMAC_M1, mode_reg);

+#if defined(CONFIG_440) + /* set speed in the ZMII bridge */ + if (speed == _100BASET) + out32(ZMII_SSR, in32(ZMII_SSR) | 0x10000000); + else + out32(ZMII_SSR, in32(ZMII_SSR) & ~0x10000000); +#endif + /* Enable broadcast and indvidual address */ out32 (EMAC_RXM, EMAC_RMR_BAE | EMAC_RMR_IAE /*| EMAC_RMR_ARRP| EMAC_RMR_SFCS | EMAC_RMR_SP */ );