[PATCH 0/4] Add Cortina Access basic DM drivers
This series contains a set of basic DM drivers compatible with Cortina Access ARM and MIPS series of SoCs.
Jason Li (4): gpio: do not include <asm/arch/gpio.h> for Cortina CAxxxx SoCs gpio: cortina_gpio: add DM_GPIO driver for CAxxxx SoCs watchdog: cortina_wdt: add support for HW WDT on CAxxxx SoCs serial: serial_cortina: add UART DM driver for CAxxxx SoCs
MAINTAINERS | 8 +++ arch/arm/include/asm/gpio.h | 2 +- drivers/gpio/Kconfig | 8 +++ drivers/gpio/Makefile | 1 + drivers/gpio/cortina_gpio.c | 113 +++++++++++++++++++++++++++++++ drivers/serial/Kconfig | 7 ++ drivers/serial/Makefile | 2 +- drivers/serial/serial_cortina.c | 129 +++++++++++++++++++++++++++++++++++ drivers/serial/serial_cortina.h | 83 +++++++++++++++++++++++ drivers/watchdog/Kconfig | 8 +++ drivers/watchdog/Makefile | 1 + drivers/watchdog/cortina_wdt.c | 144 ++++++++++++++++++++++++++++++++++++++++ 12 files changed, 504 insertions(+), 2 deletions(-) create mode 100644 drivers/gpio/cortina_gpio.c create mode 100644 drivers/serial/serial_cortina.c create mode 100644 drivers/serial/serial_cortina.h create mode 100644 drivers/watchdog/cortina_wdt.c
From: Jason Li jason.li@cortina-access.com
The Cortina CAxxxx GPIO driver maintains DM_GPIO support across different CPU ISA in the CAxxxx Soc Family; Not just ARM. Therefore, it is not desirable to split out and maintain separete gpio header file for each CPU architecture.
Signed-off-by: Jason Li jason.li@cortina-access.com Signed-off-by: Alex Nemirovsky alex.nemirovsky@cortina-access.com
---
arch/arm/include/asm/gpio.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/gpio.h b/arch/arm/include/asm/gpio.h index 6ff5f42..10af1e1 100644 --- a/arch/arm/include/asm/gpio.h +++ b/arch/arm/include/asm/gpio.h @@ -3,7 +3,7 @@ !defined(CONFIG_ARCH_BCM63158) && !defined(CONFIG_ARCH_ROCKCHIP) && \ !defined(CONFIG_ARCH_LX2160A) && !defined(CONFIG_ARCH_LS1028A) && \ !defined(CONFIG_ARCH_LS2080A) && !defined(CONFIG_ARCH_LS1088A) && \ - !defined(CONFIG_ARCH_ASPEED) + !defined(CONFIG_ARCH_ASPEED) && !defined(CONFIG_CORTINA_PLATFORM) #include <asm/arch/gpio.h> #endif #include <asm-generic/gpio.h>
On Mon, 20 Jan 2020 at 02:53, Alex Nemirovsky Alex.Nemirovsky@cortina-access.com wrote:
From: Jason Li jason.li@cortina-access.com
The Cortina CAxxxx GPIO driver maintains DM_GPIO support across different CPU ISA in the CAxxxx Soc Family; Not just ARM. Therefore, it is not desirable to split out and maintain separete gpio header file for each CPU architecture.
Signed-off-by: Jason Li jason.li@cortina-access.com Signed-off-by: Alex Nemirovsky alex.nemirovsky@cortina-access.com
arch/arm/include/asm/gpio.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Simon Glass sjg@chromium.org
From: Jason Li jason.li@cortina-access.com
DM_GPIO based GPIO controller driver for CAxxxx SoCs. This driver support multiple CPU architectures and Cortina Access SoC platforms.
Signed-off-by: Jason Li jason.li@cortina-access.com Signed-off-by: Alex Nemirovsky alex.nemirovsky@cortina-access.com ---
MAINTAINERS | 2 + drivers/gpio/Kconfig | 8 ++++ drivers/gpio/Makefile | 1 + drivers/gpio/cortina_gpio.c | 113 ++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 124 insertions(+) create mode 100644 drivers/gpio/cortina_gpio.c
diff --git a/MAINTAINERS b/MAINTAINERS index 02b2e11..b7b3359 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -179,6 +179,7 @@ S: Supported F: board/cortina/common/* F: board/cortina/common/Kconfig F: board/cortina/common/armv8/lowlevel_init.S +F: drivers/gpio/cortina_gpio.c
ARM/CZ.NIC TURRIS MOX SUPPORT M: Marek Behun marek.behun@nic.cz @@ -660,6 +661,7 @@ S: Supported F: board/cortina/common/* F: board/cortina/common/Kconfig F: board/cortina/common/mips/* +F: drivers/gpio/cortina_gpio.c
MIPS MSCC M: Gregory CLEMENT gregory.clement@bootlin.com diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 1de6f52..8a7aa5a 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -59,6 +59,14 @@ config BCM6345_GPIO help This driver supports the GPIO banks on BCM6345 SoCs.
+config CORTINA_GPIO + bool "Cortina-Access GPIO driver" + depends on DM_GPIO && CORTINA_PLATFORM + help + Enable support for the GPIO controller in Cortina CAxxxx SoCs. + This driver supports all CPU ISA variants supported by Cortina + Access CAxxxx SoCs. + config DWAPB_GPIO bool "DWAPB GPIO driver" depends on DM && DM_GPIO diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 449046b..ceae612 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -17,6 +17,7 @@ endif obj-$(CONFIG_AT91_GPIO) += at91_gpio.o obj-$(CONFIG_ATMEL_PIO4) += atmel_pio4.o obj-$(CONFIG_BCM6345_GPIO) += bcm6345_gpio.o +obj-$(CONFIG_CORTINA_GPIO) += cortina_gpio.o obj-$(CONFIG_INTEL_GPIO) += intel_gpio.o obj-$(CONFIG_INTEL_ICH6_GPIO) += intel_ich6_gpio.o obj-$(CONFIG_INTEL_BROADWELL_GPIO) += intel_broadwell_gpio.o diff --git a/drivers/gpio/cortina_gpio.c b/drivers/gpio/cortina_gpio.c new file mode 100644 index 0000000..370d475 --- /dev/null +++ b/drivers/gpio/cortina_gpio.c @@ -0,0 +1,113 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright (C) 2020 Cortina-Access + * Author: Jason Li Jason.Li@cortina-access.com + * + * GPIO Driver for Cortina Access CAxxxx Line of SoCs + */ + +#include <common.h> +#include <dm.h> +#include <asm/io.h> +#include <asm/gpio.h> +#include <linux/compat.h> +#include <linux/compiler.h> + +/* GPIO Register Map */ +#define CORTINA_GPIO_CFG 0x00 +#define CORTINA_GPIO_OUT 0x04 +#define CORTINA_GPIO_IN 0x08 +#define CORTINA_GPIO_LVL 0x0C +#define CORTINA_GPIO_EDGE 0x10 +#define CORTINA_GPIO_BOTHEDGE 0x14 +#define CORTINA_GPIO_IE 0x18 +#define CORTINA_GPIO_INT 0x1C +#define CORTINA_GPIO_STAT 0x20 + +struct cortina_gpio_bank { + void __iomem *base; +}; + +#ifdef CONFIG_DM_GPIO +static int ca_gpio_direction_input(struct udevice *dev, unsigned int offset) +{ + struct cortina_gpio_bank *priv = dev_get_priv(dev); + + setbits_32(priv->base, BIT(offset)); + return 0; +} + +static int +ca_gpio_direction_output(struct udevice *dev, unsigned int offset, int value) +{ + struct cortina_gpio_bank *priv = dev_get_priv(dev); + + clrbits_32(priv->base, BIT(offset)); + return 0; +} + +static int ca_gpio_get_value(struct udevice *dev, unsigned int offset) +{ + struct cortina_gpio_bank *priv = dev_get_priv(dev); + + return readl(priv->base + CORTINA_GPIO_IN) & BIT(offset); +} + +static int ca_gpio_set_value(struct udevice *dev, unsigned int offset, + int value) +{ + struct cortina_gpio_bank *priv = dev_get_priv(dev); + + setbits_32(priv->base + CORTINA_GPIO_OUT, BIT(offset)); + return 0; +} + +static int ca_gpio_get_function(struct udevice *dev, unsigned int offset) +{ + struct cortina_gpio_bank *priv = dev_get_priv(dev); + + if (readl(priv->base) & BIT(offset)) + return GPIOF_INPUT; + else + return GPIOF_OUTPUT; +} + +static const struct dm_gpio_ops gpio_cortina_ops = { + .direction_input = ca_gpio_direction_input, + .direction_output = ca_gpio_direction_output, + .get_value = ca_gpio_get_value, + .set_value = ca_gpio_set_value, + .get_function = ca_gpio_get_function, +}; + +static int ca_gpio_probe(struct udevice *dev) +{ + struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); + struct cortina_gpio_bank *priv = dev_get_priv(dev); + + priv->base = dev_remap_addr_index(dev, 0); + if (!priv->base) + return -EINVAL; + + uc_priv->gpio_count = dev_read_u32_default(dev, "ngpios", 32); + uc_priv->bank_name = dev->name; + + printf("Done Cortina GPIO init\n"); + return 0; +} + +static const struct udevice_id ca_gpio_ids[] = { + {.compatible = "cortina,cortina-gpio"}, + {} +}; + +U_BOOT_DRIVER(cortina_gpio) = { + .name = "cortina-gpio", + .id = UCLASS_GPIO, + .ops = &gpio_cortina_ops, + .probe = ca_gpio_probe, + .priv_auto_alloc_size = sizeof(struct cortina_gpio_bank), + .of_match = ca_gpio_ids, +}; +#endif /* CONFIG_DM_GPIO */
Am 20.01.20 um 10:53 schrieb Alex Nemirovsky:
From: Jason Li jason.li@cortina-access.com
DM_GPIO based GPIO controller driver for CAxxxx SoCs. This driver support multiple CPU architectures and Cortina Access SoC platforms.
Signed-off-by: Jason Li jason.li@cortina-access.com Signed-off-by: Alex Nemirovsky alex.nemirovsky@cortina-access.com
MAINTAINERS | 2 + drivers/gpio/Kconfig | 8 ++++ drivers/gpio/Makefile | 1 + drivers/gpio/cortina_gpio.c | 113 ++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 124 insertions(+) create mode 100644 drivers/gpio/cortina_gpio.c
diff --git a/MAINTAINERS b/MAINTAINERS index 02b2e11..b7b3359 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -179,6 +179,7 @@ S: Supported F: board/cortina/common/* F: board/cortina/common/Kconfig F: board/cortina/common/armv8/lowlevel_init.S +F: drivers/gpio/cortina_gpio.c
ARM/CZ.NIC TURRIS MOX SUPPORT M: Marek Behun marek.behun@nic.cz @@ -660,6 +661,7 @@ S: Supported F: board/cortina/common/* F: board/cortina/common/Kconfig F: board/cortina/common/mips/* +F: drivers/gpio/cortina_gpio.c
MIPS MSCC M: Gregory CLEMENT gregory.clement@bootlin.com diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 1de6f52..8a7aa5a 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -59,6 +59,14 @@ config BCM6345_GPIO help This driver supports the GPIO banks on BCM6345 SoCs.
+config CORTINA_GPIO
- bool "Cortina-Access GPIO driver"
- depends on DM_GPIO && CORTINA_PLATFORM
- help
Enable support for the GPIO controller in Cortina CAxxxx SoCs.This driver supports all CPU ISA variants supported by CortinaAccess CAxxxx SoCs.config DWAPB_GPIO bool "DWAPB GPIO driver" depends on DM && DM_GPIO diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 449046b..ceae612 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -17,6 +17,7 @@ endif obj-$(CONFIG_AT91_GPIO) += at91_gpio.o obj-$(CONFIG_ATMEL_PIO4) += atmel_pio4.o obj-$(CONFIG_BCM6345_GPIO) += bcm6345_gpio.o +obj-$(CONFIG_CORTINA_GPIO) += cortina_gpio.o obj-$(CONFIG_INTEL_GPIO) += intel_gpio.o obj-$(CONFIG_INTEL_ICH6_GPIO) += intel_ich6_gpio.o obj-$(CONFIG_INTEL_BROADWELL_GPIO) += intel_broadwell_gpio.o diff --git a/drivers/gpio/cortina_gpio.c b/drivers/gpio/cortina_gpio.c new file mode 100644 index 0000000..370d475 --- /dev/null +++ b/drivers/gpio/cortina_gpio.c @@ -0,0 +1,113 @@ +// SPDX-License-Identifier: GPL-2.0+
+/*
- Copyright (C) 2020 Cortina-Access
- Author: Jason Li Jason.Li@cortina-access.com
- GPIO Driver for Cortina Access CAxxxx Line of SoCs
- */
there shouldn't be a blank line after the SPDX identifier. Also the authorship is already recorded within Git and is redundant.
+#include <common.h> +#include <dm.h> +#include <asm/io.h> +#include <asm/gpio.h> +#include <linux/compat.h> +#include <linux/compiler.h>
+/* GPIO Register Map */ +#define CORTINA_GPIO_CFG 0x00 +#define CORTINA_GPIO_OUT 0x04 +#define CORTINA_GPIO_IN 0x08 +#define CORTINA_GPIO_LVL 0x0C +#define CORTINA_GPIO_EDGE 0x10 +#define CORTINA_GPIO_BOTHEDGE 0x14 +#define CORTINA_GPIO_IE 0x18 +#define CORTINA_GPIO_INT 0x1C +#define CORTINA_GPIO_STAT 0x20
+struct cortina_gpio_bank {
- void __iomem *base;
+};
+#ifdef CONFIG_DM_GPIO +static int ca_gpio_direction_input(struct udevice *dev, unsigned int offset) +{
- struct cortina_gpio_bank *priv = dev_get_priv(dev);
- setbits_32(priv->base, BIT(offset));
- return 0;
+}
+static int +ca_gpio_direction_output(struct udevice *dev, unsigned int offset, int value) +{
- struct cortina_gpio_bank *priv = dev_get_priv(dev);
- clrbits_32(priv->base, BIT(offset));
- return 0;
+}
+static int ca_gpio_get_value(struct udevice *dev, unsigned int offset) +{
- struct cortina_gpio_bank *priv = dev_get_priv(dev);
- return readl(priv->base + CORTINA_GPIO_IN) & BIT(offset);
+}
+static int ca_gpio_set_value(struct udevice *dev, unsigned int offset,
int value)+{
- struct cortina_gpio_bank *priv = dev_get_priv(dev);
- setbits_32(priv->base + CORTINA_GPIO_OUT, BIT(offset));
- return 0;
+}
+static int ca_gpio_get_function(struct udevice *dev, unsigned int offset) +{
- struct cortina_gpio_bank *priv = dev_get_priv(dev);
- if (readl(priv->base) & BIT(offset))
return GPIOF_INPUT;- else
return GPIOF_OUTPUT;+}
+static const struct dm_gpio_ops gpio_cortina_ops = {
- .direction_input = ca_gpio_direction_input,
- .direction_output = ca_gpio_direction_output,
- .get_value = ca_gpio_get_value,
- .set_value = ca_gpio_set_value,
- .get_function = ca_gpio_get_function,
+};
+static int ca_gpio_probe(struct udevice *dev) +{
- struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
- struct cortina_gpio_bank *priv = dev_get_priv(dev);
- priv->base = dev_remap_addr_index(dev, 0);
- if (!priv->base)
return -EINVAL;- uc_priv->gpio_count = dev_read_u32_default(dev, "ngpios", 32);
- uc_priv->bank_name = dev->name;
- printf("Done Cortina GPIO init\n");
this only blos code size and messes up the boot log. You should remove it or use debug() instead.
- return 0;
+}
+static const struct udevice_id ca_gpio_ids[] = {
- {.compatible = "cortina,cortina-gpio"},
- {}
+};
+U_BOOT_DRIVER(cortina_gpio) = {
- .name = "cortina-gpio",
- .id = UCLASS_GPIO,
- .ops = &gpio_cortina_ops,
- .probe = ca_gpio_probe,
- .priv_auto_alloc_size = sizeof(struct cortina_gpio_bank),
- .of_match = ca_gpio_ids,
+}; +#endif /* CONFIG_DM_GPIO */
Hi Alex,
On Mon, 20 Jan 2020 at 02:53, Alex Nemirovsky Alex.Nemirovsky@cortina-access.com wrote:
From: Jason Li jason.li@cortina-access.com
DM_GPIO based GPIO controller driver for CAxxxx SoCs. This driver support multiple CPU architectures and Cortina Access SoC platforms.
Signed-off-by: Jason Li jason.li@cortina-access.com Signed-off-by: Alex Nemirovsky alex.nemirovsky@cortina-access.com
MAINTAINERS | 2 + drivers/gpio/Kconfig | 8 ++++ drivers/gpio/Makefile | 1 + drivers/gpio/cortina_gpio.c | 113 ++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 124 insertions(+) create mode 100644 drivers/gpio/cortina_gpio.c
diff --git a/MAINTAINERS b/MAINTAINERS index 02b2e11..b7b3359 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -179,6 +179,7 @@ S: Supported F: board/cortina/common/* F: board/cortina/common/Kconfig F: board/cortina/common/armv8/lowlevel_init.S +F: drivers/gpio/cortina_gpio.c
ARM/CZ.NIC TURRIS MOX SUPPORT M: Marek Behun marek.behun@nic.cz @@ -660,6 +661,7 @@ S: Supported F: board/cortina/common/* F: board/cortina/common/Kconfig F: board/cortina/common/mips/* +F: drivers/gpio/cortina_gpio.c
MIPS MSCC M: Gregory CLEMENT gregory.clement@bootlin.com diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 1de6f52..8a7aa5a 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -59,6 +59,14 @@ config BCM6345_GPIO help This driver supports the GPIO banks on BCM6345 SoCs.
+config CORTINA_GPIO
bool "Cortina-Access GPIO driver"depends on DM_GPIO && CORTINA_PLATFORMhelpEnable support for the GPIO controller in Cortina CAxxxx SoCs.This driver supports all CPU ISA variants supported by CortinaAccess CAxxxx SoCs.config DWAPB_GPIO bool "DWAPB GPIO driver" depends on DM && DM_GPIO diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 449046b..ceae612 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -17,6 +17,7 @@ endif obj-$(CONFIG_AT91_GPIO) += at91_gpio.o obj-$(CONFIG_ATMEL_PIO4) += atmel_pio4.o obj-$(CONFIG_BCM6345_GPIO) += bcm6345_gpio.o +obj-$(CONFIG_CORTINA_GPIO) += cortina_gpio.o obj-$(CONFIG_INTEL_GPIO) += intel_gpio.o obj-$(CONFIG_INTEL_ICH6_GPIO) += intel_ich6_gpio.o obj-$(CONFIG_INTEL_BROADWELL_GPIO) += intel_broadwell_gpio.o diff --git a/drivers/gpio/cortina_gpio.c b/drivers/gpio/cortina_gpio.c new file mode 100644 index 0000000..370d475 --- /dev/null +++ b/drivers/gpio/cortina_gpio.c @@ -0,0 +1,113 @@ +// SPDX-License-Identifier: GPL-2.0+
+/*
- Copyright (C) 2020 Cortina-Access
- Author: Jason Li Jason.Li@cortina-access.com
- GPIO Driver for Cortina Access CAxxxx Line of SoCs
- */
+#include <common.h> +#include <dm.h> +#include <asm/io.h> +#include <asm/gpio.h> +#include <linux/compat.h> +#include <linux/compiler.h>
+/* GPIO Register Map */
How about using a struct for this reg?
+#define CORTINA_GPIO_CFG 0x00 +#define CORTINA_GPIO_OUT 0x04 +#define CORTINA_GPIO_IN 0x08 +#define CORTINA_GPIO_LVL 0x0C +#define CORTINA_GPIO_EDGE 0x10 +#define CORTINA_GPIO_BOTHEDGE 0x14 +#define CORTINA_GPIO_IE 0x18 +#define CORTINA_GPIO_INT 0x1C +#define CORTINA_GPIO_STAT 0x20
+struct cortina_gpio_bank {
void __iomem *base;+};
+#ifdef CONFIG_DM_GPIO
Drop this - it will always be true for new boards.
+static int ca_gpio_direction_input(struct udevice *dev, unsigned int offset) +{
struct cortina_gpio_bank *priv = dev_get_priv(dev);setbits_32(priv->base, BIT(offset));
blank line before return (please fix below too)
return 0;+}
+static int +ca_gpio_direction_output(struct udevice *dev, unsigned int offset, int value) +{
struct cortina_gpio_bank *priv = dev_get_priv(dev);clrbits_32(priv->base, BIT(offset));return 0;+}
+static int ca_gpio_get_value(struct udevice *dev, unsigned int offset) +{
struct cortina_gpio_bank *priv = dev_get_priv(dev);return readl(priv->base + CORTINA_GPIO_IN) & BIT(offset);+}
+static int ca_gpio_set_value(struct udevice *dev, unsigned int offset,
int value)+{
struct cortina_gpio_bank *priv = dev_get_priv(dev);setbits_32(priv->base + CORTINA_GPIO_OUT, BIT(offset));return 0;+}
+static int ca_gpio_get_function(struct udevice *dev, unsigned int offset) +{
struct cortina_gpio_bank *priv = dev_get_priv(dev);if (readl(priv->base) & BIT(offset))return GPIOF_INPUT;elsereturn GPIOF_OUTPUT;
Does this hardware not support GPIOF_FUNCTION?
+}
+static const struct dm_gpio_ops gpio_cortina_ops = {
.direction_input = ca_gpio_direction_input,.direction_output = ca_gpio_direction_output,.get_value = ca_gpio_get_value,.set_value = ca_gpio_set_value,.get_function = ca_gpio_get_function,+};
+static int ca_gpio_probe(struct udevice *dev) +{
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);struct cortina_gpio_bank *priv = dev_get_priv(dev);priv->base = dev_remap_addr_index(dev, 0);if (!priv->base)return -EINVAL;uc_priv->gpio_count = dev_read_u32_default(dev, "ngpios", 32);uc_priv->bank_name = dev->name;printf("Done Cortina GPIO init\n");
Drop, or change it to debug().
return 0;+}
+static const struct udevice_id ca_gpio_ids[] = {
{.compatible = "cortina,cortina-gpio"},{}+};
+U_BOOT_DRIVER(cortina_gpio) = {
.name = "cortina-gpio",.id = UCLASS_GPIO,.ops = &gpio_cortina_ops,.probe = ca_gpio_probe,.priv_auto_alloc_size = sizeof(struct cortina_gpio_bank),.of_match = ca_gpio_ids,+};
+#endif /* CONFIG_DM_GPIO */
2.7.4
Regards, Simon
From: Jason Li jason.li@cortina-access.com
Add support for hardware watchdog timer on all Cortina Access CAxxxx family of SoCs.
Signed-off-by: Jason Li jason.li@cortina-access.com Signed-off-by: Alex Nemirovsky alex.nemirovsky@cortina-access.com ---
MAINTAINERS | 2 + drivers/watchdog/Kconfig | 8 +++ drivers/watchdog/Makefile | 1 + drivers/watchdog/cortina_wdt.c | 144 +++++++++++++++++++++++++++++++++++++++++ 4 files changed, 155 insertions(+) create mode 100644 drivers/watchdog/cortina_wdt.c
diff --git a/MAINTAINERS b/MAINTAINERS index b7b3359..f9334f9 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -180,6 +180,7 @@ F: board/cortina/common/* F: board/cortina/common/Kconfig F: board/cortina/common/armv8/lowlevel_init.S F: drivers/gpio/cortina_gpio.c +F: drivers/watchdog/cortina_wdt.c
ARM/CZ.NIC TURRIS MOX SUPPORT M: Marek Behun marek.behun@nic.cz @@ -662,6 +663,7 @@ F: board/cortina/common/* F: board/cortina/common/Kconfig F: board/cortina/common/mips/* F: drivers/gpio/cortina_gpio.c +F: drivers/watchdog/cortina_wdt.c
MIPS MSCC M: Gregory CLEMENT gregory.clement@bootlin.com diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 8c16d69..2f7dedb 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -99,6 +99,14 @@ config WDT_CDNS Select this to enable Cadence watchdog timer, which can be found on some Xilinx Microzed Platform.
+config WDT_CORTINA + bool "Cortina Access CAxxxx watchdog timer support" + depends on WDT + help + Cortina Access CAxxxx watchdog timer support. + This driver support all CPU ISAs supported by Cortina + Access CAxxxx SoCs. + config WDT_MPC8xx bool "MPC8xx watchdog timer support" depends on WDT && MPC8xx diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index 955caef..87f92a4 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -20,6 +20,7 @@ obj-$(CONFIG_WDT_SANDBOX) += sandbox_wdt.o obj-$(CONFIG_WDT_ARMADA_37XX) += armada-37xx-wdt.o obj-$(CONFIG_WDT_ASPEED) += ast_wdt.o obj-$(CONFIG_WDT_BCM6345) += bcm6345_wdt.o +obj-$(CONFIG_WDT_CORTINA) += cortina_wdt.o obj-$(CONFIG_WDT_ORION) += orion_wdt.o obj-$(CONFIG_WDT_CDNS) += cdns_wdt.o obj-$(CONFIG_WDT_MPC8xx) += mpc8xx_wdt.o diff --git a/drivers/watchdog/cortina_wdt.c b/drivers/watchdog/cortina_wdt.c new file mode 100644 index 0000000..61df802 --- /dev/null +++ b/drivers/watchdog/cortina_wdt.c @@ -0,0 +1,144 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright (C) 2020 Cortina-Access + * Author: Jason Li jason.li@cortina-access.com + * + */ + +#include <common.h> +#include <dm.h> +#include <asm/io.h> +#include <wdt.h> + +#define CA_WDT_CTRL 0x00 +#define CA_WDT_PS 0x04 +#define CA_WDT_DIV 0x08 +#define CA_WDT_LD 0x0C +#define CA_WDT_LOADE 0x10 +#define CA_WDT_CNT 0x14 +#define CA_WDT_IE 0x18 +#define CA_WDT_INT 0x1C +#define CA_WDT_STAT 0x20 + +/* CA_WDT_CTRL */ +#define CTL_WDT_EN BIT(0) +#define CTL_WDT_RSTEN BIT(1) +#define CTL_WDT_CLK_SEL BIT(2) +/* CA_WDT_LOADE */ +#define WDT_UPD BIT(0) +#define WDT_UPD_PS BIT(1) + +/* Global config */ +#define WDT_RESET_SUB BIT(4) +#define WDT_RESET_ALL_BLOCK BIT(6) +#define WDT_RESET_REMAP BIT(7) +#define WDT_EXT_RESET BIT(8) +#define WDT_RESET_DEFAULT (WDT_EXT_RESET | WDT_RESET_REMAP | + WDT_RESET_ALL_BLOCK | WDT_RESET_SUB) + +struct ca_wdt_priv { + void __iomem *base; + void __iomem *global_config; +}; + +static void cortina_wdt_set_timeout(struct udevice *dev, u64 timeout_ms) +{ + struct ca_wdt_priv *priv = dev_get_priv(dev); + + /* Prescale using millisecond unit */ + writel(CORTINA_PER_IO_FREQ / 1000, priv->base + CA_WDT_PS); + + /* Millisecond */ + writel(1, priv->base + CA_WDT_DIV); + + writel(timeout_ms, priv->base + CA_WDT_LD); + writel(WDT_UPD | WDT_UPD_PS, priv->base + CA_WDT_LOADE); +} + +static int cortina_wdt_start(struct udevice *dev, u64 timeout, ulong flags) +{ + struct ca_wdt_priv *priv = dev_get_priv(dev); + unsigned int reg_v; + + cortina_wdt_set_timeout(dev, timeout); + + /* WDT Reset option */ + reg_v = readl(priv->global_config); + reg_v |= WDT_RESET_DEFAULT; + writel(reg_v, priv->global_config); + + /* Enable WDT */ + reg_v = readl(priv->base); + reg_v |= (CTL_WDT_EN | CTL_WDT_RSTEN | CTL_WDT_CLK_SEL); + writel(reg_v, priv->base); + + return 0; +} + +static int cortina_wdt_stop(struct udevice *dev) +{ + struct ca_wdt_priv *priv = dev_get_priv(dev); + + /* Disable WDT */ + writel(0, priv->base); + + return 0; +} + +static int cortina_wdt_reset(struct udevice *dev) +{ + struct ca_wdt_priv *priv = dev_get_priv(dev); + + /* Reload WDT counter */ + writel(WDT_UPD, priv->base + CA_WDT_LOADE); + + return 0; +} + +static int cortina_wdt_expire_now(struct udevice *dev, ulong flags) +{ + /* Set 1ms timeout to reset system */ + cortina_wdt_set_timeout(dev, 1); + hang(); + + return 0; +} + +static int cortina_wdt_probe(struct udevice *dev) +{ + struct ca_wdt_priv *priv = dev_get_priv(dev); + + priv->base = dev_remap_addr_index(dev, 0); + if (!priv->base) + return -ENOENT; + + priv->global_config = dev_remap_addr_index(dev, 1); + if (!priv->global_config) + return -ENOENT; + + /* Stop WDT */ + cortina_wdt_stop(dev); + + return 0; +} + +static const struct wdt_ops cortina_wdt_ops = { + .start = cortina_wdt_start, + .reset = cortina_wdt_reset, + .stop = cortina_wdt_stop, + .expire_now = cortina_wdt_expire_now, +}; + +static const struct udevice_id cortina_wdt_ids[] = { + {.compatible = "cortina,cortina-wdt"}, + {} +}; + +U_BOOT_DRIVER(cortina_wdt) = { + .name = "cortina_wdt", + .id = UCLASS_WDT, + .probe = cortina_wdt_probe, + .of_match = cortina_wdt_ids, + .ops = &cortina_wdt_ops, +};
On 20.01.20 10:53, Alex Nemirovsky wrote:
From: Jason Li jason.li@cortina-access.com
Add support for hardware watchdog timer on all Cortina Access CAxxxx family of SoCs.
Signed-off-by: Jason Li jason.li@cortina-access.com Signed-off-by: Alex Nemirovsky alex.nemirovsky@cortina-access.com
MAINTAINERS | 2 + drivers/watchdog/Kconfig | 8 +++ drivers/watchdog/Makefile | 1 + drivers/watchdog/cortina_wdt.c | 144 +++++++++++++++++++++++++++++++++++++++++ 4 files changed, 155 insertions(+) create mode 100644 drivers/watchdog/cortina_wdt.c
diff --git a/MAINTAINERS b/MAINTAINERS index b7b3359..f9334f9 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -180,6 +180,7 @@ F: board/cortina/common/* F: board/cortina/common/Kconfig F: board/cortina/common/armv8/lowlevel_init.S F: drivers/gpio/cortina_gpio.c +F: drivers/watchdog/cortina_wdt.c
ARM/CZ.NIC TURRIS MOX SUPPORT M: Marek Behun marek.behun@nic.cz @@ -662,6 +663,7 @@ F: board/cortina/common/* F: board/cortina/common/Kconfig F: board/cortina/common/mips/* F: drivers/gpio/cortina_gpio.c +F: drivers/watchdog/cortina_wdt.c
MIPS MSCC M: Gregory CLEMENT gregory.clement@bootlin.com diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 8c16d69..2f7dedb 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -99,6 +99,14 @@ config WDT_CDNS Select this to enable Cadence watchdog timer, which can be found on some Xilinx Microzed Platform.
+config WDT_CORTINA
- bool "Cortina Access CAxxxx watchdog timer support"
- depends on WDT
- help
Cortina Access CAxxxx watchdog timer support.This driver support all CPU ISAs supported by CortinaAccess CAxxxx SoCs.- config WDT_MPC8xx bool "MPC8xx watchdog timer support" depends on WDT && MPC8xx
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index 955caef..87f92a4 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -20,6 +20,7 @@ obj-$(CONFIG_WDT_SANDBOX) += sandbox_wdt.o obj-$(CONFIG_WDT_ARMADA_37XX) += armada-37xx-wdt.o obj-$(CONFIG_WDT_ASPEED) += ast_wdt.o obj-$(CONFIG_WDT_BCM6345) += bcm6345_wdt.o +obj-$(CONFIG_WDT_CORTINA) += cortina_wdt.o obj-$(CONFIG_WDT_ORION) += orion_wdt.o obj-$(CONFIG_WDT_CDNS) += cdns_wdt.o obj-$(CONFIG_WDT_MPC8xx) += mpc8xx_wdt.o diff --git a/drivers/watchdog/cortina_wdt.c b/drivers/watchdog/cortina_wdt.c new file mode 100644 index 0000000..61df802 --- /dev/null +++ b/drivers/watchdog/cortina_wdt.c @@ -0,0 +1,144 @@ +// SPDX-License-Identifier: GPL-2.0+
+/*
- Copyright (C) 2020 Cortina-Access
- Author: Jason Li jason.li@cortina-access.com
- */
+#include <common.h> +#include <dm.h> +#include <asm/io.h> +#include <wdt.h>
+#define CA_WDT_CTRL 0x00 +#define CA_WDT_PS 0x04 +#define CA_WDT_DIV 0x08 +#define CA_WDT_LD 0x0C +#define CA_WDT_LOADE 0x10 +#define CA_WDT_CNT 0x14 +#define CA_WDT_IE 0x18 +#define CA_WDT_INT 0x1C +#define CA_WDT_STAT 0x20
+/* CA_WDT_CTRL */ +#define CTL_WDT_EN BIT(0) +#define CTL_WDT_RSTEN BIT(1) +#define CTL_WDT_CLK_SEL BIT(2) +/* CA_WDT_LOADE */ +#define WDT_UPD BIT(0) +#define WDT_UPD_PS BIT(1)
+/* Global config */ +#define WDT_RESET_SUB BIT(4) +#define WDT_RESET_ALL_BLOCK BIT(6) +#define WDT_RESET_REMAP BIT(7) +#define WDT_EXT_RESET BIT(8) +#define WDT_RESET_DEFAULT (WDT_EXT_RESET | WDT_RESET_REMAP |
WDT_RESET_ALL_BLOCK | WDT_RESET_SUB)+struct ca_wdt_priv {
- void __iomem *base;
- void __iomem *global_config;
+};
+static void cortina_wdt_set_timeout(struct udevice *dev, u64 timeout_ms) +{
- struct ca_wdt_priv *priv = dev_get_priv(dev);
- /* Prescale using millisecond unit */
- writel(CORTINA_PER_IO_FREQ / 1000, priv->base + CA_WDT_PS);
- /* Millisecond */
- writel(1, priv->base + CA_WDT_DIV);
- writel(timeout_ms, priv->base + CA_WDT_LD);
- writel(WDT_UPD | WDT_UPD_PS, priv->base + CA_WDT_LOADE);
+}
+static int cortina_wdt_start(struct udevice *dev, u64 timeout, ulong flags) +{
- struct ca_wdt_priv *priv = dev_get_priv(dev);
- unsigned int reg_v;
- cortina_wdt_set_timeout(dev, timeout);
- /* WDT Reset option */
- reg_v = readl(priv->global_config);
- reg_v |= WDT_RESET_DEFAULT;
- writel(reg_v, priv->global_config);
- /* Enable WDT */
- reg_v = readl(priv->base);
- reg_v |= (CTL_WDT_EN | CTL_WDT_RSTEN | CTL_WDT_CLK_SEL);
- writel(reg_v, priv->base);
- return 0;
+}
+static int cortina_wdt_stop(struct udevice *dev) +{
- struct ca_wdt_priv *priv = dev_get_priv(dev);
- /* Disable WDT */
- writel(0, priv->base);
- return 0;
+}
+static int cortina_wdt_reset(struct udevice *dev) +{
- struct ca_wdt_priv *priv = dev_get_priv(dev);
- /* Reload WDT counter */
- writel(WDT_UPD, priv->base + CA_WDT_LOADE);
- return 0;
+}
+static int cortina_wdt_expire_now(struct udevice *dev, ulong flags) +{
- /* Set 1ms timeout to reset system */
- cortina_wdt_set_timeout(dev, 1);
- hang();
- return 0;
+}
+static int cortina_wdt_probe(struct udevice *dev) +{
- struct ca_wdt_priv *priv = dev_get_priv(dev);
- priv->base = dev_remap_addr_index(dev, 0);
- if (!priv->base)
return -ENOENT;- priv->global_config = dev_remap_addr_index(dev, 1);
- if (!priv->global_config)
return -ENOENT;- /* Stop WDT */
- cortina_wdt_stop(dev);
- return 0;
+}
+static const struct wdt_ops cortina_wdt_ops = {
- .start = cortina_wdt_start,
- .reset = cortina_wdt_reset,
- .stop = cortina_wdt_stop,
- .expire_now = cortina_wdt_expire_now,
+};
+static const struct udevice_id cortina_wdt_ids[] = {
- {.compatible = "cortina,cortina-wdt"},
- {}
+};
+U_BOOT_DRIVER(cortina_wdt) = {
- .name = "cortina_wdt",
- .id = UCLASS_WDT,
- .probe = cortina_wdt_probe,
- .of_match = cortina_wdt_ids,
- .ops = &cortina_wdt_ops,
+};
Looks good.
Reviewed-by: Stefan Roese sr@denx.de
Thanks, Stefan
Am 20.01.20 um 10:53 schrieb Alex Nemirovsky:
From: Jason Li jason.li@cortina-access.com
Add support for hardware watchdog timer on all Cortina Access CAxxxx family of SoCs.
Signed-off-by: Jason Li jason.li@cortina-access.com Signed-off-by: Alex Nemirovsky alex.nemirovsky@cortina-access.com
MAINTAINERS | 2 + drivers/watchdog/Kconfig | 8 +++ drivers/watchdog/Makefile | 1 + drivers/watchdog/cortina_wdt.c | 144 +++++++++++++++++++++++++++++++++++++++++ 4 files changed, 155 insertions(+) create mode 100644 drivers/watchdog/cortina_wdt.c
diff --git a/MAINTAINERS b/MAINTAINERS index b7b3359..f9334f9 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -180,6 +180,7 @@ F: board/cortina/common/* F: board/cortina/common/Kconfig F: board/cortina/common/armv8/lowlevel_init.S F: drivers/gpio/cortina_gpio.c +F: drivers/watchdog/cortina_wdt.c
ARM/CZ.NIC TURRIS MOX SUPPORT M: Marek Behun marek.behun@nic.cz @@ -662,6 +663,7 @@ F: board/cortina/common/* F: board/cortina/common/Kconfig F: board/cortina/common/mips/* F: drivers/gpio/cortina_gpio.c +F: drivers/watchdog/cortina_wdt.c
MIPS MSCC M: Gregory CLEMENT gregory.clement@bootlin.com diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 8c16d69..2f7dedb 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -99,6 +99,14 @@ config WDT_CDNS Select this to enable Cadence watchdog timer, which can be found on some Xilinx Microzed Platform.
+config WDT_CORTINA
- bool "Cortina Access CAxxxx watchdog timer support"
- depends on WDT
- help
Cortina Access CAxxxx watchdog timer support.This driver support all CPU ISAs supported by CortinaAccess CAxxxx SoCs.config WDT_MPC8xx bool "MPC8xx watchdog timer support" depends on WDT && MPC8xx diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index 955caef..87f92a4 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -20,6 +20,7 @@ obj-$(CONFIG_WDT_SANDBOX) += sandbox_wdt.o obj-$(CONFIG_WDT_ARMADA_37XX) += armada-37xx-wdt.o obj-$(CONFIG_WDT_ASPEED) += ast_wdt.o obj-$(CONFIG_WDT_BCM6345) += bcm6345_wdt.o +obj-$(CONFIG_WDT_CORTINA) += cortina_wdt.o obj-$(CONFIG_WDT_ORION) += orion_wdt.o obj-$(CONFIG_WDT_CDNS) += cdns_wdt.o obj-$(CONFIG_WDT_MPC8xx) += mpc8xx_wdt.o diff --git a/drivers/watchdog/cortina_wdt.c b/drivers/watchdog/cortina_wdt.c new file mode 100644 index 0000000..61df802 --- /dev/null +++ b/drivers/watchdog/cortina_wdt.c @@ -0,0 +1,144 @@ +// SPDX-License-Identifier: GPL-2.0+
+/*
- Copyright (C) 2020 Cortina-Access
- Author: Jason Li jason.li@cortina-access.com
- */
same comment as in patch 2/4
+#include <common.h> +#include <dm.h> +#include <asm/io.h> +#include <wdt.h>
+#define CA_WDT_CTRL 0x00 +#define CA_WDT_PS 0x04 +#define CA_WDT_DIV 0x08 +#define CA_WDT_LD 0x0C +#define CA_WDT_LOADE 0x10 +#define CA_WDT_CNT 0x14 +#define CA_WDT_IE 0x18 +#define CA_WDT_INT 0x1C +#define CA_WDT_STAT 0x20
+/* CA_WDT_CTRL */ +#define CTL_WDT_EN BIT(0) +#define CTL_WDT_RSTEN BIT(1) +#define CTL_WDT_CLK_SEL BIT(2) +/* CA_WDT_LOADE */ +#define WDT_UPD BIT(0) +#define WDT_UPD_PS BIT(1)
+/* Global config */ +#define WDT_RESET_SUB BIT(4) +#define WDT_RESET_ALL_BLOCK BIT(6) +#define WDT_RESET_REMAP BIT(7) +#define WDT_EXT_RESET BIT(8) +#define WDT_RESET_DEFAULT (WDT_EXT_RESET | WDT_RESET_REMAP |
WDT_RESET_ALL_BLOCK | WDT_RESET_SUB)+struct ca_wdt_priv {
- void __iomem *base;
- void __iomem *global_config;
+};
+static void cortina_wdt_set_timeout(struct udevice *dev, u64 timeout_ms) +{
- struct ca_wdt_priv *priv = dev_get_priv(dev);
- /* Prescale using millisecond unit */
- writel(CORTINA_PER_IO_FREQ / 1000, priv->base + CA_WDT_PS);
- /* Millisecond */
- writel(1, priv->base + CA_WDT_DIV);
- writel(timeout_ms, priv->base + CA_WDT_LD);
- writel(WDT_UPD | WDT_UPD_PS, priv->base + CA_WDT_LOADE);
+}
+static int cortina_wdt_start(struct udevice *dev, u64 timeout, ulong flags) +{
- struct ca_wdt_priv *priv = dev_get_priv(dev);
- unsigned int reg_v;
- cortina_wdt_set_timeout(dev, timeout);
- /* WDT Reset option */
- reg_v = readl(priv->global_config);
- reg_v |= WDT_RESET_DEFAULT;
- writel(reg_v, priv->global_config);
- /* Enable WDT */
- reg_v = readl(priv->base);
- reg_v |= (CTL_WDT_EN | CTL_WDT_RSTEN | CTL_WDT_CLK_SEL);
- writel(reg_v, priv->base);
setbits_32() ?
- return 0;
+}
+static int cortina_wdt_stop(struct udevice *dev) +{
- struct ca_wdt_priv *priv = dev_get_priv(dev);
- /* Disable WDT */
- writel(0, priv->base);
- return 0;
+}
+static int cortina_wdt_reset(struct udevice *dev) +{
- struct ca_wdt_priv *priv = dev_get_priv(dev);
- /* Reload WDT counter */
- writel(WDT_UPD, priv->base + CA_WDT_LOADE);
- return 0;
+}
+static int cortina_wdt_expire_now(struct udevice *dev, ulong flags) +{
- /* Set 1ms timeout to reset system */
- cortina_wdt_set_timeout(dev, 1);
- hang();
- return 0;
+}
+static int cortina_wdt_probe(struct udevice *dev) +{
- struct ca_wdt_priv *priv = dev_get_priv(dev);
- priv->base = dev_remap_addr_index(dev, 0);
- if (!priv->base)
return -ENOENT;- priv->global_config = dev_remap_addr_index(dev, 1);
- if (!priv->global_config)
return -ENOENT;- /* Stop WDT */
- cortina_wdt_stop(dev);
- return 0;
+}
+static const struct wdt_ops cortina_wdt_ops = {
- .start = cortina_wdt_start,
- .reset = cortina_wdt_reset,
- .stop = cortina_wdt_stop,
- .expire_now = cortina_wdt_expire_now,
+};
+static const struct udevice_id cortina_wdt_ids[] = {
- {.compatible = "cortina,cortina-wdt"},
- {}
+};
+U_BOOT_DRIVER(cortina_wdt) = {
- .name = "cortina_wdt",
- .id = UCLASS_WDT,
- .probe = cortina_wdt_probe,
- .of_match = cortina_wdt_ids,
- .ops = &cortina_wdt_ops,
+};
On Mon, 20 Jan 2020 at 02:53, Alex Nemirovsky Alex.Nemirovsky@cortina-access.com wrote:
From: Jason Li jason.li@cortina-access.com
Add support for hardware watchdog timer on all Cortina Access CAxxxx family of SoCs.
Signed-off-by: Jason Li jason.li@cortina-access.com Signed-off-by: Alex Nemirovsky alex.nemirovsky@cortina-access.com
MAINTAINERS | 2 + drivers/watchdog/Kconfig | 8 +++ drivers/watchdog/Makefile | 1 + drivers/watchdog/cortina_wdt.c | 144 +++++++++++++++++++++++++++++++++++++++++ 4 files changed, 155 insertions(+) create mode 100644 drivers/watchdog/cortina_wdt.c
diff --git a/MAINTAINERS b/MAINTAINERS index b7b3359..f9334f9 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -180,6 +180,7 @@ F: board/cortina/common/* F: board/cortina/common/Kconfig F: board/cortina/common/armv8/lowlevel_init.S F: drivers/gpio/cortina_gpio.c +F: drivers/watchdog/cortina_wdt.c
ARM/CZ.NIC TURRIS MOX SUPPORT M: Marek Behun marek.behun@nic.cz @@ -662,6 +663,7 @@ F: board/cortina/common/* F: board/cortina/common/Kconfig F: board/cortina/common/mips/* F: drivers/gpio/cortina_gpio.c +F: drivers/watchdog/cortina_wdt.c
MIPS MSCC M: Gregory CLEMENT gregory.clement@bootlin.com diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 8c16d69..2f7dedb 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -99,6 +99,14 @@ config WDT_CDNS Select this to enable Cadence watchdog timer, which can be found on some Xilinx Microzed Platform.
+config WDT_CORTINA
bool "Cortina Access CAxxxx watchdog timer support"depends on WDThelpCortina Access CAxxxx watchdog timer support.This driver support all CPU ISAs supported by CortinaAccess CAxxxx SoCs.config WDT_MPC8xx bool "MPC8xx watchdog timer support" depends on WDT && MPC8xx diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index 955caef..87f92a4 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -20,6 +20,7 @@ obj-$(CONFIG_WDT_SANDBOX) += sandbox_wdt.o obj-$(CONFIG_WDT_ARMADA_37XX) += armada-37xx-wdt.o obj-$(CONFIG_WDT_ASPEED) += ast_wdt.o obj-$(CONFIG_WDT_BCM6345) += bcm6345_wdt.o +obj-$(CONFIG_WDT_CORTINA) += cortina_wdt.o obj-$(CONFIG_WDT_ORION) += orion_wdt.o obj-$(CONFIG_WDT_CDNS) += cdns_wdt.o obj-$(CONFIG_WDT_MPC8xx) += mpc8xx_wdt.o diff --git a/drivers/watchdog/cortina_wdt.c b/drivers/watchdog/cortina_wdt.c new file mode 100644 index 0000000..61df802 --- /dev/null +++ b/drivers/watchdog/cortina_wdt.c @@ -0,0 +1,144 @@ +// SPDX-License-Identifier: GPL-2.0+
+/*
- Copyright (C) 2020 Cortina-Access
- Author: Jason Li jason.li@cortina-access.com
- */
+#include <common.h> +#include <dm.h> +#include <asm/io.h> +#include <wdt.h>
+#define CA_WDT_CTRL 0x00
Use stryct?
+#define CA_WDT_PS 0x04 +#define CA_WDT_DIV 0x08 +#define CA_WDT_LD 0x0C +#define CA_WDT_LOADE 0x10 +#define CA_WDT_CNT 0x14 +#define CA_WDT_IE 0x18 +#define CA_WDT_INT 0x1C +#define CA_WDT_STAT 0x20
+/* CA_WDT_CTRL */ +#define CTL_WDT_EN BIT(0) +#define CTL_WDT_RSTEN BIT(1) +#define CTL_WDT_CLK_SEL BIT(2) +/* CA_WDT_LOADE */ +#define WDT_UPD BIT(0) +#define WDT_UPD_PS BIT(1)
+/* Global config */ +#define WDT_RESET_SUB BIT(4) +#define WDT_RESET_ALL_BLOCK BIT(6) +#define WDT_RESET_REMAP BIT(7) +#define WDT_EXT_RESET BIT(8) +#define WDT_RESET_DEFAULT (WDT_EXT_RESET | WDT_RESET_REMAP |
WDT_RESET_ALL_BLOCK | WDT_RESET_SUB)
struct comment
+struct ca_wdt_priv {
void __iomem *base;void __iomem *global_config;+};
+static void cortina_wdt_set_timeout(struct udevice *dev, u64 timeout_ms) +{
struct ca_wdt_priv *priv = dev_get_priv(dev);/* Prescale using millisecond unit */writel(CORTINA_PER_IO_FREQ / 1000, priv->base + CA_WDT_PS);/* Millisecond */writel(1, priv->base + CA_WDT_DIV);writel(timeout_ms, priv->base + CA_WDT_LD);writel(WDT_UPD | WDT_UPD_PS, priv->base + CA_WDT_LOADE);+}
+static int cortina_wdt_start(struct udevice *dev, u64 timeout, ulong flags) +{
struct ca_wdt_priv *priv = dev_get_priv(dev);unsigned int reg_v;cortina_wdt_set_timeout(dev, timeout);/* WDT Reset option */reg_v = readl(priv->global_config);reg_v |= WDT_RESET_DEFAULT;writel(reg_v, priv->global_config);
setbits_le32(), and below
/* Enable WDT */reg_v = readl(priv->base);reg_v |= (CTL_WDT_EN | CTL_WDT_RSTEN | CTL_WDT_CLK_SEL);writel(reg_v, priv->base);return 0;+}
+static int cortina_wdt_stop(struct udevice *dev) +{
struct ca_wdt_priv *priv = dev_get_priv(dev);/* Disable WDT */writel(0, priv->base);return 0;+}
+static int cortina_wdt_reset(struct udevice *dev) +{
struct ca_wdt_priv *priv = dev_get_priv(dev);/* Reload WDT counter */writel(WDT_UPD, priv->base + CA_WDT_LOADE);return 0;+}
+static int cortina_wdt_expire_now(struct udevice *dev, ulong flags) +{
/* Set 1ms timeout to reset system */cortina_wdt_set_timeout(dev, 1);hang();
This hang() should be moved to the calling function, wdt_expire_now() and drivers adjusted accordingly. This is a bit like the sysreset case. This function should return -EINPROGRESS.
return 0;+}
+static int cortina_wdt_probe(struct udevice *dev) +{
struct ca_wdt_priv *priv = dev_get_priv(dev);priv->base = dev_remap_addr_index(dev, 0);if (!priv->base)return -ENOENT;
-EINVAL
priv->global_config = dev_remap_addr_index(dev, 1);if (!priv->global_config)return -ENOENT;
Same
BTW both of these should be in an ofdata_to_platadata() method.
/* Stop WDT */cortina_wdt_stop(dev);
Only this should be in the prove() method.
return 0;+}
+static const struct wdt_ops cortina_wdt_ops = {
.start = cortina_wdt_start,.reset = cortina_wdt_reset,.stop = cortina_wdt_stop,.expire_now = cortina_wdt_expire_now,+};
+static const struct udevice_id cortina_wdt_ids[] = {
{.compatible = "cortina,cortina-wdt"},{}+};
+U_BOOT_DRIVER(cortina_wdt) = {
.name = "cortina_wdt",.id = UCLASS_WDT,.probe = cortina_wdt_probe,.of_match = cortina_wdt_ids,.ops = &cortina_wdt_ops,+};
2.7.4
Regards, Simon
From: Jason Li jason.li@cortina-access.com
Add serial UART driver support for all Cortina Access CAxxxx family of SoCs.
Signed-off-by: Jason Li jason.li@cortina-access.com Signed-off-by: Alex Nemirovsky alex.nemirovsky@cortina-access.com ---
MAINTAINERS | 4 ++ drivers/serial/Kconfig | 7 +++ drivers/serial/Makefile | 2 +- drivers/serial/serial_cortina.c | 129 ++++++++++++++++++++++++++++++++++++++++ drivers/serial/serial_cortina.h | 83 ++++++++++++++++++++++++++ 5 files changed, 224 insertions(+), 1 deletion(-) create mode 100644 drivers/serial/serial_cortina.c create mode 100644 drivers/serial/serial_cortina.h
diff --git a/MAINTAINERS b/MAINTAINERS index f9334f9..2b3282b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -181,6 +181,8 @@ F: board/cortina/common/Kconfig F: board/cortina/common/armv8/lowlevel_init.S F: drivers/gpio/cortina_gpio.c F: drivers/watchdog/cortina_wdt.c +F: drivers/serial/serial_cortina.c +F: drivers/serial/serial_cortina.h
ARM/CZ.NIC TURRIS MOX SUPPORT M: Marek Behun marek.behun@nic.cz @@ -664,6 +666,8 @@ F: board/cortina/common/Kconfig F: board/cortina/common/mips/* F: drivers/gpio/cortina_gpio.c F: drivers/watchdog/cortina_wdt.c +F: drivers/serial/serial_cortina.c +F: drivers/serial/serial_cortina.h
MIPS MSCC M: Gregory CLEMENT gregory.clement@bootlin.com diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index ece7d87..9f76596 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -539,6 +539,13 @@ config BCM6345_SERIAL help Select this to enable UART on BCM6345 SoCs.
+config CORTINA_UART + bool "Cortina UART support" + depends on DM_SERIAL + help + Select this to enable UART support for Cortina-Access UART devices + found on CAxxxx SoCs. + config FSL_LINFLEXUART bool "Freescale Linflex UART support" depends on DM_SERIAL diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 06ee306..c8f2db4 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -28,13 +28,13 @@ obj-$(CONFIG_PL010_SERIAL) += serial_pl01x.o obj-$(CONFIG_PL011_SERIAL) += serial_pl01x.o obj-$(CONFIG_SYS_NS16550_SERIAL) += serial_ns16550.o endif - obj-$(CONFIG_ALTERA_UART) += altera_uart.o obj-$(CONFIG_ALTERA_JTAG_UART) += altera_jtag_uart.o obj-$(CONFIG_AR933X_UART) += serial_ar933x.o obj-$(CONFIG_ARM_DCC) += arm_dcc.o obj-$(CONFIG_ATMEL_USART) += atmel_usart.o obj-$(CONFIG_BCM6345_SERIAL) += serial_bcm6345.o +obj-$(CONFIG_CORTINA_UART) += serial_cortina.o obj-$(CONFIG_EFI_APP) += serial_efi.o obj-$(CONFIG_LPC32XX_HSUART) += lpc32xx_hsuart.o obj-$(CONFIG_MCFUART) += mcfuart.o diff --git a/drivers/serial/serial_cortina.c b/drivers/serial/serial_cortina.c new file mode 100644 index 0000000..2b52e5d --- /dev/null +++ b/drivers/serial/serial_cortina.c @@ -0,0 +1,129 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * (C) Copyright 2020 + * Cortina-Access Ltd. + * Author: Jason Li jason.li@cortina-access.com + * + */ + +/* Common UART Driver for Cortina Access CAxxxx line of SoCs */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <watchdog.h> +#include <asm/io.h> +#include <serial.h> +#include <linux/compiler.h> +#include "serial_cortina.h" + +#define IO_WRITE(addr, val) (*(unsigned int *)(addr) = (val)) +#define IO_READ(addr) (*(unsigned int *)(addr)) + +#ifdef CONFIG_DM_SERIAL + +struct ca_uart_priv { + void __iomem *base; +}; + +int ca_serial_setbrg(struct udevice *dev, int baudrate) +{ + struct ca_uart_priv *priv = dev_get_priv(dev); + unsigned int uart_ctrl, baud, sample; + + baud = CORTINA_UART_CLOCK / baudrate; + + uart_ctrl = readl(priv->base + UCFG); + uart_ctrl |= (baud << 8); + writel(uart_ctrl, priv->base + UCFG); + + sample = baud / 2; + sample = (sample < 7) ? 7 : sample; + writel(sample, priv->base + URX_SAMPLE); + + return 0; +} + +static int ca_serial_getc(struct udevice *dev) +{ + struct ca_uart_priv *priv = dev_get_priv(dev); + int ch; + + ch = readl(priv->base + URX_DATA) & 0xFF; + + return (int)ch; +} + +static int ca_serial_putc(struct udevice *dev, const char ch) +{ + struct ca_uart_priv *priv = dev_get_priv(dev); + unsigned int status; + + /* Retry if TX FIFO full */ + status = readl(priv->base + UINFO); + while (status & UINFO_TX_FIFO_FULL) + status = readl(priv->base + UINFO); + + writel(ch, priv->base + UTX_DATA); + + return 0; +} + +static int ca_serial_pending(struct udevice *dev, bool input) +{ + struct ca_uart_priv *priv = dev_get_priv(dev); + unsigned int status; + + status = readl(priv->base + UINFO); + + if (status & UINFO_RX_FIFO_EMPTY) /* empty */ + return 0; + else /* something in RX FIFO */ + return 1; +} + +static int ca_serial_probe(struct udevice *dev) +{ + struct ca_uart_priv *priv = dev_get_priv(dev); + u32 uart_ctrl; + + /* Set data, parity and stop bits */ + uart_ctrl = UCFG_EN | UCFG_TX_EN | UCFG_RX_EN | UCFG_CHAR_8; + writel(uart_ctrl, priv->base + UCFG); + + return 0; +} + +static int ca_serial_ofdata_to_platdata(struct udevice *dev) +{ + struct ca_uart_priv *priv = dev_get_priv(dev); + fdt_addr_t addr; + + addr = dev_read_addr(dev); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + priv->base = map_physmem(addr, 0, MAP_NOCACHE); + + return 0; +} + +static const struct dm_serial_ops ca_serial_ops = { + .putc = ca_serial_putc, + .pending = ca_serial_pending, + .getc = ca_serial_getc, + .setbrg = ca_serial_setbrg, +}; + +static const struct udevice_id ca_serial_ids[] = { + {.compatible = "cortina,ca-uart"}, + {} +}; + +U_BOOT_DRIVER(serial_cortina) = { +.name = "serial_cortina", .id = UCLASS_SERIAL, .of_match = + ca_serial_ids, .ofdata_to_platdata = + ca_serial_ofdata_to_platdata, .priv_auto_alloc_size = + sizeof(struct ca_uart_priv), .probe = ca_serial_probe, .ops = + &ca_serial_ops,}; +#endif /* CONFIG_DM_SERIAL */ diff --git a/drivers/serial/serial_cortina.h b/drivers/serial/serial_cortina.h new file mode 100644 index 0000000..19448f2 --- /dev/null +++ b/drivers/serial/serial_cortina.h @@ -0,0 +1,83 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * u-boot/drivers/serial/serial_cortina.h + * + * Copyright (c) Cortina-Systems Limited 2020. All rights reserved. + * Jason Li jason.li@cortina-systems.com + * + */ + +#ifndef _SERIAL_CORTINA_H_ +#define _SERIAL_CORTINA_H_ + +/* + * UART Module for Cortina Access CAxxxx line of SoCs + */ +#define UART0_BASE_ADDR CONFIG_SYS_SERIAL0 +#define UART1_BASE_ADDR CONFIG_SYS_SERIAL1 + +#define CONFIG_CONS_INDEX 0 + +/* Register definitions */ +#define UCFG 0x00 /* UART config register */ +#define UFC 0x04 /* Flow Control */ +#define URX_SAMPLE 0x08 /* UART RX Sample register */ +#define URT_TUNE 0x0C /* Fine tune of UART clk */ +#define UTX_DATA 0x10 /* UART TX Character data */ +#define URX_DATA 0x14 /* UART RX Character data */ +#define UINFO 0x18 /* UART Info */ +#define UINT_EN0 0x1C /* UART Interrupt enable 0*/ +#define UINT_EN1 0x20 /* UART Interrupt enable 1*/ +#define UINT0 0x24 /* UART Interrupt 0 setting/clearing */ +#define UINT1 0x28 /* UART Interrupt 1 setting/clearing */ +#define UINT_STAT 0x2C /* UART Interrupt Status */ + +/* UART Control Register Bit Fields */ +#define UCFG_BAUD_COUNT BIT(8) +#define UCFG_EN BIT(7) +#define UCFG_RX_EN BIT(6) +#define UCFG_TX_EN BIT(5) +#define UCFG_PARITY_EN BIT(4) +#define UCFG_PARITY_SEL BIT(3) +#define UCFG_2STOP_BIT BIT(2) +#define UCFG_CNT1 BIT(1) +#define UCFG_CNT0 BIT(0) +#define UCFG_CHAR_5 0 +#define UCFG_CHAR_6 1 +#define UCFG_CHAR_7 2 +#define UCFG_CHAR_8 3 + +#define UINFO_TX_FIFO_EMPTY BIT(3) +#define UINFO_TX_FIFO_FULL BIT(2) +#define UINFO_RX_FIFO_EMPTY BIT(1) +#define UINFO_RX_FIFO_FULL BIT(0) + +#define UINT_RX_NON_EMPTY BIT(6) +#define UINT_TX_EMPTY BIT(5) +#define UINT_RX_UNDERRUN BIT(4) +#define UINT_RX_OVERRUN BIT(3) +#define UINT_RX_PARITY_ERR BIT(2) +#define UINT_RX_STOP_ERR BIT(1) +#define UINT_TX_OVERRUN BIT(0) +#define UINT_MASK_ALL 0x7F + +/* UART CONF bits */ +#define SHF_UCONF_WL 0 +#define MSK_UCONF_WL (0x3 << SHF_UCONF_WL) +#define VAL_UCONF_WL_5 (0x0 << SHF_UCONF_WL) +#define VAL_UCONF_WL_6 (0x1 << SHF_UCONF_WL) +#define VAL_UCONF_WL_7 (0x2 << SHF_UCONF_WL) +#define VAL_UCONF_WL_8 (0x3 << SHF_UCONF_WL) + +#define SHF_UCONF_SB 2 +#define MSK_UCONF_SB (0x1 << SHF_UCONF_SB) +#define VAL_UCONF_SB_1 (0x0 << SHF_UCONF_SB) +#define VAL_UCONF_SB_2 (0x1 << SHF_UCONF_SB) + +#define SHF_UCONF_PM 3 +#define MSK_UCONF_PM (0x3 << SHF_UCONF_PM) +#define VAL_UCONF_PM_N (0x0 << SHF_UCONF_PM) +#define VAL_UCONF_PM_O (0x2 << SHF_UCONF_PM) +#define VAL_UCONF_PM_E (0x3 << SHF_UCONF_PM) + +#endif /* _SERIAL_CORTINA_H_ */
Am 20.01.20 um 10:53 schrieb Alex Nemirovsky:
From: Jason Li jason.li@cortina-access.com
Add serial UART driver support for all Cortina Access CAxxxx family of SoCs.
Signed-off-by: Jason Li jason.li@cortina-access.com Signed-off-by: Alex Nemirovsky alex.nemirovsky@cortina-access.com
MAINTAINERS | 4 ++ drivers/serial/Kconfig | 7 +++ drivers/serial/Makefile | 2 +- drivers/serial/serial_cortina.c | 129 ++++++++++++++++++++++++++++++++++++++++ drivers/serial/serial_cortina.h | 83 ++++++++++++++++++++++++++ 5 files changed, 224 insertions(+), 1 deletion(-) create mode 100644 drivers/serial/serial_cortina.c create mode 100644 drivers/serial/serial_cortina.h
diff --git a/MAINTAINERS b/MAINTAINERS index f9334f9..2b3282b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -181,6 +181,8 @@ F: board/cortina/common/Kconfig F: board/cortina/common/armv8/lowlevel_init.S F: drivers/gpio/cortina_gpio.c F: drivers/watchdog/cortina_wdt.c +F: drivers/serial/serial_cortina.c +F: drivers/serial/serial_cortina.h
ARM/CZ.NIC TURRIS MOX SUPPORT M: Marek Behun marek.behun@nic.cz @@ -664,6 +666,8 @@ F: board/cortina/common/Kconfig F: board/cortina/common/mips/* F: drivers/gpio/cortina_gpio.c F: drivers/watchdog/cortina_wdt.c +F: drivers/serial/serial_cortina.c +F: drivers/serial/serial_cortina.h
MIPS MSCC M: Gregory CLEMENT gregory.clement@bootlin.com diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index ece7d87..9f76596 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -539,6 +539,13 @@ config BCM6345_SERIAL help Select this to enable UART on BCM6345 SoCs.
+config CORTINA_UART
- bool "Cortina UART support"
- depends on DM_SERIAL
- help
Select this to enable UART support for Cortina-Access UART devicesfound on CAxxxx SoCs.config FSL_LINFLEXUART bool "Freescale Linflex UART support" depends on DM_SERIAL diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 06ee306..c8f2db4 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -28,13 +28,13 @@ obj-$(CONFIG_PL010_SERIAL) += serial_pl01x.o obj-$(CONFIG_PL011_SERIAL) += serial_pl01x.o obj-$(CONFIG_SYS_NS16550_SERIAL) += serial_ns16550.o endif
obj-$(CONFIG_ALTERA_UART) += altera_uart.o obj-$(CONFIG_ALTERA_JTAG_UART) += altera_jtag_uart.o obj-$(CONFIG_AR933X_UART) += serial_ar933x.o obj-$(CONFIG_ARM_DCC) += arm_dcc.o obj-$(CONFIG_ATMEL_USART) += atmel_usart.o obj-$(CONFIG_BCM6345_SERIAL) += serial_bcm6345.o +obj-$(CONFIG_CORTINA_UART) += serial_cortina.o obj-$(CONFIG_EFI_APP) += serial_efi.o obj-$(CONFIG_LPC32XX_HSUART) += lpc32xx_hsuart.o obj-$(CONFIG_MCFUART) += mcfuart.o diff --git a/drivers/serial/serial_cortina.c b/drivers/serial/serial_cortina.c new file mode 100644 index 0000000..2b52e5d --- /dev/null +++ b/drivers/serial/serial_cortina.c @@ -0,0 +1,129 @@ +// SPDX-License-Identifier: GPL-2.0+
+/*
- (C) Copyright 2020
- Cortina-Access Ltd.
- Author: Jason Li jason.li@cortina-access.com
- */
+/* Common UART Driver for Cortina Access CAxxxx line of SoCs */
same comment as in patch 2/4. There shouldn't be a separate comment block for the description.
+#include <common.h> +#include <dm.h> +#include <errno.h> +#include <watchdog.h> +#include <asm/io.h> +#include <serial.h> +#include <linux/compiler.h> +#include "serial_cortina.h"
+#define IO_WRITE(addr, val) (*(unsigned int *)(addr) = (val)) +#define IO_READ(addr) (*(unsigned int *)(addr))
dead code, you should use the standard I/O accessors anyway
+#ifdef CONFIG_DM_SERIAL
this ifdef is superfluous because without DM_SERIAL the whole file won't be built at all
+struct ca_uart_priv {
- void __iomem *base;
+};
+int ca_serial_setbrg(struct udevice *dev, int baudrate) +{
- struct ca_uart_priv *priv = dev_get_priv(dev);
- unsigned int uart_ctrl, baud, sample;
- baud = CORTINA_UART_CLOCK / baudrate;
- uart_ctrl = readl(priv->base + UCFG);
- uart_ctrl |= (baud << 8);
- writel(uart_ctrl, priv->base + UCFG);
setbits_32() ?
- sample = baud / 2;
- sample = (sample < 7) ? 7 : sample;
- writel(sample, priv->base + URX_SAMPLE);
- return 0;
+}
+static int ca_serial_getc(struct udevice *dev) +{
- struct ca_uart_priv *priv = dev_get_priv(dev);
- int ch;
- ch = readl(priv->base + URX_DATA) & 0xFF;
- return (int)ch;
+}
+static int ca_serial_putc(struct udevice *dev, const char ch) +{
- struct ca_uart_priv *priv = dev_get_priv(dev);
- unsigned int status;
- /* Retry if TX FIFO full */
- status = readl(priv->base + UINFO);
- while (status & UINFO_TX_FIFO_FULL)
status = readl(priv->base + UINFO);
this function must not block because retry handling is done by the serial core. If the TX FIFO is full, simply return -EAGAIN.
- writel(ch, priv->base + UTX_DATA);
- return 0;
+}
+static int ca_serial_pending(struct udevice *dev, bool input) +{
- struct ca_uart_priv *priv = dev_get_priv(dev);
- unsigned int status;
- status = readl(priv->base + UINFO);
- if (status & UINFO_RX_FIFO_EMPTY) /* empty */
return 0;- else /* something in RX FIFO */
return 1;
this function has to check TX and RX FIFO dependent on parameter "input"
+}
+static int ca_serial_probe(struct udevice *dev) +{
- struct ca_uart_priv *priv = dev_get_priv(dev);
- u32 uart_ctrl;
- /* Set data, parity and stop bits */
- uart_ctrl = UCFG_EN | UCFG_TX_EN | UCFG_RX_EN | UCFG_CHAR_8;
- writel(uart_ctrl, priv->base + UCFG);
- return 0;
+}
+static int ca_serial_ofdata_to_platdata(struct udevice *dev) +{
- struct ca_uart_priv *priv = dev_get_priv(dev);
- fdt_addr_t addr;
- addr = dev_read_addr(dev);
- if (addr == FDT_ADDR_T_NONE)
return -EINVAL;- priv->base = map_physmem(addr, 0, MAP_NOCACHE);
dev_remap_addr_index() ?
- return 0;
+}
+static const struct dm_serial_ops ca_serial_ops = {
- .putc = ca_serial_putc,
- .pending = ca_serial_pending,
- .getc = ca_serial_getc,
- .setbrg = ca_serial_setbrg,
+};
+static const struct udevice_id ca_serial_ids[] = {
- {.compatible = "cortina,ca-uart"},
- {}
+};
+U_BOOT_DRIVER(serial_cortina) = { +.name = "serial_cortina", .id = UCLASS_SERIAL, .of_match =
ca_serial_ids, .ofdata_to_platdata =ca_serial_ofdata_to_platdata, .priv_auto_alloc_size =sizeof(struct ca_uart_priv), .probe = ca_serial_probe, .ops =&ca_serial_ops,};
there should be one assignment per line
+#endif /* CONFIG_DM_SERIAL */ diff --git a/drivers/serial/serial_cortina.h b/drivers/serial/serial_cortina.h new file mode 100644 index 0000000..19448f2 --- /dev/null +++ b/drivers/serial/serial_cortina.h @@ -0,0 +1,83 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/*
- u-boot/drivers/serial/serial_cortina.h
- Copyright (c) Cortina-Systems Limited 2020. All rights reserved.
Jason Li <jason.li@cortina-systems.com>
- */
+#ifndef _SERIAL_CORTINA_H_ +#define _SERIAL_CORTINA_H_
+/*
- UART Module for Cortina Access CAxxxx line of SoCs
- */
+#define UART0_BASE_ADDR CONFIG_SYS_SERIAL0 +#define UART1_BASE_ADDR CONFIG_SYS_SERIAL1
+#define CONFIG_CONS_INDEX 0
+/* Register definitions */ +#define UCFG 0x00 /* UART config register */ +#define UFC 0x04 /* Flow Control */ +#define URX_SAMPLE 0x08 /* UART RX Sample register */ +#define URT_TUNE 0x0C /* Fine tune of UART clk */ +#define UTX_DATA 0x10 /* UART TX Character data */ +#define URX_DATA 0x14 /* UART RX Character data */ +#define UINFO 0x18 /* UART Info */ +#define UINT_EN0 0x1C /* UART Interrupt enable 0*/ +#define UINT_EN1 0x20 /* UART Interrupt enable 1*/ +#define UINT0 0x24 /* UART Interrupt 0 setting/clearing */ +#define UINT1 0x28 /* UART Interrupt 1 setting/clearing */ +#define UINT_STAT 0x2C /* UART Interrupt Status */
+/* UART Control Register Bit Fields */ +#define UCFG_BAUD_COUNT BIT(8) +#define UCFG_EN BIT(7) +#define UCFG_RX_EN BIT(6) +#define UCFG_TX_EN BIT(5) +#define UCFG_PARITY_EN BIT(4) +#define UCFG_PARITY_SEL BIT(3) +#define UCFG_2STOP_BIT BIT(2) +#define UCFG_CNT1 BIT(1) +#define UCFG_CNT0 BIT(0) +#define UCFG_CHAR_5 0 +#define UCFG_CHAR_6 1 +#define UCFG_CHAR_7 2 +#define UCFG_CHAR_8 3
+#define UINFO_TX_FIFO_EMPTY BIT(3) +#define UINFO_TX_FIFO_FULL BIT(2) +#define UINFO_RX_FIFO_EMPTY BIT(1) +#define UINFO_RX_FIFO_FULL BIT(0)
+#define UINT_RX_NON_EMPTY BIT(6) +#define UINT_TX_EMPTY BIT(5) +#define UINT_RX_UNDERRUN BIT(4) +#define UINT_RX_OVERRUN BIT(3) +#define UINT_RX_PARITY_ERR BIT(2) +#define UINT_RX_STOP_ERR BIT(1) +#define UINT_TX_OVERRUN BIT(0) +#define UINT_MASK_ALL 0x7F
+/* UART CONF bits */ +#define SHF_UCONF_WL 0 +#define MSK_UCONF_WL (0x3 << SHF_UCONF_WL) +#define VAL_UCONF_WL_5 (0x0 << SHF_UCONF_WL) +#define VAL_UCONF_WL_6 (0x1 << SHF_UCONF_WL) +#define VAL_UCONF_WL_7 (0x2 << SHF_UCONF_WL) +#define VAL_UCONF_WL_8 (0x3 << SHF_UCONF_WL)
+#define SHF_UCONF_SB 2 +#define MSK_UCONF_SB (0x1 << SHF_UCONF_SB) +#define VAL_UCONF_SB_1 (0x0 << SHF_UCONF_SB) +#define VAL_UCONF_SB_2 (0x1 << SHF_UCONF_SB)
+#define SHF_UCONF_PM 3 +#define MSK_UCONF_PM (0x3 << SHF_UCONF_PM) +#define VAL_UCONF_PM_N (0x0 << SHF_UCONF_PM) +#define VAL_UCONF_PM_O (0x2 << SHF_UCONF_PM) +#define VAL_UCONF_PM_E (0x3 << SHF_UCONF_PM)
this file should be dropped. You only need add the required register definitions to serial_cortina.c
+#endif /* _SERIAL_CORTINA_H_ */
Hi Alex,
On Mon, 20 Jan 2020 at 02:53, Alex Nemirovsky Alex.Nemirovsky@cortina-access.com wrote:
From: Jason Li jason.li@cortina-access.com
Add serial UART driver support for all Cortina Access CAxxxx family of SoCs.
Signed-off-by: Jason Li jason.li@cortina-access.com Signed-off-by: Alex Nemirovsky alex.nemirovsky@cortina-access.com
MAINTAINERS | 4 ++ drivers/serial/Kconfig | 7 +++ drivers/serial/Makefile | 2 +- drivers/serial/serial_cortina.c | 129 ++++++++++++++++++++++++++++++++++++++++ drivers/serial/serial_cortina.h | 83 ++++++++++++++++++++++++++ 5 files changed, 224 insertions(+), 1 deletion(-) create mode 100644 drivers/serial/serial_cortina.c create mode 100644 drivers/serial/serial_cortina.h
diff --git a/MAINTAINERS b/MAINTAINERS index f9334f9..2b3282b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -181,6 +181,8 @@ F: board/cortina/common/Kconfig F: board/cortina/common/armv8/lowlevel_init.S F: drivers/gpio/cortina_gpio.c F: drivers/watchdog/cortina_wdt.c +F: drivers/serial/serial_cortina.c +F: drivers/serial/serial_cortina.h
ARM/CZ.NIC TURRIS MOX SUPPORT M: Marek Behun marek.behun@nic.cz @@ -664,6 +666,8 @@ F: board/cortina/common/Kconfig F: board/cortina/common/mips/* F: drivers/gpio/cortina_gpio.c F: drivers/watchdog/cortina_wdt.c +F: drivers/serial/serial_cortina.c +F: drivers/serial/serial_cortina.h
MIPS MSCC M: Gregory CLEMENT gregory.clement@bootlin.com diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index ece7d87..9f76596 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -539,6 +539,13 @@ config BCM6345_SERIAL help Select this to enable UART on BCM6345 SoCs.
+config CORTINA_UART
bool "Cortina UART support"depends on DM_SERIALhelpSelect this to enable UART support for Cortina-Access UART devicesfound on CAxxxx SoCs.
Could you add a few more details about what the driver supports - baud rates? serial formats?
config FSL_LINFLEXUART bool "Freescale Linflex UART support" depends on DM_SERIAL diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 06ee306..c8f2db4 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -28,13 +28,13 @@ obj-$(CONFIG_PL010_SERIAL) += serial_pl01x.o obj-$(CONFIG_PL011_SERIAL) += serial_pl01x.o obj-$(CONFIG_SYS_NS16550_SERIAL) += serial_ns16550.o endif
obj-$(CONFIG_ALTERA_UART) += altera_uart.o obj-$(CONFIG_ALTERA_JTAG_UART) += altera_jtag_uart.o obj-$(CONFIG_AR933X_UART) += serial_ar933x.o obj-$(CONFIG_ARM_DCC) += arm_dcc.o obj-$(CONFIG_ATMEL_USART) += atmel_usart.o obj-$(CONFIG_BCM6345_SERIAL) += serial_bcm6345.o +obj-$(CONFIG_CORTINA_UART) += serial_cortina.o obj-$(CONFIG_EFI_APP) += serial_efi.o obj-$(CONFIG_LPC32XX_HSUART) += lpc32xx_hsuart.o obj-$(CONFIG_MCFUART) += mcfuart.o diff --git a/drivers/serial/serial_cortina.c b/drivers/serial/serial_cortina.c new file mode 100644 index 0000000..2b52e5d --- /dev/null +++ b/drivers/serial/serial_cortina.c @@ -0,0 +1,129 @@ +// SPDX-License-Identifier: GPL-2.0+
Drop that line
+/*
- (C) Copyright 2020
- Cortina-Access Ltd.
- Author: Jason Li jason.li@cortina-access.com
- */
+/* Common UART Driver for Cortina Access CAxxxx line of SoCs */
+#include <common.h> +#include <dm.h> +#include <errno.h> +#include <watchdog.h> +#include <asm/io.h> +#include <serial.h>
Move up above watchdog.h
+#include <linux/compiler.h> +#include "serial_cortina.h"
+#define IO_WRITE(addr, val) (*(unsigned int *)(addr) = (val)) +#define IO_READ(addr) (*(unsigned int *)(addr))
+#ifdef CONFIG_DM_SERIAL
Drop that
+struct ca_uart_priv {
void __iomem *base;+};
+int ca_serial_setbrg(struct udevice *dev, int baudrate) +{
struct ca_uart_priv *priv = dev_get_priv(dev);unsigned int uart_ctrl, baud, sample;baud = CORTINA_UART_CLOCK / baudrate;
Don't you have a clock driver?
uart_ctrl = readl(priv->base + UCFG);uart_ctrl |= (baud << 8);writel(uart_ctrl, priv->base + UCFG);
setbits_le32
sample = baud / 2;sample = (sample < 7) ? 7 : sample;
min(sample, 7)
writel(sample, priv->base + URX_SAMPLE);return 0;+}
+static int ca_serial_getc(struct udevice *dev) +{
struct ca_uart_priv *priv = dev_get_priv(dev);int ch;ch = readl(priv->base + URX_DATA) & 0xFF;return (int)ch;
Drop cast, it is already int
+}
+static int ca_serial_putc(struct udevice *dev, const char ch) +{
struct ca_uart_priv *priv = dev_get_priv(dev);unsigned int status;/* Retry if TX FIFO full */status = readl(priv->base + UINFO);while (status & UINFO_TX_FIFO_FULL)status = readl(priv->base + UINFO);
Drop that loop - the uclass does this for you. Just return -EAGAIN
writel(ch, priv->base + UTX_DATA);return 0;+}
+static int ca_serial_pending(struct udevice *dev, bool input) +{
struct ca_uart_priv *priv = dev_get_priv(dev);unsigned int status;status = readl(priv->base + UINFO);if (status & UINFO_RX_FIFO_EMPTY) /* empty */return 0;else /* something in RX FIFO */return 1;
?? This needs to be limplemented
+}
+static int ca_serial_probe(struct udevice *dev) +{
struct ca_uart_priv *priv = dev_get_priv(dev);u32 uart_ctrl;/* Set data, parity and stop bits */uart_ctrl = UCFG_EN | UCFG_TX_EN | UCFG_RX_EN | UCFG_CHAR_8;writel(uart_ctrl, priv->base + UCFG);return 0;+}
+static int ca_serial_ofdata_to_platdata(struct udevice *dev) +{
struct ca_uart_priv *priv = dev_get_priv(dev);fdt_addr_t addr;addr = dev_read_addr(dev);if (addr == FDT_ADDR_T_NONE)return -EINVAL;priv->base = map_physmem(addr, 0, MAP_NOCACHE);return 0;+}
+static const struct dm_serial_ops ca_serial_ops = {
.putc = ca_serial_putc,.pending = ca_serial_pending,.getc = ca_serial_getc,.setbrg = ca_serial_setbrg,+};
+static const struct udevice_id ca_serial_ids[] = {
{.compatible = "cortina,ca-uart"},{}+};
+U_BOOT_DRIVER(serial_cortina) = { +.name = "serial_cortina", .id = UCLASS_SERIAL, .of_match =
ca_serial_ids, .ofdata_to_platdata =ca_serial_ofdata_to_platdata, .priv_auto_alloc_size =sizeof(struct ca_uart_priv), .probe = ca_serial_probe, .ops =&ca_serial_ops,};+#endif /* CONFIG_DM_SERIAL */ diff --git a/drivers/serial/serial_cortina.h b/drivers/serial/serial_cortina.h new file mode 100644 index 0000000..19448f2 --- /dev/null +++ b/drivers/serial/serial_cortina.h @@ -0,0 +1,83 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/*
- u-boot/drivers/serial/serial_cortina.h
Do we need the filename here?
- Copyright (c) Cortina-Systems Limited 2020. All rights reserved.
Jason Li <jason.li@cortina-systems.com>
- */
+#ifndef _SERIAL_CORTINA_H_ +#define _SERIAL_CORTINA_H_
+/*
- UART Module for Cortina Access CAxxxx line of SoCs
- */
+#define UART0_BASE_ADDR CONFIG_SYS_SERIAL0 +#define UART1_BASE_ADDR CONFIG_SYS_SERIAL1
+#define CONFIG_CONS_INDEX 0
Drop that
+/* Register definitions */ +#define UCFG 0x00 /* UART config register */
Use a struct for registers?
+#define UFC 0x04 /* Flow Control */ +#define URX_SAMPLE 0x08 /* UART RX Sample register */ +#define URT_TUNE 0x0C /* Fine tune of UART clk */ +#define UTX_DATA 0x10 /* UART TX Character data */ +#define URX_DATA 0x14 /* UART RX Character data */ +#define UINFO 0x18 /* UART Info */ +#define UINT_EN0 0x1C /* UART Interrupt enable 0*/ +#define UINT_EN1 0x20 /* UART Interrupt enable 1*/ +#define UINT0 0x24 /* UART Interrupt 0 setting/clearing */ +#define UINT1 0x28 /* UART Interrupt 1 setting/clearing */ +#define UINT_STAT 0x2C /* UART Interrupt Status */
+/* UART Control Register Bit Fields */ +#define UCFG_BAUD_COUNT BIT(8) +#define UCFG_EN BIT(7) +#define UCFG_RX_EN BIT(6) +#define UCFG_TX_EN BIT(5) +#define UCFG_PARITY_EN BIT(4) +#define UCFG_PARITY_SEL BIT(3) +#define UCFG_2STOP_BIT BIT(2) +#define UCFG_CNT1 BIT(1) +#define UCFG_CNT0 BIT(0) +#define UCFG_CHAR_5 0 +#define UCFG_CHAR_6 1 +#define UCFG_CHAR_7 2 +#define UCFG_CHAR_8 3
+#define UINFO_TX_FIFO_EMPTY BIT(3) +#define UINFO_TX_FIFO_FULL BIT(2) +#define UINFO_RX_FIFO_EMPTY BIT(1) +#define UINFO_RX_FIFO_FULL BIT(0)
+#define UINT_RX_NON_EMPTY BIT(6) +#define UINT_TX_EMPTY BIT(5) +#define UINT_RX_UNDERRUN BIT(4) +#define UINT_RX_OVERRUN BIT(3) +#define UINT_RX_PARITY_ERR BIT(2) +#define UINT_RX_STOP_ERR BIT(1) +#define UINT_TX_OVERRUN BIT(0) +#define UINT_MASK_ALL 0x7F
+/* UART CONF bits */ +#define SHF_UCONF_WL 0 +#define MSK_UCONF_WL (0x3 << SHF_UCONF_WL) +#define VAL_UCONF_WL_5 (0x0 << SHF_UCONF_WL) +#define VAL_UCONF_WL_6 (0x1 << SHF_UCONF_WL) +#define VAL_UCONF_WL_7 (0x2 << SHF_UCONF_WL) +#define VAL_UCONF_WL_8 (0x3 << SHF_UCONF_WL)
+#define SHF_UCONF_SB 2 +#define MSK_UCONF_SB (0x1 << SHF_UCONF_SB) +#define VAL_UCONF_SB_1 (0x0 << SHF_UCONF_SB) +#define VAL_UCONF_SB_2 (0x1 << SHF_UCONF_SB)
+#define SHF_UCONF_PM 3 +#define MSK_UCONF_PM (0x3 << SHF_UCONF_PM) +#define VAL_UCONF_PM_N (0x0 << SHF_UCONF_PM) +#define VAL_UCONF_PM_O (0x2 << SHF_UCONF_PM) +#define VAL_UCONF_PM_E (0x3 << SHF_UCONF_PM)
+#endif /* _SERIAL_CORTINA_H_ */
2.7.4
Regards, Simon
On Mon, Jan 20, 2020 at 09:53:31AM +0000, Alex Nemirovsky wrote:
This series contains a set of basic DM drivers compatible with Cortina Access ARM and MIPS series of SoCs.
I'm not sure why my name appeared in the Cc list.
Please, remove it in the next versions if it's not related to me, otherwise, please be explicit why my participation is needed.
Jason Li (4): gpio: do not include <asm/arch/gpio.h> for Cortina CAxxxx SoCs gpio: cortina_gpio: add DM_GPIO driver for CAxxxx SoCs watchdog: cortina_wdt: add support for HW WDT on CAxxxx SoCs serial: serial_cortina: add UART DM driver for CAxxxx SoCs
MAINTAINERS | 8 +++ arch/arm/include/asm/gpio.h | 2 +- drivers/gpio/Kconfig | 8 +++ drivers/gpio/Makefile | 1 + drivers/gpio/cortina_gpio.c | 113 +++++++++++++++++++++++++++++++ drivers/serial/Kconfig | 7 ++ drivers/serial/Makefile | 2 +- drivers/serial/serial_cortina.c | 129 +++++++++++++++++++++++++++++++++++ drivers/serial/serial_cortina.h | 83 +++++++++++++++++++++++ drivers/watchdog/Kconfig | 8 +++ drivers/watchdog/Makefile | 1 + drivers/watchdog/cortina_wdt.c | 144 ++++++++++++++++++++++++++++++++++++++++ 12 files changed, 504 insertions(+), 2 deletions(-) create mode 100644 drivers/gpio/cortina_gpio.c create mode 100644 drivers/serial/serial_cortina.c create mode 100644 drivers/serial/serial_cortina.h create mode 100644 drivers/watchdog/cortina_wdt.c
-- 2.7.4
Hi Andy,
On Mon, Jan 20, 2020 at 1:39 PM Andy Shevchenko andriy.shevchenko@linux.intel.com wrote:
On Mon, Jan 20, 2020 at 09:53:31AM +0000, Alex Nemirovsky wrote:
This series contains a set of basic DM drivers compatible with Cortina Access ARM and MIPS series of SoCs.
I'm not sure why my name appeared in the Cc list.
I assume this is patman/get_maintainers.pl who added your email. That's usually done when MAINTAINERS is changed.
Please, remove it in the next versions if it's not related to me, otherwise, please be explicit why my participation is needed.
Jason Li (4): gpio: do not include <asm/arch/gpio.h> for Cortina CAxxxx SoCs gpio: cortina_gpio: add DM_GPIO driver for CAxxxx SoCs watchdog: cortina_wdt: add support for HW WDT on CAxxxx SoCs serial: serial_cortina: add UART DM driver for CAxxxx SoCs
MAINTAINERS | 8 +++ arch/arm/include/asm/gpio.h | 2 +- drivers/gpio/Kconfig | 8 +++ drivers/gpio/Makefile | 1 + drivers/gpio/cortina_gpio.c | 113 +++++++++++++++++++++++++++++++ drivers/serial/Kconfig | 7 ++ drivers/serial/Makefile | 2 +- drivers/serial/serial_cortina.c | 129 +++++++++++++++++++++++++++++++++++ drivers/serial/serial_cortina.h | 83 +++++++++++++++++++++++ drivers/watchdog/Kconfig | 8 +++ drivers/watchdog/Makefile | 1 + drivers/watchdog/cortina_wdt.c | 144 ++++++++++++++++++++++++++++++++++++++++ 12 files changed, 504 insertions(+), 2 deletions(-) create mode 100644 drivers/gpio/cortina_gpio.c create mode 100644 drivers/serial/serial_cortina.c create mode 100644 drivers/serial/serial_cortina.h create mode 100644 drivers/watchdog/cortina_wdt.c
-- 2.7.4
-- With Best Regards, Andy Shevchenko
On Mon, Jan 20, 2020 at 02:11:20PM +0200, Igor Opaniuk wrote:
On Mon, Jan 20, 2020 at 1:39 PM Andy Shevchenko andriy.shevchenko@linux.intel.com wrote:
On Mon, Jan 20, 2020 at 09:53:31AM +0000, Alex Nemirovsky wrote:
This series contains a set of basic DM drivers compatible with Cortina Access ARM and MIPS series of SoCs.
I'm not sure why my name appeared in the Cc list.
I assume this is patman/get_maintainers.pl who added your email.
Somebody needs to learn how to exclude not relevant people?
That's usually done when MAINTAINERS is changed.
Where? I didn't get this.
Please, remove it in the next versions if it's not related to me, otherwise, please be explicit why my participation is needed.
Jason Li (4): gpio: do not include <asm/arch/gpio.h> for Cortina CAxxxx SoCs gpio: cortina_gpio: add DM_GPIO driver for CAxxxx SoCs watchdog: cortina_wdt: add support for HW WDT on CAxxxx SoCs serial: serial_cortina: add UART DM driver for CAxxxx SoCs
MAINTAINERS | 8 +++ arch/arm/include/asm/gpio.h | 2 +- drivers/gpio/Kconfig | 8 +++ drivers/gpio/Makefile | 1 + drivers/gpio/cortina_gpio.c | 113 +++++++++++++++++++++++++++++++ drivers/serial/Kconfig | 7 ++ drivers/serial/Makefile | 2 +- drivers/serial/serial_cortina.c | 129 +++++++++++++++++++++++++++++++++++ drivers/serial/serial_cortina.h | 83 +++++++++++++++++++++++ drivers/watchdog/Kconfig | 8 +++ drivers/watchdog/Makefile | 1 + drivers/watchdog/cortina_wdt.c | 144 ++++++++++++++++++++++++++++++++++++++++ 12 files changed, 504 insertions(+), 2 deletions(-) create mode 100644 drivers/gpio/cortina_gpio.c create mode 100644 drivers/serial/serial_cortina.c create mode 100644 drivers/serial/serial_cortina.h create mode 100644 drivers/watchdog/cortina_wdt.c
On Mon, Jan 20, 2020 at 4:07 PM Andy Shevchenko andriy.shevchenko@linux.intel.com wrote:
On Mon, Jan 20, 2020 at 02:11:20PM +0200, Igor Opaniuk wrote:
On Mon, Jan 20, 2020 at 1:39 PM Andy Shevchenko andriy.shevchenko@linux.intel.com wrote:
On Mon, Jan 20, 2020 at 09:53:31AM +0000, Alex Nemirovsky wrote:
This series contains a set of basic DM drivers compatible with Cortina Access ARM and MIPS series of SoCs.
I'm not sure why my name appeared in the Cc list.
I assume this is patman/get_maintainers.pl who added your email.
Somebody needs to learn how to exclude not relevant people?
Patman does this automatically.
That's usually done when MAINTAINERS is changed.
Where? I didn't get this.
Look below
Please, remove it in the next versions if it's not related to me, otherwise, please be explicit why my participation is needed.
Jason Li (4): gpio: do not include <asm/arch/gpio.h> for Cortina CAxxxx SoCs gpio: cortina_gpio: add DM_GPIO driver for CAxxxx SoCs watchdog: cortina_wdt: add support for HW WDT on CAxxxx SoCs serial: serial_cortina: add UART DM driver for CAxxxx SoCs
MAINTAINERS | 8 +++
Here?
arch/arm/include/asm/gpio.h | 2 +- drivers/gpio/Kconfig | 8 +++ drivers/gpio/Makefile | 1 + drivers/gpio/cortina_gpio.c | 113 +++++++++++++++++++++++++++++++ drivers/serial/Kconfig | 7 ++ drivers/serial/Makefile | 2 +- drivers/serial/serial_cortina.c | 129 +++++++++++++++++++++++++++++++++++ drivers/serial/serial_cortina.h | 83 +++++++++++++++++++++++ drivers/watchdog/Kconfig | 8 +++ drivers/watchdog/Makefile | 1 + drivers/watchdog/cortina_wdt.c | 144 ++++++++++++++++++++++++++++++++++++++++ 12 files changed, 504 insertions(+), 2 deletions(-) create mode 100644 drivers/gpio/cortina_gpio.c create mode 100644 drivers/serial/serial_cortina.c create mode 100644 drivers/serial/serial_cortina.h create mode 100644 drivers/watchdog/cortina_wdt.c
-- With Best Regards, Andy Shevchenko
On Mon, Jan 20, 2020 at 04:16:53PM +0200, Igor Opaniuk wrote:
On Mon, Jan 20, 2020 at 4:07 PM Andy Shevchenko andriy.shevchenko@linux.intel.com wrote:
On Mon, Jan 20, 2020 at 02:11:20PM +0200, Igor Opaniuk wrote:
On Mon, Jan 20, 2020 at 1:39 PM Andy Shevchenko andriy.shevchenko@linux.intel.com wrote:
On Mon, Jan 20, 2020 at 09:53:31AM +0000, Alex Nemirovsky wrote:
This series contains a set of basic DM drivers compatible with Cortina Access ARM and MIPS series of SoCs.
I'm not sure why my name appeared in the Cc list.
I assume this is patman/get_maintainers.pl who added your email.
Somebody needs to learn how to exclude not relevant people?
Patman does this automatically.
Hmm... Sounds like a bug in the tool.
That's usually done when MAINTAINERS is changed.
Where? I didn't get this.
Look below
MAINTAINERS | 8 +++
Here?
Okay, and I still didn't get why it adds my name to the Cc. Is any of that change related to what I'm keeping an eye on?
P.S. To the core U-Boot maintainers, perhaps somebody, who knows that tooling, may eventually fix it to avoid spamming people on unrelated matters?
Hi Andy,
On Mon, 20 Jan 2020 at 07:53, Andy Shevchenko andriy.shevchenko@linux.intel.com wrote:
On Mon, Jan 20, 2020 at 04:16:53PM +0200, Igor Opaniuk wrote:
On Mon, Jan 20, 2020 at 4:07 PM Andy Shevchenko andriy.shevchenko@linux.intel.com wrote:
On Mon, Jan 20, 2020 at 02:11:20PM +0200, Igor Opaniuk wrote:
On Mon, Jan 20, 2020 at 1:39 PM Andy Shevchenko andriy.shevchenko@linux.intel.com wrote:
On Mon, Jan 20, 2020 at 09:53:31AM +0000, Alex Nemirovsky wrote:
This series contains a set of basic DM drivers compatible with Cortina Access ARM and MIPS series of SoCs.
I'm not sure why my name appeared in the Cc list.
I assume this is patman/get_maintainers.pl who added your email.
Somebody needs to learn how to exclude not relevant people?
Patman does this automatically.
Hmm... Sounds like a bug in the tool.
That's usually done when MAINTAINERS is changed.
Where? I didn't get this.
Look below
MAINTAINERS | 8 +++
Here?
Okay, and I still didn't get why it adds my name to the Cc. Is any of that change related to what I'm keeping an eye on?
P.S. To the core U-Boot maintainers, perhaps somebody, who knows that tooling, may eventually fix it to avoid spamming people on unrelated matters?
You can try something like this.
cat >asc (copy in the diffstat) ctrl-D for f in $(cat asc |cut -d' ' -f1-2 |tr '\n' ' '); do echo $f; ./scripts/get_maintainer.pl -f $f |grep intel; done
In this case:
drivers/watchdog/Kconfig Andy Shevchenko andriy.shevchenko@linux.intel.com (added_lines:8/103=8%,removed_lines:9/77=12%) drivers/watchdog/Makefile Andy Shevchenko andriy.shevchenko@linux.intel.com (commit_signer:1/7=14%,authored:1/7=14%,added_lines:1/6=17%,removed_lines:1/4=25%)
You have 5 commits in that directory.
Regards, Simon
participants (6)
-
Alex Nemirovsky -
Andy Shevchenko -
Daniel Schwierzeck -
Igor Opaniuk -
Simon Glass -
Stefan Roese