[U-Boot] [RFC PATCH] rockchip: asus c201 support
From: "Marty E. Plummer" hanetzer@protonmail.com
I realize this patch is not up to standards for the sake of mainlining right now, but I'm mostly interested in getting some feedback on how to make it work before getting into the nicities of mainline inclusion.
As of right now the bulk of this is the rk3288-veyron-speedy.dts file, which I assume has a similar enough boot system to the jerry and minnie.
If the resultant u-boot-spl.bin and u-boot-dtb.img are prepared according to the instructions in doc/README.rockchip and then flashed to the c201's spi memory I get very little in the way of result; the most I/O that to be seen is the board reacts to the power switch (led on, led off). I can not seem to get it to output the u-boot console to the built-in screen, and currently do not have a mini-hdmi cable to see if that is working or not (one is ordered, arrives thursday). Can't find a location to purchase a servo board for better debugging possibilities.
I was hoping someone on this mailing list could assist me in getting this to work; once a working setup is figured I'll do proper patchset for mainline inclusion.
Regards, Marty --- arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3288-veyron-speedy.dts | 203 ++++++++++++++++++++++++++++++ arch/arm/mach-rockchip/rk3288-board-spl.c | 3 +- arch/arm/mach-rockchip/rk3288/Kconfig | 11 ++ board/google/veyron/Kconfig | 16 +++ configs/chromebook_speedy_defconfig | 92 ++++++++++++++ drivers/mtd/spi/spi_flash_ids.c | 1 + 7 files changed, 326 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/rk3288-veyron-speedy.dts create mode 100644 configs/chromebook_speedy_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 7c062f0cad..c8630889dc 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -41,6 +41,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rk3288-veyron-jerry.dtb \ rk3288-veyron-mickey.dtb \ rk3288-veyron-minnie.dtb \ + rk3288-veyron-speedy.dtb \ rk3288-vyasa.dtb \ rk3328-evb.dtb \ rk3368-lion.dtb \ diff --git a/arch/arm/dts/rk3288-veyron-speedy.dts b/arch/arm/dts/rk3288-veyron-speedy.dts new file mode 100644 index 0000000000..51e155d141 --- /dev/null +++ b/arch/arm/dts/rk3288-veyron-speedy.dts @@ -0,0 +1,203 @@ +/* + * Google Veyron Speedy Rev 1+ board device tree source + * + * Copyright 2015 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0 + */ + +/dts-v1/; +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include "rk3288-veyron-chromebook.dtsi" +#include "cros-ec-sbs.dtsi" + +/ { + model = "Google Jerry"; + compatible = "google,veyron-speedy-rev9", "google,veyron-speedy-rev8", + "google,veyron-speedy-rev7", "google,veyron-speedy-rev6", + "google,veyron-speedy-rev5", "google,veyron-speedy-rev4", + "google,veyron-speedy-rev3", "google,veyron-speedy-rev2", + "google,veyron-speedy", "google,veyron", "rockchip,rk3288"; + + /* chosen { */ + /* stdout-path = &uart1; */ + /* }; */ + + panel_regulator: panel-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio7 RK_PB6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_enable_h>; + regulator-name = "panel_regulator"; + vin-supply = <&vcc33_sys>; + }; + + vcc18_lcd: vcc18-lcd { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&avdd_1v8_disp_en>; + regulator-name = "vcc18_lcd"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc18_wl>; + }; + + backlight_regulator: backlight-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&bl_pwr_en>; + regulator-name = "backlight_regulator"; + vin-supply = <&vcc33_sys>; + startup-delay-us = <15000>; + }; +}; + +&dmc { + rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d + 0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6 + 0x4 0x8 0x4 0x76 0x4 0x0 0x30 0x0 + 0x1 0x2 0x2 0x4 0x0 0x0 0xc0 0x4 + 0x8 0x1f4>; + rockchip,phy-timing = <0x48d7dd93 0x187008d8 0x121076 + 0x0 0xc3 0x6 0x1>; + rockchip,sdram-params = <0x20D266A4 0x5B6 6 533000000 6 13 0>; +}; + +&gpio_keys { + power { + gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; + }; +}; + +&backlight { + power-supply = <&backlight_regulator>; +}; + +&cpu_alert0 { + temperature = <65000>; +}; + +&cpu_alert1 { + temperature = <70000>; +}; + +&panel { + power-supply = <&panel_regulator>; +}; + +&rk808 { + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; +}; + +&sdmmc { + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio + &sdmmc_bus4>; + disable-wp; +}; + +&vcc_5v { + enable-active-high; + /* gpio = <&gpio7 21 GPIO_ACTIVE_HIGH>; */ + pinctrl-names = "default"; + pinctrl-0 = <&drv_5v>; +}; + +&vcc50_hdmi { + enable-active-high; + gpio = <&gpio5 19 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc50_hdmi_en>; +}; + +&edp { + /* pinctrl-names = "default"; */ + /* pinctrl-0 = <&edp_hpd>; */ + /delete-property/pinctrl-names; + /delete-property/pinctrl-0; + + force-hpd; +}; + +&pinctrl { + backlight { + bl_pwr_en: bl_pwr_en { + rockchip,pins = <2 12 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + buck-5v { + drv_5v: drv-5v { + rockchip,pins = <7 21 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + edp { + edp_hpd: edp_hpd { + rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_down>; + }; + }; + + emmc { + /* Make sure eMMC is not in reset */ + emmc_deassert_reset: emmc-deassert-reset { + rockchip,pins = <2 9 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hdmi { + vcc50_hdmi_en: vcc50-hdmi-en { + rockchip,pins = <5 19 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + lcd { + lcd_enable_h: lcd-en { + rockchip,pins = <7 14 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + avdd_1v8_disp_en: avdd-1v8-disp-en { + rockchip,pins = <2 13 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + dvs_1: dvs-1 { + rockchip,pins = <7 12 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + dvs_2: dvs-2 { + rockchip,pins = <7 15 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; +}; + +/* &i2c4 { */ +/* status = "okay"; */ + +/* pinctrl-names = "default"; */ +/* pinctrl-0 = <&i2c4_xfer>; */ + +/* trackpad@15 { */ +/* compatible = "elan,i2c_touchpad"; */ +/* interrupt-parent = <&gpio7>; */ +/* interrupts = <3 IRQ_TYPE_EDGE_FALLING>; */ +/* /* */ +/* * Remove the inherited pinctrl settings to avoid clashing */ +/* * with bus-wide ones. */ +/* *1/ */ +/* /delete-property/pinctrl-names; */ +/* /delete-property/pinctrl-0; */ +/* reg = <0x15>; */ +/* vcc-supply = <&vcc33_io>; */ +/* wakeup-source; */ +/* }; */ +/* }; */ diff --git a/arch/arm/mach-rockchip/rk3288-board-spl.c b/arch/arm/mach-rockchip/rk3288-board-spl.c index 6b7bf85d8d..5b76114d9b 100644 --- a/arch/arm/mach-rockchip/rk3288-board-spl.c +++ b/arch/arm/mach-rockchip/rk3288-board-spl.c @@ -69,7 +69,8 @@ u32 spl_boot_device(void) fallback: #elif defined(CONFIG_TARGET_CHROMEBOOK_JERRY) || \ defined(CONFIG_TARGET_CHROMEBIT_MICKEY) || \ - defined(CONFIG_TARGET_CHROMEBOOK_MINNIE) + defined(CONFIG_TARGET_CHROMEBOOK_MINNIE) || \ + defined(CONFIG_TARGET_CHROMEBOOK_SPEEDY) return BOOT_DEVICE_SPI; #endif return BOOT_DEVICE_MMC1; diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig b/arch/arm/mach-rockchip/rk3288/Kconfig index 4ad2940069..04377f9ea8 100644 --- a/arch/arm/mach-rockchip/rk3288/Kconfig +++ b/arch/arm/mach-rockchip/rk3288/Kconfig @@ -30,6 +30,17 @@ config TARGET_CHROMEBOOK_MINNIE functions. It includes 2 or 4GB of SDRAM and 16 or 32GB of internal MMC. The product name is ASUS Chromebook Flip.
+config TARGET_CHROMEBOOK_SPEEDY + bool "Google/Rockchip Veyron-Speedy Chromebook" + select BOARD_LATE_INIT + help + Speedy is a RK3288-based clamshell device with 2 USB 2.0 ports, + micro HDMI, an 11.6 inch display, micro-SD card, + HD camera, touchpad, wifi and Bluetooth. It includes a Chrome OS + EC (Cortex-M3) to provide access to the keyboard and battery + functions. It includes 2 or 4GB of SDRAM and 16GB of internal MMC. + The product name is Asus Chromebook C201PA. + config TARGET_EVB_RK3288 bool "Evb-RK3288" select BOARD_LATE_INIT diff --git a/board/google/veyron/Kconfig b/board/google/veyron/Kconfig index 770e9aad28..7f55d78dac 100644 --- a/board/google/veyron/Kconfig +++ b/board/google/veyron/Kconfig @@ -45,3 +45,19 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y
endif + +if TARGET_CHROMEBOOK_SPEEDY + +config SYS_BOARD + default "veyron" + +config SYS_VENDOR + default "google" + +config SYS_CONFIG_NAME + default "veyron" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + +endif diff --git a/configs/chromebook_speedy_defconfig b/configs/chromebook_speedy_defconfig new file mode 100644 index 0000000000..9626be9743 --- /dev/null +++ b/configs/chromebook_speedy_defconfig @@ -0,0 +1,92 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_ROCKCHIP_RK3288=y +# CONFIG_SPL_MMC_SUPPORT is not set +CONFIG_TARGET_CHROMEBOOK_SPEEDY=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_STACK_R_ADDR=0x80000 +CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-speedy" +CONFIG_DEBUG_UART=y +# CONFIG_ANDROID_BOOT_IMAGE is not set +CONFIG_SILENT_CONSOLE=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_SF_TEST=y +CONFIG_CMD_SPI=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_SPL_ISO_PARTITION is not set +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_SPL_PARTITION_UUIDS=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SPL_OF_PLATDATA=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +# CONFIG_SPL_SIMPLE_BUS is not set +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_I2C_CROS_EC_TUNNEL=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_I2C_MUX=y +CONFIG_DM_KEYBOARD=y +CONFIG_CROS_EC_KEYB=y +CONFIG_CROS_EC=y +CONFIG_CROS_EC_SPI=y +CONFIG_PWRSEQ=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +# CONFIG_SPL_PINCTRL_FULL is not set +CONFIG_PINCTRL_ROCKCHIP_RK3288=y +CONFIG_DM_PMIC=y +# CONFIG_SPL_PMIC_CHILDREN is not set +CONFIG_PMIC_RK8XX=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_DEBUG_UART_BASE=0xff690000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550=y +CONFIG_ROCKCHIP_SERIAL=y +CONFIG_ROCKCHIP_SPI=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_G_DNL_MANUFACTURER="Rockchip" +CONFIG_G_DNL_VENDOR_NUM=0x2207 +CONFIG_G_DNL_PRODUCT_NUM=0x320a +CONFIG_DM_VIDEO=y +CONFIG_DISPLAY=y +CONFIG_VIDEO_ROCKCHIP=y +CONFIG_DISPLAY_ROCKCHIP_EDP=y +CONFIG_DISPLAY_ROCKCHIP_HDMI=y +CONFIG_USE_TINY_PRINTF=y +CONFIG_CMD_DHRYSTONE=y +CONFIG_ERRNO_STR=y +# CONFIG_SPL_OF_LIBFDT is not set diff --git a/drivers/mtd/spi/spi_flash_ids.c b/drivers/mtd/spi/spi_flash_ids.c index 13f64e773f..cbfd8b7636 100644 --- a/drivers/mtd/spi/spi_flash_ids.c +++ b/drivers/mtd/spi/spi_flash_ids.c @@ -63,6 +63,7 @@ const struct spi_flash_info spi_flash_ids[] = { {"en25s64", INFO(0x1c3817, 0x0, 64 * 1024, 128, 0) }, #endif #ifdef CONFIG_SPI_FLASH_GIGADEVICE /* GIGADEVICE */ + {"gd25q32b", INFO(0xc84016, 0x0, 64 * 1024, 64, SECT_4K) }, {"gd25q64b", INFO(0xc84017, 0x0, 64 * 1024, 128, SECT_4K) }, {"gd25lq32", INFO(0xc86016, 0x0, 64 * 1024, 64, SECT_4K) }, #endif
On Tue, 3 Oct 2017, Marty E. Plummer wrote:
From: "Marty E. Plummer" hanetzer@protonmail.com
I realize this patch is not up to standards for the sake of mainlining right now, but I'm mostly interested in getting some feedback on how to make it work before getting into the nicities of mainline inclusion.
As of right now the bulk of this is the rk3288-veyron-speedy.dts file, which I assume has a similar enough boot system to the jerry and minnie.
If the resultant u-boot-spl.bin and u-boot-dtb.img are prepared according to the instructions in doc/README.rockchip and then flashed to the c201's spi memory I get very little in the way of result; the most I/O that to be seen is the board reacts to the power switch (led on, led off). I can not seem to get it to output the u-boot console to the built-in screen, and currently do not have a mini-hdmi cable to see if that is working or not (one is ordered, arrives thursday). Can't find a location to purchase a servo board for better debugging possibilities.
I was hoping someone on this mailing list could assist me in getting this to work; once a working setup is figured I'll do proper patchset for mainline inclusion.
Regards, Marty
For the real submission you'll need to have a more meaningful commit message: from this description it is hard to understand what exactly has been changed and why.
And, of course, you'll also need a Signed-off-by line.
arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3288-veyron-speedy.dts | 203 ++++++++++++++++++++++++++++++ arch/arm/mach-rockchip/rk3288-board-spl.c | 3 +- arch/arm/mach-rockchip/rk3288/Kconfig | 11 ++ board/google/veyron/Kconfig | 16 +++ configs/chromebook_speedy_defconfig | 92 ++++++++++++++ drivers/mtd/spi/spi_flash_ids.c | 1 + 7 files changed, 326 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/rk3288-veyron-speedy.dts create mode 100644 configs/chromebook_speedy_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 7c062f0cad..c8630889dc 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -41,6 +41,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rk3288-veyron-jerry.dtb \ rk3288-veyron-mickey.dtb \ rk3288-veyron-minnie.dtb \
- rk3288-veyron-speedy.dtb \ rk3288-vyasa.dtb \ rk3328-evb.dtb \ rk3368-lion.dtb \
diff --git a/arch/arm/dts/rk3288-veyron-speedy.dts b/arch/arm/dts/rk3288-veyron-speedy.dts new file mode 100644 index 0000000000..51e155d141 --- /dev/null +++ b/arch/arm/dts/rk3288-veyron-speedy.dts @@ -0,0 +1,203 @@ +/*
- Google Veyron Speedy Rev 1+ board device tree source
- Copyright 2015 Google, Inc
- SPDX-License-Identifier: GPL-2.0
- */
Where did this file come from? Was this taken from a vendor tree or from Linux?
+/dts-v1/; +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include "rk3288-veyron-chromebook.dtsi" +#include "cros-ec-sbs.dtsi"
+/ {
- model = "Google Jerry";
- compatible = "google,veyron-speedy-rev9", "google,veyron-speedy-rev8",
"google,veyron-speedy-rev7", "google,veyron-speedy-rev6","google,veyron-speedy-rev5", "google,veyron-speedy-rev4","google,veyron-speedy-rev3", "google,veyron-speedy-rev2","google,veyron-speedy", "google,veyron", "rockchip,rk3288";/* chosen { *//* stdout-path = &uart1; *//* }; */
Commented out sections won't be ok for the final version.
Note that the other veyron-devices have uart2 as their stdout path, so you might in fact not see any output due to the debug UART in SPL pointin to the wrong UART. You should check the setup code for the SPL stage there as well.
- panel_regulator: panel-regulator {
compatible = "regulator-fixed";enable-active-high;gpio = <&gpio7 RK_PB6 GPIO_ACTIVE_HIGH>;pinctrl-names = "default";pinctrl-0 = <&lcd_enable_h>;regulator-name = "panel_regulator";vin-supply = <&vcc33_sys>;- };
- vcc18_lcd: vcc18-lcd {
compatible = "regulator-fixed";enable-active-high;gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>;pinctrl-names = "default";pinctrl-0 = <&avdd_1v8_disp_en>;regulator-name = "vcc18_lcd";regulator-always-on;regulator-boot-on;vin-supply = <&vcc18_wl>;- };
- backlight_regulator: backlight-regulator {
compatible = "regulator-fixed";enable-active-high;gpio = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>;pinctrl-names = "default";pinctrl-0 = <&bl_pwr_en>;regulator-name = "backlight_regulator";vin-supply = <&vcc33_sys>;startup-delay-us = <15000>;- };
+};
+&dmc {
- rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d
0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x60x4 0x8 0x4 0x76 0x4 0x0 0x30 0x00x1 0x2 0x2 0x4 0x0 0x0 0xc0 0x40x8 0x1f4>;- rockchip,phy-timing = <0x48d7dd93 0x187008d8 0x121076
0x0 0xc3 0x6 0x1>;- rockchip,sdram-params = <0x20D266A4 0x5B6 6 533000000 6 13 0>;
+};
Depending on where this file came from, you may have to confirm that the DRAM init values here are correct...
+&gpio_keys {
- power {
gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;- };
+};
+&backlight {
- power-supply = <&backlight_regulator>;
+};
+&cpu_alert0 {
- temperature = <65000>;
+};
+&cpu_alert1 {
- temperature = <70000>;
+};
+&panel {
- power-supply = <&panel_regulator>;
+};
+&rk808 {
- pinctrl-names = "default";
- pinctrl-0 = <&pmic_int_l>;
+};
+&sdmmc {
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio
&sdmmc_bus4>;- disable-wp;
+};
+&vcc_5v {
- enable-active-high;
- /* gpio = <&gpio7 21 GPIO_ACTIVE_HIGH>; */
- pinctrl-names = "default";
- pinctrl-0 = <&drv_5v>;
+};
+&vcc50_hdmi {
- enable-active-high;
- gpio = <&gpio5 19 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&vcc50_hdmi_en>;
+};
+&edp {
- /* pinctrl-names = "default"; */
- /* pinctrl-0 = <&edp_hpd>; */
- /delete-property/pinctrl-names;
- /delete-property/pinctrl-0;
- force-hpd;
+};
+&pinctrl {
- backlight {
bl_pwr_en: bl_pwr_en {rockchip,pins = <2 12 RK_FUNC_GPIO &pcfg_pull_none>;};- };
- buck-5v {
drv_5v: drv-5v {rockchip,pins = <7 21 RK_FUNC_GPIO &pcfg_pull_none>;};- };
- edp {
edp_hpd: edp_hpd {rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_down>;};- };
- emmc {
/* Make sure eMMC is not in reset */emmc_deassert_reset: emmc-deassert-reset {rockchip,pins = <2 9 RK_FUNC_GPIO &pcfg_pull_none>;};- };
- hdmi {
vcc50_hdmi_en: vcc50-hdmi-en {rockchip,pins = <5 19 RK_FUNC_GPIO &pcfg_pull_none>;};- };
- lcd {
lcd_enable_h: lcd-en {rockchip,pins = <7 14 RK_FUNC_GPIO &pcfg_pull_none>;};avdd_1v8_disp_en: avdd-1v8-disp-en {rockchip,pins = <2 13 RK_FUNC_GPIO &pcfg_pull_none>;};- };
- pmic {
dvs_1: dvs-1 {rockchip,pins = <7 12 RK_FUNC_GPIO &pcfg_pull_down>;};dvs_2: dvs-2 {rockchip,pins = <7 15 RK_FUNC_GPIO &pcfg_pull_down>;};- };
+};
+/* &i2c4 { */ +/* status = "okay"; */
+/* pinctrl-names = "default"; */ +/* pinctrl-0 = <&i2c4_xfer>; */
+/* trackpad@15 { */ +/* compatible = "elan,i2c_touchpad"; */ +/* interrupt-parent = <&gpio7>; */ +/* interrupts = <3 IRQ_TYPE_EDGE_FALLING>; */ +/* /* */ +/* * Remove the inherited pinctrl settings to avoid clashing */ +/* * with bus-wide ones. */ +/* *1/ */ +/* /delete-property/pinctrl-names; */ +/* /delete-property/pinctrl-0; */ +/* reg = <0x15>; */ +/* vcc-supply = <&vcc33_io>; */ +/* wakeup-source; */ +/* }; */ +/* }; */
Again: commented-out parts will not be acceptable for a merge.
diff --git a/arch/arm/mach-rockchip/rk3288-board-spl.c b/arch/arm/mach-rockchip/rk3288-board-spl.c index 6b7bf85d8d..5b76114d9b 100644 --- a/arch/arm/mach-rockchip/rk3288-board-spl.c +++ b/arch/arm/mach-rockchip/rk3288-board-spl.c @@ -69,7 +69,8 @@ u32 spl_boot_device(void) fallback: #elif defined(CONFIG_TARGET_CHROMEBOOK_JERRY) || \ defined(CONFIG_TARGET_CHROMEBIT_MICKEY) || \
defined(CONFIG_TARGET_CHROMEBOOK_MINNIE)
defined(CONFIG_TARGET_CHROMEBOOK_MINNIE) || \defined(CONFIG_TARGET_CHROMEBOOK_SPEEDY)#endif return BOOT_DEVICE_MMC1; diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig b/arch/arm/mach-rockchip/rk3288/Kconfig index 4ad2940069..04377f9ea8 100644 --- a/arch/arm/mach-rockchip/rk3288/Kconfig +++ b/arch/arm/mach-rockchip/rk3288/Kconfig @@ -30,6 +30,17 @@ config TARGET_CHROMEBOOK_MINNIE functions. It includes 2 or 4GB of SDRAM and 16 or 32GB of internal MMC. The product name is ASUS Chromebook Flip.
+config TARGET_CHROMEBOOK_SPEEDY
- bool "Google/Rockchip Veyron-Speedy Chromebook"
- select BOARD_LATE_INIT
- help
Speedy is a RK3288-based clamshell device with 2 USB 2.0 ports,micro HDMI, an 11.6 inch display, micro-SD card,HD camera, touchpad, wifi and Bluetooth. It includes a Chrome OSEC (Cortex-M3) to provide access to the keyboard and batteryfunctions. It includes 2 or 4GB of SDRAM and 16GB of internal MMC.The product name is Asus Chromebook C201PA.config TARGET_EVB_RK3288 bool "Evb-RK3288" select BOARD_LATE_INIT diff --git a/board/google/veyron/Kconfig b/board/google/veyron/Kconfig index 770e9aad28..7f55d78dac 100644 --- a/board/google/veyron/Kconfig +++ b/board/google/veyron/Kconfig @@ -45,3 +45,19 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y
endif
+if TARGET_CHROMEBOOK_SPEEDY
+config SYS_BOARD
- default "veyron"
+config SYS_VENDOR
- default "google"
+config SYS_CONFIG_NAME
- default "veyron"
+config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
+endif diff --git a/configs/chromebook_speedy_defconfig b/configs/chromebook_speedy_defconfig new file mode 100644 index 0000000000..9626be9743 --- /dev/null +++ b/configs/chromebook_speedy_defconfig @@ -0,0 +1,92 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_ROCKCHIP_RK3288=y +# CONFIG_SPL_MMC_SUPPORT is not set +CONFIG_TARGET_CHROMEBOOK_SPEEDY=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_STACK_R_ADDR=0x80000 +CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-speedy" +CONFIG_DEBUG_UART=y +# CONFIG_ANDROID_BOOT_IMAGE is not set +CONFIG_SILENT_CONSOLE=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_SF_TEST=y +CONFIG_CMD_SPI=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_SPL_ISO_PARTITION is not set +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_SPL_PARTITION_UUIDS=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SPL_OF_PLATDATA=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +# CONFIG_SPL_SIMPLE_BUS is not set +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_I2C_CROS_EC_TUNNEL=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_I2C_MUX=y +CONFIG_DM_KEYBOARD=y +CONFIG_CROS_EC_KEYB=y +CONFIG_CROS_EC=y +CONFIG_CROS_EC_SPI=y +CONFIG_PWRSEQ=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +# CONFIG_SPL_PINCTRL_FULL is not set +CONFIG_PINCTRL_ROCKCHIP_RK3288=y +CONFIG_DM_PMIC=y +# CONFIG_SPL_PMIC_CHILDREN is not set +CONFIG_PMIC_RK8XX=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_DEBUG_UART_BASE=0xff690000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550=y +CONFIG_ROCKCHIP_SERIAL=y +CONFIG_ROCKCHIP_SPI=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_G_DNL_MANUFACTURER="Rockchip" +CONFIG_G_DNL_VENDOR_NUM=0x2207 +CONFIG_G_DNL_PRODUCT_NUM=0x320a +CONFIG_DM_VIDEO=y +CONFIG_DISPLAY=y +CONFIG_VIDEO_ROCKCHIP=y +CONFIG_DISPLAY_ROCKCHIP_EDP=y +CONFIG_DISPLAY_ROCKCHIP_HDMI=y +CONFIG_USE_TINY_PRINTF=y +CONFIG_CMD_DHRYSTONE=y +CONFIG_ERRNO_STR=y +# CONFIG_SPL_OF_LIBFDT is not set diff --git a/drivers/mtd/spi/spi_flash_ids.c b/drivers/mtd/spi/spi_flash_ids.c index 13f64e773f..cbfd8b7636 100644 --- a/drivers/mtd/spi/spi_flash_ids.c +++ b/drivers/mtd/spi/spi_flash_ids.c @@ -63,6 +63,7 @@ const struct spi_flash_info spi_flash_ids[] = { {"en25s64", INFO(0x1c3817, 0x0, 64 * 1024, 128, 0) }, #endif #ifdef CONFIG_SPI_FLASH_GIGADEVICE /* GIGADEVICE */
- {"gd25q32b", INFO(0xc84016, 0x0, 64 * 1024, 64, SECT_4K) },
This should go into a separate patch, as it's unrelated to the the other changes and will have to be merged separately (most likely through another custodian's tree).
Note that I didn't look up the device datasheet to confirm the device-id and whether the SECT_4K capability is really present.
{"gd25q64b", INFO(0xc84017, 0x0, 64 * 1024, 128, SECT_4K) }, {"gd25lq32", INFO(0xc86016, 0x0, 64 * 1024, 64, SECT_4K) }, #endif
So, regarding my old patchset. Thanks to the generous support of Simon, I have been able to use a google servo board to obtain an output log of my boot failure. Whereas Simon got the following:
U-Boot SPL 2017.11-rc2-00017-g6cda208-dirty (Oct 19 2017 - 17:20:26) Trying to boot from SPI
U-Boot 2017.11-rc2-00017-g6cda208-dirty (Oct 19 2017 - 17:20:26 -0600)
Model: Google Speedy DRAM: 2 GiB MMC: dwmmc@ff0c0000: 1, dwmmc@ff0d0000: 2, dwmmc@ff0f0000: 0 Using default environment
In: cros-ec-keyb Out: vidconsole Err: vidconsole Model: Google Speedy Net: Net Initialization Skipped No ethernet found. Hit any key to stop autoboot: 0 =>
On his 2 GiB Asus C201, I only get the following:
U-Boot SPL 2017.11-rc2-00017-g6cda208-dirty (Oct 19 2017 - 17:20:26) Trying to boot from SPI
U-Boot 2017.11-rc2-00017-g6cda208-dirty (Oct 19 2017 - 17:20:26 -0600)
Model: Google Speedy DRAM: 0 Bytes
Further, after rebasing my patch against master to commit ec1754f091c3c06d76592a3f9fecf6184f27e4c9 I don't get any output at all, except for one of those unicode mojibake <?> characters everytime I hit the servo reset button.
It seems somewhere along the lines between 0def58f7fd (upstream/master) Merge git://git.denx.de/u-boot-x86 and ec1754f091 (upstream/master) Prepare v2018.05-rc3 something went funky.
If someone with one of the supported rockchip chromebooks could dry the above commit I would greatly appreciate it.
Regards,
Marty
Hi Marty,
On 3 October 2017 at 16:03, Marty E. Plummer hanetzer@startmail.com wrote:
From: "Marty E. Plummer" hanetzer@protonmail.com
I realize this patch is not up to standards for the sake of mainlining right now, but I'm mostly interested in getting some feedback on how to make it work before getting into the nicities of mainline inclusion.
As of right now the bulk of this is the rk3288-veyron-speedy.dts file, which I assume has a similar enough boot system to the jerry and minnie.
If the resultant u-boot-spl.bin and u-boot-dtb.img are prepared according to the instructions in doc/README.rockchip and then flashed to the c201's spi memory I get very little in the way of result; the most I/O that to be seen is the board reacts to the power switch (led on, led off). I can not seem to get it to output the u-boot console to the built-in screen, and currently do not have a mini-hdmi cable to see if that is working or not (one is ordered, arrives thursday). Can't find a location to purchase a servo board for better debugging possibilities.
I was hoping someone on this mailing list could assist me in getting this to work; once a working setup is figured I'll do proper patchset for mainline inclusion.
This boots for me:
U-Boot SPL 2017.11-rc2-00017-g6cda208-dirty (Oct 19 2017 - 17:20:26) Trying to boot from SPI
U-Boot 2017.11-rc2-00017-g6cda208-dirty (Oct 19 2017 - 17:20:26 -0600)
Model: Google Speedy DRAM: 2 GiB MMC: dwmmc@ff0c0000: 1, dwmmc@ff0d0000: 2, dwmmc@ff0f0000: 0 Using default environment
In: cros-ec-keyb Out: vidconsole Err: vidconsole Model: Google Speedy Net: Net Initialization Skipped No ethernet found. Hit any key to stop autoboot: 0 =>
The display and keyboard work also. About 15% of the time it hangs at 'Using default environment' for about 5 seconds. Not sure why. Sometimes I see a blank screen in that case. Also the screen is very slow (as if the cache is off), even through the 'dhrystone' command shows a healthy 2421 DMIPS.
After building in b/chromebook_speedy I use this to write it to an em100 SPI emulator:
./b/chromebook_speedy/tools/mkimage -n rk3288 -T rkspi -d b/chromebook_speedy/spl/u-boot-spl.bin spl.bin && dd if=spl.bin of=spl-out.bin bs=128K conv=sync && cat spl-out.bin b/chromebook_speedy/u-boot.img >out.bin && dd if=out.bin of=out.bin.pad bs=4M conv=sync && sudo em100 -s -c GD25LQ32 -d out.bin.pad -r
The image is out.bin.pad. See here for my version:
https://drive.google.com/open?id=0B7WYZbZ9zd-3ZUJPUHItejR0QnM
I applied your patch to:
0def58f (upstream/master) Merge git://git.denx.de/u-boot-x86
and my only change was to change the model to 'Google Speedy' in the .dts file.
I wonder if you might have a different model to me? You can check this by booting into dev mode, logging in as root and typing:
cbmem -c |grep -i ram
My 'RAM Config' is 0.
Also with cbmem -c I can see that it has a compat preference of google,veyron-speedy-rev5
Regards, Simon
participants (3)
-
Marty E. Plummer -
Philipp Tomsich -
Simon Glass