HI: I use a 8MB TOP FLASH, with CFI driver can not handle this type, becasue SECT info order is for BOTTOM FLASH, so I modefied for it. Next version can detect bootloc :-)

Enjoy

Roger Huang

diff -rc u-boot/drivers/cfi_flash.c u-boot.cameo/drivers/cfi_flash.c *** u-boot/drivers/cfi_flash.c 2006-07-31 14:25:47.000000000 +0800 --- u-boot.cameo/drivers/cfi_flash.c 2006-07-31 12:39:55.000000000 +0800 *************** *** 1173,1179 **** } tmp = flash_read_long (info, 0, FLASH_OFFSET_ERASE_REGIONS + ! i * 4); erase_region_size = (tmp & 0xffff) ? ((tmp & 0xffff) * 256) : 128; tmp >>= 16; --- 1173,1184 ---- } tmp = flash_read_long (info, 0, FLASH_OFFSET_ERASE_REGIONS + ! #ifdef CFG_FLASH_SECT_INFO_REVS ! (num_erase_regions - i - 1) * ! #else ! i * ! #endif ! 4); erase_region_size = (tmp & 0xffff) ? ((tmp & 0xffff) * 256) : 128; tmp >>= 16; diff -rc u-boot/drivers/ns16550.c u-boot.cameo/drivers/ns16550.c *** u-boot/drivers/ns16550.c 2006-07-31 14:25:47.000000000 +0800 --- u-boot.cameo/drivers/ns16550.c 2006-07-27 13:08:00.000000000 +0800 *************** *** 23,28 **** --- 23,31 ---- com_port->lcr = LCR_BKSE | LCRVAL; com_port->dll = baud_divisor & 0xff; com_port->dlm = (baud_divisor >> 8) & 0xff; + #ifdef CFG_NS16550A_PSR + com_port->fcr = CFG_NS16550A_PSR; + #endif com_port->lcr = LCRVAL; com_port->mcr = MCRVAL; com_port->fcr = FCRVAL; diff -rc u-boot/README u-boot.cameo/README *** u-boot/README 2006-07-31 14:25:45.000000000 +0800 --- u-boot.cameo/README 2006-07-31 12:39:06.000000000 +0800 *************** *** 1818,1823 **** --- 1818,1826 ---- is useful, if some of the configured banks are only optionally available.

+ - CFG_FLASH_SECT_INFO_REVS + Reverse sector infomation order for broken CFI top devices + - CFG_RX_ETH_BUFFER: Defines the number of ethernet receive buffers. On some ethernet controllers it is recommended to set this value