[U-Boot] [PATCH 00/12] ARM: dra7: Add support for dra76-evm
dra76 family is a high-performance, infotainment application device, based on OMAP architecture on a 28-nm technology. This contains most of the subsystems, peripherals that are available on dra74, dra72 family. This SoC mainly features Subsystems: - 2 x Cortex-A15 with max speed of 1.8GHz - 2 X DSP - 2 X Cortex-M4 IPU - ISS - CAL - DSS - VPE - VIP Connectivity peripherals: - 1 USB3.0 and 3 USB2.0 subsystems - 2 x SATA - 2 x PCI Express Gen2 - 3-port Gigabit ethernet switch - 2 x CAN - MCAN
This series adds support for dra76-evm.
Tested on dra76-evm: MMC boot: http://pastebin.ubuntu.com/25295219/ eMMC boot: http://pastebin.ubuntu.com/25295222/ SPI boot: http://pastebin.ubuntu.com/25295229/
Keerthy (2): configs: dra7xx: Enable LP87565 related configs board: ti: dra76-evm: Add the pmic data
Lokesh Vutla (9): arm: omap5+: Add board specific ldo powering palmas: Add support for powering different ldos board: ti: dra76-evm: Add epprom support board: ti: dra76-evm: Add DDR data board: ti: dra76-evm: Add the pinmux data board: ti: dra76-evm: Add support for powering on mmc ldo env: ti: boot: Select dtb name for dra76 ARM: dts: dra7-evm: sync DT with latest Linux ARM: dts: dra76-evm: Add initial support
Praneeth Bajjuri (1): arm: dra76: Add support for ES1.0 detection
arch/arm/dts/Makefile | 2 +- arch/arm/dts/dra7-evm.dts | 533 ++------------------------------ arch/arm/dts/dra76-evm.dts | 423 +++++++++++++++++++++++++ arch/arm/dts/dra76x.dtsi | 19 ++ arch/arm/include/asm/arch-omap5/clock.h | 9 + arch/arm/include/asm/arch-omap5/omap.h | 1 + arch/arm/include/asm/omap_common.h | 9 + arch/arm/include/asm/omap_mmc.h | 1 + arch/arm/mach-omap2/omap5/hw_data.c | 44 +++ arch/arm/mach-omap2/omap5/hwinit.c | 19 +- arch/arm/mach-omap2/omap5/sdram.c | 2 + board/ti/dra7xx/evm.c | 140 ++++++++- board/ti/dra7xx/mux_data.h | 294 ++++++++++++++++++ configs/dra7xx_evm_defconfig | 4 +- configs/dra7xx_hs_evm_defconfig | 4 +- drivers/power/palmas.c | 11 +- include/environment/ti/boot.h | 2 + include/palmas.h | 6 +- 18 files changed, 999 insertions(+), 524 deletions(-) create mode 100644 arch/arm/dts/dra76-evm.dts create mode 100644 arch/arm/dts/dra76x.dtsi
It is not necessary all omap5+ based uses the same PMIC to poweron mmc. So add support for enabling mmc based on board.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- arch/arm/include/asm/omap_mmc.h | 1 + arch/arm/mach-omap2/omap5/hwinit.c | 16 ++++++---------- board/ti/dra7xx/evm.c | 14 ++++++++++++++ 3 files changed, 21 insertions(+), 10 deletions(-)
diff --git a/arch/arm/include/asm/omap_mmc.h b/arch/arm/include/asm/omap_mmc.h index f6eb51ee3c..fd33408622 100644 --- a/arch/arm/include/asm/omap_mmc.h +++ b/arch/arm/include/asm/omap_mmc.h @@ -174,4 +174,5 @@ int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio, int wp_gpio);
void vmmc_pbias_config(uint voltage); +void board_mmc_poweron_ldo(uint voltage); #endif /* OMAP_MMC_H_ */ diff --git a/arch/arm/mach-omap2/omap5/hwinit.c b/arch/arm/mach-omap2/omap5/hwinit.c index afe59e0b58..42b0d6121c 100644 --- a/arch/arm/mach-omap2/omap5/hwinit.c +++ b/arch/arm/mach-omap2/omap5/hwinit.c @@ -455,10 +455,14 @@ void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb, }
#if defined(CONFIG_PALMAS_POWER) +__weak void board_mmc_poweron_ldo(uint voltage) +{ + palmas_mmc1_poweron_ldo(voltage); + +} void vmmc_pbias_config(uint voltage) { u32 value = 0; - struct vcores_data const *vcores = *omap_vcores;
value = readl((*ctrl)->control_pbias); value &= ~SDCARD_PWRDNZ; @@ -467,15 +471,7 @@ void vmmc_pbias_config(uint voltage) value &= ~SDCARD_BIAS_PWRDNZ; writel(value, (*ctrl)->control_pbias);
- if (vcores->core.pmic->i2c_slave_addr == 0x60) { - if (voltage == LDO_VOLT_3V0) - voltage = 0x19; - else if (voltage == LDO_VOLT_1V8) - voltage = 0xa; - lp873x_mmc1_poweron_ldo(voltage); - } else { - palmas_mmc1_poweron_ldo(voltage); - } + board_mmc_poweron_ldo(voltage);
value = readl((*ctrl)->control_pbias); value |= SDCARD_BIAS_PWRDNZ; diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index 7d36f03fa1..e202ebf207 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -710,6 +710,20 @@ int board_mmc_init(bd_t *bis) omap_mmc_init(1, 0, 0, -1, -1); return 0; } + +void board_mmc_poweron_ldo(uint voltage) +{ + if (board_is_dra71x_evm()) { + if (voltage == LDO_VOLT_3V0) + voltage = 0x19; + else if (voltage == LDO_VOLT_1V8) + voltage = 0xa; + lp873x_mmc1_poweron_ldo(voltage); + } else { + palmas_mmc1_poweron_ldo(voltage); + } + +} #endif
#ifdef CONFIG_USB_DWC3
On Sat, Aug 12, 2017 at 11:59:22AM +0530, Lokesh Vutla wrote:
It is not necessary all omap5+ based uses the same PMIC to poweron mmc. So add support for enabling mmc based on board.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com
Reviewed-by: Tom Rini trini@konsulko.com
It is not necessary that ldo1 is used to power on mmc. So, add support for passing ldo registers for powering on mmc.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- arch/arm/mach-omap2/omap5/hwinit.c | 2 +- board/ti/dra7xx/evm.c | 2 +- drivers/power/palmas.c | 11 ++++------- include/palmas.h | 2 +- 4 files changed, 7 insertions(+), 10 deletions(-)
diff --git a/arch/arm/mach-omap2/omap5/hwinit.c b/arch/arm/mach-omap2/omap5/hwinit.c index 42b0d6121c..2050560a37 100644 --- a/arch/arm/mach-omap2/omap5/hwinit.c +++ b/arch/arm/mach-omap2/omap5/hwinit.c @@ -457,7 +457,7 @@ void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb, #if defined(CONFIG_PALMAS_POWER) __weak void board_mmc_poweron_ldo(uint voltage) { - palmas_mmc1_poweron_ldo(voltage); + palmas_mmc1_poweron_ldo(LDO1_VOLTAGE, LDO1_CTRL, voltage);
} void vmmc_pbias_config(uint voltage) diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index e202ebf207..ba3b477a6f 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -720,7 +720,7 @@ void board_mmc_poweron_ldo(uint voltage) voltage = 0xa; lp873x_mmc1_poweron_ldo(voltage); } else { - palmas_mmc1_poweron_ldo(voltage); + palmas_mmc1_poweron_ldo(LDO1_VOLTAGE, LDO1_CTRL, voltage); }
} diff --git a/drivers/power/palmas.c b/drivers/power/palmas.c index 4e9895987c..ddf777c26b 100644 --- a/drivers/power/palmas.c +++ b/drivers/power/palmas.c @@ -42,24 +42,21 @@ int lp873x_mmc1_poweron_ldo(uint voltage) } #endif
-int palmas_mmc1_poweron_ldo(uint voltage) +int palmas_mmc1_poweron_ldo(uint ldo_volt, uint ldo_ctrl, uint voltage) { u8 val = 0;
#if defined(CONFIG_DRA7XX) int ret; - /* - * Currently valid for the dra7xx_evm board: - * Set TPS659038 LDO1 to 3.0 V or 1.8V - */ - ret = palmas_i2c_write_u8(TPS65903X_CHIP_P1, LDO1_VOLTAGE, voltage); + + ret = palmas_i2c_write_u8(TPS65903X_CHIP_P1, ldo_volt, voltage); if (ret) { printf("tps65903x: could not set LDO1 voltage.\n"); return ret; } /* TURN ON LDO1 */ val = RSC_MODE_SLEEP | RSC_MODE_ACTIVE; - ret = palmas_i2c_write_u8(TPS65903X_CHIP_P1, LDO1_CTRL, val); + ret = palmas_i2c_write_u8(TPS65903X_CHIP_P1, ldo_ctrl, val); if (ret) { printf("tps65903x: could not turn on LDO1.\n"); return ret; diff --git a/include/palmas.h b/include/palmas.h index d676617344..404c2b3ca7 100644 --- a/include/palmas.h +++ b/include/palmas.h @@ -129,7 +129,7 @@ static inline int palmas_i2c_read_u8(u8 chip_no, u8 reg, u8 *val) }
void palmas_init_settings(void); -int palmas_mmc1_poweron_ldo(uint voltage); +int palmas_mmc1_poweron_ldo(uint ldo_volt, uint ldo_ctrl, uint voltage); int lp873x_mmc1_poweron_ldo(uint voltage); int twl603x_mmc1_set_ldo9(u8 vsel); int twl603x_audio_power(u8 on);
On Sat, Aug 12, 2017 at 11:59:23AM +0530, Lokesh Vutla wrote:
It is not necessary that ldo1 is used to power on mmc. So, add support for passing ldo registers for powering on mmc.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com
Reviewed-by: Tom Rini trini@konsulko.com
From: Keerthy j-keerthy@ti.com
Enable LP87565 related configs
Signed-off-by: Keerthy j-keerthy@ti.com Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- configs/dra7xx_evm_defconfig | 2 ++ configs/dra7xx_hs_evm_defconfig | 2 ++ 2 files changed, 4 insertions(+)
diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig index 0c4452a1d1..c151f49e30 100644 --- a/configs/dra7xx_evm_defconfig +++ b/configs/dra7xx_evm_defconfig @@ -67,11 +67,13 @@ CONFIG_SPL_PHY=y CONFIG_DM_PMIC=y CONFIG_PMIC_PALMAS=y CONFIG_PMIC_LP873X=y +CONFIG_PMIC_LP87565=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_REGULATOR_PALMAS=y CONFIG_DM_REGULATOR_LP873X=y +CONFIG_DM_REGULATOR_LP87565=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y CONFIG_DM_SPI=y diff --git a/configs/dra7xx_hs_evm_defconfig b/configs/dra7xx_hs_evm_defconfig index 75b77fa947..dba9f06bd6 100644 --- a/configs/dra7xx_hs_evm_defconfig +++ b/configs/dra7xx_hs_evm_defconfig @@ -70,11 +70,13 @@ CONFIG_SPL_PHY=y CONFIG_DM_PMIC=y CONFIG_PMIC_PALMAS=y CONFIG_PMIC_LP873X=y +CONFIG_PMIC_LP87565=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_REGULATOR_PALMAS=y CONFIG_DM_REGULATOR_LP873X=y ++CONFIG_DM_REGULATOR_LP87565=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y CONFIG_DM_SPI=y
On Sat, Aug 12, 2017 at 11:59:24AM +0530, Lokesh Vutla wrote:
From: Keerthy j-keerthy@ti.com
Enable LP87565 related configs
Signed-off-by: Keerthy j-keerthy@ti.com Signed-off-by: Lokesh Vutla lokeshvutla@ti.com
configs/dra7xx_evm_defconfig | 2 ++ configs/dra7xx_hs_evm_defconfig | 2 ++ 2 files changed, 4 insertions(+)
Please switch to imply'ing all of the relevant PMICs so that these do not get out of sync, thanks!
From: Praneeth Bajjuri praneeth@ti.com
dra76 family is a high-performance, infotainment application device, based on OMAP architecture on a 28-nm technology. This contains most of the subsystems, peripherals that are available on dra74, dra72 family. This SoC mainly features Subsystems: - 2 x Cortex-A15 with max speed of 1.8GHz - 2 X DSP - 2 X Cortex-M4 IPU - ISS - CAL - DSS - VPE - VIP Connectivity peripherals: - 1 USB3.0 and 3 USB2.0 subsystems - 2 x SATA - 2 x PCI Express Gen2 - 3-port Gigabit ethernet switch - 2 x CAN - MCAN
Adding CPU detection support for the dra76 ES1.0 soc and update prcm, control module, dplls data.
Signed-off-by: Praneeth Bajjuri praneeth@ti.com Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- arch/arm/include/asm/arch-omap5/omap.h | 1 + arch/arm/include/asm/omap_common.h | 8 ++++++++ arch/arm/mach-omap2/omap5/hw_data.c | 27 +++++++++++++++++++++++++++ arch/arm/mach-omap2/omap5/hwinit.c | 3 +++ 4 files changed, 39 insertions(+)
diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index 2f005dd3ad..3e15839858 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -58,6 +58,7 @@ #define OMAP5430_CONTROL_ID_CODE_ES2_0 0x1B94202F #define OMAP5432_CONTROL_ID_CODE_ES1_0 0x0B99802F #define OMAP5432_CONTROL_ID_CODE_ES2_0 0x1B99802F +#define DRA762_CONTROL_ID_CODE_ES1_0 0x0BB5002F #define DRA752_CONTROL_ID_CODE_ES1_0 0x0B99002F #define DRA752_CONTROL_ID_CODE_ES1_1 0x1B99002F #define DRA752_CONTROL_ID_CODE_ES2_0 0x2B99002F diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index ef5c481349..e951b232d6 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -722,6 +722,7 @@ static inline u8 is_omap54xx(void)
#define DRA7XX 0x07000000 #define DRA72X 0x07200000 +#define DRA76X 0x07600000
static inline u8 is_dra7xx(void) { @@ -734,6 +735,12 @@ static inline u8 is_dra72x(void) extern u32 *const omap_si_rev; return (*omap_si_rev & 0xFFF00000) == DRA72X; } + +static inline u8 is_dra76x(void) +{ + extern u32 *const omap_si_rev; + return ((*omap_si_rev & 0xFFF00000) == DRA76X); +} #endif
/* @@ -761,6 +768,7 @@ static inline u8 is_dra72x(void) #define OMAP5432_ES2_0 0x54320200
/* DRA7XX */ +#define DRA762_ES1_0 0x07620100 #define DRA752_ES1_0 0x07520100 #define DRA752_ES1_1 0x07520110 #define DRA752_ES2_0 0x07520200 diff --git a/arch/arm/mach-omap2/omap5/hw_data.c b/arch/arm/mach-omap2/omap5/hw_data.c index a8a6b8a869..4c4e245a6e 100644 --- a/arch/arm/mach-omap2/omap5/hw_data.c +++ b/arch/arm/mach-omap2/omap5/hw_data.c @@ -113,6 +113,16 @@ static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = { {10, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 38.4 MHz */ };
+static const struct dpll_params per_dpll_params_768mhz_dra76x[NUM_SYS_CLKS] = { + {32, 0, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1}, /* 12 MHz */ + {96, 4, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1}, /* 20 MHz */ + {160, 6, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1}, /* 16.8 MHz */ + {20, 0, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1}, /* 19.2 MHz */ + {192, 12, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {10, 0, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1}, /* 38.4 MHz */ +}; + static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = { {1165, 11, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ @@ -234,6 +244,17 @@ struct dplls omap5_dplls_es2 = { .ddr = NULL };
+struct dplls dra76x_dplls = { + .mpu = mpu_dpll_params_1ghz, + .core = core_dpll_params_2128mhz_dra7xx, + .per = per_dpll_params_768mhz_dra76x, + .abe = abe_dpll_params_sysclk2_361267khz, + .iva = iva_dpll_params_2330mhz_dra7xx, + .usb = usb_dpll_params_1920mhz, + .ddr = ddr_dpll_params_2664mhz, + .gmac = gmac_dpll_params_2000mhz, +}; + struct dplls dra7xx_dplls = { .mpu = mpu_dpll_params_1ghz, .core = core_dpll_params_2128mhz_dra7xx, @@ -700,6 +721,12 @@ void __weak hw_data_init(void) *ctrl = &omap5_ctrl; break;
+ case DRA762_ES1_0: + *prcm = &dra7xx_prcm; + *dplls_data = &dra76x_dplls; + *ctrl = &dra7xx_ctrl; + break; + case DRA752_ES1_0: case DRA752_ES1_1: case DRA752_ES2_0: diff --git a/arch/arm/mach-omap2/omap5/hwinit.c b/arch/arm/mach-omap2/omap5/hwinit.c index 2050560a37..e54547b5d9 100644 --- a/arch/arm/mach-omap2/omap5/hwinit.c +++ b/arch/arm/mach-omap2/omap5/hwinit.c @@ -362,6 +362,9 @@ void init_omap_revision(void) case OMAP5432_CONTROL_ID_CODE_ES2_0: *omap_si_rev = OMAP5432_ES2_0; break; + case DRA762_CONTROL_ID_CODE_ES1_0: + *omap_si_rev = DRA762_ES1_0; + break; case DRA752_CONTROL_ID_CODE_ES1_0: *omap_si_rev = DRA752_ES1_0; break;
On Sat, Aug 12, 2017 at 11:59:25AM +0530, Lokesh Vutla wrote:
From: Praneeth Bajjuri praneeth@ti.com
dra76 family is a high-performance, infotainment application device, based on OMAP architecture on a 28-nm technology. This contains most of the subsystems, peripherals that are available on dra74, dra72 family. This SoC mainly features Subsystems:
- 2 x Cortex-A15 with max speed of 1.8GHz
- 2 X DSP
- 2 X Cortex-M4 IPU
- ISS
- CAL
- DSS
- VPE
- VIP
Connectivity peripherals:
- 1 USB3.0 and 3 USB2.0 subsystems
- 2 x SATA
- 2 x PCI Express Gen2
- 3-port Gigabit ethernet switch
- 2 x CAN
- MCAN
Adding CPU detection support for the dra76 ES1.0 soc and update prcm, control module, dplls data.
Signed-off-by: Praneeth Bajjuri praneeth@ti.com Signed-off-by: Lokesh Vutla lokeshvutla@ti.com
Reviewed-by: Tom Rini trini@konsulko.com
The dra76-evm is a board based on TI's DRA76 processor Add eeprom support
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- board/ti/dra7xx/evm.c | 5 +++++ 1 file changed, 5 insertions(+)
diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index ba3b477a6f..08d96c369d 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -34,6 +34,7 @@ #include "mux_data.h" #include "../common/board_detect.h"
+#define board_is_dra76x_evm() board_ti_is("DRA76/7x") #define board_is_dra74x_evm() board_ti_is("5777xCPU") #define board_is_dra72x_evm() board_ti_is("DRA72x-T") #define board_is_dra71x_evm() board_ti_is("DRA79x,D") @@ -547,6 +548,8 @@ int board_late_init(void) name = "dra71x"; else name = "dra72x"; + } else if (is_dra76x()) { + name = "dra76x"; } else { name = "dra7xx"; } @@ -595,6 +598,8 @@ void do_board_detect(void) bname = "DRA72x EVM"; } else if (board_is_dra71x_evm()) { bname = "DRA71x EVM"; + } else if (board_is_dra76x_evm()) { + bname = "DRA76x EVM"; } else { /* If EEPROM is not populated */ if (is_dra72x())
On Sat, Aug 12, 2017 at 11:59:26AM +0530, Lokesh Vutla wrote:
The dra76-evm is a board based on TI's DRA76 processor Add eeprom support
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com
Reviewed-by: Tom Rini trini@konsulko.com
From: Keerthy j-keerthy@ti.com
dra76-evm uses lp8736 and tps65917 pmic for powering on various peripherals. Add data for these pmics and register for dra76-evm.
Signed-off-by: Keerthy j-keerthy@ti.com Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- arch/arm/include/asm/arch-omap5/clock.h | 9 ++++++ arch/arm/include/asm/omap_common.h | 1 + arch/arm/mach-omap2/omap5/hw_data.c | 16 +++++++++++ board/ti/dra7xx/evm.c | 50 +++++++++++++++++++++++++++++++++ 4 files changed, 76 insertions(+)
diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h index 0c99bbdc93..d37c202c18 100644 --- a/arch/arm/include/asm/arch-omap5/clock.h +++ b/arch/arm/include/asm/arch-omap5/clock.h @@ -327,6 +327,9 @@ /* Offset is 0.73V for LP873x */ #define LP873X_BUCK_BASE_VOLT_UV 730000
+/* Offset is 0.73V for LP87565 */ +#define LP87565_BUCK_BASE_VOLT_UV 730000 + /* TPS659038 */ #define TPS659038_I2C_SLAVE_ADDR 0x58 #define TPS659038_REG_ADDR_SMPS12 0x23 @@ -340,6 +343,7 @@ #define TPS65917_REG_ADDR_SMPS1 0x23 #define TPS65917_REG_ADDR_SMPS2 0x27 #define TPS65917_REG_ADDR_SMPS3 0x2F +#define TPS65917_REG_ADDR_SMPS4 0x33
/* LP873X */ #define LP873X_I2C_SLAVE_ADDR 0x60 @@ -347,6 +351,11 @@ #define LP873X_REG_ADDR_BUCK1 0x7 #define LP873X_REG_ADDR_LDO1 0xA
+/* LP87565 */ +#define LP87565_I2C_SLAVE_ADDR 0x61 +#define LP87565_REG_ADDR_BUCK01 0xA +#define LP87565_REG_ADDR_BUCK23 0xE + /* TPS */ #define TPS62361_I2C_SLAVE_ADDR 0x60 #define TPS62361_REG_ADDR_SET0 0x0 diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index e951b232d6..b34ad41325 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -607,6 +607,7 @@ extern struct omap_sys_ctrl_regs const dra7xx_ctrl;
extern struct pmic_data tps659038; extern struct pmic_data lp8733; +extern struct pmic_data lp87565;
void hw_data_init(void);
diff --git a/arch/arm/mach-omap2/omap5/hw_data.c b/arch/arm/mach-omap2/omap5/hw_data.c index 4c4e245a6e..d6174fb5c7 100644 --- a/arch/arm/mach-omap2/omap5/hw_data.c +++ b/arch/arm/mach-omap2/omap5/hw_data.c @@ -306,6 +306,22 @@ struct pmic_data tps659038 = { .gpio_en = 0, };
+/* The LP87565*/ +struct pmic_data lp87565 = { + .base_offset = LP873X_BUCK_BASE_VOLT_UV, + .step = 5000, /* 5 mV represented in uV */ + /* + * Offset codes 0 - 0x13 Invalid. + * Offset codes 0x14 0x17 give 10mV steps + * Offset codes 0x17 through 0x9D give 5mV steps + * So let us start with our operating range from .73V + */ + .start_code = 0x17, + .i2c_slave_addr = 0x60, + .pmic_bus_init = gpi2c_init, + .pmic_write = palmas_i2c_write_u8, +}; + /* The LP8732 and LP8733 are software-compatible, use common struct */ struct pmic_data lp8733 = { .base_offset = LP873X_BUCK_BASE_VOLT_UV, diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index 08d96c369d..7ae8d2ff73 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -357,6 +357,54 @@ struct vcores_data dra752_volts = { .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK, };
+struct vcores_data dra76x_volts = { + .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM, + .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM, + .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .mpu.addr = LP87565_REG_ADDR_BUCK01, + .mpu.pmic = &lp87565, + .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK, + + .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM, + .eve.value[OPP_OD] = VDD_EVE_DRA7_OD, + .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH, + .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM, + .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD, + .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH, + .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .eve.addr = TPS65917_REG_ADDR_SMPS1, + .eve.pmic = &tps659038, + .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK, + + .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM, + .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD, + .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH, + .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM, + .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD, + .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH, + .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .gpu.addr = LP87565_REG_ADDR_BUCK23, + .gpu.pmic = &lp87565, + .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK, + + .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM, + .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM, + .core.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .core.addr = TPS65917_REG_ADDR_SMPS3, + .core.pmic = &tps659038, + + .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM, + .iva.value[OPP_OD] = VDD_IVA_DRA7_OD, + .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH, + .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM, + .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD, + .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH, + .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .iva.addr = TPS65917_REG_ADDR_SMPS4, + .iva.pmic = &tps659038, + .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK, +}; + struct vcores_data dra722_volts = { .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM, .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM, @@ -622,6 +670,8 @@ void vcores_init(void) *omap_vcores = &dra722_volts; } else if (board_is_dra71x_evm()) { *omap_vcores = &dra718_volts; + } else if (board_is_dra76x_evm()) { + *omap_vcores = &dra76x_volts; } else { /* If EEPROM is not populated */ if (is_dra72x())
On Sat, Aug 12, 2017 at 11:59:27AM +0530, Lokesh Vutla wrote:
From: Keerthy j-keerthy@ti.com
dra76-evm uses lp8736 and tps65917 pmic for powering on various peripherals. Add data for these pmics and register for dra76-evm.
Signed-off-by: Keerthy j-keerthy@ti.com Signed-off-by: Lokesh Vutla lokeshvutla@ti.com
Reviewed-by: Tom Rini trini@konsulko.com
dra76-evm has the ddr parts connectedi running at 666MHz: EMIF1: MT41K512M16HA-125 AIT:A x 2 EMIF2: MT41K512M8RH-125-AAT:E x 4 Add support for configuring the above DDR parts.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- arch/arm/mach-omap2/omap5/hw_data.c | 1 + arch/arm/mach-omap2/omap5/sdram.c | 2 ++ board/ti/dra7xx/evm.c | 61 +++++++++++++++++++++++++++++++++++-- 3 files changed, 62 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-omap2/omap5/hw_data.c b/arch/arm/mach-omap2/omap5/hw_data.c index d6174fb5c7..d0d5d6804c 100644 --- a/arch/arm/mach-omap2/omap5/hw_data.c +++ b/arch/arm/mach-omap2/omap5/hw_data.c @@ -781,6 +781,7 @@ void get_ioregs(const struct ctrl_ioregs **regs) case DRA752_ES1_0: case DRA752_ES1_1: case DRA752_ES2_0: + case DRA762_ES1_0: *regs = &ioregs_dra7xx_es1; break; case DRA722_ES1_0: diff --git a/arch/arm/mach-omap2/omap5/sdram.c b/arch/arm/mach-omap2/omap5/sdram.c index 7712923d85..67ff63b9f6 100644 --- a/arch/arm/mach-omap2/omap5/sdram.c +++ b/arch/arm/mach-omap2/omap5/sdram.c @@ -480,6 +480,7 @@ void __weak emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, *regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz; *size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz); break; + case DRA762_ES1_0: case DRA722_ES2_0: *regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2; *size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2); @@ -709,6 +710,7 @@ const struct read_write_regs *get_bug_regs(u32 *iterations) *iterations = sizeof(omap5_bug_00339_regs)/ sizeof(omap5_bug_00339_regs[0]); break; + case DRA762_ES1_0: case DRA752_ES1_0: case DRA752_ES1_1: case DRA752_ES2_0: diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index 7ae8d2ff73..f9d0b05a16 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -210,6 +210,56 @@ const struct emif_regs emif2_ddr3_532_mhz_1cs_2G = { .emif_rd_wr_exec_thresh = 0x00000305 };
+const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra76 = { + .sdram_config_init = 0x61862B32, + .sdram_config = 0x61862B32, + .sdram_config2 = 0x00000000, + .ref_ctrl = 0x0000514C, + .ref_ctrl_final = 0x0000144A, + .sdram_tim1 = 0xD113783C, + .sdram_tim2 = 0x30B47FE3, + .sdram_tim3 = 0x409F8AD8, + .read_idle_ctrl = 0x00050000, + .zq_config = 0x5007190B, + .temp_alert_config = 0x00000000, + .emif_ddr_phy_ctlr_1_init = 0x0824400D, + .emif_ddr_phy_ctlr_1 = 0x0E24400D, + .emif_ddr_ext_phy_ctrl_1 = 0x04040100, + .emif_ddr_ext_phy_ctrl_2 = 0x006B009F, + .emif_ddr_ext_phy_ctrl_3 = 0x006B00A2, + .emif_ddr_ext_phy_ctrl_4 = 0x006B00A8, + .emif_ddr_ext_phy_ctrl_5 = 0x006B00A8, + .emif_rd_wr_lvl_rmp_win = 0x00000000, + .emif_rd_wr_lvl_rmp_ctl = 0x80000000, + .emif_rd_wr_lvl_ctl = 0x00000000, + .emif_rd_wr_exec_thresh = 0x00000305 +}; + +const struct emif_regs emif_2_regs_ddr3_666_mhz_1cs_dra76 = { + .sdram_config_init = 0x61862B32, + .sdram_config = 0x61862B32, + .sdram_config2 = 0x00000000, + .ref_ctrl = 0x0000514C, + .ref_ctrl_final = 0x0000144A, + .sdram_tim1 = 0xD113781C, + .sdram_tim2 = 0x30B47FE3, + .sdram_tim3 = 0x409F8AD8, + .read_idle_ctrl = 0x00050000, + .zq_config = 0x5007190B, + .temp_alert_config = 0x00000000, + .emif_ddr_phy_ctlr_1_init = 0x0824400D, + .emif_ddr_phy_ctlr_1 = 0x0E24400D, + .emif_ddr_ext_phy_ctrl_1 = 0x04040100, + .emif_ddr_ext_phy_ctrl_2 = 0x006B009F, + .emif_ddr_ext_phy_ctrl_3 = 0x006B00A2, + .emif_ddr_ext_phy_ctrl_4 = 0x006B00A8, + .emif_ddr_ext_phy_ctrl_5 = 0x006B00A8, + .emif_rd_wr_lvl_rmp_win = 0x00000000, + .emif_rd_wr_lvl_rmp_ctl = 0x80000000, + .emif_rd_wr_lvl_ctl = 0x00000000, + .emif_rd_wr_exec_thresh = 0x00000305 +}; + void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs) { u64 ram_size; @@ -235,6 +285,12 @@ void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs) break; } break; + case DRA762_ES1_0: + if (emif_nr == 1) + *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra76; + else + *regs = &emif_2_regs_ddr3_666_mhz_1cs_dra76; + break; case DRA722_ES1_0: case DRA722_ES2_0: if (ram_size < CONFIG_MAX_MEM_MAPPED) @@ -290,6 +346,7 @@ void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs) ram_size = board_ti_get_emif_size();
switch (omap_revision()) { + case DRA762_ES1_0: case DRA752_ES1_0: case DRA752_ES1_1: case DRA752_ES2_0: @@ -1010,8 +1067,8 @@ static inline void vtt_regulator_enable(void) if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL) return;
- /* Do not enable VTT for DRA722 */ - if (is_dra72x()) + /* Do not enable VTT for DRA722 or DRA76x */ + if (is_dra72x() || is_dra76x()) return;
/*
On Sat, Aug 12, 2017 at 11:59:28AM +0530, Lokesh Vutla wrote:
dra76-evm has the ddr parts connectedi running at 666MHz: EMIF1: MT41K512M16HA-125 AIT:A x 2 EMIF2: MT41K512M8RH-125-AAT:E x 4 Add support for configuring the above DDR parts.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com
Reviewed-by: Tom Rini trini@konsulko.com
Adding pinmux and IODELAY data for dra76-evm.
Signed-off-by: Vignesh R vigneshr@ti.com Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- board/ti/dra7xx/evm.c | 6 + board/ti/dra7xx/mux_data.h | 294 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 300 insertions(+)
diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index f9d0b05a16..d66bbeafca 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -783,6 +783,12 @@ void recalibrate_iodelay(void) iodelay = dra742_es1_1_iodelay_cfg_array; niodelays = ARRAY_SIZE(dra742_es1_1_iodelay_cfg_array); break; + case DRA762_ES1_0: + pads = dra76x_core_padconf_array; + npads = ARRAY_SIZE(dra76x_core_padconf_array); + iodelay = dra76x_es1_0_iodelay_cfg_array; + niodelays = ARRAY_SIZE(dra76x_es1_0_iodelay_cfg_array); + break; default: case DRA752_ES2_0: pads = dra74x_core_padconf_array; diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h index 2cc4be31b2..3c3a19a0e1 100644 --- a/board/ti/dra7xx/mux_data.h +++ b/board/ti/dra7xx/mux_data.h @@ -698,6 +698,194 @@ const struct pad_conf_entry dra74x_core_padconf_array[] = { {WAKEUP2, (M14)}, /* Wakeup2.gpio1_2 */ };
+const struct pad_conf_entry dra76x_core_padconf_array[] = { + {GPMC_AD0, (M3 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad0.vout3_d0 */ + {GPMC_AD1, (M3 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad1.vout3_d1 */ + {GPMC_AD2, (M3 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad2.vout3_d2 */ + {GPMC_AD3, (M3 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad3.vout3_d3 */ + {GPMC_AD4, (M3 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad4.vout3_d4 */ + {GPMC_AD5, (M3 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad5.vout3_d5 */ + {GPMC_AD6, (M3 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad6.vout3_d6 */ + {GPMC_AD7, (M3 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad7.vout3_d7 */ + {GPMC_AD8, (M3 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad8.vout3_d8 */ + {GPMC_AD9, (M3 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad9.vout3_d9 */ + {GPMC_AD10, (M3 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad10.vout3_d10 */ + {GPMC_AD11, (M3 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad11.vout3_d11 */ + {GPMC_AD12, (M3 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad12.vout3_d12 */ + {GPMC_AD13, (M3 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad13.vout3_d13 */ + {GPMC_AD14, (M3 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad14.vout3_d14 */ + {GPMC_AD15, (M3 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad15.vout3_d15 */ + {GPMC_A0, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a0.vout3_d16 */ + {GPMC_A1, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a1.vout3_d17 */ + {GPMC_A2, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a2.vout3_d18 */ + {GPMC_A3, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a3.vout3_d19 */ + {GPMC_A4, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a4.vout3_d20 */ + {GPMC_A5, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a5.vout3_d21 */ + {GPMC_A6, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a6.vout3_d22 */ + {GPMC_A7, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a7.vout3_d23 */ + {GPMC_A8, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a8.vout3_hsync */ + {GPMC_A9, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a9.vout3_vsync */ + {GPMC_A10, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a10.vout3_de */ + {GPMC_A11, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_a11.gpio2_1 */ + {GPMC_A12, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_a12.gpio2_2 */ + {GPMC_A13, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a13.qspi1_rtclk */ + {GPMC_A14, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a14.qspi1_d3 */ + {GPMC_A15, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a15.qspi1_d2 */ + {GPMC_A16, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a16.qspi1_d0 */ + {GPMC_A17, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a17.qspi1_d1 */ + {GPMC_A18, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a18.qspi1_sclk */ + {GPMC_A19, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a19.mmc2_dat4 */ + {GPMC_A20, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a20.mmc2_dat5 */ + {GPMC_A21, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a21.mmc2_dat6 */ + {GPMC_A22, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a22.mmc2_dat7 */ + {GPMC_A23, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a23.mmc2_clk */ + {GPMC_A24, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a24.mmc2_dat0 */ + {GPMC_A25, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a25.mmc2_dat1 */ + {GPMC_A26, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a26.mmc2_dat2 */ + {GPMC_A27, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a27.mmc2_dat3 */ + {GPMC_CS1, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_cs1.mmc2_cmd */ + {GPMC_CS0, (M0 | PIN_INPUT_PULLUP)}, /* gpmc_cs0.gpmc_cs0 */ + {GPMC_CS2, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_cs2.qspi1_cs0 */ + {GPMC_CS3, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_cs3.vout3_clk */ + {GPMC_ADVN_ALE, (M0 | PIN_INPUT_PULLUP)}, /* gpmc_advn_ale.gpmc_advn_ale */ + {GPMC_OEN_REN, (M0 | PIN_INPUT_PULLUP)}, /* gpmc_oen_ren.gpmc_oen_ren */ + {GPMC_WEN, (M0 | PIN_INPUT_PULLUP)}, /* gpmc_wen.gpmc_wen */ + {GPMC_BEN0, (M0 | PIN_INPUT_PULLUP)}, /* gpmc_ben0.gpmc_ben0 */ + {GPMC_WAIT0, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* gpmc_wait0.gpmc_wait0 */ + {VIN1A_FLD0, (M14 | PIN_INPUT_PULLUP)}, /* vin1a_fld0.gpio3_1 */ + {VIN2A_CLK0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_clk0.vin2a_clk0 */ + {VIN2A_DE0, (M15 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_de0.Driveroff */ + {VIN2A_FLD0, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_fld0.gpio3_30 */ + {VIN2A_HSYNC0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_hsync0.vin2a_hsync0 */ + {VIN2A_VSYNC0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_vsync0.vin2a_vsync0 */ + {VIN2A_D0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d0.vin2a_d0 */ + {VIN2A_D1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d1.vin2a_d1 */ + {VIN2A_D2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d2.vin2a_d2 */ + {VIN2A_D3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d3.vin2a_d3 */ + {VIN2A_D4, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d4.vin2a_d4 */ + {VIN2A_D5, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d5.vin2a_d5 */ + {VIN2A_D6, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d6.vin2a_d6 */ + {VIN2A_D7, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d7.vin2a_d7 */ + {VIN2A_D8, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d8.vin2a_d8 */ + {VIN2A_D9, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d9.vin2a_d9 */ + {VIN2A_D10, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d10.vin2a_d10 */ + {VIN2A_D11, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d11.vin2a_d11 */ + {VIN2A_D12, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d12.rgmii1_txc */ + {VIN2A_D13, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d13.rgmii1_txctl */ + {VIN2A_D14, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d14.rgmii1_txd3 */ + {VIN2A_D15, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d15.rgmii1_txd2 */ + {VIN2A_D16, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d16.rgmii1_txd1 */ + {VIN2A_D17, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d17.rgmii1_txd0 */ + {VIN2A_D18, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d18.rgmii1_rxc */ + {VIN2A_D19, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d19.rgmii1_rxctl */ + {VIN2A_D20, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d20.rgmii1_rxd3 */ + {VIN2A_D21, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d21.rgmii1_rxd2 */ + {VIN2A_D22, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d22.rgmii1_rxd1 */ + {VIN2A_D23, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d23.rgmii1_rxd0 */ + {VOUT1_CLK, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_clk.vout1_clk */ + {VOUT1_DE, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_de.vout1_de */ + {VOUT1_FLD, (M14 | PIN_INPUT_PULLUP)}, /* vout1_fld.gpio4_21 */ + {VOUT1_HSYNC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_hsync.vout1_hsync */ + {VOUT1_VSYNC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_vsync.vout1_vsync */ + {VOUT1_D0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d0.vout1_d0 */ + {VOUT1_D1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d1.vout1_d1 */ + {VOUT1_D2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d2.vout1_d2 */ + {VOUT1_D3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d3.vout1_d3 */ + {VOUT1_D4, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d4.vout1_d4 */ + {VOUT1_D5, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d5.vout1_d5 */ + {VOUT1_D6, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d6.vout1_d6 */ + {VOUT1_D7, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d7.vout1_d7 */ + {VOUT1_D8, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d8.vout1_d8 */ + {VOUT1_D9, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d9.vout1_d9 */ + {VOUT1_D10, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d10.vout1_d10 */ + {VOUT1_D11, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d11.vout1_d11 */ + {VOUT1_D12, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d12.vout1_d12 */ + {VOUT1_D13, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d13.vout1_d13 */ + {VOUT1_D14, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d14.vout1_d14 */ + {VOUT1_D15, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d15.vout1_d15 */ + {VOUT1_D16, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d16.vout1_d16 */ + {VOUT1_D17, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d17.vout1_d17 */ + {VOUT1_D18, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d18.vout1_d18 */ + {VOUT1_D19, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d19.vout1_d19 */ + {VOUT1_D20, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d20.vout1_d20 */ + {VOUT1_D21, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d21.vout1_d21 */ + {VOUT1_D22, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d22.vout1_d22 */ + {VOUT1_D23, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d23.vout1_d23 */ + {MDIO_MCLK, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mdio_mclk.mdio_mclk */ + {MDIO_D, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mdio_d.mdio_d */ + {RGMII0_TXC, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_txc.rgmii0_txc */ + {RGMII0_TXCTL, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_txctl.rgmii0_txctl */ + {RGMII0_TXD3, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_txd3.rgmii0_txd3 */ + {RGMII0_TXD2, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_txd2.rgmii0_txd2 */ + {RGMII0_TXD1, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_txd1.rgmii0_txd1 */ + {RGMII0_TXD0, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_txd0.rgmii0_txd0 */ + {RGMII0_RXC, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxc.rgmii0_rxc */ + {RGMII0_RXCTL, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxctl.rgmii0_rxctl */ + {RGMII0_RXD3, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxd3.rgmii0_rxd3 */ + {RGMII0_RXD2, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxd2.rgmii0_rxd2 */ + {RGMII0_RXD1, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxd1.rgmii0_rxd1 */ + {RGMII0_RXD0, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxd0.rgmii0_rxd0 */ + {USB1_DRVVBUS, (M0 | PIN_INPUT_SLEW)}, /* usb1_drvvbus.usb1_drvvbus */ + {USB2_DRVVBUS, (M0 | PIN_INPUT_SLEW)}, /* usb2_drvvbus.usb2_drvvbus */ + {GPIO6_14, (M9 | PIN_INPUT_PULLUP)}, /* gpio6_14.i2c3_sda */ + {GPIO6_15, (M9 | PIN_INPUT_PULLUP)}, /* gpio6_15.i2c3_scl */ + {GPIO6_16, (M0 | PIN_INPUT_PULLUP)}, /* gpio6_16.gpio6_16 */ + {XREF_CLK2, (M5 | PIN_INPUT_PULLDOWN)}, /* xref_clk2.atl_clk2 */ + {MCASP1_ACLKX, (M14 | 0x00070000)}, /* mcasp1_aclkx.gpio7_31 */ + {MCASP1_FSX, (M14 | PIN_INPUT | SLEWCONTROL)}, /* mcasp1_fsx.gpio7_30 */ + {MCASP1_AXR0, (M10 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr0.i2c5_sda */ + {MCASP1_AXR1, (M10 | 0x000f0000)}, /* mcasp1_axr1.i2c5_scl */ + {MCASP1_AXR2, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr2.gpio5_4 */ + {MCASP1_AXR3, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr3.gpio5_5 */ + {MCASP1_AXR4, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr4.gpio5_6 */ + {MCASP1_AXR5, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr5.gpio5_7 */ + {MCASP1_AXR6, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr6.gpio5_8 */ + {MCASP1_AXR7, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr7.gpio5_9 */ + {MCASP1_AXR12, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)}, /* mcasp1_axr12.mcasp7_axr0 */ + {MCASP1_AXR13, (M1 | PIN_INPUT_SLEW)}, /* mcasp1_axr13.mcasp7_axr1 */ + {MCASP1_AXR14, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)}, /* mcasp1_axr14.mcasp7_aclkx */ + {MCASP1_AXR15, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)}, /* mcasp1_axr15.mcasp7_fsx */ + {MCASP2_ACLKR, (M15 | PIN_INPUT_PULLUP)}, /* mcasp2_aclkr.Driveroff */ + {MCASP3_ACLKX, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp3_aclkx.mcasp3_aclkx */ + {MCASP3_FSX, (M0 | PIN_INPUT_SLEW)}, /* mcasp3_fsx.mcasp3_fsx */ + {MCASP3_AXR0, (M0 | PIN_INPUT_SLEW)}, /* mcasp3_axr0.mcasp3_axr0 */ + {MCASP3_AXR1, (M0 | PIN_INPUT_SLEW | VIRTUAL_MODE6)}, /* mcasp3_axr1.mcasp3_axr1 */ + {MMC1_CLK, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_clk.mmc1_clk */ + {MMC1_CMD, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_cmd.mmc1_cmd */ + {MMC1_DAT0, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat0.mmc1_dat0 */ + {MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat1.mmc1_dat1 */ + {MMC1_DAT2, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat2.mmc1_dat2 */ + {MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat3.mmc1_dat3 */ + {MMC1_SDCD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mmc1_sdcd.mmc1_sdcd */ + {MMC1_SDWP, (M14 | PIN_INPUT_SLEW)}, /* mmc1_sdwp.gpio6_28 */ + {SPI1_SCLK, (M0 | PIN_INPUT_PULLDOWN)}, /* spi1_sclk.spi1_sclk */ + {SPI1_D1, (M0 | PIN_INPUT_PULLDOWN)}, /* spi1_d1.spi1_d1 */ + {SPI1_D0, (M0 | PIN_INPUT_PULLDOWN)}, /* spi1_d0.spi1_d0 */ + {SPI1_CS0, (M0 | PIN_INPUT_PULLUP)}, /* spi1_cs0.spi1_cs0 */ + {SPI1_CS2, (M6 | 0x000f0000)}, /* spi1_cs2.hdmi1_hpd */ + {SPI1_CS3, (M6 | 0x000f0000)}, /* spi1_cs3.hdmi1_cec */ + {SPI2_SCLK, (M1 | PIN_INPUT_PULLDOWN)}, /* spi2_sclk.uart3_rxd */ + {SPI2_D1, (M1 | PIN_INPUT_SLEW)}, /* spi2_d1.uart3_txd */ + {SPI2_D0, (M1 | PIN_INPUT_SLEW)}, /* spi2_d0.uart3_ctsn */ + {SPI2_CS0, (M1 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi2_cs0.uart3_rtsn */ + {DCAN1_TX, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* dcan1_tx.dcan1_tx */ + {DCAN1_RX, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* dcan1_rx.dcan1_rx */ + {UART1_RXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* uart1_rxd.uart1_rxd */ + {UART1_TXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* uart1_txd.uart1_txd */ + {UART1_CTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart1_ctsn.mmc4_clk */ + {UART1_RTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart1_rtsn.mmc4_cmd */ + {UART2_RXD, (M3 | PIN_INPUT_PULLUP)}, /* N/A.mmc4_dat0 */ + {UART2_TXD, (M3 | PIN_INPUT_PULLUP)}, /* uart2_txd.mmc4_dat1 */ + {UART2_CTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart2_ctsn.mmc4_dat2 */ + {UART2_RTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart2_rtsn.mmc4_dat3 */ + {I2C2_SDA, (M1 | PIN_INPUT_PULLUP)}, /* i2c2_sda.hdmi1_ddc_scl */ + {I2C2_SCL, (M1 | PIN_INPUT_PULLUP)}, /* i2c2_scl.hdmi1_ddc_sda */ + {WAKEUP0, (M14 | PIN_OUTPUT)}, /* N/A.gpio1_0 */ + {WAKEUP1, (M14 | PIN_OUTPUT)}, /* N/A.gpio1_1 */ + {WAKEUP2, (M1 | PIN_OUTPUT)}, /* N/A.sys_nirq2 */ + {WAKEUP3, (M1 | PIN_OUTPUT)}, /* N/A.sys_nirq1 */ +}; + #ifdef CONFIG_IODELAY_RECALIBRATION const struct iodelay_cfg_entry dra742_es1_1_iodelay_cfg_array[] = { {0x06F0, 480, 0}, /* CFG_RGMII0_RXC_IN */ @@ -826,6 +1014,112 @@ const struct iodelay_cfg_entry dra742_es2_0_iodelay_cfg_array[] = { {0x0188, 590, 0}, /* CFG_GPMC_A18_OUT */ {0x0374, 0, 0}, /* CFG_GPMC_CS2_OUT */ }; + +const struct iodelay_cfg_entry dra76x_es1_0_iodelay_cfg_array[] = { + {0x011C, 787, 0}, /* CFG_GPMC_A0_OUT */ + {0x0128, 1181, 0}, /* CFG_GPMC_A10_OUT */ + {0x0144, 0, 0}, /* CFG_GPMC_A13_IN */ + {0x0150, 2149, 1052}, /* CFG_GPMC_A14_IN */ + {0x015C, 2121, 997}, /* CFG_GPMC_A15_IN */ + {0x0168, 2159, 1134}, /* CFG_GPMC_A16_IN */ + {0x0170, 0, 0}, /* CFG_GPMC_A16_OUT */ + {0x0174, 2135, 1085}, /* CFG_GPMC_A17_IN */ + {0x0188, 0, 0}, /* CFG_GPMC_A18_OUT */ + {0x01A0, 592, 0}, /* CFG_GPMC_A1_OUT */ + {0x020C, 641, 0}, /* CFG_GPMC_A2_OUT */ + {0x0218, 1481, 0}, /* CFG_GPMC_A3_OUT */ + {0x0224, 1775, 0}, /* CFG_GPMC_A4_OUT */ + {0x0230, 785, 0}, /* CFG_GPMC_A5_OUT */ + {0x023C, 848, 0}, /* CFG_GPMC_A6_OUT */ + {0x0248, 851, 0}, /* CFG_GPMC_A7_OUT */ + {0x0254, 1783, 0}, /* CFG_GPMC_A8_OUT */ + {0x0260, 951, 0}, /* CFG_GPMC_A9_OUT */ + {0x026C, 1091, 0}, /* CFG_GPMC_AD0_OUT */ + {0x0278, 1027, 0}, /* CFG_GPMC_AD10_OUT */ + {0x0284, 824, 0}, /* CFG_GPMC_AD11_OUT */ + {0x0290, 1196, 0}, /* CFG_GPMC_AD12_OUT */ + {0x029C, 754, 0}, /* CFG_GPMC_AD13_OUT */ + {0x02A8, 665, 0}, /* CFG_GPMC_AD14_OUT */ + {0x02B4, 1027, 0}, /* CFG_GPMC_AD15_OUT */ + {0x02C0, 937, 0}, /* CFG_GPMC_AD1_OUT */ + {0x02CC, 1168, 0}, /* CFG_GPMC_AD2_OUT */ + {0x02D8, 872, 0}, /* CFG_GPMC_AD3_OUT */ + {0x02E4, 1092, 0}, /* CFG_GPMC_AD4_OUT */ + {0x02F0, 576, 0}, /* CFG_GPMC_AD5_OUT */ + {0x02FC, 1113, 0}, /* CFG_GPMC_AD6_OUT */ + {0x0308, 943, 0}, /* CFG_GPMC_AD7_OUT */ + {0x0314, 0, 0}, /* CFG_GPMC_AD8_OUT */ + {0x0320, 0, 0}, /* CFG_GPMC_AD9_OUT */ + {0x0374, 0, 0}, /* CFG_GPMC_CS2_OUT */ + {0x0380, 1801, 948}, /* CFG_GPMC_CS3_OUT */ + {0x06F0, 451, 0}, /* CFG_RGMII0_RXC_IN */ + {0x06FC, 127, 1571}, /* CFG_RGMII0_RXCTL_IN */ + {0x0708, 165, 1178}, /* CFG_RGMII0_RXD0_IN */ + {0x0714, 136, 1302}, /* CFG_RGMII0_RXD1_IN */ + {0x0720, 0, 1520}, /* CFG_RGMII0_RXD2_IN */ + {0x072C, 28, 1690}, /* CFG_RGMII0_RXD3_IN */ + {0x0740, 121, 0}, /* CFG_RGMII0_TXC_OUT */ + {0x074C, 60, 0}, /* CFG_RGMII0_TXCTL_OUT */ + {0x0758, 153, 0}, /* CFG_RGMII0_TXD0_OUT */ + {0x0764, 35, 0}, /* CFG_RGMII0_TXD1_OUT */ + {0x0770, 0, 0}, /* CFG_RGMII0_TXD2_OUT */ + {0x077C, 172, 0}, /* CFG_RGMII0_TXD3_OUT */ + {0x0A38, 0, 0}, /* CFG_VIN2A_CLK0_IN */ + {0x0A44, 2180, 0}, /* CFG_VIN2A_D0_IN */ + {0x0A50, 2297, 110}, /* CFG_VIN2A_D10_IN */ + {0x0A5C, 1938, 0}, /* CFG_VIN2A_D11_IN */ + {0x0A70, 147, 0}, /* CFG_VIN2A_D12_OUT */ + {0x0A7C, 110, 0}, /* CFG_VIN2A_D13_OUT */ + {0x0A88, 18, 0}, /* CFG_VIN2A_D14_OUT */ + {0x0A94, 82, 0}, /* CFG_VIN2A_D15_OUT */ + {0x0AA0, 33, 0}, /* CFG_VIN2A_D16_OUT */ + {0x0AAC, 0, 0}, /* CFG_VIN2A_D17_OUT */ + {0x0AB0, 417, 0}, /* CFG_VIN2A_D18_IN */ + {0x0ABC, 156, 843}, /* CFG_VIN2A_D19_IN */ + {0x0AC8, 2326, 309}, /* CFG_VIN2A_D1_IN */ + {0x0AD4, 223, 1413}, /* CFG_VIN2A_D20_IN */ + {0x0AE0, 169, 1415}, /* CFG_VIN2A_D21_IN */ + {0x0AEC, 43, 1150}, /* CFG_VIN2A_D22_IN */ + {0x0AF8, 0, 1210}, /* CFG_VIN2A_D23_IN */ + {0x0B04, 2057, 0}, /* CFG_VIN2A_D2_IN */ + {0x0B10, 2440, 257}, /* CFG_VIN2A_D3_IN */ + {0x0B1C, 2142, 0}, /* CFG_VIN2A_D4_IN */ + {0x0B28, 2455, 252}, /* CFG_VIN2A_D5_IN */ + {0x0B34, 1883, 0}, /* CFG_VIN2A_D6_IN */ + {0x0B40, 2229, 0}, /* CFG_VIN2A_D7_IN */ + {0x0B4C, 2250, 151}, /* CFG_VIN2A_D8_IN */ + {0x0B58, 2279, 27}, /* CFG_VIN2A_D9_IN */ + {0x0B7C, 2233, 0}, /* CFG_VIN2A_HSYNC0_IN */ + {0x0B88, 1936, 0}, /* CFG_VIN2A_VSYNC0_IN */ + {0x0B9C, 1281, 497}, /* CFG_VOUT1_CLK_OUT */ + {0x0BA8, 379, 0}, /* CFG_VOUT1_D0_OUT */ + {0x0BB4, 441, 0}, /* CFG_VOUT1_D10_OUT */ + {0x0BC0, 461, 0}, /* CFG_VOUT1_D11_OUT */ + {0x0BCC, 1189, 0}, /* CFG_VOUT1_D12_OUT */ + {0x0BD8, 312, 0}, /* CFG_VOUT1_D13_OUT */ + {0x0BE4, 298, 0}, /* CFG_VOUT1_D14_OUT */ + {0x0BF0, 284, 0}, /* CFG_VOUT1_D15_OUT */ + {0x0BFC, 152, 0}, /* CFG_VOUT1_D16_OUT */ + {0x0C08, 216, 0}, /* CFG_VOUT1_D17_OUT */ + {0x0C14, 408, 0}, /* CFG_VOUT1_D18_OUT */ + {0x0C20, 519, 0}, /* CFG_VOUT1_D19_OUT */ + {0x0C2C, 475, 0}, /* CFG_VOUT1_D1_OUT */ + {0x0C38, 316, 0}, /* CFG_VOUT1_D20_OUT */ + {0x0C44, 59, 0}, /* CFG_VOUT1_D21_OUT */ + {0x0C50, 221, 0}, /* CFG_VOUT1_D22_OUT */ + {0x0C5C, 96, 0}, /* CFG_VOUT1_D23_OUT */ + {0x0C68, 264, 0}, /* CFG_VOUT1_D2_OUT */ + {0x0C74, 421, 0}, /* CFG_VOUT1_D3_OUT */ + {0x0C80, 1257, 0}, /* CFG_VOUT1_D4_OUT */ + {0x0C8C, 432, 0}, /* CFG_VOUT1_D5_OUT */ + {0x0C98, 436, 0}, /* CFG_VOUT1_D6_OUT */ + {0x0CA4, 440, 0}, /* CFG_VOUT1_D7_OUT */ + {0x0CB0, 81, 100}, /* CFG_VOUT1_D8_OUT */ + {0x0CBC, 471, 0}, /* CFG_VOUT1_D9_OUT */ + {0x0CC8, 0, 0}, /* CFG_VOUT1_DE_OUT */ + {0x0CE0, 0, 0}, /* CFG_VOUT1_HSYNC_OUT */ + {0x0CEC, 815, 0}, /* CFG_VOUT1_VSYNC_OUT */ +}; #endif
#endif /* _MUX_DATA_DRA7XX_H_ */
On Sat, Aug 12, 2017 at 11:59:29AM +0530, Lokesh Vutla wrote:
Adding pinmux and IODELAY data for dra76-evm.
Signed-off-by: Vignesh R vigneshr@ti.com Signed-off-by: Lokesh Vutla lokeshvutla@ti.com
Reviewed-by: Tom Rini trini@konsulko.com
ldo4 is used to poweron mmc on dra76-evm. Enable it.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- board/ti/dra7xx/evm.c | 2 ++ include/palmas.h | 4 ++++ 2 files changed, 6 insertions(+)
diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index d66bbeafca..14c06f5eda 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -837,6 +837,8 @@ void board_mmc_poweron_ldo(uint voltage) else if (voltage == LDO_VOLT_1V8) voltage = 0xa; lp873x_mmc1_poweron_ldo(voltage); + } else if (board_is_dra76x_evm()) { + palmas_mmc1_poweron_ldo(LDO4_VOLTAGE, LDO4_CTRL, voltage); } else { palmas_mmc1_poweron_ldo(LDO1_VOLTAGE, LDO1_CTRL, voltage); } diff --git a/include/palmas.h b/include/palmas.h index 404c2b3ca7..d366c98d22 100644 --- a/include/palmas.h +++ b/include/palmas.h @@ -38,6 +38,10 @@ #define LDO2_CTRL 0x52 #define LDO2_VOLTAGE 0x53
+/* LDO2 control/voltage */ +#define LDO4_CTRL 0x5e +#define LDO4_VOLTAGE 0x5f + /* LDO9 control/voltage */ #define LDO9_CTRL 0x60 #define LDO9_VOLTAGE 0x61
On Sat, Aug 12, 2017 at 11:59:30AM +0530, Lokesh Vutla wrote:
ldo4 is used to poweron mmc on dra76-evm. Enable it.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com
Reviewed-by: Tom Rini trini@konsulko.com
Select dtb name for dra76-evm.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- include/environment/ti/boot.h | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/include/environment/ti/boot.h b/include/environment/ti/boot.h index 1c3ae40a99..01f7f7a300 100644 --- a/include/environment/ti/boot.h +++ b/include/environment/ti/boot.h @@ -44,6 +44,8 @@ "setenv fdtfile dra72-evm.dtb; fi;" \ "if test $board_name = dra71x; then " \ "setenv fdtfile dra71-evm.dtb; fi;" \ + "if test $board_name = dra76x; then " \ + "setenv fdtfile dra76-evm.dtb; fi;" \ "if test $board_name = beagle_x15; then " \ "setenv fdtfile am57xx-beagle-x15.dtb; fi;" \ "if test $board_name = beagle_x15_revb1; then " \
On Sat, Aug 12, 2017 at 11:59:31AM +0530, Lokesh Vutla wrote:
Select dtb name for dra76-evm.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com
Reviewed-by: Tom Rini trini@konsulko.com
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- arch/arm/dts/dra7-evm.dts | 276 ++++------------------------------------------ 1 file changed, 23 insertions(+), 253 deletions(-)
diff --git a/arch/arm/dts/dra7-evm.dts b/arch/arm/dts/dra7-evm.dts index 4d882ab338..511862c5f3 100644 --- a/arch/arm/dts/dra7-evm.dts +++ b/arch/arm/dts/dra7-evm.dts @@ -156,204 +156,6 @@ };
&dra7_pmx_core { - pinctrl-names = "default"; - pinctrl-0 = <&vtt_pin>; - - vtt_pin: pinmux_vtt_pin { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x37b4, PIN_OUTPUT | MUX_MODE14) /* spi1_cs1.gpio7_11 */ - >; - }; - - i2c1_pins: pinmux_i2c1_pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3800, PIN_INPUT | MUX_MODE0) /* i2c1_sda */ - DRA7XX_CORE_IOPAD(0x3804, PIN_INPUT | MUX_MODE0) /* i2c1_scl */ - >; - }; - - i2c2_pins: pinmux_i2c2_pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3808, PIN_INPUT | MUX_MODE0) /* i2c2_sda */ - DRA7XX_CORE_IOPAD(0x380c, PIN_INPUT | MUX_MODE0) /* i2c2_scl */ - >; - }; - - i2c3_pins: pinmux_i2c3_pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3688, PIN_INPUT | MUX_MODE9) /* gpio6_14.i2c3_sda */ - DRA7XX_CORE_IOPAD(0x368c, PIN_INPUT | MUX_MODE9) /* gpio6_15.i2c3_scl */ - >; - }; - - mcspi1_pins: pinmux_mcspi1_pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x37a4, PIN_INPUT | MUX_MODE0) /* spi1_sclk */ - DRA7XX_CORE_IOPAD(0x37a8, PIN_INPUT | MUX_MODE0) /* spi1_d1 */ - DRA7XX_CORE_IOPAD(0x37ac, PIN_INPUT | MUX_MODE0) /* spi1_d0 */ - DRA7XX_CORE_IOPAD(0x37b0, PIN_INPUT_SLEW | MUX_MODE0) /* spi1_cs0 */ - DRA7XX_CORE_IOPAD(0x37b8, PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs2.hdmi1_hpd */ - DRA7XX_CORE_IOPAD(0x37bc, PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs3.hdmi1_cec */ - >; - }; - - mcspi2_pins: pinmux_mcspi2_pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x37c0, PIN_INPUT | MUX_MODE0) /* spi2_sclk */ - DRA7XX_CORE_IOPAD(0x37c4, PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */ - DRA7XX_CORE_IOPAD(0x37c8, PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */ - DRA7XX_CORE_IOPAD(0x37cc, PIN_INPUT_SLEW | MUX_MODE0) /* spi2_cs0 */ - >; - }; - - uart1_pins: pinmux_uart1_pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x37e0, PIN_INPUT_SLEW | MUX_MODE0) /* uart1_rxd */ - DRA7XX_CORE_IOPAD(0x37e4, PIN_INPUT_SLEW | MUX_MODE0) /* uart1_txd */ - DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT | MUX_MODE3) /* uart1_ctsn */ - DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT | MUX_MODE3) /* uart1_rtsn */ - >; - }; - - uart2_pins: pinmux_uart2_pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT | MUX_MODE0) /* uart2_rxd */ - DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT | MUX_MODE0) /* uart2_txd */ - DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT | MUX_MODE0) /* uart2_ctsn */ - DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT | MUX_MODE0) /* uart2_rtsn */ - >; - }; - - uart3_pins: pinmux_uart3_pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3648, PIN_INPUT_SLEW | MUX_MODE0) /* uart3_rxd */ - DRA7XX_CORE_IOPAD(0x364c, PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */ - >; - }; - - usb1_pins: pinmux_usb1_pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3680, PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */ - >; - }; - - usb2_pins: pinmux_usb2_pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3684, PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */ - >; - }; - - nand_flash_x16: nand_flash_x16 { - /* On DRA7 EVM, GPMC_WPN and NAND_BOOTn comes from DIP switch - * So NAND flash requires following switch settings: - * SW5.1 (NAND_BOOTn) = ON (LOW) - * SW5.9 (GPMC_WPN) = OFF (HIGH) - */ - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3400, PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */ - DRA7XX_CORE_IOPAD(0x3404, PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */ - DRA7XX_CORE_IOPAD(0x3408, PIN_INPUT | MUX_MODE0) /* gpmc_ad2 */ - DRA7XX_CORE_IOPAD(0x340c, PIN_INPUT | MUX_MODE0) /* gpmc_ad3 */ - DRA7XX_CORE_IOPAD(0x3410, PIN_INPUT | MUX_MODE0) /* gpmc_ad4 */ - DRA7XX_CORE_IOPAD(0x3414, PIN_INPUT | MUX_MODE0) /* gpmc_ad5 */ - DRA7XX_CORE_IOPAD(0x3418, PIN_INPUT | MUX_MODE0) /* gpmc_ad6 */ - DRA7XX_CORE_IOPAD(0x341c, PIN_INPUT | MUX_MODE0) /* gpmc_ad7 */ - DRA7XX_CORE_IOPAD(0x3420, PIN_INPUT | MUX_MODE0) /* gpmc_ad8 */ - DRA7XX_CORE_IOPAD(0x3424, PIN_INPUT | MUX_MODE0) /* gpmc_ad9 */ - DRA7XX_CORE_IOPAD(0x3428, PIN_INPUT | MUX_MODE0) /* gpmc_ad10 */ - DRA7XX_CORE_IOPAD(0x342c, PIN_INPUT | MUX_MODE0) /* gpmc_ad11 */ - DRA7XX_CORE_IOPAD(0x3430, PIN_INPUT | MUX_MODE0) /* gpmc_ad12 */ - DRA7XX_CORE_IOPAD(0x3434, PIN_INPUT | MUX_MODE0) /* gpmc_ad13 */ - DRA7XX_CORE_IOPAD(0x3438, PIN_INPUT | MUX_MODE0) /* gpmc_ad14 */ - DRA7XX_CORE_IOPAD(0x343c, PIN_INPUT | MUX_MODE0) /* gpmc_ad15 */ - DRA7XX_CORE_IOPAD(0x34d8, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0 */ - DRA7XX_CORE_IOPAD(0x34cc, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */ - DRA7XX_CORE_IOPAD(0x34b4, PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_csn0 */ - DRA7XX_CORE_IOPAD(0x34c4, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */ - DRA7XX_CORE_IOPAD(0x34c8, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */ - DRA7XX_CORE_IOPAD(0x34d0, PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle */ - >; - }; - - cpsw_default: cpsw_default { - pinctrl-single,pins = < - /* Slave 1 */ - DRA7XX_CORE_IOPAD(0x3650, PIN_OUTPUT | MUX_MODE0) /* rgmii0_txc.rgmii0_txc */ - DRA7XX_CORE_IOPAD(0x3654, PIN_OUTPUT | MUX_MODE0) /* rgmii0_txctl.rgmii0_txctl */ - DRA7XX_CORE_IOPAD(0x3658, PIN_OUTPUT | MUX_MODE0) /* rgmii0_td3.rgmii0_txd3 */ - DRA7XX_CORE_IOPAD(0x365c, PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd2.rgmii0_txd2 */ - DRA7XX_CORE_IOPAD(0x3660, PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd1.rgmii0_txd1 */ - DRA7XX_CORE_IOPAD(0x3664, PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd0.rgmii0_txd0 */ - DRA7XX_CORE_IOPAD(0x3668, PIN_INPUT | MUX_MODE0) /* rgmii0_rxc.rgmii0_rxc */ - DRA7XX_CORE_IOPAD(0x366c, PIN_INPUT | MUX_MODE0) /* rgmii0_rxctl.rgmii0_rxctl */ - DRA7XX_CORE_IOPAD(0x3670, PIN_INPUT | MUX_MODE0) /* rgmii0_rxd3.rgmii0_rxd3 */ - DRA7XX_CORE_IOPAD(0x3674, PIN_INPUT | MUX_MODE0) /* rgmii0_rxd2.rgmii0_rxd2 */ - DRA7XX_CORE_IOPAD(0x3678, PIN_INPUT | MUX_MODE0) /* rgmii0_rxd1.rgmii0_rxd1 */ - DRA7XX_CORE_IOPAD(0x367c, PIN_INPUT | MUX_MODE0) /* rgmii0_rxd0.rgmii0_rxd0 */ - - /* Slave 2 */ - DRA7XX_CORE_IOPAD(0x3598, PIN_OUTPUT | MUX_MODE3) /* vin2a_d12.rgmii1_txc */ - DRA7XX_CORE_IOPAD(0x359c, PIN_OUTPUT | MUX_MODE3) /* vin2a_d13.rgmii1_tctl */ - DRA7XX_CORE_IOPAD(0x35a0, PIN_OUTPUT | MUX_MODE3) /* vin2a_d14.rgmii1_td3 */ - DRA7XX_CORE_IOPAD(0x35a4, PIN_OUTPUT | MUX_MODE3) /* vin2a_d15.rgmii1_td2 */ - DRA7XX_CORE_IOPAD(0x35a8, PIN_OUTPUT | MUX_MODE3) /* vin2a_d16.rgmii1_td1 */ - DRA7XX_CORE_IOPAD(0x35ac, PIN_OUTPUT | MUX_MODE3) /* vin2a_d17.rgmii1_td0 */ - DRA7XX_CORE_IOPAD(0x35b0, PIN_INPUT | MUX_MODE3) /* vin2a_d18.rgmii1_rclk */ - DRA7XX_CORE_IOPAD(0x35b4, PIN_INPUT | MUX_MODE3) /* vin2a_d19.rgmii1_rctl */ - DRA7XX_CORE_IOPAD(0x35b8, PIN_INPUT | MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */ - DRA7XX_CORE_IOPAD(0x35bc, PIN_INPUT | MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */ - DRA7XX_CORE_IOPAD(0x35c0, PIN_INPUT | MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */ - DRA7XX_CORE_IOPAD(0x35c4, PIN_INPUT | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */ - >; - - }; - - cpsw_sleep: cpsw_sleep { - pinctrl-single,pins = < - /* Slave 1 */ - DRA7XX_CORE_IOPAD(0x3650, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x3654, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x3658, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x365c, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x3660, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x3664, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x3668, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x366c, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x3670, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x3674, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x3678, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x367c, MUX_MODE15) - - /* Slave 2 */ - DRA7XX_CORE_IOPAD(0x3598, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x359c, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35a0, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35a4, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35a8, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35ac, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35b0, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35b4, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35b8, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35bc, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35c0, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35c4, MUX_MODE15) - >; - }; - - davinci_mdio_default: davinci_mdio_default { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x363c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_d.mdio_d */ - DRA7XX_CORE_IOPAD(0x3640, PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ - >; - }; - - davinci_mdio_sleep: davinci_mdio_sleep { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x363c, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x3640, MUX_MODE15) - >; - }; - dcan1_pins_default: dcan1_pins_default { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */ @@ -368,41 +170,39 @@ >; };
- atl_pins: pinmux_atl_pins { + mmc1_pins_default: mmc1_pins_default { pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3698, PIN_OUTPUT | MUX_MODE5) /* xref_clk1.atl_clk1 */ - DRA7XX_CORE_IOPAD(0x369c, PIN_OUTPUT | MUX_MODE5) /* xref_clk2.atl_clk2 */ + DRA7XX_CORE_IOPAD(0x376c, PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */ + DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ + DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ + DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ + DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ + DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ + DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ >; };
- mcasp3_pins: pinmux_mcasp3_pins { + mmc1_pins_sdr12: pinmux_mmc1_sdr12_pins { pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3724, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_aclkx */ - DRA7XX_CORE_IOPAD(0x3728, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_fsx */ - DRA7XX_CORE_IOPAD(0x372c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr0 */ - DRA7XX_CORE_IOPAD(0x3730, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr1 */ - >; - }; - - mcasp3_sleep_pins: pinmux_mcasp3_sleep_pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3724, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x3728, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x372c, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x3730, MUX_MODE15) + DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ + DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ + DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ + DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ + DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ + DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ >; }; };
&i2c1 { status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; clock-frequency = <400000>;
tps659038: tps659038@58 { compatible = "ti,tps659038"; reg = <0x58>; + ti,palmas-override-powerhold; + ti,system-power-controller;
tps659038_pmic { compatible = "ti,tps659038-pmic"; @@ -587,8 +387,6 @@
&i2c2 { status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; clock-frequency = <400000>;
pcf_hdmi: gpio@26 { @@ -608,41 +406,29 @@
&i2c3 { status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_pins>; clock-frequency = <400000>; };
&mcspi1 { status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mcspi1_pins>; };
&mcspi2 { status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mcspi2_pins>; };
&uart1 { status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, <&dra7_pmx_core 0x3e0>; };
&uart2 { status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; };
&uart3 { status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; };
&mmc1 { @@ -738,14 +524,10 @@
&usb1 { dr_mode = "peripheral"; - pinctrl-names = "default"; - pinctrl-0 = <&usb1_pins>; };
&usb2 { dr_mode = "host"; - pinctrl-names = "default"; - pinctrl-0 = <&usb2_pins>; };
&elm { @@ -753,9 +535,12 @@ };
&gpmc { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&nand_flash_x16>; + /* + * For the existing IOdelay configuration via U-Boot we don't + * support NAND on dra7-evm. Keep it disabled. Enabling it + * requires a different configuration by U-Boot. + */ + status = "disabled"; ranges = <0 0 0x08000000 0x01000000>; /* minimum GPMC partition = 16MB */ nand@0,0 { compatible = "ti,omap2-nand"; @@ -851,9 +636,6 @@
&mac { status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&cpsw_default>; - pinctrl-1 = <&cpsw_sleep>; dual_emac; };
@@ -869,12 +651,6 @@ dual_emac_res_vlan = <2>; };
-&davinci_mdio { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&davinci_mdio_default>; - pinctrl-1 = <&davinci_mdio_sleep>; -}; - &dcan1 { status = "ok"; pinctrl-names = "default", "sleep", "active"; @@ -884,9 +660,6 @@ };
&atl { - pinctrl-names = "default"; - pinctrl-0 = <&atl_pins>; - assigned-clocks = <&abe_dpll_sys_clk_mux>, <&atl_gfclk_mux>, <&dpll_abe_ck>, @@ -905,9 +678,6 @@
&mcasp3 { #sound-dai-cells = <0>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&mcasp3_pins>; - pinctrl-1 = <&mcasp3_sleep_pins>;
assigned-clocks = <&mcasp3_ahclkx_mux>; assigned-clock-parents = <&atl_clkin2_ck>;
On Sat, Aug 12, 2017 at 11:59:32AM +0530, Lokesh Vutla wrote:
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com
arch/arm/dts/dra7-evm.dts | 276 ++++------------------------------------------ 1 file changed, 23 insertions(+), 253 deletions(-)
Please include a commit message to say what rev we're syncing with, and we should probably cover dra7* while we're at it (and first move anything U-Boot centric to a -u-boot.dtsi so this goes cleaner in the future, if we're not there already). Thanks!
On Tuesday 15 August 2017 02:58 AM, Tom Rini wrote:
On Sat, Aug 12, 2017 at 11:59:32AM +0530, Lokesh Vutla wrote:
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com
arch/arm/dts/dra7-evm.dts | 276 ++++------------------------------------------ 1 file changed, 23 insertions(+), 253 deletions(-)
Please include a commit message to say what rev we're syncing with, and we should probably cover dra7* while we're at it (and first move anything U-Boot centric to a -u-boot.dtsi so this goes cleaner in the future, if we're not there already). Thanks!
Sure, Ill take care of this in v2.
Thanks and regards, Lokesh
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- arch/arm/dts/Makefile | 2 +- arch/arm/dts/dra7-evm-common.dtsi | 259 +++++++++++++++++++++++ arch/arm/dts/dra7-evm.dts | 271 ++---------------------- arch/arm/dts/dra76-evm.dts | 423 ++++++++++++++++++++++++++++++++++++++ arch/arm/dts/dra76x.dtsi | 19 ++ board/ti/dra7xx/evm.c | 4 +- configs/dra7xx_evm_defconfig | 2 +- configs/dra7xx_hs_evm_defconfig | 2 +- 8 files changed, 723 insertions(+), 259 deletions(-) create mode 100644 arch/arm/dts/dra7-evm-common.dtsi create mode 100644 arch/arm/dts/dra76-evm.dts create mode 100644 arch/arm/dts/dra76x.dtsi
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index c2dc240edf..67f4bffefd 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -174,7 +174,7 @@ dtb-$(CONFIG_ARCH_SOCFPGA) += \ socfpga_cyclone5_vining_fpga.dtb
dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb \ - dra72-evm-revc.dtb dra71-evm.dtb + dra72-evm-revc.dtb dra71-evm.dtb dra76-evm.dtb dtb-$(CONFIG_TARGET_AM57XX_EVM) += am57xx-beagle-x15.dtb \ am57xx-beagle-x15-revb1.dtb \ am572x-idk.dtb \ diff --git a/arch/arm/dts/dra7-evm-common.dtsi b/arch/arm/dts/dra7-evm-common.dtsi new file mode 100644 index 0000000000..9a4314b5ef --- /dev/null +++ b/arch/arm/dts/dra7-evm-common.dtsi @@ -0,0 +1,259 @@ +/* + * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/clk/ti-dra7-atl.h> +#include <dt-bindings/input/input.h> + +/ { + chosen { + stdout-path = &uart1; + tick-timer = &timer2; + }; + + extcon_usb1: extcon_usb1 { + compatible = "linux,extcon-usb-gpio"; + id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>; + }; + + sound0: sound0 { + compatible = "simple-audio-card"; + simple-audio-card,name = "DRA7xx-EVM"; + simple-audio-card,widgets = + "Headphone", "Headphone Jack", + "Line", "Line Out", + "Microphone", "Mic Jack", + "Line", "Line In"; + simple-audio-card,routing = + "Headphone Jack", "HPLOUT", + "Headphone Jack", "HPROUT", + "Line Out", "LLOUT", + "Line Out", "RLOUT", + "MIC3L", "Mic Jack", + "MIC3R", "Mic Jack", + "Mic Jack", "Mic Bias", + "LINE1L", "Line In", + "LINE1R", "Line In"; + simple-audio-card,format = "dsp_b"; + simple-audio-card,bitclock-master = <&sound0_master>; + simple-audio-card,frame-master = <&sound0_master>; + simple-audio-card,bitclock-inversion; + + sound0_master: simple-audio-card,cpu { + sound-dai = <&mcasp3>; + system-clock-frequency = <5644800>; + }; + + simple-audio-card,codec { + sound-dai = <&tlv320aic3106>; + clocks = <&atl_clkin2_ck>; + }; + }; + + leds { + compatible = "gpio-leds"; + led0 { + label = "dra7:usr1"; + gpios = <&pcf_lcd 4 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led1 { + label = "dra7:usr2"; + gpios = <&pcf_lcd 5 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led2 { + label = "dra7:usr3"; + gpios = <&pcf_lcd 6 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led3 { + label = "dra7:usr4"; + gpios = <&pcf_lcd 7 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + autorepeat; + + USER1 { + label = "btnUser1"; + linux,code = <BTN_0>; + gpios = <&pcf_lcd 2 GPIO_ACTIVE_LOW>; + }; + + USER2 { + label = "btnUser2"; + linux,code = <BTN_1>; + gpios = <&pcf_lcd 3 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&i2c3 { + status = "okay"; + clock-frequency = <400000>; +}; + +&mcspi1 { + status = "okay"; +}; + +&mcspi2 { + status = "okay"; +}; + +&uart1 { + status = "okay"; + interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, + <&dra7_pmx_core 0x3e0>; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&qspi { + status = "okay"; + + spi-max-frequency = <76800000>; + m25p80@0 { + compatible = "s25fl256s1", "spi-flash"; + spi-max-frequency = <76800000>; + reg = <0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + #address-cells = <1>; + #size-cells = <1>; + + /* MTD partition table. + * The ROM checks the first four physical blocks + * for a valid file to boot and the flash here is + * 64KiB block size. + */ + partition@0 { + label = "QSPI.SPL"; + reg = <0x00000000 0x000010000>; + }; + partition@1 { + label = "QSPI.SPL.backup1"; + reg = <0x00010000 0x00010000>; + }; + partition@2 { + label = "QSPI.SPL.backup2"; + reg = <0x00020000 0x00010000>; + }; + partition@3 { + label = "QSPI.SPL.backup3"; + reg = <0x00030000 0x00010000>; + }; + partition@4 { + label = "QSPI.u-boot"; + reg = <0x00040000 0x00100000>; + }; + partition@5 { + label = "QSPI.u-boot-spl-os"; + reg = <0x00140000 0x00080000>; + }; + partition@6 { + label = "QSPI.u-boot-env"; + reg = <0x001c0000 0x00010000>; + }; + partition@7 { + label = "QSPI.u-boot-env.backup1"; + reg = <0x001d0000 0x0010000>; + }; + partition@8 { + label = "QSPI.kernel"; + reg = <0x001e0000 0x0800000>; + }; + partition@9 { + label = "QSPI.file-system"; + reg = <0x009e0000 0x01620000>; + }; + }; +}; + +&omap_dwc3_1 { + extcon = <&extcon_usb1>; +}; + +&usb1 { + dr_mode = "otg"; + extcon = <&extcon_usb1>; +}; + +&usb2 { + dr_mode = "host"; +}; + +&atl { + assigned-clocks = <&abe_dpll_sys_clk_mux>, + <&atl_gfclk_mux>, + <&dpll_abe_ck>, + <&dpll_abe_m2x2_ck>, + <&atl_clkin2_ck>; + assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>; + assigned-clock-rates = <0>, <0>, <180633600>, <361267200>, <5644800>; + + status = "okay"; + + atl2 { + bws = <DRA7_ATL_WS_MCASP2_FSX>; + aws = <DRA7_ATL_WS_MCASP3_FSX>; + }; +}; + +&mcasp3 { + #sound-dai-cells = <0>; + + assigned-clocks = <&mcasp3_ahclkx_mux>; + assigned-clock-parents = <&atl_clkin2_ck>; + + status = "okay"; + + op-mode = <0>; /* MCASP_IIS_MODE */ + tdm-slots = <2>; + /* 4 serializer */ + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ + 1 2 0 0 + >; + tx-num-evt = <32>; + rx-num-evt = <32>; +}; + +&mailbox5 { + status = "okay"; + mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { + status = "okay"; + }; + mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { + status = "okay"; + }; +}; + +&mailbox6 { + status = "okay"; + mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { + status = "okay"; + }; + mbox_dsp2_ipc3x: mbox_dsp2_ipc3x { + status = "okay"; + }; +}; diff --git a/arch/arm/dts/dra7-evm.dts b/arch/arm/dts/dra7-evm.dts index 511862c5f3..c3009bda62 100644 --- a/arch/arm/dts/dra7-evm.dts +++ b/arch/arm/dts/dra7-evm.dts @@ -8,19 +8,12 @@ /dts-v1/;
#include "dra74x.dtsi" -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/clk/ti-dra7-atl.h> -#include <dt-bindings/input/input.h> +#include "dra7-evm-common.dtsi"
/ { model = "TI DRA742"; compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7";
- chosen { - stdout-path = &uart1; - tick-timer = &timer2; - }; - memory@0 { device_type = "memory"; reg = <0x0 0x80000000 0x0 0x60000000>; /* 1536 MB */ @@ -52,11 +45,6 @@ regulator-max-microvolt = <1800000>; };
- extcon_usb1: extcon_usb1 { - compatible = "linux,extcon-usb-gpio"; - id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>; - }; - extcon_usb2: extcon_usb2 { compatible = "linux,extcon-usb-gpio"; id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>; @@ -74,85 +62,6 @@ gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>; };
- sound0: sound0 { - compatible = "simple-audio-card"; - simple-audio-card,name = "DRA7xx-EVM"; - simple-audio-card,widgets = - "Headphone", "Headphone Jack", - "Line", "Line Out", - "Microphone", "Mic Jack", - "Line", "Line In"; - simple-audio-card,routing = - "Headphone Jack", "HPLOUT", - "Headphone Jack", "HPROUT", - "Line Out", "LLOUT", - "Line Out", "RLOUT", - "MIC3L", "Mic Jack", - "MIC3R", "Mic Jack", - "Mic Jack", "Mic Bias", - "LINE1L", "Line In", - "LINE1R", "Line In"; - simple-audio-card,format = "dsp_b"; - simple-audio-card,bitclock-master = <&sound0_master>; - simple-audio-card,frame-master = <&sound0_master>; - simple-audio-card,bitclock-inversion; - - sound0_master: simple-audio-card,cpu { - sound-dai = <&mcasp3>; - system-clock-frequency = <5644800>; - }; - - simple-audio-card,codec { - sound-dai = <&tlv320aic3106>; - clocks = <&atl_clkin2_ck>; - }; - }; - - leds { - compatible = "gpio-leds"; - led0 { - label = "dra7:usr1"; - gpios = <&pcf_lcd 4 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led1 { - label = "dra7:usr2"; - gpios = <&pcf_lcd 5 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led2 { - label = "dra7:usr3"; - gpios = <&pcf_lcd 6 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led3 { - label = "dra7:usr4"; - gpios = <&pcf_lcd 7 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - autorepeat; - - USER1 { - label = "btnUser1"; - linux,code = <BTN_0>; - gpios = <&pcf_lcd 2 GPIO_ACTIVE_LOW>; - }; - - USER2 { - label = "btnUser2"; - linux,code = <BTN_1>; - gpios = <&pcf_lcd 3 GPIO_ACTIVE_LOW>; - }; - }; };
&dra7_pmx_core { @@ -182,14 +91,18 @@ >; };
- mmc1_pins_sdr12: pinmux_mmc1_sdr12_pins { + mmc2_pins_default: mmc2_pins_default { pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ - DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ - DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ - DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ - DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ - DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ + DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ + DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ + DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ + DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ + DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ + DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ + DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ + DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ + DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ + DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ >; }; }; @@ -366,7 +279,6 @@ interrupts = <11 IRQ_TYPE_EDGE_FALLING>; interrupt-controller; #interrupt-cells = <2>; - u-boot,i2c-offset-len = <0>; };
tlv320aic3106: tlv320aic3106@19 { @@ -404,35 +316,10 @@ }; };
-&i2c3 { - status = "okay"; - clock-frequency = <400000>; -}; - -&mcspi1 { - status = "okay"; -}; - -&mcspi2 { - status = "okay"; -}; - -&uart1 { - status = "okay"; - interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, - <&dra7_pmx_core 0x3e0>; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - &mmc1 { status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins_default>; vmmc-supply = <&evm_3v3_sd>; vmmc_aux-supply = <&ldo1_reg>; bus-width = <4>; @@ -445,6 +332,8 @@
&mmc2 { status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins_default>; vmmc-supply = <&evm_3v3_sw>; bus-width = <8>; }; @@ -453,83 +342,10 @@ cpu0-supply = <&smps123_reg>; };
-&qspi { - status = "okay"; - - spi-max-frequency = <76800000>; - m25p80@0 { - compatible = "s25fl256s1", "spi-flash"; - spi-max-frequency = <76800000>; - reg = <0>; - spi-tx-bus-width = <1>; - spi-rx-bus-width = <4>; - #address-cells = <1>; - #size-cells = <1>; - - /* MTD partition table. - * The ROM checks the first four physical blocks - * for a valid file to boot and the flash here is - * 64KiB block size. - */ - partition@0 { - label = "QSPI.SPL"; - reg = <0x00000000 0x000010000>; - }; - partition@1 { - label = "QSPI.SPL.backup1"; - reg = <0x00010000 0x00010000>; - }; - partition@2 { - label = "QSPI.SPL.backup2"; - reg = <0x00020000 0x00010000>; - }; - partition@3 { - label = "QSPI.SPL.backup3"; - reg = <0x00030000 0x00010000>; - }; - partition@4 { - label = "QSPI.u-boot"; - reg = <0x00040000 0x00100000>; - }; - partition@5 { - label = "QSPI.u-boot-spl-os"; - reg = <0x00140000 0x00080000>; - }; - partition@6 { - label = "QSPI.u-boot-env"; - reg = <0x001c0000 0x00010000>; - }; - partition@7 { - label = "QSPI.u-boot-env.backup1"; - reg = <0x001d0000 0x0010000>; - }; - partition@8 { - label = "QSPI.kernel"; - reg = <0x001e0000 0x0800000>; - }; - partition@9 { - label = "QSPI.file-system"; - reg = <0x009e0000 0x01620000>; - }; - }; -}; - -&omap_dwc3_1 { - extcon = <&extcon_usb1>; -}; - &omap_dwc3_2 { extcon = <&extcon_usb2>; };
-&usb1 { - dr_mode = "peripheral"; -}; - -&usb2 { - dr_mode = "host"; -}; - &elm { status = "okay"; }; @@ -658,58 +474,3 @@ pinctrl-1 = <&dcan1_pins_sleep>; pinctrl-2 = <&dcan1_pins_default>; }; - -&atl { - assigned-clocks = <&abe_dpll_sys_clk_mux>, - <&atl_gfclk_mux>, - <&dpll_abe_ck>, - <&dpll_abe_m2x2_ck>, - <&atl_clkin2_ck>; - assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>; - assigned-clock-rates = <0>, <0>, <180633600>, <361267200>, <5644800>; - - status = "okay"; - - atl2 { - bws = <DRA7_ATL_WS_MCASP2_FSX>; - aws = <DRA7_ATL_WS_MCASP3_FSX>; - }; -}; - -&mcasp3 { - #sound-dai-cells = <0>; - - assigned-clocks = <&mcasp3_ahclkx_mux>; - assigned-clock-parents = <&atl_clkin2_ck>; - - status = "okay"; - - op-mode = <0>; /* MCASP_IIS_MODE */ - tdm-slots = <2>; - /* 4 serializer */ - serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ - 1 2 0 0 - >; - tx-num-evt = <32>; - rx-num-evt = <32>; -}; - -&mailbox5 { - status = "okay"; - mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { - status = "okay"; - }; - mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { - status = "okay"; - }; -}; - -&mailbox6 { - status = "okay"; - mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { - status = "okay"; - }; - mbox_dsp2_ipc3x: mbox_dsp2_ipc3x { - status = "okay"; - }; -}; diff --git a/arch/arm/dts/dra76-evm.dts b/arch/arm/dts/dra76-evm.dts new file mode 100644 index 0000000000..0f8b983e66 --- /dev/null +++ b/arch/arm/dts/dra76-evm.dts @@ -0,0 +1,423 @@ +/* + * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +#include "dra76x.dtsi" +#include "dra7-evm-common.dtsi" +#include <dt-bindings/net/ti-dp83867.h> + +/ { + model = "TI DRA762 EVM"; + compatible = "ti,dra76-evm", "ti,dra762", "ti,dra7"; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x80000000>; + }; + + vsys_12v0: fixedregulator-vsys12v0 { + /* main supply */ + compatible = "regulator-fixed"; + regulator-name = "vsys_12v0"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; + regulator-boot-on; + }; + + vsys_5v0: fixedregulator-vsys5v0 { + /* Output of Cntlr B of TPS43351-Q1 on dra76-evm */ + compatible = "regulator-fixed"; + regulator-name = "vsys_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vsys_12v0>; + regulator-always-on; + regulator-boot-on; + }; + + vsys_3v3: fixedregulator-vsys3v3 { + /* Output of Cntlr A of TPS43351-Q1 on dra76-evm */ + compatible = "regulator-fixed"; + regulator-name = "vsys_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vsys_12v0>; + regulator-always-on; + regulator-boot-on; + }; + + vio_3v3: fixedregulator-vio_3v3 { + compatible = "regulator-fixed"; + regulator-name = "vio_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vsys_3v3>; + regulator-always-on; + regulator-boot-on; + }; + + vio_3v3_sd: fixedregulator-sd { + compatible = "regulator-fixed"; + regulator-name = "vio_3v3_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vio_3v3>; + enable-active-high; + gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; + }; + + vio_1v8: fixedregulator-vio_1v8 { + compatible = "regulator-fixed"; + regulator-name = "vio_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&smps5_reg>; + }; + + vtt_fixed: fixedregulator-vtt { + compatible = "regulator-fixed"; + regulator-name = "vtt_fixed"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + vin-supply = <&vsys_3v3>; + regulator-always-on; + regulator-boot-on; + }; + + aic_dvdd: fixedregulator-aic_dvdd { + /* TPS77018DBVT */ + compatible = "regulator-fixed"; + regulator-name = "aic_dvdd"; + vin-supply = <&vio_3v3>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; +}; + +&dra7_pmx_core { + mmc1_pins_default: mmc1_pins_default { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x376c, PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */ + DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ + DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ + DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ + DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ + DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ + DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ + >; + }; + + mmc1_pins_sdr12: pinmux_mmc1_sdr12_pins { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ + DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ + DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ + DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ + DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ + DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ + >; + }; + + mmc2_pins_default: mmc2_pins_default { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ + DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ + DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ + DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ + DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ + DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ + DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ + DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ + DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ + DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ + >; + }; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <400000>; + + tps65917: tps65917@58 { + compatible = "ti,tps65917"; + reg = <0x58>; + ti,system-power-controller; + interrupt-controller; + #interrupt-cells = <2>; + + tps65917_pmic { + compatible = "ti,tps65917-pmic"; + + smps12-in-supply = <&vsys_3v3>; + smps3-in-supply = <&vsys_3v3>; + smps4-in-supply = <&vsys_3v3>; + smps5-in-supply = <&vsys_3v3>; + ldo1-in-supply = <&vsys_3v3>; + ldo2-in-supply = <&vsys_3v3>; + ldo3-in-supply = <&vsys_5v0>; + ldo4-in-supply = <&vsys_5v0>; + ldo5-in-supply = <&vsys_3v3>; + + tps65917_regulators: regulators { + smps12_reg: smps12 { + /* VDD_DSPEVE */ + regulator-name = "smps12"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1250000>; + regulator-always-on; + regulator-boot-on; + }; + + smps3_reg: smps3 { + /* VDD_CORE */ + regulator-name = "smps3"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1250000>; + regulator-boot-on; + regulator-always-on; + }; + + smps4_reg: smps4 { + /* VDD_IVA */ + regulator-name = "smps4"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1250000>; + regulator-always-on; + regulator-boot-on; + }; + + smps5_reg: smps5 { + /* VDDS1V8 */ + regulator-name = "smps5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: ldo1 { + /* LDO1_OUT --> VDA_PHY1_1V8 */ + regulator-name = "ldo1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-allow-bypass; + }; + + ldo2_reg: ldo2 { + /* LDO2_OUT --> VDA_PHY2_1V8 */ + regulator-name = "ldo2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-allow-bypass; + regulator-always-on; + }; + + ldo3_reg: ldo3 { + /* VDA_USB_3V3 */ + regulator-name = "ldo3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5_reg: ldo5 { + /* VDDA_1V8_PLL */ + regulator-name = "ldo5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo4_reg: ldo4 { + /* VDD_SDIO_DV */ + regulator-name = "ldo4"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + tps65917_power_button { + compatible = "ti,palmas-pwrbutton"; + interrupt-parent = <&tps65917>; + interrupts = <1 IRQ_TYPE_NONE>; + wakeup-source; + ti,palmas-long-press-seconds = <6>; + }; + }; + + lp87565: lp87565@60 { + compatible = "ti,lp87565-q1"; + reg = <0x60>; + + buck10-in-supply =<&vsys_3v3>; + buck23-in-supply =<&vsys_3v3>; + + regulators: regulators { + buck10_reg: buck10 { + /*VDD_MPU*/ + regulator-name = "buck10"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1250000>; + regulator-always-on; + regulator-boot-on; + }; + + buck23_reg: buck23 { + /* VDD_GPU*/ + regulator-name = "buck23"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1250000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + pcf_lcd: pcf8757@20 { + compatible = "ti,pcf8575", "nxp,pcf8575"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_EDGE_FALLING>; + }; + + pcf_gpio_21: pcf8757@21 { + compatible = "ti,pcf8575", "nxp,pcf8575"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pcf_hdmi: pcf8575@26 { + compatible = "ti,pcf8575", "nxp,pcf8575"; + reg = <0x26>; + gpio-controller; + #gpio-cells = <2>; + p1 { + /* vin6_sel_s0: high: VIN6, low: audio */ + gpio-hog; + gpios = <1 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "vin6_sel_s0"; + }; + }; + + tlv320aic3106: tlv320aic3106@19 { + #sound-dai-cells = <0>; + compatible = "ti,tlv320aic3106"; + reg = <0x19>; + adc-settle-ms = <40>; + ai3x-micbias-vg = <1>; /* 2.0V */ + status = "okay"; + + /* Regulators */ + AVDD-supply = <&vio_3v3>; + IOVDD-supply = <&vio_3v3>; + DRVDD-supply = <&vio_3v3>; + DVDD-supply = <&aic_dvdd>; + }; +}; + +&cpu0 { + vdd-supply = <&buck10_reg>; +}; + +&mmc1 { + status = "okay"; + vmmc-supply = <&vio_3v3_sd>; + vmmc_aux-supply = <&ldo4_reg>; + bus-width = <4>; + /* + * SDCD signal is not being used here - using the fact that GPIO mode + * is always hardwired. + */ + cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins_default>; +}; + +&mmc2 { + status = "okay"; + vmmc-supply = <&vio_1v8>; + bus-width = <8>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins_default>; +}; + +/* No RTC on this device */ +&rtc { + status = "disabled"; +}; + +&mac { + status = "okay"; + + dual_emac; +}; + +&cpsw_emac0 { + phy-handle = <&dp83867_0>; + phy-mode = "rgmii-id"; + dual_emac_res_vlan = <1>; +}; + +&cpsw_emac1 { + phy-handle = <&dp83867_1>; + phy-mode = "rgmii-id"; + dual_emac_res_vlan = <2>; +}; + +&davinci_mdio { + dp83867_0: ethernet-phy@2 { + reg = <2>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; + ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>; + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>; + ti,min-output-impedance; + ti,dp83867-rxctrl-strap-quirk; + }; + + dp83867_1: ethernet-phy@3 { + reg = <3>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; + ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>; + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>; + ti,min-output-impedance; + ti,dp83867-rxctrl-strap-quirk; + }; +}; + +&usb2_phy1 { + phy-supply = <&ldo3_reg>; +}; + +&usb2_phy2 { + phy-supply = <&ldo3_reg>; +}; + +&qspi { + spi-max-frequency = <96000000>; + m25p80@0 { + spi-max-frequency = <96000000>; + }; +}; diff --git a/arch/arm/dts/dra76x.dtsi b/arch/arm/dts/dra76x.dtsi new file mode 100644 index 0000000000..1c88c581ff --- /dev/null +++ b/arch/arm/dts/dra76x.dtsi @@ -0,0 +1,19 @@ +/* + * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "dra74x.dtsi" + +/ { + compatible = "ti,dra762", "ti,dra7"; + +}; + +/* MCAN interrupts are hard-wired to irqs 67, 68 */ +&crossbar_mpu { + ti,irqs-skip = <10 67 68 133 139 140>; +}; diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index 14c06f5eda..c57ce3b3ac 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -1116,7 +1116,9 @@ int board_fit_config_name_match(const char *name) } else if (!strcmp(name, "dra72-evm")) { return 0; } - } else if (!is_dra72x() && !strcmp(name, "dra7-evm")) { + } else if (is_dra76x() && !strcmp(name, "dra76-evm")) { + return 0; + } else if (!is_dra72x() && !is_dra76x() && !strcmp(name, "dra7-evm")) { return 0; }
diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig index c151f49e30..f74328e3d6 100644 --- a/configs/dra7xx_evm_defconfig +++ b/configs/dra7xx_evm_defconfig @@ -37,7 +37,7 @@ CONFIG_FASTBOOT_FLASH_MMC_DEV=1 CONFIG_ISO_PARTITION=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_LIST="dra7-evm dra72-evm dra72-evm-revc dra71-evm" +CONFIG_OF_LIST="dra7-evm dra72-evm dra72-evm-revc dra71-evm dra76-evm" CONFIG_DM=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y diff --git a/configs/dra7xx_hs_evm_defconfig b/configs/dra7xx_hs_evm_defconfig index dba9f06bd6..0f25b25e2c 100644 --- a/configs/dra7xx_hs_evm_defconfig +++ b/configs/dra7xx_hs_evm_defconfig @@ -42,7 +42,7 @@ CONFIG_FASTBOOT_FLASH_MMC_DEV=1 CONFIG_ISO_PARTITION=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_LIST="dra7-evm dra72-evm dra72-evm-revc dra71-evm" +CONFIG_OF_LIST="dra7-evm dra72-evm dra72-evm-revc dra71-evm dra76-evm" CONFIG_DM=y CONFIG_SPL_DM=y CONFIG_REGMAP=y
On Sat, Aug 12, 2017 at 11:59:33AM +0530, Lokesh Vutla wrote:
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com
arch/arm/dts/Makefile | 2 +- arch/arm/dts/dra7-evm-common.dtsi | 259 +++++++++++++++++++++++ arch/arm/dts/dra7-evm.dts | 271 ++---------------------- arch/arm/dts/dra76-evm.dts | 423 ++++++++++++++++++++++++++++++++++++++ arch/arm/dts/dra76x.dtsi | 19 ++ board/ti/dra7xx/evm.c | 4 +- configs/dra7xx_evm_defconfig | 2 +- configs/dra7xx_hs_evm_defconfig | 2 +- 8 files changed, 723 insertions(+), 259 deletions(-) create mode 100644 arch/arm/dts/dra7-evm-common.dtsi create mode 100644 arch/arm/dts/dra76-evm.dts create mode 100644 arch/arm/dts/dra76x.dtsi
Some of these syncs should be in the previous patch, please have a commit message, and if the skeleton of dra76-evm.dts isn't upstream just yet, have you submitted it? Thanks!
participants (2)
-
Lokesh Vutla -
Tom Rini