This function is called from outside the driver. It should be placed into common SoC code. Move it.

Also rename the driver symbol to be more consistent with the other rockchip clock drivers.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v2: None

arch/arm/include/asm/arch-rockchip/cru_rk3399.h | 6 +++++ arch/arm/mach-rockchip/rk3399/Makefile | 1 + arch/arm/mach-rockchip/rk3399/clk_rk3399.c | 33 +++++++++++++++++++++++++ drivers/clk/rockchip/clk_rk3399.c | 24 +----------------- 4 files changed, 41 insertions(+), 23 deletions(-) create mode 100644 arch/arm/mach-rockchip/rk3399/clk_rk3399.c

diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3399.h b/arch/arm/include/asm/arch-rockchip/cru_rk3399.h index 6776e48..98fba2b 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rk3399.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3399.h @@ -9,6 +9,12 @@

#include <common.h>

+/* Private data for the clock driver - used by rockchip_get_cru() */ +struct rk3399_clk_priv { + struct rk3399_cru *cru; + ulong rate; +}; + struct rk3399_pmucru { u32 ppll_con[6]; u32 reserved[0x1a]; diff --git a/arch/arm/mach-rockchip/rk3399/Makefile b/arch/arm/mach-rockchip/rk3399/Makefile index 607f9c9..98ebeac 100644 --- a/arch/arm/mach-rockchip/rk3399/Makefile +++ b/arch/arm/mach-rockchip/rk3399/Makefile @@ -4,5 +4,6 @@ # SPDX-License-Identifier: GPL-2.0+ #

+obj-y += clk_rk3399.o obj-y += rk3399.o obj-y += syscon_rk3399.o diff --git a/arch/arm/mach-rockchip/rk3399/clk_rk3399.c b/arch/arm/mach-rockchip/rk3399/clk_rk3399.c new file mode 100644 index 0000000..7663591 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3399/clk_rk3399.c @@ -0,0 +1,33 @@ +/* + * Copyright (C) 2016 Google, Inc + * Written by Simon Glass sjg@chromium.org + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <syscon.h> +#include <asm/arch/clock.h> +#include <asm/arch/cru_rk3399.h> + +int rockchip_get_clk(struct udevice **devp) +{ + return uclass_get_device_by_driver(UCLASS_CLK, + DM_GET_DRIVER(rockchip_rk3399_pmuclk), devp); +} + +void *rockchip_get_cru(void) +{ + struct rk3399_clk_priv *priv; + struct udevice *dev; + int ret; + + ret = rockchip_get_clk(&dev); + if (ret) + return ERR_PTR(ret); + + priv = dev_get_priv(dev); + + return priv->cru; +} diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index ea0ce2a..2e87e4b 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -18,11 +18,6 @@

DECLARE_GLOBAL_DATA_PTR;

-struct rk3399_clk_priv { - struct rk3399_cru *cru; - ulong rate; -}; - struct rk3399_pmuclk_priv { struct rk3399_pmucru *pmucru; }; @@ -780,23 +775,6 @@ static struct clk_ops rk3399_clk_ops = { .set_rate = rk3399_clk_set_rate, };

-void *rockchip_get_cru(void) -{ - struct udevice *dev; - fdt_addr_t *addr; - int ret; - - ret = uclass_get_device_by_name(UCLASS_CLK, "clk_rk3399", &dev); - if (ret) - return ERR_PTR(ret); - - addr = dev_get_addr_ptr(dev); - if ((fdt_addr_t)addr == FDT_ADDR_T_NONE) - return ERR_PTR(-EINVAL); - - return addr; -} - static int rk3399_clk_probe(struct udevice *dev) { struct rk3399_clk_priv *priv = dev_get_priv(dev); @@ -990,7 +968,7 @@ static const struct udevice_id rk3399_pmuclk_ids[] = { { } };

-U_BOOT_DRIVER(pmuclk_rk3399) = { +U_BOOT_DRIVER(rockchip_rk3399_pmuclk) = { .name = "pmuclk_rk3399", .id = UCLASS_CLK, .of_match = rk3399_pmuclk_ids,

Hi Simon,

On 10/02/2016 10:04 AM, Simon Glass wrote:

This function is called from outside the driver. It should be placed into common SoC code. Move it.

Also rename the driver symbol to be more consistent with the other rockchip clock drivers.

Signed-off-by: Simon Glass sjg@chromium.org

Changes in v2: None

arch/arm/include/asm/arch-rockchip/cru_rk3036.h | 6 +++++ arch/arm/mach-rockchip/rk3036/Makefile | 2 ++ arch/arm/mach-rockchip/rk3036/clk_rk3036.c | 33 +++++++++++++++++++++++++ drivers/clk/rockchip/clk_rk3036.c | 24 +----------------- 4 files changed, 42 insertions(+), 23 deletions(-) create mode 100644 arch/arm/mach-rockchip/rk3036/clk_rk3036.c

diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3036.h b/arch/arm/include/asm/arch-rockchip/cru_rk3036.h index 7ecc8ee..aaef4b9 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rk3036.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3036.h @@ -24,6 +24,12 @@ #define PERI_HCLK_HZ 148500000 #define PERI_PCLK_HZ 74250000

+/* Private data for the clock driver - used by rockchip_get_cru() */ +struct rk3036_clk_priv {

• struct rk3036_cru *cru;
• ulong rate;

+};

• struct rk3036_cru { struct rk3036_pll { unsigned int con0;

diff --git a/arch/arm/mach-rockchip/rk3036/Makefile b/arch/arm/mach-rockchip/rk3036/Makefile index 916a7a4..20d28f7 100644 --- a/arch/arm/mach-rockchip/rk3036/Makefile +++ b/arch/arm/mach-rockchip/rk3036/Makefile @@ -4,6 +4,8 @@ # SPDX-License-Identifier: GPL-2.0+ #

+obj-y += clk_rk3036.o

• ifndef CONFIG_SPL_BUILD obj-y += syscon_rk3036.o endif

diff --git a/arch/arm/mach-rockchip/rk3036/clk_rk3036.c b/arch/arm/mach-rockchip/rk3036/clk_rk3036.c new file mode 100644 index 0000000..6a06afb --- /dev/null +++ b/arch/arm/mach-rockchip/rk3036/clk_rk3036.c @@ -0,0 +1,33 @@ +/*

• • Copyright (C) 2016 Google, Inc
• • Written by Simon Glass sjg@chromium.org
• • SPDX-License-Identifier: GPL-2.0+
• */

+#include <common.h> +#include <dm.h> +#include <syscon.h> +#include <asm/arch/clock.h> +#include <asm/arch/cru_rk3036.h>

+int rockchip_get_clk(struct udevice **devp) +{

• return uclass_get_device_by_driver(UCLASS_CLK,

• 	DM_GET_DRIVER(rockchip_rk3036_cru), devp);
  

+}

+void *rockchip_get_cru(void) +{

• struct rk3036_clk_priv *priv;
• struct udevice *dev;
• int ret;
• ret = rockchip_get_clk(&dev);
• if (ret)

• return ERR_PTR(ret);
  

• priv = dev_get_priv(dev);
• return priv->cru;

+} diff --git a/drivers/clk/rockchip/clk_rk3036.c b/drivers/clk/rockchip/clk_rk3036.c index 8899b0c..7e3bf96 100644 --- a/drivers/clk/rockchip/clk_rk3036.c +++ b/drivers/clk/rockchip/clk_rk3036.c @@ -19,11 +19,6 @@

DECLARE_GLOBAL_DATA_PTR;

-struct rk3036_clk_priv {

• struct rk3036_cru *cru;
• ulong rate;

-};

• enum { VCO_MAX_HZ = 2400U * 1000000, VCO_MIN_HZ = 600 * 1000000,

@@ -49,23 +44,6 @@ enum { static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1); static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);

-void *rockchip_get_cru(void) -{

• struct udevice *dev;
• fdt_addr_t addr;
• int ret;
• ret = uclass_get_device(UCLASS_CLK, 0, &dev);
• if (ret)

• return ERR_PTR(ret);
  

• addr = dev_get_addr(dev);
• if (addr == FDT_ADDR_T_NONE)

• return ERR_PTR(-EINVAL);
  

• return (void *)addr;

-}

• static int rkclk_set_pll(struct rk3036_cru *cru, enum rk_clk_id clk_id, const struct pll_div *div) {

@@ -371,7 +349,7 @@ static const struct udevice_id rk3036_clk_ids[] = { { } };

-U_BOOT_DRIVER(clk_rk3036) = { +U_BOOT_DRIVER(rockchip_rk3036_cru) = { .name = "clk_rk3036", .id = UCLASS_CLK, .of_match = rk3036_clk_ids,

Reviewed-by: Kever Yang kever.yang@rock-chips.com

Thanks, - Kever