[U-Boot-Users] linux doesn't boot when CS for initial cache disabled

Here is what I did:
I'm testing with an IBM Walnut board (PPC405GP) with u-boot 0.3.0 and 2.4.17 kernel from Montavista. After booting u-boot and loading the kernel via tftp, I submit the following commands on the console:
=> setdcr 12 0012: 00000004 ? 7 0012: 00000007 ? . => setdcr 13 0013: 400da000 ? 0 0013: 00000000 ? .
This disables CS7, which is used for the temporary stack in my configuration.
The kernel function start_here (arch/ppc/kernel/head_4xx.S) is the place where the MMU is used first. Setting a breakpoint (in my case at 0xc00022d0) and trying to trace from this point with my BDI2000 results in a data machine check interrupt:
BDI>bi 0xc00022d0 Breakpoint identification is 0 BDI>go - TARGET: target has entered debug mode BDI>info Target state : debug mode Debug entry cause : instruction breakpoint Current PC : 0xc00022d0 Current CR : 0x24004004 Current MSR : 0x00001030 Current LR : 0x0000001c BDI>ti Target state : debug mode Debug entry cause : JTAG stop request Current PC : 0x00000280 Current CR : 0x28004004 Current MSR : 0x00000000 Current LR : 0xc0002b34 # Step timeout detected BDI>
Unfortunately I have no idea why this happens. Looking at the register contents I found that the address of the temporary stack (0x40000000) is still stored in r2, but this should have no effect on booting the kernel???
BDI>rd GPR00: c00022d0 07f9f5e8 40000000 c10003c0 GPR04: c0000000 00000000 007ffc00 007ffc0e GPR08: 07fc9f10 000186a0 00000003 00000002 GPR12: 00000000 c01605b0 07fe5800 00000000 GPR16: 00000001 007ffc0e 007ffc00 ffffffff GPR20: 00000000 07fe2398 07f9fe88 00000002 GPR24: 00000000 00000000 007ffb90 007ffc0e GPR28: 007ffc00 00000000 00000000 007ffb90 CR : 24004004 MSR: 00001030 BDI>
Any ideas?
Best regards,
Thomas Schaefer
____________________________________
GIGA STREAM - UMTS Technologies GmbH
Konrad-Zuse-Str. 7 66115 Saarbrücken
Tel.: + 49 (0)681 / 95916 - 203 Fax: + 49 (0)681 / 95916 - 100 E-mail: tschaefer@giga-stream.de
participants (1)
-
Thomas Schäfer