[U-Boot] [PATCH 1/6] p1014rdb: set ddr bus width properly depending on SVR
Currently, for NAND boot for the P1010/4RDB we hard code the DDR configuration. We can still dynamically set the DDR bus width in the nand spl so the P1010/4RDB boards can boot from the same u-boot image
Signed-off-by: Matthew McClintock msm@freescale.com --- arch/powerpc/include/asm/fsl_ddr_sdram.h | 1 + nand_spl/board/freescale/p1010rdb/nand_boot.c | 11 +++++++++++ 2 files changed, 12 insertions(+)
diff --git a/arch/powerpc/include/asm/fsl_ddr_sdram.h b/arch/powerpc/include/asm/fsl_ddr_sdram.h index 93639ba..157ae24 100644 --- a/arch/powerpc/include/asm/fsl_ddr_sdram.h +++ b/arch/powerpc/include/asm/fsl_ddr_sdram.h @@ -88,6 +88,7 @@ typedef ddr3_spd_eeprom_t generic_spd_eeprom_t; #define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000 #define SDRAM_CFG_SDRAM_TYPE_SHIFT 24 #define SDRAM_CFG_DYN_PWR 0x00200000 +#define SDRAM_CFG_DBW_MASK 0x00180000 #define SDRAM_CFG_32_BE 0x00080000 #define SDRAM_CFG_16_BE 0x00100000 #define SDRAM_CFG_8_BE 0x00040000 diff --git a/nand_spl/board/freescale/p1010rdb/nand_boot.c b/nand_spl/board/freescale/p1010rdb/nand_boot.c index 16eeb61..1f89ab5 100644 --- a/nand_spl/board/freescale/p1010rdb/nand_boot.c +++ b/nand_spl/board/freescale/p1010rdb/nand_boot.c @@ -35,6 +35,7 @@ unsigned long ddr_freq_mhz; void sdram_init(void) { ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR; + u32 svr = mfspr(SPRN_SVR);
out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL | SDRAM_CFG_32_BE); out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS); @@ -70,6 +71,16 @@ void sdram_init(void) out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5); out_be32(&ddr->ddr_zq_cntl, CONFIG_SYS_DDR_ZQ_CONTROL);
+ /* P1014 and it's derivatives support max 16bit DDR width */ + if (svr == SVR_P1014) { + __raw_writel(ddr->sdram_cfg & ~SDRAM_CFG_DBW_MASK, &ddr->sdram_cfg); + __raw_writel(ddr->sdram_cfg | SDRAM_CFG_16_BE, &ddr->sdram_cfg); + /* For CS0_BNDS we divide the start and end address by 2, so we can just + * shift the entire register to achieve the desired result and the mask + * the value so we don't write reserved fields */ + __raw_writel((CONFIG_SYS_DDR_CS0_BNDS >> 1) & 0x0fff0fff, &ddr->cs0_bnds); + } + /* mimic 500us delay, with busy isync() loop */ udelay(100);
There was an extra 0 in front of the value we were using to mask, remove it to improve the code.
Also fix the value written to ddr_sdram_cfg to set the bus width properly to 16 bits
Signed-off-by: Matthew McClintock msm@freescale.com --- board/freescale/p1010rdb/ddr.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/board/freescale/p1010rdb/ddr.c b/board/freescale/p1010rdb/ddr.c index 10c5a42..6d00caf 100644 --- a/board/freescale/p1010rdb/ddr.c +++ b/board/freescale/p1010rdb/ddr.c @@ -147,10 +147,11 @@ phys_size_t fixed_sdram(void) cpu = gd->cpu; /* P1014 and it's derivatives support max 16bit DDR width */ if (cpu->soc_ver == SVR_P1014) { + ddr_cfg_regs.ddr_sdram_cfg &= ~SDRAM_CFG_DBW_MASK; ddr_cfg_regs.ddr_sdram_cfg |= SDRAM_CFG_16_BE; - ddr_cfg_regs.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS >> 1; - ddr_cfg_regs.ddr_sdram_cfg &= ~0x00180000; - ddr_cfg_regs.ddr_sdram_cfg |= 0x001080000; + /* divide SA and EA by two and then mask the rest so we don't + * write to reserved fields */ + ddr_cfg_regs.cs[0].bnds = (CONFIG_SYS_DDR_CS0_BNDS >> 1) & 0x0fff0fff; }
ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
We were not comparing the SVRs properly previously. This comparison will properly shift the SVR and mask off the E bit
This fixes the boot output to show the correct DDR bus width:
512 MiB (DDR3, 16-bit, CL=5, ECC off)
instead of
512 MiB (DDR3, 32-bit, CL=5, ECC off)
Signed-off-by: Matthew McClintock msm@freescale.com --- nand_spl/board/freescale/p1010rdb/nand_boot.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/nand_spl/board/freescale/p1010rdb/nand_boot.c b/nand_spl/board/freescale/p1010rdb/nand_boot.c index 1f89ab5..f5294d0 100644 --- a/nand_spl/board/freescale/p1010rdb/nand_boot.c +++ b/nand_spl/board/freescale/p1010rdb/nand_boot.c @@ -35,7 +35,8 @@ unsigned long ddr_freq_mhz; void sdram_init(void) { ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR; - u32 svr = mfspr(SPRN_SVR); + /* mask off E bit */ + u32 svr = SVR_SOC_VER(mfspr(SPRN_SVR));
out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL | SDRAM_CFG_32_BE); out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS);
Let's use the more appropriate udelay for the nand_spl. While we can't make use of u-boot's full udelay we can atl east use a for loop that won't get optimized away .Since we have the bus clock we can use the timebase to calculate wall time.
Looked at reusing the u-boot udelay functions but it pulls in a lot of code as well as depends on the gd struct and would require a lot of rework
Signed-off-by: Matthew McClintock msm@freescale.com --- nand_spl/board/freescale/common.c | 36 +++++++++++++++++++++ nand_spl/board/freescale/p1010rdb/Makefile | 6 +++- nand_spl/board/freescale/p1010rdb/nand_boot.c | 8 ++--- nand_spl/board/freescale/p1_p2_rdb_pc/Makefile | 6 +++- nand_spl/board/freescale/p1_p2_rdb_pc/nand_boot.c | 9 ++---- 5 files changed, 52 insertions(+), 13 deletions(-) create mode 100644 nand_spl/board/freescale/common.c
diff --git a/nand_spl/board/freescale/common.c b/nand_spl/board/freescale/common.c new file mode 100644 index 0000000..9008cf4 --- /dev/null +++ b/nand_spl/board/freescale/common.c @@ -0,0 +1,36 @@ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * Author: Matthew McClintock msm@freescale.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + + + +#include <common.h> +#include <asm/processor.h> + +extern u32 bus_clk; + +void udelay(unsigned long usec) { + u32 ticks_per_usec = bus_clk / (8 * 1000000); + u32 ticks = ticks_per_usec * usec; + u32 s = mfspr(SPRN_TBRL); + + while ((mfspr(SPRN_TBRL)-s) < ticks); +} diff --git a/nand_spl/board/freescale/p1010rdb/Makefile b/nand_spl/board/freescale/p1010rdb/Makefile index 8d240ea..cdbd492 100644 --- a/nand_spl/board/freescale/p1010rdb/Makefile +++ b/nand_spl/board/freescale/p1010rdb/Makefile @@ -39,7 +39,8 @@ CFLAGS += -DCONFIG_NAND_SPL
SOBJS = start.o resetvec.o ticks.o COBJS = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \ - nand_boot.o nand_boot_fsl_ifc.o ns16550.o tlb.o tlb_table.o + nand_boot.o nand_boot_fsl_ifc.o ns16550.o tlb.o tlb_table.o \ + ../common.o
SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) @@ -123,6 +124,9 @@ ifneq ($(OBJTREE), $(SRCTREE)) $(obj)nand_boot.c: @rm -f $(obj)nand_boot.c ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c +$(obj)../common.c: + @rm -f $(obj)../common.c + ln -s $(SRCTREE)/nand_spl/board/freescale/common.c $(obj)../common.c endif
######################################################################### diff --git a/nand_spl/board/freescale/p1010rdb/nand_boot.c b/nand_spl/board/freescale/p1010rdb/nand_boot.c index f5294d0..931e562 100644 --- a/nand_spl/board/freescale/p1010rdb/nand_boot.c +++ b/nand_spl/board/freescale/p1010rdb/nand_boot.c @@ -28,8 +28,6 @@ #include <asm/fsl_ddr_sdram.h> #include <asm/fsl_law.h>
-#define udelay(x) { int j; for (j = 0; j < x * 10000; j++) isync(); } - unsigned long ddr_freq_mhz;
void sdram_init(void) @@ -82,8 +80,7 @@ void sdram_init(void) __raw_writel((CONFIG_SYS_DDR_CS0_BNDS >> 1) & 0x0fff0fff, &ddr->cs0_bnds); }
- /* mimic 500us delay, with busy isync() loop */ - udelay(100); + udelay(500);
/* Let the controller go */ out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN); @@ -91,10 +88,11 @@ void sdram_init(void) set_next_law(CONFIG_SYS_NAND_DDR_LAW, LAW_SIZE_1G, LAW_TRGT_IF_DDR_1); }
+u32 bus_clk; + void board_init_f(ulong bootflag) { u32 plat_ratio, ddr_ratio; - unsigned long bus_clk; ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
/* initialize selected port with appropriate baud rate */ diff --git a/nand_spl/board/freescale/p1_p2_rdb_pc/Makefile b/nand_spl/board/freescale/p1_p2_rdb_pc/Makefile index 475cc49..46cf709 100644 --- a/nand_spl/board/freescale/p1_p2_rdb_pc/Makefile +++ b/nand_spl/board/freescale/p1_p2_rdb_pc/Makefile @@ -39,7 +39,8 @@ CFLAGS += -DCONFIG_NAND_SPL
SOBJS = start.o resetvec.o COBJS = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \ - nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o + nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o \ + ../common.o
SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) @@ -119,6 +120,9 @@ ifneq ($(OBJTREE), $(SRCTREE)) $(obj)nand_boot.c: @rm -f $(obj)nand_boot.c ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c +$(obj)../common.c: + @rm -f $(obj)../common.c + ln -s $(SRCTREE)/nand_spl/board/freescale/common.c $(obj)../common.c endif
######################################################################### diff --git a/nand_spl/board/freescale/p1_p2_rdb_pc/nand_boot.c b/nand_spl/board/freescale/p1_p2_rdb_pc/nand_boot.c index b9796ea..e7906e8 100644 --- a/nand_spl/board/freescale/p1_p2_rdb_pc/nand_boot.c +++ b/nand_spl/board/freescale/p1_p2_rdb_pc/nand_boot.c @@ -26,11 +26,6 @@ #include <asm/fsl_law.h> #include <asm/fsl_ddr_sdram.h>
-#define udelay(x) {int i, j; \ - for (i = 0; i < x; i++) \ - for (j = 0; j < 10000; j++) \ - ; } - /* * Fixed sdram init -- doesn't use serial presence detect. */ @@ -74,9 +69,11 @@ void sdram_init(void) set_next_law(0, CONFIG_SYS_SDRAM_SIZE_LAW, LAW_TRGT_IF_DDR_1); }
+u32 bus_clk; + void board_init_f(ulong bootflag) { - u32 plat_ratio, bus_clk; + u32 plat_ratio; ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; #ifndef CONFIG_QE ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
On 08/13/2012 01:10 PM, Matthew McClintock wrote:
Let's use the more appropriate udelay for the nand_spl. While we can't make use of u-boot's full udelay we can atl east use a for loop that won't get optimized away .Since we have the bus clock we can use the timebase to calculate wall time.
Looked at reusing the u-boot udelay functions but it pulls in a lot of code as well as depends on the gd struct and would require a lot of rework
What's wrong with depending on the gd struct?
+extern u32 bus_clk;
Change to gd->bus_clk as mentioned in patch 5/6.
+void udelay(unsigned long usec) {
- u32 ticks_per_usec = bus_clk / (8 * 1000000);
- u32 ticks = ticks_per_usec * usec;
- u32 s = mfspr(SPRN_TBRL);
- while ((mfspr(SPRN_TBRL)-s) < ticks);
+}
Opening brace goes on its own line for function definitions. Use spaces around that '-'.
Dividing the bus clock by 8 only works for e500v1/v2, but this isn't labelled as specific to those cores.
diff --git a/nand_spl/board/freescale/p1010rdb/Makefile b/nand_spl/board/freescale/p1010rdb/Makefile index 8d240ea..cdbd492 100644 --- a/nand_spl/board/freescale/p1010rdb/Makefile +++ b/nand_spl/board/freescale/p1010rdb/Makefile @@ -39,7 +39,8 @@ CFLAGS += -DCONFIG_NAND_SPL
SOBJS = start.o resetvec.o ticks.o COBJS = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \
nand_boot.o nand_boot_fsl_ifc.o ns16550.o tlb.o tlb_table.o
nand_boot.o nand_boot_fsl_ifc.o ns16550.o tlb.o tlb_table.o \../common.oSRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) @@ -123,6 +124,9 @@ ifneq ($(OBJTREE), $(SRCTREE)) $(obj)nand_boot.c: @rm -f $(obj)nand_boot.c ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c +$(obj)../common.c:
- @rm -f $(obj)../common.c
- ln -s $(SRCTREE)/nand_spl/board/freescale/common.c $(obj)../common.c
endif
Why are you creating a link in the parent directory?
-Scott
On Mon, Aug 13, 2012 at 5:56 PM, Scott Wood scottwood@freescale.com wrote:
On 08/13/2012 01:10 PM, Matthew McClintock wrote:
Let's use the more appropriate udelay for the nand_spl. While we can't make use of u-boot's full udelay we can atl east use a for loop that won't get optimized away .Since we have the bus clock we can use the timebase to calculate wall time.
Looked at reusing the u-boot udelay functions but it pulls in a lot of code as well as depends on the gd struct and would require a lot of rework
What's wrong with depending on the gd struct?
Perhaps the wording is wrong a bit off. It's just pulling in other stuff and as you know we are very space constrained.
+extern u32 bus_clk;
Change to gd->bus_clk as mentioned in patch 5/6.
Yes, v2 was already sent: http://patchwork.ozlabs.org/patch/177047/
+void udelay(unsigned long usec) {
u32 ticks_per_usec = bus_clk / (8 * 1000000);u32 ticks = ticks_per_usec * usec;u32 s = mfspr(SPRN_TBRL);while ((mfspr(SPRN_TBRL)-s) < ticks);+}
Opening brace goes on its own line for function definitions. Use spaces around that '-'.
Will fix.
Dividing the bus clock by 8 only works for e500v1/v2, but this isn't labelled as specific to those cores.
Updated to use CONFIG_SYS_FSL_TBCLK_DIV
diff --git a/nand_spl/board/freescale/p1010rdb/Makefile b/nand_spl/board/freescale/p1010rdb/Makefile index 8d240ea..cdbd492 100644 --- a/nand_spl/board/freescale/p1010rdb/Makefile +++ b/nand_spl/board/freescale/p1010rdb/Makefile @@ -39,7 +39,8 @@ CFLAGS += -DCONFIG_NAND_SPL
SOBJS = start.o resetvec.o ticks.o COBJS = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \
nand_boot.o nand_boot_fsl_ifc.o ns16550.o tlb.o tlb_table.o
nand_boot.o nand_boot_fsl_ifc.o ns16550.o tlb.o tlb_table.o \../common.oSRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) @@ -123,6 +124,9 @@ ifneq ($(OBJTREE), $(SRCTREE)) $(obj)nand_boot.c: @rm -f $(obj)nand_boot.c ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c +$(obj)../common.c:
@rm -f $(obj)../common.cln -s $(SRCTREE)/nand_spl/board/freescale/common.c $(obj)../common.cendif
Why are you creating a link in the parent directory?
The typical build process picks out files needed for the build and symlinks them to nand_spl folder - or if building out of tree then it symlinks to the out of tree folder. This is true for all files in nand_spl as it currently exists not just this new file.
-M
On 08/13/2012 06:14 PM, McClintock Matthew-B29882 wrote:
On Mon, Aug 13, 2012 at 5:56 PM, Scott Wood scottwood@freescale.com wrote:
On 08/13/2012 01:10 PM, Matthew McClintock wrote:
Let's use the more appropriate udelay for the nand_spl. While we can't make use of u-boot's full udelay we can atl east use a for loop that won't get optimized away .Since we have the bus clock we can use the timebase to calculate wall time.
Looked at reusing the u-boot udelay functions but it pulls in a lot of code as well as depends on the gd struct and would require a lot of rework
What's wrong with depending on the gd struct?
Perhaps the wording is wrong a bit off. It's just pulling in other stuff and as you know we are very space constrained.
A struct definition doesn't take up space. Maybe you meant a dependency on certain specific code that puts things in the gd struct?
@@ -123,6 +124,9 @@ ifneq ($(OBJTREE), $(SRCTREE)) $(obj)nand_boot.c: @rm -f $(obj)nand_boot.c ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c +$(obj)../common.c:
@rm -f $(obj)../common.cln -s $(SRCTREE)/nand_spl/board/freescale/common.c $(obj)../common.cendif
Why are you creating a link in the parent directory?
The typical build process picks out files needed for the build and symlinks them to nand_spl folder - or if building out of tree then it symlinks to the out of tree folder. This is true for all files in nand_spl as it currently exists not just this new file.
This is the first time I've seen a link go in $(obj)../ rather than $(obj)
-Scott
On Mon, Aug 13, 2012 at 6:22 PM, Scott Wood scottwood@freescale.com wrote:
On 08/13/2012 06:14 PM, McClintock Matthew-B29882 wrote:
On Mon, Aug 13, 2012 at 5:56 PM, Scott Wood scottwood@freescale.com wrote:
On 08/13/2012 01:10 PM, Matthew McClintock wrote:
Let's use the more appropriate udelay for the nand_spl. While we can't make use of u-boot's full udelay we can atl east use a for loop that won't get optimized away .Since we have the bus clock we can use the timebase to calculate wall time.
Looked at reusing the u-boot udelay functions but it pulls in a lot of code as well as depends on the gd struct and would require a lot of rework
What's wrong with depending on the gd struct?
Perhaps the wording is wrong a bit off. It's just pulling in other stuff and as you know we are very space constrained.
A struct definition doesn't take up space. Maybe you meant a dependency on certain specific code that puts things in the gd struct?
Correct.
@@ -123,6 +124,9 @@ ifneq ($(OBJTREE), $(SRCTREE)) $(obj)nand_boot.c: @rm -f $(obj)nand_boot.c ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c +$(obj)../common.c:
@rm -f $(obj)../common.cln -s $(SRCTREE)/nand_spl/board/freescale/common.c $(obj)../common.cendif
Why are you creating a link in the parent directory?
The typical build process picks out files needed for the build and symlinks them to nand_spl folder - or if building out of tree then it symlinks to the out of tree folder. This is true for all files in nand_spl as it currently exists not just this new file.
This is the first time I've seen a link go in $(obj)../ rather than $(obj)
It's because that's where the includes reference it. When building in tree, it does nothing because it can just reference the C file in the parent directory. When it's out of tree - we need to install the symlink in the proper location in the build folder.
-M
On 08/13/2012 06:28 PM, McClintock Matthew-B29882 wrote:
On Mon, Aug 13, 2012 at 6:22 PM, Scott Wood scottwood@freescale.com wrote:
On 08/13/2012 06:14 PM, McClintock Matthew-B29882 wrote:
On Mon, Aug 13, 2012 at 5:56 PM, Scott Wood scottwood@freescale.com wrote:
On 08/13/2012 01:10 PM, Matthew McClintock wrote:
Let's use the more appropriate udelay for the nand_spl. While we can't make use of u-boot's full udelay we can atl east use a for loop that won't get optimized away .Since we have the bus clock we can use the timebase to calculate wall time.
Looked at reusing the u-boot udelay functions but it pulls in a lot of code as well as depends on the gd struct and would require a lot of rework
What's wrong with depending on the gd struct?
Perhaps the wording is wrong a bit off. It's just pulling in other stuff and as you know we are very space constrained.
A struct definition doesn't take up space. Maybe you meant a dependency on certain specific code that puts things in the gd struct?
Correct.
@@ -123,6 +124,9 @@ ifneq ($(OBJTREE), $(SRCTREE)) $(obj)nand_boot.c: @rm -f $(obj)nand_boot.c ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c +$(obj)../common.c:
@rm -f $(obj)../common.cln -s $(SRCTREE)/nand_spl/board/freescale/common.c $(obj)../common.cendif
Why are you creating a link in the parent directory?
The typical build process picks out files needed for the build and symlinks them to nand_spl folder - or if building out of tree then it symlinks to the out of tree folder. This is true for all files in nand_spl as it currently exists not just this new file.
This is the first time I've seen a link go in $(obj)../ rather than $(obj)
It's because that's where the includes reference it. When building in tree, it does nothing because it can just reference the C file in the parent directory. When it's out of tree - we need to install the symlink in the proper location in the build folder.
I'm not thrilled with it, but it shouldn't have long to live since new-spl doesn't do the symlink thing.
-Scott
We have a requirement to wait a period of time before enabling the DDR controller
Signed-off-by: Matthew McClintock msm@freescale.com --- nand_spl/board/freescale/p1023rds/Makefile | 6 +++++- nand_spl/board/freescale/p1023rds/nand_boot.c | 14 ++++++++++++-- 2 files changed, 17 insertions(+), 3 deletions(-)
diff --git a/nand_spl/board/freescale/p1023rds/Makefile b/nand_spl/board/freescale/p1023rds/Makefile index 168e868..da43521 100644 --- a/nand_spl/board/freescale/p1023rds/Makefile +++ b/nand_spl/board/freescale/p1023rds/Makefile @@ -34,7 +34,8 @@ CFLAGS += -DCONFIG_NAND_SPL
SOBJS = start.o resetvec.o COBJS = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \ - nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o + nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o \ + ../common.o
SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) @@ -114,6 +115,9 @@ ifneq ($(OBJTREE), $(SRCTREE)) $(obj)nand_boot.c: @rm -f $(obj)nand_boot.c ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c +$(obj)../common.c: + @rm -f $(obj)../common.c + ln -s $(SRCTREE)/nand_spl/board/freescale/common.c $(obj)../common.c endif
######################################################################### diff --git a/nand_spl/board/freescale/p1023rds/nand_boot.c b/nand_spl/board/freescale/p1023rds/nand_boot.c index 0065c87..9309936 100644 --- a/nand_spl/board/freescale/p1023rds/nand_boot.c +++ b/nand_spl/board/freescale/p1023rds/nand_boot.c @@ -25,6 +25,7 @@ #include <asm/io.h> #include <nand.h> #include <asm/fsl_law.h> +#include <asm/fsl_ddr_sdram.h>
/* Fixed sdram init -- doesn't use serial presence detect. */ void sdram_init(void) @@ -53,12 +54,21 @@ void sdram_init(void) out_be32(&ddr->ddr_wrlvl_cntl, CONFIG_SYS_DDR_WRLVL_CNTL); out_be32(&ddr->ddr_cdr1, CONFIG_SYS_DDR_CDR_1); out_be32(&ddr->ddr_cdr2, CONFIG_SYS_DDR_CDR_2); - out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL); + /* Set, but do not enable the memory */ + out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN); + + asm volatile("sync;isync"); + udelay(500); + + /* Let the controller go */ + out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN); }
+u32 bus_clk; + void board_init_f(ulong bootflag) { - u32 plat_ratio, bus_clk; + u32 plat_ratio; ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
/* initialize selected port with appropriate baud rate */
On 08/13/2012 01:10 PM, Matthew McClintock wrote:
We have a requirement to wait a period of time before enabling the DDR controller
Signed-off-by: Matthew McClintock msm@freescale.com
nand_spl/board/freescale/p1023rds/Makefile | 6 +++++- nand_spl/board/freescale/p1023rds/nand_boot.c | 14 ++++++++++++-- 2 files changed, 17 insertions(+), 3 deletions(-)
diff --git a/nand_spl/board/freescale/p1023rds/Makefile b/nand_spl/board/freescale/p1023rds/Makefile index 168e868..da43521 100644 --- a/nand_spl/board/freescale/p1023rds/Makefile +++ b/nand_spl/board/freescale/p1023rds/Makefile @@ -34,7 +34,8 @@ CFLAGS += -DCONFIG_NAND_SPL
SOBJS = start.o resetvec.o COBJS = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \
nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o
nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o \../common.oSRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) @@ -114,6 +115,9 @@ ifneq ($(OBJTREE), $(SRCTREE)) $(obj)nand_boot.c: @rm -f $(obj)nand_boot.c ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c +$(obj)../common.c:
- @rm -f $(obj)../common.c
- ln -s $(SRCTREE)/nand_spl/board/freescale/common.c $(obj)../common.c
endif
######################################################################### diff --git a/nand_spl/board/freescale/p1023rds/nand_boot.c b/nand_spl/board/freescale/p1023rds/nand_boot.c index 0065c87..9309936 100644 --- a/nand_spl/board/freescale/p1023rds/nand_boot.c +++ b/nand_spl/board/freescale/p1023rds/nand_boot.c @@ -25,6 +25,7 @@ #include <asm/io.h> #include <nand.h> #include <asm/fsl_law.h> +#include <asm/fsl_ddr_sdram.h>
/* Fixed sdram init -- doesn't use serial presence detect. */ void sdram_init(void) @@ -53,12 +54,21 @@ void sdram_init(void) out_be32(&ddr->ddr_wrlvl_cntl, CONFIG_SYS_DDR_WRLVL_CNTL); out_be32(&ddr->ddr_cdr1, CONFIG_SYS_DDR_CDR_1); out_be32(&ddr->ddr_cdr2, CONFIG_SYS_DDR_CDR_2);
- out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL);
- /* Set, but do not enable the memory */
- out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN);
- asm volatile("sync;isync");
- udelay(500);
- /* Let the controller go */
- out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN);
}
+u32 bus_clk;
void board_init_f(ulong bootflag) {
- u32 plat_ratio, bus_clk;
u32 plat_ratio; ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
/* initialize selected port with appropriate baud rate */
This is before relocation, so you can't use global variables. Use gd->bus_clk.
In our SDK where this code has already been applied, I spent some debug time tracking why the first word of the SPL was getting corrupted (the BSS goes right after the end of the NAND buffer and it wraps around), when trying to find the cause of other corruption (the rest was bad DDR settings).
-Scott
On Mon, Aug 13, 2012 at 1:18 PM, Scott Wood scottwood@freescale.com wrote:
On 08/13/2012 01:10 PM, Matthew McClintock wrote:
We have a requirement to wait a period of time before enabling the DDR controller
Signed-off-by: Matthew McClintock msm@freescale.com
nand_spl/board/freescale/p1023rds/Makefile | 6 +++++- nand_spl/board/freescale/p1023rds/nand_boot.c | 14 ++++++++++++-- 2 files changed, 17 insertions(+), 3 deletions(-)
diff --git a/nand_spl/board/freescale/p1023rds/Makefile b/nand_spl/board/freescale/p1023rds/Makefile index 168e868..da43521 100644 --- a/nand_spl/board/freescale/p1023rds/Makefile +++ b/nand_spl/board/freescale/p1023rds/Makefile @@ -34,7 +34,8 @@ CFLAGS += -DCONFIG_NAND_SPL
SOBJS = start.o resetvec.o COBJS = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \
nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o
nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o \../common.oSRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) @@ -114,6 +115,9 @@ ifneq ($(OBJTREE), $(SRCTREE)) $(obj)nand_boot.c: @rm -f $(obj)nand_boot.c ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c +$(obj)../common.c:
@rm -f $(obj)../common.cln -s $(SRCTREE)/nand_spl/board/freescale/common.c $(obj)../common.cendif
######################################################################### diff --git a/nand_spl/board/freescale/p1023rds/nand_boot.c b/nand_spl/board/freescale/p1023rds/nand_boot.c index 0065c87..9309936 100644 --- a/nand_spl/board/freescale/p1023rds/nand_boot.c +++ b/nand_spl/board/freescale/p1023rds/nand_boot.c @@ -25,6 +25,7 @@ #include <asm/io.h> #include <nand.h> #include <asm/fsl_law.h> +#include <asm/fsl_ddr_sdram.h>
/* Fixed sdram init -- doesn't use serial presence detect. */ void sdram_init(void) @@ -53,12 +54,21 @@ void sdram_init(void) out_be32(&ddr->ddr_wrlvl_cntl, CONFIG_SYS_DDR_WRLVL_CNTL); out_be32(&ddr->ddr_cdr1, CONFIG_SYS_DDR_CDR_1); out_be32(&ddr->ddr_cdr2, CONFIG_SYS_DDR_CDR_2);
out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL);
/* Set, but do not enable the memory */out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN);asm volatile("sync;isync");udelay(500);/* Let the controller go */out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN);}
+u32 bus_clk;
void board_init_f(ulong bootflag) {
u32 plat_ratio, bus_clk;
u32 plat_ratio; ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; /* initialize selected port with appropriate baud rate */This is before relocation, so you can't use global variables. Use gd->bus_clk.
In our SDK where this code has already been applied, I spent some debug time tracking why the first word of the SPL was getting corrupted (the BSS goes right after the end of the NAND buffer and it wraps around), when trying to find the cause of other corruption (the rest was bad DDR settings).
Thanks, v2 coming.
-M
This change reduces the SPL size by removing the redundant syncs produced by out_be32 and just replies on one final sync
Done with:
sed -r '/in_be32/b; s/(out_be32)(([^,]*),\s+(.*))/__raw_writel(\3, \2)/g' -i `git grep --name-only sdram_init nand_spl/`
Signed-off-by: Matthew McClintock msm@freescale.com --- nand_spl/board/freescale/p1010rdb/nand_boot.c | 54 ++++++++++----------- nand_spl/board/freescale/p1023rds/nand_boot.c | 42 ++++++++-------- nand_spl/board/freescale/p1_p2_rdb_pc/nand_boot.c | 48 +++++++++--------- 3 files changed, 71 insertions(+), 73 deletions(-)
diff --git a/nand_spl/board/freescale/p1010rdb/nand_boot.c b/nand_spl/board/freescale/p1010rdb/nand_boot.c index 931e562..7190b00 100644 --- a/nand_spl/board/freescale/p1010rdb/nand_boot.c +++ b/nand_spl/board/freescale/p1010rdb/nand_boot.c @@ -36,39 +36,37 @@ void sdram_init(void) /* mask off E bit */ u32 svr = SVR_SOC_VER(mfspr(SPRN_SVR));
- out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL | SDRAM_CFG_32_BE); - out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS); - out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG); - out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_CONTROL_2); - out_be32(&ddr->sdram_data_init, CONFIG_SYS_DDR_DATA_INIT); + __raw_writel(CONFIG_SYS_DDR_CONTROL | SDRAM_CFG_32_BE, &ddr->sdram_cfg); + __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds); + __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config); + __raw_writel(CONFIG_SYS_DDR_CONTROL_2, &ddr->sdram_cfg_2); + __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init);
if (ddr_freq_mhz < 700) { - out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3_667); - out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0_667); - out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1_667); - out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2_667); - out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_MODE_1_667); - out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2_667); - out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL_667); - out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CTRL_667); - out_be32(&ddr->ddr_wrlvl_cntl, - CONFIG_SYS_DDR_WRLVL_CONTROL_667); + __raw_writel(CONFIG_SYS_DDR_TIMING_3_667, &ddr->timing_cfg_3); + __raw_writel(CONFIG_SYS_DDR_TIMING_0_667, &ddr->timing_cfg_0); + __raw_writel(CONFIG_SYS_DDR_TIMING_1_667, &ddr->timing_cfg_1); + __raw_writel(CONFIG_SYS_DDR_TIMING_2_667, &ddr->timing_cfg_2); + __raw_writel(CONFIG_SYS_DDR_MODE_1_667, &ddr->sdram_mode); + __raw_writel(CONFIG_SYS_DDR_MODE_2_667, &ddr->sdram_mode_2); + __raw_writel(CONFIG_SYS_DDR_INTERVAL_667, &ddr->sdram_interval); + __raw_writel(CONFIG_SYS_DDR_CLK_CTRL_667, &ddr->sdram_clk_cntl); + __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_667, &ddr->ddr_wrlvl_cntl); } else { - out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3_800); - out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0_800); - out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1_800); - out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2_800); - out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_MODE_1_800); - out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2_800); - out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL_800); - out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CTRL_800); - out_be32(&ddr->ddr_wrlvl_cntl, - CONFIG_SYS_DDR_WRLVL_CONTROL_800); + __raw_writel(CONFIG_SYS_DDR_TIMING_3_800, &ddr->timing_cfg_3); + __raw_writel(CONFIG_SYS_DDR_TIMING_0_800, &ddr->timing_cfg_0); + __raw_writel(CONFIG_SYS_DDR_TIMING_1_800, &ddr->timing_cfg_1); + __raw_writel(CONFIG_SYS_DDR_TIMING_2_800, &ddr->timing_cfg_2); + __raw_writel(CONFIG_SYS_DDR_MODE_1_800, &ddr->sdram_mode); + __raw_writel(CONFIG_SYS_DDR_MODE_2_800, &ddr->sdram_mode_2); + __raw_writel(CONFIG_SYS_DDR_INTERVAL_800, &ddr->sdram_interval); + __raw_writel(CONFIG_SYS_DDR_CLK_CTRL_800, &ddr->sdram_clk_cntl); + __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_800, &ddr->ddr_wrlvl_cntl); }
- out_be32(&ddr->timing_cfg_4, CONFIG_SYS_DDR_TIMING_4); - out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5); - out_be32(&ddr->ddr_zq_cntl, CONFIG_SYS_DDR_ZQ_CONTROL); + __raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4); + __raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5); + __raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl);
/* P1014 and it's derivatives support max 16bit DDR width */ if (svr == SVR_P1014) { diff --git a/nand_spl/board/freescale/p1023rds/nand_boot.c b/nand_spl/board/freescale/p1023rds/nand_boot.c index 9309936..a63fc8d 100644 --- a/nand_spl/board/freescale/p1023rds/nand_boot.c +++ b/nand_spl/board/freescale/p1023rds/nand_boot.c @@ -34,28 +34,28 @@ void sdram_init(void)
set_next_law(0, LAW_SIZE_2G, LAW_TRGT_IF_DDR_1);
- out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS); - out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG); - out_be32(&ddr->cs1_bnds, CONFIG_SYS_DDR_CS1_BNDS); - out_be32(&ddr->cs1_config, CONFIG_SYS_DDR_CS1_CONFIG); - out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); - out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0); - out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); - out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); - out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_CONTROL2); - out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_MODE_1); - out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2); - out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL); - out_be32(&ddr->sdram_data_init, CONFIG_SYS_DDR_DATA_INIT); - out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CTRL); - out_be32(&ddr->timing_cfg_4, CONFIG_SYS_DDR_TIMING_4); - out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5); - out_be32(&ddr->ddr_zq_cntl, CONFIG_SYS_DDR_ZQ_CNTL); - out_be32(&ddr->ddr_wrlvl_cntl, CONFIG_SYS_DDR_WRLVL_CNTL); - out_be32(&ddr->ddr_cdr1, CONFIG_SYS_DDR_CDR_1); - out_be32(&ddr->ddr_cdr2, CONFIG_SYS_DDR_CDR_2); + __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds); + __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config); + __raw_writel(CONFIG_SYS_DDR_CS1_BNDS, &ddr->cs1_bnds); + __raw_writel(CONFIG_SYS_DDR_CS1_CONFIG, &ddr->cs1_config); + __raw_writel(CONFIG_SYS_DDR_TIMING_3, &ddr->timing_cfg_3); + __raw_writel(CONFIG_SYS_DDR_TIMING_0, &ddr->timing_cfg_0); + __raw_writel(CONFIG_SYS_DDR_TIMING_1, &ddr->timing_cfg_1); + __raw_writel(CONFIG_SYS_DDR_TIMING_2, &ddr->timing_cfg_2); + __raw_writel(CONFIG_SYS_DDR_CONTROL2, &ddr->sdram_cfg_2); + __raw_writel(CONFIG_SYS_DDR_MODE_1, &ddr->sdram_mode); + __raw_writel(CONFIG_SYS_DDR_MODE_2, &ddr->sdram_mode_2); + __raw_writel(CONFIG_SYS_DDR_INTERVAL, &ddr->sdram_interval); + __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init); + __raw_writel(CONFIG_SYS_DDR_CLK_CTRL, &ddr->sdram_clk_cntl); + __raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4); + __raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5); + __raw_writel(CONFIG_SYS_DDR_ZQ_CNTL, &ddr->ddr_zq_cntl); + __raw_writel(CONFIG_SYS_DDR_WRLVL_CNTL, &ddr->ddr_wrlvl_cntl); + __raw_writel(CONFIG_SYS_DDR_CDR_1, &ddr->ddr_cdr1); + __raw_writel(CONFIG_SYS_DDR_CDR_2, &ddr->ddr_cdr2); /* Set, but do not enable the memory */ - out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN); + __raw_writel(CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN, &ddr->sdram_cfg);
asm volatile("sync;isync"); udelay(500); diff --git a/nand_spl/board/freescale/p1_p2_rdb_pc/nand_boot.c b/nand_spl/board/freescale/p1_p2_rdb_pc/nand_boot.c index e7906e8..db9b571 100644 --- a/nand_spl/board/freescale/p1_p2_rdb_pc/nand_boot.c +++ b/nand_spl/board/freescale/p1_p2_rdb_pc/nand_boot.c @@ -33,32 +33,32 @@ void sdram_init(void) { ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR;
- out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS); - out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG); + __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds); + __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config); #if CONFIG_CHIP_SELECTS_PER_CTRL > 1 - out_be32(&ddr->cs1_bnds, CONFIG_SYS_DDR_CS1_BNDS); - out_be32(&ddr->cs1_config, CONFIG_SYS_DDR_CS1_CONFIG); + __raw_writel(CONFIG_SYS_DDR_CS1_BNDS, &ddr->cs1_bnds); + __raw_writel(CONFIG_SYS_DDR_CS1_CONFIG, &ddr->cs1_config); #endif - out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); - out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0); - out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); - out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); + __raw_writel(CONFIG_SYS_DDR_TIMING_3, &ddr->timing_cfg_3); + __raw_writel(CONFIG_SYS_DDR_TIMING_0, &ddr->timing_cfg_0); + __raw_writel(CONFIG_SYS_DDR_TIMING_1, &ddr->timing_cfg_1); + __raw_writel(CONFIG_SYS_DDR_TIMING_2, &ddr->timing_cfg_2);
- out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_CONTROL_2); - out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_MODE_1); - out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2); + __raw_writel(CONFIG_SYS_DDR_CONTROL_2, &ddr->sdram_cfg_2); + __raw_writel(CONFIG_SYS_DDR_MODE_1, &ddr->sdram_mode); + __raw_writel(CONFIG_SYS_DDR_MODE_2, &ddr->sdram_mode_2);
- out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL); - out_be32(&ddr->sdram_data_init, CONFIG_SYS_DDR_DATA_INIT); - out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CTRL); + __raw_writel(CONFIG_SYS_DDR_INTERVAL, &ddr->sdram_interval); + __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init); + __raw_writel(CONFIG_SYS_DDR_CLK_CTRL, &ddr->sdram_clk_cntl);
- out_be32(&ddr->timing_cfg_4, CONFIG_SYS_DDR_TIMING_4); - out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5); - out_be32(&ddr->ddr_zq_cntl, CONFIG_SYS_DDR_ZQ_CONTROL); - out_be32(&ddr->ddr_wrlvl_cntl, CONFIG_SYS_DDR_WRLVL_CONTROL); + __raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4); + __raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5); + __raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl); + __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL, &ddr->ddr_wrlvl_cntl);
/* Set, but do not enable the memory */ - out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN); + __raw_writel(CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN, &ddr->sdram_cfg);
asm volatile("sync;isync"); udelay(500); @@ -91,13 +91,13 @@ void board_init_f(ulong bootflag)
#ifndef CONFIG_QE /* init DDR3 reset signal */ - out_be32(&pgpio->gpdir, 0x02000000); - out_be32(&pgpio->gpodr, 0x00200000); - out_be32(&pgpio->gpdat, 0x00000000); + __raw_writel(0x02000000, &pgpio->gpdir); + __raw_writel(0x00200000, &pgpio->gpodr); + __raw_writel(0x00000000, &pgpio->gpdat); udelay(1000); - out_be32(&pgpio->gpdat, 0x00200000); + __raw_writel(0x00200000, &pgpio->gpdat); udelay(1000); - out_be32(&pgpio->gpdir, 0x00000000); + __raw_writel(0x00000000, &pgpio->gpdir); #endif
/* Initialize the DDR3 */
On 08/13/2012 01:10 PM, Matthew McClintock wrote:
This change reduces the SPL size by removing the redundant syncs produced by out_be32 and just replies on one final sync
Done with:
sed -r '/in_be32/b; s/(out_be32)(([^,]*),\s+(.*))/__raw_writel(\3, \2)/g' -i `git grep --name-only sdram_init nand_spl/`
Signed-off-by: Matthew McClintock msm@freescale.com
nand_spl/board/freescale/p1010rdb/nand_boot.c | 54 ++++++++++----------- nand_spl/board/freescale/p1023rds/nand_boot.c | 42 ++++++++-------- nand_spl/board/freescale/p1_p2_rdb_pc/nand_boot.c | 48 +++++++++--------- 3 files changed, 71 insertions(+), 73 deletions(-)
This should come first if the other patches break without it, to preserve bisectability.
Note that I'm going to try to convert this stuff (at least one board as an example, but hopefully it should be easy enough to do additional boards once the first is done) to the new spl Really Soon Now(tm), so it doesn't make much sense to fiddle around with the old stuff right now unless I miss the merge window. I'll incorporate these changes into the new-spl version. I may do that by applying these patches first, but I'd rather they not go via the mpc85xx tree (and please CC me on NAND patches).
-Scott
On Mon, Aug 13, 2012 at 6:23 PM, Scott Wood scottwood@freescale.com wrote:
On 08/13/2012 01:10 PM, Matthew McClintock wrote:
This change reduces the SPL size by removing the redundant syncs produced by out_be32 and just replies on one final sync
Done with:
sed -r '/in_be32/b; s/(out_be32)(([^,]*),\s+(.*))/__raw_writel(\3, \2)/g' -i `git grep --name-only sdram_init nand_spl/`
Signed-off-by: Matthew McClintock msm@freescale.com
nand_spl/board/freescale/p1010rdb/nand_boot.c | 54 ++++++++++----------- nand_spl/board/freescale/p1023rds/nand_boot.c | 42 ++++++++-------- nand_spl/board/freescale/p1_p2_rdb_pc/nand_boot.c | 48 +++++++++--------- 3 files changed, 71 insertions(+), 73 deletions(-)
This should come first if the other patches break without it, to preserve bisectability.
I think they all work on at least some compilers.... not that that's extremely helpful.
-M
Note that I'm going to try to convert this stuff (at least one board as an example, but hopefully it should be easy enough to do additional boards once the first is done) to the new spl Really Soon Now(tm), so it doesn't make much sense to fiddle around with the old stuff right now unless I miss the merge window. I'll incorporate these changes into the new-spl version. I may do that by applying these patches first, but I'd rather they not go via the mpc85xx tree (and please CC me on NAND patches).
-Scott
U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
On 08/13/2012 06:31 PM, McClintock Matthew-B29882 wrote:
On Mon, Aug 13, 2012 at 6:23 PM, Scott Wood scottwood@freescale.com wrote:
On 08/13/2012 01:10 PM, Matthew McClintock wrote:
This change reduces the SPL size by removing the redundant syncs produced by out_be32 and just replies on one final sync
Done with:
sed -r '/in_be32/b; s/(out_be32)(([^,]*),\s+(.*))/__raw_writel(\3, \2)/g' -i `git grep --name-only sdram_init nand_spl/`
Signed-off-by: Matthew McClintock msm@freescale.com
nand_spl/board/freescale/p1010rdb/nand_boot.c | 54 ++++++++++----------- nand_spl/board/freescale/p1023rds/nand_boot.c | 42 ++++++++-------- nand_spl/board/freescale/p1_p2_rdb_pc/nand_boot.c | 48 +++++++++--------- 3 files changed, 71 insertions(+), 73 deletions(-)
This should come first if the other patches break without it, to preserve bisectability.
I think they all work on at least some compilers.... not that that's extremely helpful.
Was this patch meant to free up room for the other patches, or was it just bundled in because it's touching the same code?
-Scott
On Mon, Aug 13, 2012 at 6:34 PM, Scott Wood scottwood@freescale.com wrote:
On 08/13/2012 06:31 PM, McClintock Matthew-B29882 wrote:
On Mon, Aug 13, 2012 at 6:23 PM, Scott Wood scottwood@freescale.com wrote:
On 08/13/2012 01:10 PM, Matthew McClintock wrote:
This change reduces the SPL size by removing the redundant syncs produced by out_be32 and just replies on one final sync
Done with:
sed -r '/in_be32/b; s/(out_be32)(([^,]*),\s+(.*))/__raw_writel(\3, \2)/g' -i `git grep --name-only sdram_init nand_spl/`
Signed-off-by: Matthew McClintock msm@freescale.com
nand_spl/board/freescale/p1010rdb/nand_boot.c | 54 ++++++++++----------- nand_spl/board/freescale/p1023rds/nand_boot.c | 42 ++++++++-------- nand_spl/board/freescale/p1_p2_rdb_pc/nand_boot.c | 48 +++++++++--------- 3 files changed, 71 insertions(+), 73 deletions(-)
This should come first if the other patches break without it, to preserve bisectability.
I think they all work on at least some compilers.... not that that's extremely helpful.
Was this patch meant to free up room for the other patches, or was it just bundled in because it's touching the same code?
I believe I was tasked with fixing builds on our newer toolchains (or was it older toolchains?) since some combinations ran out of space. The exact reasoning escapes me, also why did it last a well...
I can reorder them if you would like...
-M
On 08/13/2012 06:23 PM, Scott Wood wrote:
On 08/13/2012 01:10 PM, Matthew McClintock wrote:
This change reduces the SPL size by removing the redundant syncs produced by out_be32 and just replies on one final sync
Done with:
sed -r '/in_be32/b; s/(out_be32)(([^,]*),\s+(.*))/__raw_writel(\3, \2)/g' -i `git grep --name-only sdram_init nand_spl/`
Signed-off-by: Matthew McClintock msm@freescale.com
nand_spl/board/freescale/p1010rdb/nand_boot.c | 54 ++++++++++----------- nand_spl/board/freescale/p1023rds/nand_boot.c | 42 ++++++++-------- nand_spl/board/freescale/p1_p2_rdb_pc/nand_boot.c | 48 +++++++++--------- 3 files changed, 71 insertions(+), 73 deletions(-)
This should come first if the other patches break without it, to preserve bisectability.
Note that I'm going to try to convert this stuff (at least one board as an example, but hopefully it should be easy enough to do additional boards once the first is done) to the new spl Really Soon Now(tm), so it doesn't make much sense to fiddle around with the old stuff right now unless I miss the merge window. I'll incorporate these changes into the new-spl version. I may do that by applying these patches first, but I'd rather they not go via the mpc85xx tree (and please CC me on NAND patches).
I'm not going to have this working by the end of the merge window, so these patches can go in as is. Andy, do you want to take them or should I?
-Scott
I'm ok if you take them. I should be doing a push today, so either way works for me.
On Aug 18, 2012, at 2:05 PM, Scott Wood wrote:
On 08/13/2012 06:23 PM, Scott Wood wrote:
On 08/13/2012 01:10 PM, Matthew McClintock wrote:
This change reduces the SPL size by removing the redundant syncs produced by out_be32 and just replies on one final sync
Done with:
sed -r '/in_be32/b; s/(out_be32)(([^,]*),\s+(.*))/__raw_writel(\3, \2)/g' -i `git grep --name-only sdram_init nand_spl/`
Signed-off-by: Matthew McClintock msm@freescale.com
nand_spl/board/freescale/p1010rdb/nand_boot.c | 54 ++++++++++----------- nand_spl/board/freescale/p1023rds/nand_boot.c | 42 ++++++++-------- nand_spl/board/freescale/p1_p2_rdb_pc/nand_boot.c | 48 +++++++++--------- 3 files changed, 71 insertions(+), 73 deletions(-)
This should come first if the other patches break without it, to preserve bisectability.
Note that I'm going to try to convert this stuff (at least one board as an example, but hopefully it should be easy enough to do additional boards once the first is done) to the new spl Really Soon Now(tm), so it doesn't make much sense to fiddle around with the old stuff right now unless I miss the merge window. I'll incorporate these changes into the new-spl version. I may do that by applying these patches first, but I'd rather they not go via the mpc85xx tree (and please CC me on NAND patches).
I'm not going to have this working by the end of the merge window, so these patches can go in as is. Andy, do you want to take them or should I?
-Scott
On 08/20/2012 11:11 AM, Andy Fleming wrote:
I'm ok if you take them. I should be doing a push today, so either way works for me.
If you're doing one today, go ahead and take them:
Acked-by: Scott Wood scottwood@freescale.com
-Scott
participants (4)
-
Andy Fleming -
Matthew McClintock -
McClintock Matthew-B29882 -
Scott Wood