[U-Boot] [PATCH 0/8] i.MX25: Miscellaneus fixes
These are the fixes I needed to do to get my board going.
[PATCH 1/8] i.MX25: add mxc_get_clock infrastructure
SD-controller (fsl_esdhc.c) needs a clock frequency in gd->sdhc_clk. I tried to follow the idea of other architectures.
[PATCH 2/8] i.MX: Add target flashable to offset 0
Helps flashing with openocd
[PATCH 4/8] i.MX25: Has a GPIO4 too
GPIO4 is used in our board
[PATCH 5/8] MXC FEC: Resolve speed before configuring gasket
Without this 10BaseT doesn't work
First and second OOB bytes are used for bad block indication
USB controller in the i.MX25 has PORTSC register like the controller in i.MX31
BTW, I can't understand what is the meaning of writing into &ehci->control. I can't find such a register from reference manuals of i.MX25, 28 nor 31.
[PATCH 3/8] Build: Ignore build tree and IDE control file [PATCH 6/8] i.MX25: Add Exertus EXE4026 board
Maybe these does not belong into this series but I didn't know how to exclude them from this series.
Signed-off-by: Timo Ketola timo@exertus.fi --- arch/arm/cpu/arm926ejs/mx25/generic.c | 27 +++++++++++++++++++++++++++ arch/arm/include/asm/arch-mx25/clock.h | 23 +++++++++++++++++++++++ 2 files changed, 50 insertions(+), 0 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/mx25/generic.c b/arch/arm/cpu/arm926ejs/mx25/generic.c index 9cadb7c..8b07dae 100644 --- a/arch/arm/cpu/arm926ejs/mx25/generic.c +++ b/arch/arm/cpu/arm926ejs/mx25/generic.c @@ -28,10 +28,15 @@ #include <asm/io.h> #include <asm/arch/imx-regs.h> #include <asm/arch/imx25-pinmux.h> +#include <asm/arch/clock.h> #ifdef CONFIG_MXC_MMC #include <asm/arch/mxcmmc.h> #endif
+#ifdef CONFIG_FSL_ESDHC +DECLARE_GLOBAL_DATA_PTR; +#endif + /* * get the system pll clock in Hz * @@ -105,6 +110,20 @@ ulong imx_get_perclk(int clk) return lldiv(fref, div); }
+unsigned int mxc_get_clock(enum mxc_clock clk) +{ + if (clk >= MXC_CLK_NUM) + return -1; + switch (clk) { + case MXC_ARM_CLK: + return imx_get_armclk(); + case MXC_FEC_CLK: + return imx_get_ahbclk(); + default: + return imx_get_perclk(clk); + } +} + u32 get_cpu_rev(void) { u32 srev; @@ -182,6 +201,14 @@ int cpu_eth_init(bd_t *bis) #endif }
+int get_clocks(void) +{ +#ifdef CONFIG_FSL_ESDHC + gd->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); +#endif + return 0; +} + /* * Initializes on-chip MMC controllers. * to override, implement board_mmc_init() diff --git a/arch/arm/include/asm/arch-mx25/clock.h b/arch/arm/include/asm/arch-mx25/clock.h index c59f588..0f47eaf 100644 --- a/arch/arm/include/asm/arch-mx25/clock.h +++ b/arch/arm/include/asm/arch-mx25/clock.h @@ -26,11 +26,34 @@ #ifndef __ASM_ARCH_CLOCK_H #define __ASM_ARCH_CLOCK_H
+enum mxc_clock { + MXC_CSI_CLK, + MXC_EPIT_CLK, + MXC_ESAI_CLK, + MXC_ESDHC1_CLK, + MXC_ESDHC2_CLK, + MXC_GPT_CLK, + MXC_I2C_CLK, + MXC_LCDC_CLK, + MXC_NFC_CLK, + MXC_OWIRE_CLK, + MXC_PWM_CLK, + MXC_SIM1_CLK, + MXC_SIM2_CLK, + MXC_SSI1_CLK, + MXC_SSI2_CLK, + MXC_UART_CLK, + MXC_ARM_CLK, + MXC_FEC_CLK, + MXC_CLK_NUM +}; + ulong imx_get_perclk(int clk); ulong imx_get_ahbclk(void);
#define imx_get_uartclk() imx_get_perclk(15) #define imx_get_fecclk() (imx_get_ahbclk()/2)
+unsigned int mxc_get_clock(enum mxc_clock clk);
#endif /* __ASM_ARCH_CLOCK_H */
.imx image directly from mkimage must be flashed at offset 0x400 into the nand. Thats a little hard with e.g. openocd.
Signed-off-by: Timo Ketola timo@exertus.fi --- Makefile | 3 +++ 1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/Makefile b/Makefile index 1446131..b3f1279 100644 --- a/Makefile +++ b/Makefile @@ -410,6 +410,9 @@ $(obj)u-boot.imx: $(obj)u-boot.bin $(obj)tools/mkimage -n $(CONFIG_IMX_CONFIG) -T imximage \ -e $(CONFIG_SYS_TEXT_BASE) -d $< $@
+$(obj)u-boot-nand.imx: $(obj)u-boot.imx + dd if=$< of=$@ seek=2 + $(obj)u-boot.kwb: $(obj)u-boot.bin $(obj)tools/mkimage -n $(CONFIG_SYS_KWD_CONFIG) -T kwbimage \ -a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE) -d $< $@
On 12/04/2012 11:33, Timo Ketola wrote:
.imx image directly from mkimage must be flashed at offset 0x400 into the nand. Thats a little hard with e.g. openocd.
Signed-off-by: Timo Ketola timo@exertus.fi
Hi Timo,
Makefile | 3 +++ 1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/Makefile b/Makefile index 1446131..b3f1279 100644 --- a/Makefile +++ b/Makefile @@ -410,6 +410,9 @@ $(obj)u-boot.imx: $(obj)u-boot.bin $(obj)tools/mkimage -n $(CONFIG_IMX_CONFIG) -T imximage \ -e $(CONFIG_SYS_TEXT_BASE) -d $< $@
+$(obj)u-boot-nand.imx: $(obj)u-boot.imx
dd if=$< of=$@ seek=2
I wonder why we need this in u-boot code and to set this rule in the main Makefile. You can always do this after generating u-boot.
The rules here are to generate the u-boot.imx. Then the same image can be stored at different addresses. Depending on the i.MX SOC, ofssets can be different (MX5 / MX6 have different offsets for NOR / NAND / oneNAND).
Best regards, Stefano Babic
On 12.04.2012 14:11, Stefano Babic wrote:
On 12/04/2012 11:33, Timo Ketola wrote:
+$(obj)u-boot-nand.imx: $(obj)u-boot.imx
dd if=$< of=$@ seek=2I wonder why we need this in u-boot code and to set this rule in the main Makefile. You can always do this after generating u-boot.
Older U-Boot (from FreeScale) made an .imx image with 1KB padding which I could flash directly into the NAND at offset 0. Now I had to do manually that dd-magic (before I put it in Makefile) because openocd doesn't allow to flash at offset 0x400 (it demands write-page alignment).
The rules here are to generate the u-boot.imx. Then the same image can be stored at different addresses. Depending on the i.MX SOC, ofssets can be different (MX5 / MX6 have different offsets for NOR / NAND / oneNAND).
I prefer a build system which generates an image ready for flashing but perhaps I have to do that outside of U-Boot, somehow.
--
Timo
Signed-off-by: Timo Ketola timo@exertus.fi --- .gitignore | 4 ++++ 1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/.gitignore b/.gitignore index e4e95e2..3f5eaa7 100644 --- a/.gitignore +++ b/.gitignore @@ -15,6 +15,9 @@ *.patch *.bin
+# Build tree +/build-* + # # Top-level generic files # @@ -38,6 +41,7 @@ /u-boot.ais /u-boot.dtb /u-boot.sb +/u-boot.geany
# # Generated files
On 12/04/2012 11:33, Timo Ketola wrote:
Signed-off-by: Timo Ketola timo@exertus.fi
Hi Timo,
+/u-boot.geany
What is this ? I do not find any occurency in u-boot tree.
Best regards, Stefano Babic
On 12.04.2012 14:13, Stefano Babic wrote:
+/u-boot.geany
What is this ? I do not find any occurency in u-boot tree.
It is my IDE control file. I didn't want to publish this patch at all but I have still a lot of learning about git.
--
Timo
On 12/04/2012 13:24, Timo Ketola wrote:
On 12.04.2012 14:13, Stefano Babic wrote:
+/u-boot.geany
What is this ? I do not find any occurency in u-boot tree.
It is my IDE control file. I didn't want to publish this patch at all but I have still a lot of learning about git.
Ah, ok, do not worry. I wondered what it could be.
Can be helpful for you to define your global .gitignore file for your own setup ?
You could add a ~/.gitignore with:
/build-* /uboot.gean
and then in u-boot tree you can issue the command:
$ git config --global core.excludesfile ~/.gitignore
Then all files defined in your global setting are excluded.
Best regards, Stefano Babic
Dear "Timo Ketola",
In message 1334223234-23383-4-git-send-email-timo@exertus.fi you wrote:
Signed-off-by: Timo Ketola timo@exertus.fi
.gitignore | 4 ++++ 1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/.gitignore b/.gitignore index e4e95e2..3f5eaa7 100644 --- a/.gitignore +++ b/.gitignore @@ -15,6 +15,9 @@ *.patch *.bin
+# Build tree +/build-*
# # Top-level generic files # @@ -38,6 +41,7 @@ /u-boot.ais /u-boot.dtb /u-boot.sb +/u-boot.geany
What the heck is u-boot.geany ? I cannot see anything like this in mainline.
Best regards,
Wolfgang Denk
On 09.08.2012 23:26, Wolfgang Denk wrote:
Dear "Timo Ketola",
In message 1334223234-23383-4-git-send-email-timo@exertus.fi you wrote:
Signed-off-by: Timo Ketola timo@exertus.fi
.gitignore | 4 ++++ 1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/.gitignore b/.gitignore
...
+/u-boot.geany
What the heck is u-boot.geany ? I cannot see anything like this in mainline.
It is the control file of my IDE (Geany). This patch was dropped long time ago.
--
Timo
Signed-off-by: Timo Ketola timo@exertus.fi --- drivers/gpio/mxc_gpio.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/gpio/mxc_gpio.c b/drivers/gpio/mxc_gpio.c index df6bbbb..b5972fd 100644 --- a/drivers/gpio/mxc_gpio.c +++ b/drivers/gpio/mxc_gpio.c @@ -40,7 +40,7 @@ static unsigned long gpio_ports[] = { [0] = GPIO1_BASE_ADDR, [1] = GPIO2_BASE_ADDR, [2] = GPIO3_BASE_ADDR, -#if defined(CONFIG_MX51) || defined(CONFIG_MX53) || defined(CONFIG_MX6Q) +#if defined(CONFIG_MX25) || defined(CONFIG_MX51) || defined(CONFIG_MX53) || defined(CONFIG_MX6Q) [3] = GPIO4_BASE_ADDR, #endif #if defined(CONFIG_MX53) || defined(CONFIG_MX6Q)
On 12/04/2012 11:33, Timo Ketola wrote:
Signed-off-by: Timo Ketola timo@exertus.fi
drivers/gpio/mxc_gpio.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/gpio/mxc_gpio.c b/drivers/gpio/mxc_gpio.c index df6bbbb..b5972fd 100644 --- a/drivers/gpio/mxc_gpio.c +++ b/drivers/gpio/mxc_gpio.c @@ -40,7 +40,7 @@ static unsigned long gpio_ports[] = { [0] = GPIO1_BASE_ADDR, [1] = GPIO2_BASE_ADDR, [2] = GPIO3_BASE_ADDR, -#if defined(CONFIG_MX51) || defined(CONFIG_MX53) || defined(CONFIG_MX6Q) +#if defined(CONFIG_MX25) || defined(CONFIG_MX51) || defined(CONFIG_MX53) || defined(CONFIG_MX6Q) [3] = GPIO4_BASE_ADDR, #endif #if defined(CONFIG_MX53) || defined(CONFIG_MX6Q)
Acked-by : Stefano Babic sbabic@denx.de
Best regards, Stefano Babic
Dear "Timo Ketola",
In message 1334223234-23383-5-git-send-email-timo@exertus.fi you wrote:
Signed-off-by: Timo Ketola timo@exertus.fi
drivers/gpio/mxc_gpio.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/gpio/mxc_gpio.c b/drivers/gpio/mxc_gpio.c index df6bbbb..b5972fd 100644 --- a/drivers/gpio/mxc_gpio.c +++ b/drivers/gpio/mxc_gpio.c @@ -40,7 +40,7 @@ static unsigned long gpio_ports[] = { [0] = GPIO1_BASE_ADDR, [1] = GPIO2_BASE_ADDR, [2] = GPIO3_BASE_ADDR, -#if defined(CONFIG_MX51) || defined(CONFIG_MX53) || defined(CONFIG_MX6Q) +#if defined(CONFIG_MX25) || defined(CONFIG_MX51) || defined(CONFIG_MX53) || defined(CONFIG_MX6Q)
line over 80 characters
Please make sure to run your patches through checkpatch !
Best regards,
Wolfgang Denk
Hi Timo,
On 12.04.2012 15:10, Wolfgang Denk wrote:
Please make sure to run your patches through checkpatch !
Sorry about that.
Now I could use some help about how to best edit my commits...
What works very nicely for me is to do the changes, do "git add" on them and then do a
COMMIT=<commit> ; git commit --squash=$COMMIT ; git rebase -i --autosquash ${COMMIT}^
(substitute <commit> with the commit-ID of the commit in question). In the editor you can decide to add more to the messages, or simply leave them as is.
I'm sure you will find the details on how this works and why in the manual ;)
Cheers Detlev
On 12.04.2012 16:09, Detlev Zundel wrote:
What works very nicely for me is to do the changes, do "git add" on them and then do a
COMMIT=<commit> ; git commit --squash=$COMMIT ; git rebase -i --autosquash ${COMMIT}^
Thanks - thats the kind of handholding I'm missing...
--
Timo
Signed-off-by: Timo Ketola timo@exertus.fi --- drivers/net/fec_mxc.c | 41 ++++++++++++++++++++++------------------- 1 files changed, 22 insertions(+), 19 deletions(-)
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index 1fdd071..5d11df2 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -406,6 +406,22 @@ static int fec_open(struct eth_device *edev) */ writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN, &fec->eth->ecntrl); +#ifdef CONFIG_PHYLIB + if (!fec->phydev) + fec_eth_phy_config(edev); + if (fec->phydev) { + /* Start up the PHY */ + phy_startup(fec->phydev); + speed = fec->phydev->speed; + } else { + speed = _100BASET; + } +#else + miiphy_wait_aneg(edev); + speed = miiphy_speed(edev->name, fec->phy_id); + // FIXME: useless call: miiphy_duplex(edev->name, fec->phy_id); +#endif + #if defined(CONFIG_MX25) || defined(CONFIG_MX53) udelay(100); /* @@ -418,9 +434,12 @@ static int fec_open(struct eth_device *edev) /* wait for the gasket to be disabled */ while (readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) udelay(2); - - /* configure gasket for RMII, 50 MHz, no loopback, and no echo */ - writew(MIIGSK_CFGR_IF_MODE_RMII, &fec->eth->miigsk_cfgr); + if (speed == _100BASET) + /* configure gasket for RMII, 50 MHz, no loopback, and no echo */ + writew(MIIGSK_CFGR_IF_MODE_RMII, &fec->eth->miigsk_cfgr); + else + /* configure gasket for RMII, 5 MHz, no loopback, and no echo */ + writew(MIIGSK_CFGR_IF_MODE_RMII | MIIGSK_CFGR_FRCONT, &fec->eth->miigsk_cfgr);
/* re-enable the gasket */ writew(MIIGSK_ENR_EN, &fec->eth->miigsk_enr); @@ -435,22 +454,6 @@ static int fec_open(struct eth_device *edev) } #endif
-#ifdef CONFIG_PHYLIB - if (!fec->phydev) - fec_eth_phy_config(edev); - if (fec->phydev) { - /* Start up the PHY */ - phy_startup(fec->phydev); - speed = fec->phydev->speed; - } else { - speed = _100BASET; - } -#else - miiphy_wait_aneg(edev); - speed = miiphy_speed(edev->name, fec->phy_id); - miiphy_duplex(edev->name, fec->phy_id); -#endif - #ifdef FEC_QUIRK_ENET_MAC { u32 ecr = readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_SPEED;
On 12/04/2012 11:33, Timo Ketola wrote:
Signed-off-by: Timo Ketola timo@exertus.fi
Hi Timo,
drivers/net/fec_mxc.c | 41 ++++++++++++++++++++++------------------- 1 files changed, 22 insertions(+), 19 deletions(-)
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index 1fdd071..5d11df2 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c
Please consider to rebase your patch on u-boot-imx, next branch. There are already a couple of patches related to gasket and MII.
@@ -406,6 +406,22 @@ static int fec_open(struct eth_device *edev) */ writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN, &fec->eth->ecntrl); +#ifdef CONFIG_PHYLIB
- if (!fec->phydev)
fec_eth_phy_config(edev);- if (fec->phydev) {
/* Start up the PHY */phy_startup(fec->phydev);speed = fec->phydev->speed;- } else {
speed = _100BASET;- }
+#else
- miiphy_wait_aneg(edev);
- speed = miiphy_speed(edev->name, fec->phy_id);
- // FIXME: useless call: miiphy_duplex(edev->name, fec->phy_id);
This is dead code. // comments are not allowed, comment should be real comments, not used to disable code. Why are you disabling ? Please explain the reason and, if it is required, provide a separate patch for this.
+#endif
#if defined(CONFIG_MX25) || defined(CONFIG_MX53) udelay(100); /* @@ -418,9 +434,12 @@ static int fec_open(struct eth_device *edev) /* wait for the gasket to be disabled */ while (readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) udelay(2);
- /* configure gasket for RMII, 50 MHz, no loopback, and no echo */
- writew(MIIGSK_CFGR_IF_MODE_RMII, &fec->eth->miigsk_cfgr);
- if (speed == _100BASET)
/* configure gasket for RMII, 50 MHz, no loopback, and no echo */writew(MIIGSK_CFGR_IF_MODE_RMII, &fec->eth->miigsk_cfgr);- else
/* configure gasket for RMII, 5 MHz, no loopback, and no echo */writew(MIIGSK_CFGR_IF_MODE_RMII | MIIGSK_CFGR_FRCONT, &fec->eth->miigsk_cfgr);
Right, this is correct for 10Mhz Ethernet.
Best regards, Stefano Babic
On 12.04.2012 15:05, Stefano Babic wrote:
On 12/04/2012 11:33, Timo Ketola wrote:
Signed-off-by: Timo Ketolatimo@exertus.fi
--- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c
Please consider to rebase your patch on u-boot-imx, next branch. There are already a couple of patches related to gasket and MII.
u-boot-imx is separate repository, right? So I have to clone that and apply my patches manually, right?
- // FIXME: useless call: miiphy_duplex(edev->name, fec->phy_id);
This is dead code. // comments are not allowed, comment should be real comments, not used to disable code. Why are you disabling ? Please explain the reason and, if it is required, provide a separate patch for this.
Return value is discarded and I didn't find any side effects. So it seems to be dead call. If agreed, then I'll edit the patch.
--
Timo
On 12/04/2012 15:16, Timo Ketola wrote:
On 12.04.2012 15:05, Stefano Babic wrote:
On 12/04/2012 11:33, Timo Ketola wrote:
Signed-off-by: Timo Ketolatimo@exertus.fi
--- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c
Please consider to rebase your patch on u-boot-imx, next branch. There are already a couple of patches related to gasket and MII.
u-boot-imx is separate repository, right?
Right.
So I have to clone that and apply my patches manually, right?
Yes, and maybe you should rebase some of them. Because we are very near to the release, I put new patches into the -next branch.
- // FIXME: useless call: miiphy_duplex(edev->name, fec->phy_id);
This is dead code. // comments are not allowed, comment should be real comments, not used to disable code. Why are you disabling ? Please explain the reason and, if it is required, provide a separate patch for this.
Return value is discarded and I didn't find any side effects. So it seems to be dead call. If agreed, then I'll edit the patch.
Return value is discharged, but I presume the function is called to print out the status. The function itself printf "PHY duplex" or "PHY AN duplex", that you drop if you remove the call.
Best regards, Stefano Babic
Dear "Timo Ketola",
In message 1334223234-23383-6-git-send-email-timo@exertus.fi you wrote:
Signed-off-by: Timo Ketola timo@exertus.fi
drivers/net/fec_mxc.c | 41 ++++++++++++++++++++++------------------- 1 files changed, 22 insertions(+), 19 deletions(-)
...
- // FIXME: useless call: miiphy_duplex(edev->name, fec->phy_id);
ERROR: do not use C99 // comments
/* configure gasket for RMII, 50 MHz, no loopback, and no echo */
WARNING: line over 80 characters
writew(MIIGSK_CFGR_IF_MODE_RMII, &fec->eth->miigsk_cfgr);- else
/* configure gasket for RMII, 5 MHz, no loopback, and no echo */writew(MIIGSK_CFGR_IF_MODE_RMII | MIIGSK_CFGR_FRCONT, &fec->eth->miigsk_cfgr);
WARNING: line over 80 characters
Best regards,
Wolfgang Denk
On 4/12/2012 2:33 AM, Timo Ketola wrote:
Signed-off-by: Timo Ketolatimo@exertus.fi
drivers/net/fec_mxc.c | 41 ++++++++++++++++++++++------------------- 1 files changed, 22 insertions(+), 19 deletions(-)
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index 1fdd071..5d11df2 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -406,6 +406,22 @@ static int fec_open(struct eth_device *edev) */ writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN, &fec->eth->ecntrl); +#ifdef CONFIG_PHYLIB
- if (!fec->phydev)
fec_eth_phy_config(edev);- if (fec->phydev) {
/* Start up the PHY */phy_startup(fec->phydev);speed = fec->phydev->speed;- } else {
speed = _100BASET;- }
+#else
- miiphy_wait_aneg(edev);
- speed = miiphy_speed(edev->name, fec->phy_id);
- // FIXME: useless call: miiphy_duplex(edev->name, fec->phy_id);
+#endif
- #if defined(CONFIG_MX25) || defined(CONFIG_MX53) udelay(100); /*
@@ -418,9 +434,12 @@ static int fec_open(struct eth_device *edev) /* wait for the gasket to be disabled */ while (readw(&fec->eth->miigsk_enr)& MIIGSK_ENR_READY) udelay(2);
- /* configure gasket for RMII, 50 MHz, no loopback, and no echo */
- writew(MIIGSK_CFGR_IF_MODE_RMII,&fec->eth->miigsk_cfgr);
- if (speed == _100BASET)
/* configure gasket for RMII, 50 MHz, no loopback, and no echo */writew(MIIGSK_CFGR_IF_MODE_RMII,&fec->eth->miigsk_cfgr);- else
/* configure gasket for RMII, 5 MHz, no loopback, and no echo */writew(MIIGSK_CFGR_IF_MODE_RMII | MIIGSK_CFGR_FRCONT,&fec->eth->miigsk_cfgr);
This will break gigabit speed. How about
if (speed != _10BASET)
/* re-enable the gasket */ writew(MIIGSK_ENR_EN,&fec->eth->miigsk_enr); @@ -435,22 +454,6 @@ static int fec_open(struct eth_device *edev) } #endif
-#ifdef CONFIG_PHYLIB
- if (!fec->phydev)
fec_eth_phy_config(edev);- if (fec->phydev) {
/* Start up the PHY */phy_startup(fec->phydev);speed = fec->phydev->speed;- } else {
speed = _100BASET;- }
-#else
- miiphy_wait_aneg(edev);
- speed = miiphy_speed(edev->name, fec->phy_id);
- miiphy_duplex(edev->name, fec->phy_id);
-#endif
- #ifdef FEC_QUIRK_ENET_MAC { u32 ecr = readl(&fec->eth->ecntrl)& ~FEC_ECNTRL_SPEED;
On 12.04.2012 22:59, Troy Kisky wrote:
On 4/12/2012 2:33 AM, Timo Ketola wrote:
Signed-off-by: Timo Ketolatimo@exertus.fi
- if (speed == _100BASET)
This will break gigabit speed. How about
if (speed != _10BASET)
Looks fine to me. I'll put it that way in v2.
--
Timo
Signed-off-by: Timo Ketola timo@exertus.fi --- boards.cfg | 1 + 1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/boards.cfg b/boards.cfg index 28cc345..44e80ed 100644 --- a/boards.cfg +++ b/boards.cfg @@ -155,6 +155,7 @@ rd6281a arm arm926ejs - Marvell sheevaplug arm arm926ejs - Marvell kirkwood dockstar arm arm926ejs - Seagate kirkwood jadecpu arm arm926ejs jadecpu syteco mb86r0x +exe4026 arm arm926ejs exe4026 exertus mx25 exe4026:IMX_CONFIG=board/exertus/exe4026/imximage.cfg mx25pdk arm arm926ejs mx25pdk freescale mx25 mx25pdk:IMX_CONFIG=board/freescale/mx25pdk/imximage.cfg tx25 arm arm926ejs tx25 karo mx25 zmx25 arm arm926ejs zmx25 syteco mx25
Hi Timo,
On Thu, Apr 12, 2012 at 6:33 AM, Timo Ketola timo@exertus.fi wrote:
Signed-off-by: Timo Ketola timo@exertus.fi
boards.cfg | Â Â 1 + Â 1 files changed, 1 insertions(+), 0 deletions(-)
Thanks for your contributions.
Please provide some more details in the commit message about this board, which peripherals are currently supported, where does it boot from, etc.
Please also add an entry for your board in the MAINTAINERS file.
You seem to have missed to do a "git add" for the files you introduced here ,ie, board/exertus/exe4026/ directory.
On 12.04.2012 13:43, Fabio Estevam wrote:
Please provide some more details in the commit message about this board, which peripherals are currently supported, where does it boot from, etc.
Please also add an entry for your board in the MAINTAINERS file.
You seem to have missed to do a "git add" for the files you introduced here ,ie, board/exertus/exe4026/ directory.
Yes, I will, but actually I didn't want to publish my board specific files and changes just yet. I committed all those changes into my git tree but now I don't know how to exclude this one (6/8, and perhaps 3/8) from git-send-email to send a cleaner series. I don't know either how to use git-send-email to send a single patch. I'll need to learn more about git - or can you or somebody here tell me right away? Do I perhaps have to create a second branch where I merge the relevant commits?
--
Timo
On 12/04/2012 11:33, Timo Ketola wrote:
Signed-off-by: Timo Ketola timo@exertus.fi
boards.cfg | 1 + 1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/boards.cfg b/boards.cfg index 28cc345..44e80ed 100644 --- a/boards.cfg +++ b/boards.cfg @@ -155,6 +155,7 @@ rd6281a arm arm926ejs - Marvell sheevaplug arm arm926ejs - Marvell kirkwood dockstar arm arm926ejs - Seagate kirkwood jadecpu arm arm926ejs jadecpu syteco mb86r0x +exe4026 arm arm926ejs exe4026 exertus mx25 exe4026:IMX_CONFIG=board/exertus/exe4026/imximage.cfg mx25pdk arm arm926ejs mx25pdk freescale mx25 mx25pdk:IMX_CONFIG=board/freescale/mx25pdk/imximage.cfg tx25 arm arm926ejs tx25 karo mx25 zmx25 arm arm926ejs zmx25 syteco mx25
I assume you write also some code for this board. Maybe forgotten ?
Best regards, Stefano Babic
On 12.04.2012 15:06, Stefano Babic wrote:
+exe4026 arm arm926ejs exe4026 exertus mx25 exe4026:IMX_CONFIG=board/exertus/exe4026/imximage.cfg
I assume you write also some code for this board. Maybe forgotten ?
Yes, later. I have hard time with git-send-email selecting exactly what I want to send.
--
Timo
On 12/04/2012 14:09, Timo Ketola wrote:
On 12.04.2012 15:06, Stefano Babic wrote:
+exe4026 arm arm926ejs exe4026 exertus mx25 exe4026:IMX_CONFIG=board/exertus/exe4026/imximage.cfg
Hi Timo,
I assume you write also some code for this board. Maybe forgotten ?
Yes, later. I have hard time with git-send-email selecting exactly what I want to send.
If you don't already know, maybe this site can help:
http://www.denx.de/wiki/U-Boot/Patches
And if I understand what you are want, maybe the simple way is to add a branch and to cherry-pick (git cherry-pick) only the commit you want later send from your main branch. Then you can run "git format patch" to get the patchset.
Please also add always a changelog in your patches, so we can easy find changes from previous versions. And please help us adding in CC the maintainer of the subsystem your patch is thought to change (me for i.MX related parts).
Best regards, Stefano Babic
Signed-off-by: Timo Ketola timo@exertus.fi --- drivers/mtd/nand/mxc_nand.c | 35 +++++++++++++++++++++++++++++++++++ 1 files changed, 35 insertions(+), 0 deletions(-)
diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c index 35e89a0..73813a2 100644 --- a/drivers/mtd/nand/mxc_nand.c +++ b/drivers/mtd/nand/mxc_nand.c @@ -1302,12 +1302,47 @@ static void mxc_setup_config1(void) #define mxc_setup_config1() #endif
+#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT + +static u8 bbt_pattern[] = {'B', 'b', 't', '0' }; +static u8 mirror_pattern[] = {'1', 't', 'b', 'B' }; + +static struct nand_bbt_descr bbt_main_descr = { + .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | + NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, + .offs = 2, + .len = 4, + .veroffs = 6, + .maxblocks = 4, + .pattern = bbt_pattern, +}; + +static struct nand_bbt_descr bbt_mirror_descr = { + .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | + NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, + .offs = 2, + .len = 4, + .veroffs = 6, + .maxblocks = 4, + .pattern = mirror_pattern, +}; + +#endif + int board_nand_init(struct nand_chip *this) { struct mtd_info *mtd; uint16_t tmp; int err = 0;
+#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT + + this->options = NAND_USE_FLASH_BBT; + this->bbt_td = &bbt_main_descr; + this->bbt_md = &bbt_mirror_descr; + +#endif + /* structures must be linked */ mtd = &host->mtd; mtd->priv = this;
Signed-off-by: Timo Ketola timo@exertus.fi --- drivers/usb/host/ehci-mxc.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/usb/host/ehci-mxc.c b/drivers/usb/host/ehci-mxc.c index 61dbccd..65f40a4 100644 --- a/drivers/usb/host/ehci-mxc.c +++ b/drivers/usb/host/ehci-mxc.c @@ -125,7 +125,7 @@ int ehci_hcd_init(void) hcor = (struct ehci_hcor *)((uint32_t) hccr + HC_LENGTH(ehci_readl(&hccr->cr_capbase))); setbits_le32(&ehci->usbmode, CM_HOST); -#ifdef CONFIG_MX31 +#if defined(CONFIG_MX31) || defined(CONFIG_MX25) setbits_le32(&ehci->control, USB_EN);
__raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
These are the fixes I needed to do to get my board going.
Changes in v2: - Rebased to u-boot-imx next - Patch 2: Fixed too long lines - Patch 3: Try not to break Gbit ether Changed configuration option putting gasket into RMII mode to CONFIG_RMII I'm not too sure how this should be done. CONFIG_MII is normally used for this but its original purpose was to enable MII *management* interface, I think... - Patch 9: Add .imx target in the spirit of commit 303838
Defining CONFIG_FSL_ESDHC brings in a call to get_clocks, so let's implement get_clocks function. This is how it seems to be implemented elsewhere.
Signed-off-by: Timo Ketola timo@exertus.fi --- arch/arm/cpu/arm926ejs/mx25/generic.c | 27 +++++++++++++++++++++++++++ arch/arm/include/asm/arch-mx25/clock.h | 23 +++++++++++++++++++++++ 2 files changed, 50 insertions(+), 0 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/mx25/generic.c b/arch/arm/cpu/arm926ejs/mx25/generic.c index 9cadb7c..8b07dae 100644 --- a/arch/arm/cpu/arm926ejs/mx25/generic.c +++ b/arch/arm/cpu/arm926ejs/mx25/generic.c @@ -28,10 +28,15 @@ #include <asm/io.h> #include <asm/arch/imx-regs.h> #include <asm/arch/imx25-pinmux.h> +#include <asm/arch/clock.h> #ifdef CONFIG_MXC_MMC #include <asm/arch/mxcmmc.h> #endif
+#ifdef CONFIG_FSL_ESDHC +DECLARE_GLOBAL_DATA_PTR; +#endif + /* * get the system pll clock in Hz * @@ -105,6 +110,20 @@ ulong imx_get_perclk(int clk) return lldiv(fref, div); }
+unsigned int mxc_get_clock(enum mxc_clock clk) +{ + if (clk >= MXC_CLK_NUM) + return -1; + switch (clk) { + case MXC_ARM_CLK: + return imx_get_armclk(); + case MXC_FEC_CLK: + return imx_get_ahbclk(); + default: + return imx_get_perclk(clk); + } +} + u32 get_cpu_rev(void) { u32 srev; @@ -182,6 +201,14 @@ int cpu_eth_init(bd_t *bis) #endif }
+int get_clocks(void) +{ +#ifdef CONFIG_FSL_ESDHC + gd->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); +#endif + return 0; +} + /* * Initializes on-chip MMC controllers. * to override, implement board_mmc_init() diff --git a/arch/arm/include/asm/arch-mx25/clock.h b/arch/arm/include/asm/arch-mx25/clock.h index c59f588..0f47eaf 100644 --- a/arch/arm/include/asm/arch-mx25/clock.h +++ b/arch/arm/include/asm/arch-mx25/clock.h @@ -26,11 +26,34 @@ #ifndef __ASM_ARCH_CLOCK_H #define __ASM_ARCH_CLOCK_H
+enum mxc_clock { + MXC_CSI_CLK, + MXC_EPIT_CLK, + MXC_ESAI_CLK, + MXC_ESDHC1_CLK, + MXC_ESDHC2_CLK, + MXC_GPT_CLK, + MXC_I2C_CLK, + MXC_LCDC_CLK, + MXC_NFC_CLK, + MXC_OWIRE_CLK, + MXC_PWM_CLK, + MXC_SIM1_CLK, + MXC_SIM2_CLK, + MXC_SSI1_CLK, + MXC_SSI2_CLK, + MXC_UART_CLK, + MXC_ARM_CLK, + MXC_FEC_CLK, + MXC_CLK_NUM +}; + ulong imx_get_perclk(int clk); ulong imx_get_ahbclk(void);
#define imx_get_uartclk() imx_get_perclk(15) #define imx_get_fecclk() (imx_get_ahbclk()/2)
+unsigned int mxc_get_clock(enum mxc_clock clk);
#endif /* __ASM_ARCH_CLOCK_H */
Signed-off-by: Timo Ketola timo@exertus.fi --- drivers/gpio/mxc_gpio.c | 3 ++- 1 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/drivers/gpio/mxc_gpio.c b/drivers/gpio/mxc_gpio.c index df6bbbb..3e94ac3 100644 --- a/drivers/gpio/mxc_gpio.c +++ b/drivers/gpio/mxc_gpio.c @@ -40,7 +40,8 @@ static unsigned long gpio_ports[] = { [0] = GPIO1_BASE_ADDR, [1] = GPIO2_BASE_ADDR, [2] = GPIO3_BASE_ADDR, -#if defined(CONFIG_MX51) || defined(CONFIG_MX53) || defined(CONFIG_MX6Q) +#if defined(CONFIG_MX25) || defined(CONFIG_MX51) || defined(CONFIG_MX53) || \ + defined(CONFIG_MX6Q) [3] = GPIO4_BASE_ADDR, #endif #if defined(CONFIG_MX53) || defined(CONFIG_MX6Q)
Gasket needs a different configuration for 10BaseT than for higher speeds.
Signed-off-by: Timo Ketola timo@exertus.fi --- drivers/net/fec_mxc.c | 43 ++++++++++++++++++++++++------------------- 1 files changed, 24 insertions(+), 19 deletions(-)
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index 824a199..48a69d4 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -440,6 +440,22 @@ static int fec_open(struct eth_device *edev) */ writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN, &fec->eth->ecntrl); +#ifdef CONFIG_PHYLIB + if (!fec->phydev) + fec_eth_phy_config(edev); + if (fec->phydev) { + /* Start up the PHY */ + phy_startup(fec->phydev); + speed = fec->phydev->speed; + } else { + speed = _100BASET; + } +#else + miiphy_wait_aneg(edev); + speed = miiphy_speed(edev->name, fec->phy_id); + miiphy_duplex(edev->name, fec->phy_id); +#endif + #if defined(CONFIG_MX25) || defined(CONFIG_MX53) udelay(100); /* @@ -453,9 +469,14 @@ static int fec_open(struct eth_device *edev) while (readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) udelay(2);
-#if !defined(CONFIG_MII) - /* configure gasket for RMII, 50 MHz, no loopback, and no echo */ - writew(MIIGSK_CFGR_IF_MODE_RMII, &fec->eth->miigsk_cfgr); +#if defined(CONFIG_RMII) + if (speed != _10BASET) + /* configure gasket for RMII, 50MHz, no loopback, and no echo */ + writew(MIIGSK_CFGR_IF_MODE_RMII, &fec->eth->miigsk_cfgr); + else + /* configure gasket for RMII, 5MHz, no loopback, and no echo */ + writew(MIIGSK_CFGR_IF_MODE_RMII | MIIGSK_CFGR_FRCONT, + &fec->eth->miigsk_cfgr); #else /* configure gasket for MII, no loopback, and no echo */ writew(MIIGSK_CFGR_IF_MODE_MII, &fec->eth->miigsk_cfgr); @@ -474,22 +495,6 @@ static int fec_open(struct eth_device *edev) } #endif
-#ifdef CONFIG_PHYLIB - if (!fec->phydev) - fec_eth_phy_config(edev); - if (fec->phydev) { - /* Start up the PHY */ - phy_startup(fec->phydev); - speed = fec->phydev->speed; - } else { - speed = _100BASET; - } -#else - miiphy_wait_aneg(edev); - speed = miiphy_speed(edev->name, fec->phy_id); - miiphy_duplex(edev->name, fec->phy_id); -#endif - #ifdef FEC_QUIRK_ENET_MAC { u32 ecr = readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_SPEED;
First two bytes of the first OOB of erase block are reserved for factory bad block marking, usually.
Signed-off-by: Timo Ketola timo@exertus.fi --- drivers/mtd/nand/mxc_nand.c | 35 +++++++++++++++++++++++++++++++++++ 1 files changed, 35 insertions(+), 0 deletions(-)
diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c index 35e89a0..73813a2 100644 --- a/drivers/mtd/nand/mxc_nand.c +++ b/drivers/mtd/nand/mxc_nand.c @@ -1302,12 +1302,47 @@ static void mxc_setup_config1(void) #define mxc_setup_config1() #endif
+#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT + +static u8 bbt_pattern[] = {'B', 'b', 't', '0' }; +static u8 mirror_pattern[] = {'1', 't', 'b', 'B' }; + +static struct nand_bbt_descr bbt_main_descr = { + .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | + NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, + .offs = 2, + .len = 4, + .veroffs = 6, + .maxblocks = 4, + .pattern = bbt_pattern, +}; + +static struct nand_bbt_descr bbt_mirror_descr = { + .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | + NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, + .offs = 2, + .len = 4, + .veroffs = 6, + .maxblocks = 4, + .pattern = mirror_pattern, +}; + +#endif + int board_nand_init(struct nand_chip *this) { struct mtd_info *mtd; uint16_t tmp; int err = 0;
+#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT + + this->options = NAND_USE_FLASH_BBT; + this->bbt_td = &bbt_main_descr; + this->bbt_md = &bbt_mirror_descr; + +#endif + /* structures must be linked */ mtd = &host->mtd; mtd->priv = this;
On 04/13/2012 06:20 AM, Timo Ketola wrote:
First two bytes of the first OOB of erase block are reserved for factory bad block marking, usually.
Signed-off-by: Timo Ketola timo@exertus.fi
drivers/mtd/nand/mxc_nand.c | 35 +++++++++++++++++++++++++++++++++++ 1 files changed, 35 insertions(+), 0 deletions(-)
So what happened before? The default is at offset 8, which doesn't conflict with the bad block marker. It seems the actual issue is a conflict with ECC?
And NAND_USE_FLASH_BBT wasn't defined before, so a better subject line for this patch would be "nand/mxc: support flash-based BBT".
diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c index 35e89a0..73813a2 100644 --- a/drivers/mtd/nand/mxc_nand.c +++ b/drivers/mtd/nand/mxc_nand.c @@ -1302,12 +1302,47 @@ static void mxc_setup_config1(void) #define mxc_setup_config1() #endif
+#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
+static u8 bbt_pattern[] = {'B', 'b', 't', '0' }; +static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
+static struct nand_bbt_descr bbt_main_descr = {
- .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,- .offs = 2,
- .len = 4,
- .veroffs = 6,
- .maxblocks = 4,
- .pattern = bbt_pattern,
+};
+static struct nand_bbt_descr bbt_mirror_descr = {
- .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,- .offs = 2,
- .len = 4,
- .veroffs = 6,
- .maxblocks = 4,
- .pattern = mirror_pattern,
+};
+#endif
Won't veroffs = 6 conflict with ECC in the MXC_NFC_V1 case?
What about 8-bit small page support, in which case the bad block marker is at offset 5?
int board_nand_init(struct nand_chip *this) { struct mtd_info *mtd; uint16_t tmp; int err = 0;
+#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
- this->options = NAND_USE_FLASH_BBT;
- this->bbt_td = &bbt_main_descr;
- this->bbt_md = &bbt_mirror_descr;
+#endif
Please remove those blank lines inside the ifdef.
-Scott
On 13.04.2012 20:19, Scott Wood wrote:
On 04/13/2012 06:20 AM, Timo Ketola wrote:
First two bytes of the first OOB of erase block are reserved for factory bad block marking, usually.
Signed-off-by: Timo Ketolatimo@exertus.fi
drivers/mtd/nand/mxc_nand.c | 35 +++++++++++++++++++++++++++++++++++ 1 files changed, 35 insertions(+), 0 deletions(-)
So what happened before? The default is at offset 8, which doesn't conflict with the bad block marker. It seems the actual issue is a conflict with ECC?
You seem to be right. I think I was badly confused with the kernel behaviour.
And NAND_USE_FLASH_BBT wasn't defined before, so a better subject line for this patch would be "nand/mxc: support flash-based BBT".
Most probably right too.
Won't veroffs = 6 conflict with ECC in the MXC_NFC_V1 case?
Seems to.
What about 8-bit small page support, in which case the bad block marker is at offset 5?
What about putting into the block
#if defined(MXC_NFC_V1) #ifndef CONFIG_SYS_NAND_LARGEPAGE
defines for pattern and version offsets and use them in bbt_*_descr initializations? Or should they be in board configuration file?
+#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
- this->options = NAND_USE_FLASH_BBT;
- this->bbt_td =&bbt_main_descr;
- this->bbt_md =&bbt_mirror_descr;
+#endif
Please remove those blank lines inside the ifdef.
Ok
--
Timo
On 04/13/2012 01:12 PM, Timo Ketola wrote:
On 13.04.2012 20:19, Scott Wood wrote:
On 04/13/2012 06:20 AM, Timo Ketola wrote:
First two bytes of the first OOB of erase block are reserved for factory bad block marking, usually.
Signed-off-by: Timo Ketolatimo@exertus.fi
drivers/mtd/nand/mxc_nand.c | 35 +++++++++++++++++++++++++++++++++++ 1 files changed, 35 insertions(+), 0 deletions(-)
So what happened before? The default is at offset 8, which doesn't conflict with the bad block marker. It seems the actual issue is a conflict with ECC?
You seem to be right. I think I was badly confused with the kernel behaviour.
It looks like Linux wants the BBT to be at offset zero. Is there any plan to fix that? The two really should match...
What about 8-bit small page support, in which case the bad block marker is at offset 5?
What about putting into the block
#if defined(MXC_NFC_V1) #ifndef CONFIG_SYS_NAND_LARGEPAGE
defines for pattern and version offsets and use them in bbt_*_descr initializations?
Sure.
Or should they be in board configuration file?
I don't think it belongs in the board config file (unless there's existing behavior that has to be matched for compatibility on a specific board).
-Scott
On 13.04.2012 21:17, Scott Wood wrote:
It looks like Linux wants the BBT to be at offset zero.
I have not dug too deeply into the BBT logic in kernel but maybe it could be possible to place BBT patterns over the factory markers. Then, when the code scans for BBT blocks, it should ignore factory markers and react only on BBT patterns. But I don't really know if this is the idea in kernel.
--
Timo
On 13.04.2012 21:17, Scott Wood wrote:
It looks like Linux wants the BBT to be at offset zero. Is there any plan to fix that? The two really should match...
Somewhere in the process I got an impression that BBT couldn't be placed over the area where factory markers would be. But you made me think and I reverted the offset in my kernel back to zero and changed U-Boot accordingly. It seems to work perfectly like that. So I think now that the offset at zero is right.
Should I post v3 patchset now or only this one again or minimize noise and wait for more comments?
--
Timo
Signed-off-by: Timo Ketola timo@exertus.fi --- drivers/usb/host/ehci-mxc.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/usb/host/ehci-mxc.c b/drivers/usb/host/ehci-mxc.c index 61dbccd..65f40a4 100644 --- a/drivers/usb/host/ehci-mxc.c +++ b/drivers/usb/host/ehci-mxc.c @@ -125,7 +125,7 @@ int ehci_hcd_init(void) hcor = (struct ehci_hcor *)((uint32_t) hccr + HC_LENGTH(ehci_readl(&hccr->cr_capbase))); setbits_le32(&ehci->usbmode, CM_HOST); -#ifdef CONFIG_MX31 +#if defined(CONFIG_MX31) || defined(CONFIG_MX25) setbits_le32(&ehci->control, USB_EN);
__raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
The reference manual of i.MX25 (nor i.MX31) does not define such register. This seems to access read only UH2_CAPLENGTH register (if CONFIG_MXC_USB_PORT is zero).
Signed-off-by: Timo Ketola timo@exertus.fi --- drivers/usb/host/ehci-mxc.c | 2 -- 1 files changed, 0 insertions(+), 2 deletions(-)
diff --git a/drivers/usb/host/ehci-mxc.c b/drivers/usb/host/ehci-mxc.c index 65f40a4..6f4df58 100644 --- a/drivers/usb/host/ehci-mxc.c +++ b/drivers/usb/host/ehci-mxc.c @@ -126,8 +126,6 @@ int ehci_hcd_init(void) HC_LENGTH(ehci_readl(&hccr->cr_capbase))); setbits_le32(&ehci->usbmode, CM_HOST); #if defined(CONFIG_MX31) || defined(CONFIG_MX25) - setbits_le32(&ehci->control, USB_EN); - __raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc); #endif mxc_set_usbcontrol(CONFIG_MXC_USB_PORT, CONFIG_MXC_USB_FLAGS);
One might want to define CONFIG_SYS_FSL_ESDHC_ADDR with the macro already define in imx-regs.h, e.g. with IMX_MMC_SDHC1_BASE. Then the header must be included here.
Signed-off-by: Timo Ketola timo@exertus.fi --- drivers/mmc/fsl_esdhc.c | 1 + 1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index a2f35e3..5ada747 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -36,6 +36,7 @@ #include <fsl_esdhc.h> #include <fdt_support.h> #include <asm/io.h> +#include <asm/arch/imx-regs.h>
DECLARE_GLOBAL_DATA_PTR;
There is already CONFIG_SYS_NAND_BASE (or CONFIG_SYS_NAND_BASE_LIST) which must be defined for nand.c. Use that. nand.c sets IO_ADDR_R with that.
Signed-off-by: Timo Ketola timo@exertus.fi --- drivers/mtd/nand/mxc_nand.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c index 73813a2..fcee20d 100644 --- a/drivers/mtd/nand/mxc_nand.c +++ b/drivers/mtd/nand/mxc_nand.c @@ -1361,7 +1361,7 @@ int board_nand_init(struct nand_chip *this) this->read_buf = mxc_nand_read_buf; this->verify_buf = mxc_nand_verify_buf;
- host->regs = (struct nfc_regs __iomem *)CONFIG_MXC_NAND_REGS_BASE; + host->regs = this->IO_ADDR_R; host->clk_act = 1;
#ifdef CONFIG_MXC_NAND_HWECC
On 04/13/2012 06:21 AM, Timo Ketola wrote:
There is already CONFIG_SYS_NAND_BASE (or CONFIG_SYS_NAND_BASE_LIST) which must be defined for nand.c. Use that. nand.c sets IO_ADDR_R with that.
Signed-off-by: Timo Ketola timo@exertus.fi
drivers/mtd/nand/mxc_nand.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c index 73813a2..fcee20d 100644 --- a/drivers/mtd/nand/mxc_nand.c +++ b/drivers/mtd/nand/mxc_nand.c @@ -1361,7 +1361,7 @@ int board_nand_init(struct nand_chip *this) this->read_buf = mxc_nand_read_buf; this->verify_buf = mxc_nand_verify_buf;
- host->regs = (struct nfc_regs __iomem *)CONFIG_MXC_NAND_REGS_BASE;
- host->regs = this->IO_ADDR_R; host->clk_act = 1;
#ifdef CONFIG_MXC_NAND_HWECC
Actually, I'd rather we go the other direction and deprecate CONFIG_SYS_NAND_BASE (see CONFIG_SYS_NAND_SELF_INIT).
-Scott
On 13.04.2012 20:21, Scott Wood wrote:
On 04/13/2012 06:21 AM, Timo Ketola wrote:
There is already CONFIG_SYS_NAND_BASE (or CONFIG_SYS_NAND_BASE_LIST) which must be defined for nand.c. Use that. nand.c sets IO_ADDR_R with that. ...
Actually, I'd rather we go the other direction and deprecate CONFIG_SYS_NAND_BASE (see CONFIG_SYS_NAND_SELF_INIT).
Maybe it's better for me to drop this patch...
--
Timo
Signed-off-by: Timo Ketola timo@exertus.fi --- arch/arm/cpu/arm926ejs/config.mk | 6 ++++++ 1 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/config.mk b/arch/arm/cpu/arm926ejs/config.mk index ffb2e6c..6a3a1bb 100644 --- a/arch/arm/cpu/arm926ejs/config.mk +++ b/arch/arm/cpu/arm926ejs/config.mk @@ -31,3 +31,9 @@ PLATFORM_CPPFLAGS += -march=armv5te # ========================================================================= PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT) + +ifneq ($(CONFIG_IMX_CONFIG),) + +ALL-y += $(obj)u-boot.imx + +endif
These are the fixes I needed to do to get my board going.
Changes in v3: - Dropped old patch number 8 "imx: nand: Don't invent new..." - Changed the subject of patch 4 - Changed the BBT pattern offsets (patch 4); They are now zero as in Linux
Changes in v2: - Rebased to u-boot-imx next - Patch 2: Fixed too long lines - Patch 3: Try not to break Gbit ether Changed configuration option putting gasket into RMII mode to CONFIG_RMII I'm not too sure how this should be done. CONFIG_MII is normally used for this but its original purpose was to enable MII *management* interface, I think... - Patch 9: Add .imx target in the spirit of commit 303838
Defining CONFIG_FSL_ESDHC brings in a call to get_clocks, so let's implement get_clocks function. This is how it seems to be implemented elsewhere.
Signed-off-by: Timo Ketola timo@exertus.fi --- arch/arm/cpu/arm926ejs/mx25/generic.c | 27 +++++++++++++++++++++++++++ arch/arm/include/asm/arch-mx25/clock.h | 23 +++++++++++++++++++++++ 2 files changed, 50 insertions(+), 0 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/mx25/generic.c b/arch/arm/cpu/arm926ejs/mx25/generic.c index 9cadb7c..8b07dae 100644 --- a/arch/arm/cpu/arm926ejs/mx25/generic.c +++ b/arch/arm/cpu/arm926ejs/mx25/generic.c @@ -28,10 +28,15 @@ #include <asm/io.h> #include <asm/arch/imx-regs.h> #include <asm/arch/imx25-pinmux.h> +#include <asm/arch/clock.h> #ifdef CONFIG_MXC_MMC #include <asm/arch/mxcmmc.h> #endif
+#ifdef CONFIG_FSL_ESDHC +DECLARE_GLOBAL_DATA_PTR; +#endif + /* * get the system pll clock in Hz * @@ -105,6 +110,20 @@ ulong imx_get_perclk(int clk) return lldiv(fref, div); }
+unsigned int mxc_get_clock(enum mxc_clock clk) +{ + if (clk >= MXC_CLK_NUM) + return -1; + switch (clk) { + case MXC_ARM_CLK: + return imx_get_armclk(); + case MXC_FEC_CLK: + return imx_get_ahbclk(); + default: + return imx_get_perclk(clk); + } +} + u32 get_cpu_rev(void) { u32 srev; @@ -182,6 +201,14 @@ int cpu_eth_init(bd_t *bis) #endif }
+int get_clocks(void) +{ +#ifdef CONFIG_FSL_ESDHC + gd->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); +#endif + return 0; +} + /* * Initializes on-chip MMC controllers. * to override, implement board_mmc_init() diff --git a/arch/arm/include/asm/arch-mx25/clock.h b/arch/arm/include/asm/arch-mx25/clock.h index c59f588..0f47eaf 100644 --- a/arch/arm/include/asm/arch-mx25/clock.h +++ b/arch/arm/include/asm/arch-mx25/clock.h @@ -26,11 +26,34 @@ #ifndef __ASM_ARCH_CLOCK_H #define __ASM_ARCH_CLOCK_H
+enum mxc_clock { + MXC_CSI_CLK, + MXC_EPIT_CLK, + MXC_ESAI_CLK, + MXC_ESDHC1_CLK, + MXC_ESDHC2_CLK, + MXC_GPT_CLK, + MXC_I2C_CLK, + MXC_LCDC_CLK, + MXC_NFC_CLK, + MXC_OWIRE_CLK, + MXC_PWM_CLK, + MXC_SIM1_CLK, + MXC_SIM2_CLK, + MXC_SSI1_CLK, + MXC_SSI2_CLK, + MXC_UART_CLK, + MXC_ARM_CLK, + MXC_FEC_CLK, + MXC_CLK_NUM +}; + ulong imx_get_perclk(int clk); ulong imx_get_ahbclk(void);
#define imx_get_uartclk() imx_get_perclk(15) #define imx_get_fecclk() (imx_get_ahbclk()/2)
+unsigned int mxc_get_clock(enum mxc_clock clk);
#endif /* __ASM_ARCH_CLOCK_H */
Dear "Timo Ketola",
In message 1334735852-23415-2-git-send-email-timo@exertus.fi you wrote:
Defining CONFIG_FSL_ESDHC brings in a call to get_clocks, so let's implement get_clocks function. This is how it seems to be implemented elsewhere.
Signed-off-by: Timo Ketola timo@exertus.fi
arch/arm/cpu/arm926ejs/mx25/generic.c | 27 +++++++++++++++++++++++++++ arch/arm/include/asm/arch-mx25/clock.h | 23 +++++++++++++++++++++++ 2 files changed, 50 insertions(+), 0 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/mx25/generic.c b/arch/arm/cpu/arm926ejs/mx25/generic.c
...
I understand this is a (eventually modified ?) reposting of patches you posted before. in this case it is mandatory not only to mark this in the Subject, but also to provide a detailled change log (below the "---" line); see http://www.denx.de/wiki/view/U-Boot/Patches#Sending_updated_patch_versions
I'm not going to try to find out which review comments you have included, and what you changed to do so; sorry, but I don;t have that much time.
Please consider the whole patch series ignored.
Best regards,
Wolfgang Denk
On 18.04.2012 12:23, Wolfgang Denk wrote:
Dear "Timo Ketola",
In message1334735852-23415-2-git-send-email-timo@exertus.fi you wrote:
Defining CONFIG_FSL_ESDHC brings in a call to get_clocks, so let's implement get_clocks function. This is how it seems to be implemented elsewhere. ...
...
I understand this is a (eventually modified ?) reposting of patches you posted before.
Yes
in this case it is mandatory not only to mark this in the Subject,
Ok, how to do that I learned just now.
but also to provide a detailled change log (below the "---" line); see http://www.denx.de/wiki/view/U-Boot/Patches#Sending_updated_patch_versions
I tried to provide that in the 0/x message but do you mean that I should provide it separately for every single patch? I see that your reference asks just that.
I was in impression that 'git send-email' (alone) would do the right thing but it doesn't give me opportunity to edit actual patch messages, only the cover letter. And I saw many examples of people putting the log in the cover letter. So how do people do that? 'git format-patch' then manually edit patch files, then send them with 'git send-email'?
I'm not going to try to find out which review comments you have included, and what you changed to do so; sorry, but I don;t have that much time.
So do I have to reference review comments somehow?
Please consider the whole patch series ignored.
Ok
--
Timo
Signed-off-by: Timo Ketola timo@exertus.fi --- drivers/gpio/mxc_gpio.c | 3 ++- 1 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/drivers/gpio/mxc_gpio.c b/drivers/gpio/mxc_gpio.c index df6bbbb..3e94ac3 100644 --- a/drivers/gpio/mxc_gpio.c +++ b/drivers/gpio/mxc_gpio.c @@ -40,7 +40,8 @@ static unsigned long gpio_ports[] = { [0] = GPIO1_BASE_ADDR, [1] = GPIO2_BASE_ADDR, [2] = GPIO3_BASE_ADDR, -#if defined(CONFIG_MX51) || defined(CONFIG_MX53) || defined(CONFIG_MX6Q) +#if defined(CONFIG_MX25) || defined(CONFIG_MX51) || defined(CONFIG_MX53) || \ + defined(CONFIG_MX6Q) [3] = GPIO4_BASE_ADDR, #endif #if defined(CONFIG_MX53) || defined(CONFIG_MX6Q)
Gasket needs a different configuration for 10BaseT than for higher speeds.
Signed-off-by: Timo Ketola timo@exertus.fi --- drivers/net/fec_mxc.c | 43 ++++++++++++++++++++++++------------------- 1 files changed, 24 insertions(+), 19 deletions(-)
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index 824a199..48a69d4 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -440,6 +440,22 @@ static int fec_open(struct eth_device *edev) */ writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN, &fec->eth->ecntrl); +#ifdef CONFIG_PHYLIB + if (!fec->phydev) + fec_eth_phy_config(edev); + if (fec->phydev) { + /* Start up the PHY */ + phy_startup(fec->phydev); + speed = fec->phydev->speed; + } else { + speed = _100BASET; + } +#else + miiphy_wait_aneg(edev); + speed = miiphy_speed(edev->name, fec->phy_id); + miiphy_duplex(edev->name, fec->phy_id); +#endif + #if defined(CONFIG_MX25) || defined(CONFIG_MX53) udelay(100); /* @@ -453,9 +469,14 @@ static int fec_open(struct eth_device *edev) while (readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) udelay(2);
-#if !defined(CONFIG_MII) - /* configure gasket for RMII, 50 MHz, no loopback, and no echo */ - writew(MIIGSK_CFGR_IF_MODE_RMII, &fec->eth->miigsk_cfgr); +#if defined(CONFIG_RMII) + if (speed != _10BASET) + /* configure gasket for RMII, 50MHz, no loopback, and no echo */ + writew(MIIGSK_CFGR_IF_MODE_RMII, &fec->eth->miigsk_cfgr); + else + /* configure gasket for RMII, 5MHz, no loopback, and no echo */ + writew(MIIGSK_CFGR_IF_MODE_RMII | MIIGSK_CFGR_FRCONT, + &fec->eth->miigsk_cfgr); #else /* configure gasket for MII, no loopback, and no echo */ writew(MIIGSK_CFGR_IF_MODE_MII, &fec->eth->miigsk_cfgr); @@ -474,22 +495,6 @@ static int fec_open(struct eth_device *edev) } #endif
-#ifdef CONFIG_PHYLIB - if (!fec->phydev) - fec_eth_phy_config(edev); - if (fec->phydev) { - /* Start up the PHY */ - phy_startup(fec->phydev); - speed = fec->phydev->speed; - } else { - speed = _100BASET; - } -#else - miiphy_wait_aneg(edev); - speed = miiphy_speed(edev->name, fec->phy_id); - miiphy_duplex(edev->name, fec->phy_id); -#endif - #ifdef FEC_QUIRK_ENET_MAC { u32 ecr = readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_SPEED;
Signed-off-by: Timo Ketola timo@exertus.fi --- drivers/mtd/nand/mxc_nand.c | 35 +++++++++++++++++++++++++++++++++++ 1 files changed, 35 insertions(+), 0 deletions(-)
diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c index 35e89a0..d97e7c3 100644 --- a/drivers/mtd/nand/mxc_nand.c +++ b/drivers/mtd/nand/mxc_nand.c @@ -1302,12 +1302,47 @@ static void mxc_setup_config1(void) #define mxc_setup_config1() #endif
+#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT + +static u8 bbt_pattern[] = {'B', 'b', 't', '0' }; +static u8 mirror_pattern[] = {'1', 't', 'b', 'B' }; + +static struct nand_bbt_descr bbt_main_descr = { + .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | + NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, + .offs = 0, + .len = 4, + .veroffs = 4, + .maxblocks = 4, + .pattern = bbt_pattern, +}; + +static struct nand_bbt_descr bbt_mirror_descr = { + .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | + NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, + .offs = 0, + .len = 4, + .veroffs = 4, + .maxblocks = 4, + .pattern = mirror_pattern, +}; + +#endif + int board_nand_init(struct nand_chip *this) { struct mtd_info *mtd; uint16_t tmp; int err = 0;
+#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT + + this->options = NAND_USE_FLASH_BBT; + this->bbt_td = &bbt_main_descr; + this->bbt_md = &bbt_mirror_descr; + +#endif + /* structures must be linked */ mtd = &host->mtd; mtd->priv = this;
On 04/18/2012 02:57 AM, Timo Ketola wrote:
+#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
- this->options = NAND_USE_FLASH_BBT;
- this->bbt_td = &bbt_main_descr;
- this->bbt_md = &bbt_mirror_descr;
+#endif
Remove those blank lines, and use |= for options like is done with NAND_BUSWIDTH_16.
-Scott
Signed-off-by: Timo Ketola timo@exertus.fi --- drivers/usb/host/ehci-mxc.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/usb/host/ehci-mxc.c b/drivers/usb/host/ehci-mxc.c index 61dbccd..65f40a4 100644 --- a/drivers/usb/host/ehci-mxc.c +++ b/drivers/usb/host/ehci-mxc.c @@ -125,7 +125,7 @@ int ehci_hcd_init(void) hcor = (struct ehci_hcor *)((uint32_t) hccr + HC_LENGTH(ehci_readl(&hccr->cr_capbase))); setbits_le32(&ehci->usbmode, CM_HOST); -#ifdef CONFIG_MX31 +#if defined(CONFIG_MX31) || defined(CONFIG_MX25) setbits_le32(&ehci->control, USB_EN);
__raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
The reference manual of i.MX25 (nor i.MX31) does not define such register. This seems to access read only UH2_CAPLENGTH register (if CONFIG_MXC_USB_PORT is zero).
Signed-off-by: Timo Ketola timo@exertus.fi --- drivers/usb/host/ehci-mxc.c | 2 -- 1 files changed, 0 insertions(+), 2 deletions(-)
diff --git a/drivers/usb/host/ehci-mxc.c b/drivers/usb/host/ehci-mxc.c index 65f40a4..6f4df58 100644 --- a/drivers/usb/host/ehci-mxc.c +++ b/drivers/usb/host/ehci-mxc.c @@ -126,8 +126,6 @@ int ehci_hcd_init(void) HC_LENGTH(ehci_readl(&hccr->cr_capbase))); setbits_le32(&ehci->usbmode, CM_HOST); #if defined(CONFIG_MX31) || defined(CONFIG_MX25) - setbits_le32(&ehci->control, USB_EN); - __raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc); #endif mxc_set_usbcontrol(CONFIG_MXC_USB_PORT, CONFIG_MXC_USB_FLAGS);
On 18/04/2012 09:57, Timo Ketola wrote:
The reference manual of i.MX25 (nor i.MX31) does not define such register. This seems to access read only UH2_CAPLENGTH register (if CONFIG_MXC_USB_PORT is zero).
Signed-off-by: Timo Ketola timo@exertus.fi
Hi Timo,
drivers/usb/host/ehci-mxc.c | 2 -- 1 files changed, 0 insertions(+), 2 deletions(-)
diff --git a/drivers/usb/host/ehci-mxc.c b/drivers/usb/host/ehci-mxc.c index 65f40a4..6f4df58 100644 --- a/drivers/usb/host/ehci-mxc.c +++ b/drivers/usb/host/ehci-mxc.c @@ -126,8 +126,6 @@ int ehci_hcd_init(void) HC_LENGTH(ehci_readl(&hccr->cr_capbase))); setbits_le32(&ehci->usbmode, CM_HOST); #if defined(CONFIG_MX31) || defined(CONFIG_MX25)
As far as I can see, only MX31 and MX25 boards are using this file. Other i.MX have its own initialization file. So #if defined(CONFIG_MX31) || defined(CONFIG_MX25) is always true.
However, where is this code ? In current u-boot I see only #if defined(CONFIG_MX31) at this line. Is it your patch correct ?
- setbits_le32(&ehci->control, USB_EN);
As far as I can see, it tries to overwrite a capability register, that is for our luck read-only. Good catch !
Best regards, Stefano Babic
On 18.04.2012 12:05, Stefano Babic wrote:
As far as I can see, only MX31 and MX25 boards are using this file. Other i.MX have its own initialization file. So #if defined(CONFIG_MX31) || defined(CONFIG_MX25) is always true.
So, would it be OK to remove this check altogether?
However, where is this code ? In current u-boot I see only #if defined(CONFIG_MX31) at this line. Is it your patch correct ?
My previous patch 5 touched that one.
- setbits_le32(&ehci->control, USB_EN);
As far as I can see, it tries to overwrite a capability register, that is for our luck read-only. Good catch !
Thanks.
--
Timo
On 18/04/2012 11:15, Timo Ketola wrote:
On 18.04.2012 12:05, Stefano Babic wrote:
As far as I can see, only MX31 and MX25 boards are using this file. Other i.MX have its own initialization file. So #if defined(CONFIG_MX31) || defined(CONFIG_MX25) is always true.
So, would it be OK to remove this check altogether?
Yes, I think so - if the file is compiled only by i.MX25 or i.MX31 boards, it makes no sense.
Best regards, Stefano Babic
One might want to define CONFIG_SYS_FSL_ESDHC_ADDR with the macro already define in imx-regs.h, e.g. with IMX_MMC_SDHC1_BASE. Then the header must be included here.
Signed-off-by: Timo Ketola timo@exertus.fi --- drivers/mmc/fsl_esdhc.c | 1 + 1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index a2f35e3..5ada747 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -36,6 +36,7 @@ #include <fsl_esdhc.h> #include <fdt_support.h> #include <asm/io.h> +#include <asm/arch/imx-regs.h>
DECLARE_GLOBAL_DATA_PTR;
On 18/04/2012 09:57, Timo Ketola wrote:
One might want to define CONFIG_SYS_FSL_ESDHC_ADDR with the macro already define in imx-regs.h, e.g. with IMX_MMC_SDHC1_BASE. Then the header must be included here.
Signed-off-by: Timo Ketola timo@exertus.fi
drivers/mmc/fsl_esdhc.c | 1 + 1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index a2f35e3..5ada747 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -36,6 +36,7 @@ #include <fsl_esdhc.h> #include <fdt_support.h> #include <asm/io.h> +#include <asm/arch/imx-regs.h>
NAK. There is a good reason to avoid it. The fsl_esdhc driver is common to both i.MX and PowerPc architecture, and of course PowerPC have not imx-regs.h. And CONFIG_SYS_FSL_ESDHC_ADDR cannot be set by a macro in imx-regs.h, because it is different on PowerPC.
By the way, why do you need it if you do not use that macro ?
Best regards, Stefano Babic
On 18.04.2012 11:43, Stefano Babic wrote:
On 18/04/2012 09:57, Timo Ketola wrote:
One might want to define CONFIG_SYS_FSL_ESDHC_ADDR with the macro already define in imx-regs.h, e.g. with IMX_MMC_SDHC1_BASE. Then the header must be included here. ... diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c ... +#include<asm/arch/imx-regs.h>
NAK. There is a good reason to avoid it. The fsl_esdhc driver is common to both i.MX and PowerPc architecture, and of course PowerPC have not imx-regs.h. And CONFIG_SYS_FSL_ESDHC_ADDR cannot be set by a macro in imx-regs.h, because it is different on PowerPC.
Ok, I was afraid about something like that and tried first to include it in board configuration but that broke something else (at least arm926ejs didn't compile any more).
By the way, why do you need it if you do not use that macro ?
I use it in my board (support of which I'm preparing to send) configuration file and I think it is annoying to write a literal constant there which is already defined in imx-regs.h.
PPC seems to use a predefined macro from asm/immap_8xxx.h files. Where is that file included?
--
Timo
On 18/04/2012 11:11, Timo Ketola wrote:
Ok, I was afraid about something like that and tried first to include it in board configuration but that broke something else (at least arm926ejs didn't compile any more).
By the way, why do you need it if you do not use that macro ?
I use it in my board (support of which I'm preparing to send) configuration file and I think it is annoying to write a literal constant there which is already defined in imx-regs.h.
fsl_esdhc.c includes config.h. If your board configuration file includes imx-regs.h, as most i.MX boards do, the file is automatically included, I suppose.
PPC seems to use a predefined macro from asm/immap_8xxx.h files. Where is that file included?
It is a different way. The board configuration file includes the register description file, so for example immap_86xx.h, immap_85xx.h, or imx-regs.h, and defines CONFIG_SYS_FSL_ESDHC_ADDR using its own specific macro, if any, for example:
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
Why is it not enough for you to set in your board configuration file:
#define CONFIG_SYS_FSL_ESDHC_ADDR IMX_MMC_SDHC1_BASE
Best regards, Stefano Babic
On 18.04.2012 13:30, Stefano Babic wrote:
On 18/04/2012 11:11, Timo Ketola wrote:
Ok, I was afraid about something like that and tried first to include it in board configuration but that broke something else (at least arm926ejs didn't compile any more).
By the way, why do you need it if you do not use that macro ?
I use it in my board (support of which I'm preparing to send) configuration file and I think it is annoying to write a literal constant there which is already defined in imx-regs.h.
fsl_esdhc.c includes config.h. If your board configuration file includes imx-regs.h, as most i.MX boards do, the file is automatically included, I suppose.
I tried that but then:
.../u-boot-imx/build-exe4026/include/asm/arch/imx-regs.h:43:2: error: expected specifier-qualifier-list before ‘u32’
when compiling
arch/arm/cpu/arm926ejs/cpu.o
PPC seems to use a predefined macro from asm/immap_8xxx.h files. Where is that file included?
It is a different way. The board configuration file includes the register description file, so for example immap_86xx.h, immap_85xx.h,
Where? I don't see an example. But I see them included in common.h. Should there be also imx-regs? Seems to work if I do so.
or imx-regs.h, and defines CONFIG_SYS_FSL_ESDHC_ADDR using its own specific macro, if any, for example:
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
Why is it not enough for you to set in your board configuration file:
#define CONFIG_SYS_FSL_ESDHC_ADDR IMX_MMC_SDHC1_BASE
I tried also exactly that, but then:
fsl_esdhc.c:544:20: error: ‘IMX_MMC_SDHC1_BASE’ undeclared (first use in this function)
fsl_esdhc.c seems not to see imx-regs.h file.
Then I tried to include imx-regs.h in fsl_esdhc.c and 'MAKEALL -a arm' was happy.
Maybe the right fix is to include imx-regs in common.h? What would be the right expression for #ifdef?
--
Timo
On 18/04/2012 13:05, Timo Ketola wrote:
fsl_esdhc.c includes config.h. If your board configuration file includes imx-regs.h, as most i.MX boards do, the file is automatically included, I suppose.
I tried that but then:
.../u-boot-imx/build-exe4026/include/asm/arch/imx-regs.h:43:2: error: expected specifier-qualifier-list before ‘u32’
when compiling
arch/arm/cpu/arm926ejs/cpu.o
Well, I have not said that there cannot be other issues. At first glance you must include asm/types.h, in cpu.c or in imx-regs.h.
PPC seems to use a predefined macro from asm/immap_8xxx.h files. Where is that file included?
It is a different way. The board configuration file includes the register description file, so for example immap_86xx.h, immap_85xx.h,
Where? I don't see an example.
For PPC86xx I can see at least:
arch/powerpc/cpu/mpc86xx/mpc8641_serdes.c:#include <asm/immap_86xx.h> arch/powerpc/cpu/mpc86xx/mpc8610_serdes.c:#include <asm/immap_86xx.h> board/freescale/mpc8610hpcd/mpc8610hpcd.c:#include <asm/immap_86xx.h> board/freescale/mpc8641hpcn/mpc8641hpcn.c:#include <asm/immap_86xx.h>
But I see them included in common.h. Should there be also imx-regs? Seems to work if I do so.
No, this is wrong.
or imx-regs.h, and defines CONFIG_SYS_FSL_ESDHC_ADDR using its own specific macro, if any, for example:
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
Why is it not enough for you to set in your board configuration file:
#define CONFIG_SYS_FSL_ESDHC_ADDR IMX_MMC_SDHC1_BASE
I tried also exactly that, but then:
fsl_esdhc.c:544:20: error: ‘IMX_MMC_SDHC1_BASE’ undeclared (first use in this function)
...then imx-regs.h was not included...
fsl_esdhc.c seems not to see imx-regs.h file.
Then I tried to include imx-regs.h in fsl_esdhc.c and 'MAKEALL -a arm' was happy.
Maybe the right fix is to include imx-regs in common.h?
No. common.h, as the name suggests, is for all architectures, not only for i.MX. We cannot fix i:MX and break other boards.
Best regards, Stefano Babic
On 18.04.2012 18:05, Stefano Babic wrote:
On 18/04/2012 13:05, Timo Ketola wrote:
Stefano Babic wrote:
Timo Ketola wrote:
PPC seems to use a predefined macro from asm/immap_8xxx.h files. Where is that file included?
It is a different way. The board configuration file includes the register description file, so for example immap_86xx.h, immap_85xx.h,
Where? I don't see an example.
For PPC86xx I can see at least:
arch/powerpc/cpu/mpc86xx/mpc8641_serdes.c:#include<asm/immap_86xx.h> arch/powerpc/cpu/mpc86xx/mpc8610_serdes.c:#include<asm/immap_86xx.h> board/freescale/mpc8610hpcd/mpc8610hpcd.c:#include<asm/immap_86xx.h> board/freescale/mpc8641hpcn/mpc8641hpcn.c:#include<asm/immap_86xx.h>
Yes, I saw those but when you said that board configuration file includes those, I thought that you meant the header files in include/configs.
But I see them included in common.h. Should there be also imx-regs? Seems to work if I do so.
No, this is wrong.
...
Then I tried to include imx-regs.h in fsl_esdhc.c and 'MAKEALL -a arm' was happy.
Maybe the right fix is to include imx-regs in common.h?
No. common.h, as the name suggests, is for all architectures, not only for i.MX. We cannot fix i:MX and break other boards.
But why PPC register description files are included there then? For example line 87:
#ifdef CONFIG_MPC86xx #include <mpc86xx.h> #include <asm/immap_86xx.h> #endif
Is that deprecated?
And how would adding imx file with the same logic break other boards? I mean, putting there:
#if defined(CONFIG_MX25) || defined(CONFIG_MX31) || ... #include <asm/arch/imx-regs.h> #endif
But if the board configuration file in include/configs is the correct place to include it, I shall then find the obstacle on that approach...
--
Timo
On 18.04.2012 19:27, Timo Ketola wrote:
But if the board configuration file in include/configs is the correct place to include it, I shall then find the obstacle on that approach...
Ok, including asm/arch/imx-regs.h in board configuration file *and* asm/types.h in asm/arch/imx-regs.h file seems to make build happy. This would be the right fix then?
--
Timo
Signed-off-by: Timo Ketola timo@exertus.fi --- arch/arm/cpu/arm926ejs/config.mk | 6 ++++++ 1 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/config.mk b/arch/arm/cpu/arm926ejs/config.mk index ffb2e6c..6a3a1bb 100644 --- a/arch/arm/cpu/arm926ejs/config.mk +++ b/arch/arm/cpu/arm926ejs/config.mk @@ -31,3 +31,9 @@ PLATFORM_CPPFLAGS += -march=armv5te # ========================================================================= PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT) + +ifneq ($(CONFIG_IMX_CONFIG),) + +ALL-y += $(obj)u-boot.imx + +endif
Hi,
Please, don't get confused about the subject lines which suggest that I sent nine patches. At the last second I dropped the last patch and decided to send it separately.
Stefano, did you get the "[PATCH 0/8 v3]..." message as a CC. I don't see you in CC list in the bounce I got myself and yet I have your address in .git/config *and* I see you in my following messages. I don't understand...
--
Timo
On 18/04/2012 09:57, Timo Ketola wrote:
These are the fixes I needed to do to get my board going.
Hi Timo,
Changes in v3:
- Dropped old patch number 8 "imx: nand: Don't invent new..."
- Changed the subject of patch 4
- Changed the BBT pattern offsets (patch 4); They are now zero as in Linux
You must change the subject of the patch and introduce an enumeration. Your patchset should start with "[PATCH V3". This can easy automatically done by "git format-patch" with --subject-prefix "PATCH V3".
Best regards, Stefano Babic
I'm preparing to include Exertus board adaptation. This is the fourth version of this patchset and the history is showing my deep learning curve with git and formatting good patches. So please bear with me.
I assumed that 'git send-email' (alone) would be a handy way to send patches but it proved to produce disappointing results, at least in my hands. I switched to trying 'git format-patch; edit; git send-email'. Lets see how this goes...
The board, for which I'm trying to adapt, uses some peripherals (esdhc, gpio4) and functionalities (flash based BBT) which apparently are not yet used in other i.MX25 boards. This patchset fixes some issues in using those peripherals in i.MX25 environment and some bugs.
Changes in contents of the patchset:
V3: - Dropped patch 8
V2: - Dropped patches 2, 3 and 6 - Added patches 6, 7, 8 and 9
I hope and believe that all comments given to me so far are covered in these patches.
Timo Ketola (8): i.MX25: esdhc: Add mxc_get_clock infrastructure i.MX25: This architecture has a GPIO4 too imx: fec: Resolve speed before configuring gasket imx: nand: Support flash based BBT i.MX25: usb: Set PORTSCx register imx: usb: There is no such register i.MX2: Include asm/types.h in arch-mx25/imx-regs.h imx: Add u-boot.imx as target for ARM9 i.MX SOCs
arch/arm/cpu/arm926ejs/config.mk | 6 ++++ arch/arm/cpu/arm926ejs/mx25/generic.c | 27 ++++++++++++++++++ arch/arm/include/asm/arch-mx25/clock.h | 23 +++++++++++++++ arch/arm/include/asm/arch-mx25/imx-regs.h | 3 ++ drivers/gpio/mxc_gpio.c | 3 +- drivers/mtd/nand/mxc_nand.c | 33 ++++++++++++++++++++++ drivers/net/fec_mxc.c | 43 ++++++++++++++++------------- drivers/usb/host/ehci-mxc.c | 4 --- 8 files changed, 118 insertions(+), 24 deletions(-)
Defining CONFIG_FSL_ESDHC brings in a call to get_clocks, so let's implement get_clocks function. This is how it seems to be implemented elsewhere.
Signed-off-by: Timo Ketola timo@exertus.fi ---
Changes in v4: - Rewrapped commit message
Changes in v2: - Rebased to u-boot-imx next
arch/arm/cpu/arm926ejs/mx25/generic.c | 27 +++++++++++++++++++++++++++ arch/arm/include/asm/arch-mx25/clock.h | 23 +++++++++++++++++++++++ 2 files changed, 50 insertions(+), 0 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/mx25/generic.c b/arch/arm/cpu/arm926ejs/mx25/generic.c index 9cadb7c..8b07dae 100644 --- a/arch/arm/cpu/arm926ejs/mx25/generic.c +++ b/arch/arm/cpu/arm926ejs/mx25/generic.c @@ -28,10 +28,15 @@ #include <asm/io.h> #include <asm/arch/imx-regs.h> #include <asm/arch/imx25-pinmux.h> +#include <asm/arch/clock.h> #ifdef CONFIG_MXC_MMC #include <asm/arch/mxcmmc.h> #endif
+#ifdef CONFIG_FSL_ESDHC +DECLARE_GLOBAL_DATA_PTR; +#endif + /* * get the system pll clock in Hz * @@ -105,6 +110,20 @@ ulong imx_get_perclk(int clk) return lldiv(fref, div); }
+unsigned int mxc_get_clock(enum mxc_clock clk) +{ + if (clk >= MXC_CLK_NUM) + return -1; + switch (clk) { + case MXC_ARM_CLK: + return imx_get_armclk(); + case MXC_FEC_CLK: + return imx_get_ahbclk(); + default: + return imx_get_perclk(clk); + } +} + u32 get_cpu_rev(void) { u32 srev; @@ -182,6 +201,14 @@ int cpu_eth_init(bd_t *bis) #endif }
+int get_clocks(void) +{ +#ifdef CONFIG_FSL_ESDHC + gd->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); +#endif + return 0; +} + /* * Initializes on-chip MMC controllers. * to override, implement board_mmc_init() diff --git a/arch/arm/include/asm/arch-mx25/clock.h b/arch/arm/include/asm/arch-mx25/clock.h index c59f588..0f47eaf 100644 --- a/arch/arm/include/asm/arch-mx25/clock.h +++ b/arch/arm/include/asm/arch-mx25/clock.h @@ -26,11 +26,34 @@ #ifndef __ASM_ARCH_CLOCK_H #define __ASM_ARCH_CLOCK_H
+enum mxc_clock { + MXC_CSI_CLK, + MXC_EPIT_CLK, + MXC_ESAI_CLK, + MXC_ESDHC1_CLK, + MXC_ESDHC2_CLK, + MXC_GPT_CLK, + MXC_I2C_CLK, + MXC_LCDC_CLK, + MXC_NFC_CLK, + MXC_OWIRE_CLK, + MXC_PWM_CLK, + MXC_SIM1_CLK, + MXC_SIM2_CLK, + MXC_SSI1_CLK, + MXC_SSI2_CLK, + MXC_UART_CLK, + MXC_ARM_CLK, + MXC_FEC_CLK, + MXC_CLK_NUM +}; + ulong imx_get_perclk(int clk); ulong imx_get_ahbclk(void);
#define imx_get_uartclk() imx_get_perclk(15) #define imx_get_fecclk() (imx_get_ahbclk()/2)
+unsigned int mxc_get_clock(enum mxc_clock clk);
#endif /* __ASM_ARCH_CLOCK_H */
On 19/04/2012 10:55, Timo Ketola wrote:
Defining CONFIG_FSL_ESDHC brings in a call to get_clocks, so let's implement get_clocks function. This is how it seems to be implemented elsewhere.
Signed-off-by: Timo Ketola timo@exertus.fi
Changes in v4:
- Rewrapped commit message
Changes in v2:
- Rebased to u-boot-imx next
arch/arm/cpu/arm926ejs/mx25/generic.c | 27 +++++++++++++++++++++++++++ arch/arm/include/asm/arch-mx25/clock.h | 23 +++++++++++++++++++++++ 2 files changed, 50 insertions(+), 0 deletions(-)
Acked-by: Stefano Babic sbabic@denx.de
Best regards, Stefano Babic
On 19/04/2012 10:55, Timo Ketola wrote:
Defining CONFIG_FSL_ESDHC brings in a call to get_clocks, so let's implement get_clocks function. This is how it seems to be implemented elsewhere.
Signed-off-by: Timo Ketola timo@exertus.fi
Changes in v4:
- Rewrapped commit message
Changes in v2:
- Rebased to u-boot-imx next
arch/arm/cpu/arm926ejs/mx25/generic.c | 27 +++++++++++++++++++++++++++ arch/arm/include/asm/arch-mx25/clock.h | 23 +++++++++++++++++++++++ 2 files changed, 50 insertions(+), 0 deletions(-)
Applied to u-boot-imx, thanks.
Best regards, Stefano Babic
Signed-off-by: Timo Ketola timo@exertus.fi ---
Changes in v2: - Dropped patches 2 and 3 so this one changed from 4 to 2 - Rebased to u-boot-imx next - Fixed too long line
drivers/gpio/mxc_gpio.c | 3 ++- 1 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/drivers/gpio/mxc_gpio.c b/drivers/gpio/mxc_gpio.c index df6bbbb..3e94ac3 100644 --- a/drivers/gpio/mxc_gpio.c +++ b/drivers/gpio/mxc_gpio.c @@ -40,7 +40,8 @@ static unsigned long gpio_ports[] = { [0] = GPIO1_BASE_ADDR, [1] = GPIO2_BASE_ADDR, [2] = GPIO3_BASE_ADDR, -#if defined(CONFIG_MX51) || defined(CONFIG_MX53) || defined(CONFIG_MX6Q) +#if defined(CONFIG_MX25) || defined(CONFIG_MX51) || defined(CONFIG_MX53) || \ + defined(CONFIG_MX6Q) [3] = GPIO4_BASE_ADDR, #endif #if defined(CONFIG_MX53) || defined(CONFIG_MX6Q)
On 19/04/2012 10:55, Timo Ketola wrote:
Signed-off-by: Timo Ketola timo@exertus.fi
Changes in v2:
- Dropped patches 2 and 3 so this one changed from 4 to 2
- Rebased to u-boot-imx next
- Fixed too long line
drivers/gpio/mxc_gpio.c | 3 ++- 1 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/drivers/gpio/mxc_gpio.c b/drivers/gpio/mxc_gpio.c index df6bbbb..3e94ac3 100644 --- a/drivers/gpio/mxc_gpio.c +++ b/drivers/gpio/mxc_gpio.c @@ -40,7 +40,8 @@ static unsigned long gpio_ports[] = { [0] = GPIO1_BASE_ADDR, [1] = GPIO2_BASE_ADDR, [2] = GPIO3_BASE_ADDR, -#if defined(CONFIG_MX51) || defined(CONFIG_MX53) || defined(CONFIG_MX6Q) +#if defined(CONFIG_MX25) || defined(CONFIG_MX51) || defined(CONFIG_MX53) || \
defined(CONFIG_MX6Q)#endif #if defined(CONFIG_MX53) || defined(CONFIG_MX6Q)
Acked-by: Stefano Babic sbabic@denx.de
Best regards, Stefano Babic
On 19/04/2012 10:55, Timo Ketola wrote:
Signed-off-by: Timo Ketola timo@exertus.fi
Changes in v2:
- Dropped patches 2 and 3 so this one changed from 4 to 2
- Rebased to u-boot-imx next
- Fixed too long line
Applied to u-boot-imx, thanks.
Best regards, Stefano Babic
Gasket needs a different configuration for 10BaseT than for higher speeds.
Signed-off-by: Timo Ketola timo@exertus.fi ---
Changes in v4: - Rewrapped commit message
Changes in v2: - Dropped patches 2 and 3 so this one changed from 5 to 3 - Rebased to u-boot-imx next - Removed the remove of 'miiphy_duplex' call - Changed 'speed == _100BASET' to 'speed != _10BASET' to not to break _1000BASET - Changed configuration option to put gasket into RMII mode from !CONFIG_MII to CONFIG_RMII. I'm not too sure how this should be done though. !CONFIG_MII is normally used for this but its original purpose was to enable MII *management* interface, I think...
drivers/net/fec_mxc.c | 43 ++++++++++++++++++++++++------------------- 1 files changed, 24 insertions(+), 19 deletions(-)
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index 824a199..48a69d4 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -440,6 +440,22 @@ static int fec_open(struct eth_device *edev) */ writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN, &fec->eth->ecntrl); +#ifdef CONFIG_PHYLIB + if (!fec->phydev) + fec_eth_phy_config(edev); + if (fec->phydev) { + /* Start up the PHY */ + phy_startup(fec->phydev); + speed = fec->phydev->speed; + } else { + speed = _100BASET; + } +#else + miiphy_wait_aneg(edev); + speed = miiphy_speed(edev->name, fec->phy_id); + miiphy_duplex(edev->name, fec->phy_id); +#endif + #if defined(CONFIG_MX25) || defined(CONFIG_MX53) udelay(100); /* @@ -453,9 +469,14 @@ static int fec_open(struct eth_device *edev) while (readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) udelay(2);
-#if !defined(CONFIG_MII) - /* configure gasket for RMII, 50 MHz, no loopback, and no echo */ - writew(MIIGSK_CFGR_IF_MODE_RMII, &fec->eth->miigsk_cfgr); +#if defined(CONFIG_RMII) + if (speed != _10BASET) + /* configure gasket for RMII, 50MHz, no loopback, and no echo */ + writew(MIIGSK_CFGR_IF_MODE_RMII, &fec->eth->miigsk_cfgr); + else + /* configure gasket for RMII, 5MHz, no loopback, and no echo */ + writew(MIIGSK_CFGR_IF_MODE_RMII | MIIGSK_CFGR_FRCONT, + &fec->eth->miigsk_cfgr); #else /* configure gasket for MII, no loopback, and no echo */ writew(MIIGSK_CFGR_IF_MODE_MII, &fec->eth->miigsk_cfgr); @@ -474,22 +495,6 @@ static int fec_open(struct eth_device *edev) } #endif
-#ifdef CONFIG_PHYLIB - if (!fec->phydev) - fec_eth_phy_config(edev); - if (fec->phydev) { - /* Start up the PHY */ - phy_startup(fec->phydev); - speed = fec->phydev->speed; - } else { - speed = _100BASET; - } -#else - miiphy_wait_aneg(edev); - speed = miiphy_speed(edev->name, fec->phy_id); - miiphy_duplex(edev->name, fec->phy_id); -#endif - #ifdef FEC_QUIRK_ENET_MAC { u32 ecr = readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_SPEED;
On 19/04/2012 10:55, Timo Ketola wrote:
Gasket needs a different configuration for 10BaseT than for higher speeds.
Signed-off-by: Timo Ketola timo@exertus.fi
Acked-by: Stefano Babic sbabic@denx.de
Best regards, Stefano Babic
On 4/19/2012 1:55 AM, Timo Ketola wrote:
Gasket needs a different configuration for 10BaseT than for higher speeds.
Signed-off-by: Timo Ketolatimo@exertus.fi
Changes in v4:
- Rewrapped commit message
Changes in v2:
Dropped patches 2 and 3 so this one changed from 5 to 3
Rebased to u-boot-imx next
Removed the remove of 'miiphy_duplex' call
Changed 'speed == _100BASET' to 'speed != _10BASET' to not to break _1000BASET
Changed configuration option to put gasket into RMII mode from !CONFIG_MII to CONFIG_RMII. I'm not too sure how this should be done though. !CONFIG_MII is normally used for this but its original purpose was to enable MII *management* interface, I think...
drivers/net/fec_mxc.c | 43 ++++++++++++++++++++++++------------------- 1 files changed, 24 insertions(+), 19 deletions(-)
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index 824a199..48a69d4 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -440,6 +440,22 @@ static int fec_open(struct eth_device *edev) */ writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN, &fec->eth->ecntrl); +#ifdef CONFIG_PHYLIB
- if (!fec->phydev)
fec_eth_phy_config(edev);- if (fec->phydev) {
/* Start up the PHY */phy_startup(fec->phydev);speed = fec->phydev->speed;- } else {
speed = _100BASET;- }
+#else
- miiphy_wait_aneg(edev);
- speed = miiphy_speed(edev->name, fec->phy_id);
- miiphy_duplex(edev->name, fec->phy_id);
+#endif
- #if defined(CONFIG_MX25) || defined(CONFIG_MX53) udelay(100); /*
@@ -453,9 +469,14 @@ static int fec_open(struct eth_device *edev) while (readw(&fec->eth->miigsk_enr)& MIIGSK_ENR_READY) udelay(2);
-#if !defined(CONFIG_MII)
- /* configure gasket for RMII, 50 MHz, no loopback, and no echo */
- writew(MIIGSK_CFGR_IF_MODE_RMII,&fec->eth->miigsk_cfgr);
+#if defined(CONFIG_RMII)
While this change seems to make sense, it could break some boards. Please split out to a separate patch, and leave as !defined(CONFIG_MII) for this patch.
Thanks Troy
On 19.04.2012 22:27, Troy Kisky wrote:
On 4/19/2012 1:55 AM, Timo Ketola wrote:
-#if !defined(CONFIG_MII)
- /* configure gasket for RMII, 50 MHz, no loopback, and no echo */
- writew(MIIGSK_CFGR_IF_MODE_RMII,&fec->eth->miigsk_cfgr);
+#if defined(CONFIG_RMII)
While this change seems to make sense, it could break some boards.
Please explain how. Every board using fec_mxc define CONFIG_MII - they have to:
#ifndef CONFIG_MII #error "CONFIG_MII has to be defined!" #endif
Please split out to a separate patch, and leave as !defined(CONFIG_MII) for this patch.
Stefano?
--
Timo
On 4/19/2012 1:18 PM, Timo Ketola wrote:
On 19.04.2012 22:27, Troy Kisky wrote:
On 4/19/2012 1:55 AM, Timo Ketola wrote:
-#if !defined(CONFIG_MII)
- /* configure gasket for RMII, 50 MHz, no loopback, and no echo */
- writew(MIIGSK_CFGR_IF_MODE_RMII,&fec->eth->miigsk_cfgr);
+#if defined(CONFIG_RMII)
While this change seems to make sense, it could break some boards.
Please explain how. Every board using fec_mxc define CONFIG_MII - they have to:
#ifndef CONFIG_MII #error "CONFIG_MII has to be defined!" #endif
Does every board that has a gasket define CONFIG_RMII?
Or are you saying that every board with a gasket is already broken?
On 4/19/2012 2:13 PM, Troy Kisky wrote:
On 4/19/2012 1:18 PM, Timo Ketola wrote:
On 19.04.2012 22:27, Troy Kisky wrote:
On 4/19/2012 1:55 AM, Timo Ketola wrote:
-#if !defined(CONFIG_MII)
- /* configure gasket for RMII, 50 MHz, no loopback, and no echo */
- writew(MIIGSK_CFGR_IF_MODE_RMII,&fec->eth->miigsk_cfgr);
+#if defined(CONFIG_RMII)
While this change seems to make sense, it could break some boards.
Please explain how. Every board using fec_mxc define CONFIG_MII - they have to:
#ifndef CONFIG_MII #error "CONFIG_MII has to be defined!" #endif
Does every board that has a gasket define CONFIG_RMII?
Or are you saying that every board with a gasket is already broken?
That should be "Or are you saying that every board using a reduced pin code is alread broken?"
U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[undeleted Stefano from CC-list]
On 20.04.2012 00:23, Troy Kisky wrote:
On 4/19/2012 2:13 PM, Troy Kisky wrote:
On 4/19/2012 1:18 PM, Timo Ketola wrote:
On 19.04.2012 22:27, Troy Kisky wrote:
On 4/19/2012 1:55 AM, Timo Ketola wrote:
-#if !defined(CONFIG_MII)
- /* configure gasket for RMII, 50 MHz, no loopback, and no echo */
- writew(MIIGSK_CFGR_IF_MODE_RMII,&fec->eth->miigsk_cfgr);
+#if defined(CONFIG_RMII)
While this change seems to make sense, it could break some boards.
Please explain how. Every board using fec_mxc define CONFIG_MII - they have to:
#ifndef CONFIG_MII #error "CONFIG_MII has to be defined!" #endif
Does every board that has a gasket define CONFIG_RMII?
Our board will be first.
Or are you saying that every board with a gasket is already broken?
That should be "Or are you saying that every board using a reduced pin code is alread broken?"
Yes, if there were one. Is there?
--
Timo
On 20/04/2012 06:35, Timo Ketola wrote:
[undeleted Stefano from CC-list]
Hi Timo, hi Troy,
On 20.04.2012 00:23, Troy Kisky wrote:
On 4/19/2012 2:13 PM, Troy Kisky wrote:
On 4/19/2012 1:18 PM, Timo Ketola wrote:
On 19.04.2012 22:27, Troy Kisky wrote:
On 4/19/2012 1:55 AM, Timo Ketola wrote:
-#if !defined(CONFIG_MII)
- /* configure gasket for RMII, 50 MHz, no loopback, and no echo */
- writew(MIIGSK_CFGR_IF_MODE_RMII,&fec->eth->miigsk_cfgr);
+#if defined(CONFIG_RMII)
While this change seems to make sense, it could break some boards.
Please explain how. Every board using fec_mxc define CONFIG_MII - they have to:
#ifndef CONFIG_MII #error "CONFIG_MII has to be defined!" #endif
Does every board that has a gasket define CONFIG_RMII?
as far as I can see, there are some inconsistencies. All boards define CONFIG_MII, but they really need CONFIG_RMII, because only with my last patch I set the gasket for MII. The driver has always set in a fixed way the gasket for RMII, independently if CONFIG_RMII or CONFIG_MII was set, and that is also wrong.
I would say that the configuration file of most boards using fec_mxc must be changed.
And then fec_mxc.c does not need at all these lines: #ifndef CONFIG_MII #error "CONFIG_MII has to be defined!" #endif
Boards are compiled clean without them. Correct me if I am wrong, but it seems the correct way to do is to drop the unneeded check in the above lines and sets CONFIG_RMII for all boards except the only one (ima3-mx53), that needs really MII.
Best regards, Stefano Babic
Dear Stefano, Troy, Scott,
On 20.04.2012 10:30, Stefano Babic wrote:
On 20/04/2012 06:35, Timo Ketola wrote:
[undeleted Stefano from CC-list]
Hi Timo, hi Troy,
On 20.04.2012 00:23, Troy Kisky wrote:
On 4/19/2012 2:13 PM, Troy Kisky wrote:
On 4/19/2012 1:18 PM, Timo Ketola wrote:
On 19.04.2012 22:27, Troy Kisky wrote:
On 4/19/2012 1:55 AM, Timo Ketola wrote: > -#if !defined(CONFIG_MII) > - /* configure gasket for RMII, 50 MHz, no loopback, and no echo */ > - writew(MIIGSK_CFGR_IF_MODE_RMII,&fec->eth->miigsk_cfgr); > +#if defined(CONFIG_RMII)
While this change seems to make sense, it could break some boards.
Please explain how. Every board using fec_mxc define CONFIG_MII - they have to:
#ifndef CONFIG_MII #error "CONFIG_MII has to be defined!" #endif
Does every board that has a gasket define CONFIG_RMII?
as far as I can see, there are some inconsistencies. All boards define CONFIG_MII, but they really need CONFIG_RMII, because only with my last patch I set the gasket for MII. The driver has always set in a fixed way the gasket for RMII, independently if CONFIG_RMII or CONFIG_MII was set, and that is also wrong.
Ah, so, to answer Troy, there really is RMII boards (which maybe was obvious to all others than me; I reasoned in wrong direction: because they would be already broken with this code, there could be none) and they were already broken.
I would say that the configuration file of most boards using fec_mxc must be changed.
And then fec_mxc.c does not need at all these lines: #ifndef CONFIG_MII #error "CONFIG_MII has to be defined!" #endif
Functionally this does nothing of course but I can imagine the reasoning behind that check: If I understand correctly, fec_mxc depends on MII management interface (for example miiphy_wait_aneg). Then, if CONFIG_MII is not defined, there is inconsistency because configuration says "don't use MII" but fec_mxc still uses it. I don't know whether this causes any confusion.
Boards are compiled clean without them. Correct me if I am wrong, but it seems the correct way to do is to drop the unneeded check in the above lines and sets CONFIG_RMII for all boards except the only one (ima3-mx53), that needs really MII.
Agreed regarding CONFIG_RMII. With dropping the check I'm OK either way. Furthermore, I might like to propose to change the name of the configuration variable CONFIG_MII to CONFIG_MII_MGM or something like that. That might reduce confusion (at least I have been quite confused).
--
Timo
On 20/04/2012 10:54, Timo Ketola wrote:
as far as I can see, there are some inconsistencies. All boards define CONFIG_MII, but they really need CONFIG_RMII, because only with my last patch I set the gasket for MII. The driver has always set in a fixed way the gasket for RMII, independently if CONFIG_RMII or CONFIG_MII was set, and that is also wrong.
Quite right, you have the second board. The ima3 board I added uses also MII instead of RMII. However, I think that something went wrong, as I understand rereading the code.
Functionally this does nothing of course but I can imagine the reasoning behind that check: If I understand correctly, fec_mxc depends on MII management interface (for example miiphy_wait_aneg). Then, if CONFIG_MII is not defined, there is inconsistency because configuration says "don't use MII" but fec_mxc still uses it. I don't know whether this causes any confusion.
It creates some confusion...
Boards are compiled clean without them. Correct me if I am wrong, but it seems the correct way to do is to drop the unneeded check in the above lines and sets CONFIG_RMII for all boards except the only one (ima3-mx53), that needs really MII.
Agreed regarding CONFIG_RMII. With dropping the check I'm OK either way. Furthermore, I might like to propose to change the name of the configuration variable CONFIG_MII to CONFIG_MII_MGM or something like that. That might reduce confusion (at least I have been quite confused).
Support for MX28 added recently CONFIG_FEC_XCV_TYPE. To augment the confusion, CONFIG_FEC_XCV_TYPE is set to MII100 as default, and this let assume that most boards are running with MII if they do not define it. Really all MX5 boards use RMII, not MII. Not only, by setting the RCR register, there is an attempt to set reserved bits on MX5 SOCs, because MX5 defines only bits 0-5. It seems that writing to reserved bits does not produce effects, but it is quite dangerous and not compliant with SOC manual.
So at the end we have multiple configuration switches (CONFIG_MII, CONFIG_RMII, and CONFIG_FEC_XCV_TYPE) to set the same thing, and this is not really good ;-((
I assume that setting CONFIG_FEC_XCV_TYPE as default to MII100 was to avoid to break building not MX28 boards, but as you can see generates other problems. I think it is really better that there is *no* default, and each board sets explicitely its own type.
Instead of using CONFIG_MII or CONFIG_RMII, we can make use of CONFIG_FEC_XCV_TYPE, as it was already introduced, but making it consistent for all boards.
Support for MII in FEC is in u-boot-imx/next in the last patch, and it is not yet merged. I think I am going to drop that patch from my tree, so that we start again from a clean situation (mainline).
Best regards, Stefano Babic
On 23.04.2012 10:55, Stefano Babic wrote:
Instead of using CONFIG_MII or CONFIG_RMII, we can make use of CONFIG_FEC_XCV_TYPE, as it was already introduced, but making it consistent for all boards.
Second for that.
--
Timo
On 4/19/2012 1:55 AM, Timo Ketola wrote:
Gasket needs a different configuration for 10BaseT than for higher speeds.
Signed-off-by: Timo Ketolatimo@exertus.fi
Changes in v4:
- Rewrapped commit message
Changes in v2:
Dropped patches 2 and 3 so this one changed from 5 to 3
Rebased to u-boot-imx next
Removed the remove of 'miiphy_duplex' call
Changed 'speed == _100BASET' to 'speed != _10BASET' to not to break _1000BASET
Changed configuration option to put gasket into RMII mode from !CONFIG_MII to CONFIG_RMII. I'm not too sure how this should be done though. !CONFIG_MII is normally used for this but its original purpose was to enable MII *management* interface, I think...
drivers/net/fec_mxc.c | 43 ++++++++++++++++++++++++------------------- 1 files changed, 24 insertions(+), 19 deletions(-)
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index 824a199..48a69d4 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -440,6 +440,22 @@ static int fec_open(struct eth_device *edev) */ writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN, &fec->eth->ecntrl); +#ifdef CONFIG_PHYLIB
- if (!fec->phydev)
fec_eth_phy_config(edev);- if (fec->phydev) {
/* Start up the PHY */phy_startup(fec->phydev);speed = fec->phydev->speed;- } else {
speed = _100BASET;- }
+#else
- miiphy_wait_aneg(edev);
- speed = miiphy_speed(edev->name, fec->phy_id);
- miiphy_duplex(edev->name, fec->phy_id);
+#endif
- #if defined(CONFIG_MX25) || defined(CONFIG_MX53) udelay(100); /*
@@ -453,9 +469,14 @@ static int fec_open(struct eth_device *edev) while (readw(&fec->eth->miigsk_enr)& MIIGSK_ENR_READY) udelay(2);
-#if !defined(CONFIG_MII)
- /* configure gasket for RMII, 50 MHz, no loopback, and no echo */
- writew(MIIGSK_CFGR_IF_MODE_RMII,&fec->eth->miigsk_cfgr);
+#if defined(CONFIG_RMII)
- if (speed != _10BASET)
/* configure gasket for RMII, 50MHz, no loopback, and no echo */writew(MIIGSK_CFGR_IF_MODE_RMII,&fec->eth->miigsk_cfgr);- else
/* configure gasket for RMII, 5MHz, no loopback, and no echo */writew(MIIGSK_CFGR_IF_MODE_RMII | MIIGSK_CFGR_FRCONT,&fec->eth->miigsk_cfgr);@@ -474,22 +495,6 @@ static int fec_open(struct eth_device *edev) } #endif
Can you fix 10BASET for non-reduced pin count boards as well?
Thanks Troy
[undeleted Stefano from CC-list]
On 20.04.2012 00:28, Troy Kisky wrote:
On 4/19/2012 1:55 AM, Timo Ketola wrote:
...
- if (speed != _10BASET)
...
Can you fix 10BASET for non-reduced pin count boards as well?
Are they broken? How? If they are, I'm afraid I don't have a board to test.
--
Timo
Signed-off-by: Timo Ketola timo@exertus.fi ---
Changes in v4: - Removed blank lines inside #ifdef - Manipulate 'this->options' with '|=' instead of '='
Changes in v3: - Changed the subject - Changed the BBT pattern offsets (patch 4); They are now zero as in Linux
Changes in v2: - Dropped patches 2, 3 and 6 so this one changed from 7 to 4 - Rebased to u-boot-imx next
drivers/mtd/nand/mxc_nand.c | 33 +++++++++++++++++++++++++++++++++ 1 files changed, 33 insertions(+), 0 deletions(-)
diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c index 35e89a0..936186f 100644 --- a/drivers/mtd/nand/mxc_nand.c +++ b/drivers/mtd/nand/mxc_nand.c @@ -1302,12 +1302,45 @@ static void mxc_setup_config1(void) #define mxc_setup_config1() #endif
+#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT + +static u8 bbt_pattern[] = {'B', 'b', 't', '0' }; +static u8 mirror_pattern[] = {'1', 't', 'b', 'B' }; + +static struct nand_bbt_descr bbt_main_descr = { + .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | + NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, + .offs = 0, + .len = 4, + .veroffs = 4, + .maxblocks = 4, + .pattern = bbt_pattern, +}; + +static struct nand_bbt_descr bbt_mirror_descr = { + .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | + NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, + .offs = 0, + .len = 4, + .veroffs = 4, + .maxblocks = 4, + .pattern = mirror_pattern, +}; + +#endif + int board_nand_init(struct nand_chip *this) { struct mtd_info *mtd; uint16_t tmp; int err = 0;
+#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT + this->options |= NAND_USE_FLASH_BBT; + this->bbt_td = &bbt_main_descr; + this->bbt_md = &bbt_mirror_descr; +#endif + /* structures must be linked */ mtd = &host->mtd; mtd->priv = this;
On 04/19/2012 03:55 AM, Timo Ketola wrote:
Signed-off-by: Timo Ketola timo@exertus.fi
Changes in v4:
- Removed blank lines inside #ifdef
- Manipulate 'this->options' with '|=' instead of '='
Changes in v3:
- Changed the subject
- Changed the BBT pattern offsets (patch 4); They are now zero as in Linux
Changes in v2:
- Dropped patches 2, 3 and 6 so this one changed from 7 to 4
- Rebased to u-boot-imx next
drivers/mtd/nand/mxc_nand.c | 33 +++++++++++++++++++++++++++++++++ 1 files changed, 33 insertions(+), 0 deletions(-)
Acked-by: Scott Wood scottwood@freescale.com
-Scott
On 19/04/2012 10:55, Timo Ketola wrote:
Signed-off-by: Timo Ketola timo@exertus.fi
Changes in v4:
- Removed blank lines inside #ifdef
- Manipulate 'this->options' with '|=' instead of '='
Changes in v3:
- Changed the subject
- Changed the BBT pattern offsets (patch 4); They are now zero as in Linux
Changes in v2:
- Dropped patches 2, 3 and 6 so this one changed from 7 to 4
- Rebased to u-boot-imx next
Applied to u-boot-imx, thanks.
Best regards, Stefano Babic
The USB controller in i.MX25 has a PORTSCx registers which should be set. In this regard it is similar to the controller in i.MX31. As this file is compiled only with i.MX25 and -31, #ifdef check can be removed.
Signed-off-by: Timo Ketola timo@exertus.fi ---
Changes in v4: - Reworded subject to shorten it - Added commit message - Changed the fix from adding i.MX25 to removing the check altogether
Changes in v2: - Dropped patches 2, 3 and 6 so this one changed from 8 to 5 - Rebased to u-boot-imx next
drivers/usb/host/ehci-mxc.c | 2 -- 1 files changed, 0 insertions(+), 2 deletions(-)
diff --git a/drivers/usb/host/ehci-mxc.c b/drivers/usb/host/ehci-mxc.c index 61dbccd..7384580 100644 --- a/drivers/usb/host/ehci-mxc.c +++ b/drivers/usb/host/ehci-mxc.c @@ -125,11 +125,9 @@ int ehci_hcd_init(void) hcor = (struct ehci_hcor *)((uint32_t) hccr + HC_LENGTH(ehci_readl(&hccr->cr_capbase))); setbits_le32(&ehci->usbmode, CM_HOST); -#ifdef CONFIG_MX31 setbits_le32(&ehci->control, USB_EN);
__raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc); -#endif mxc_set_usbcontrol(CONFIG_MXC_USB_PORT, CONFIG_MXC_USB_FLAGS);
udelay(10000);
On 19/04/2012 10:55, Timo Ketola wrote:
The USB controller in i.MX25 has a PORTSCx registers which should be set. In this regard it is similar to the controller in i.MX31. As this file is compiled only with i.MX25 and -31, #ifdef check can be removed.
Signed-off-by: Timo Ketola timo@exertus.fi
Acked-by: Stefano Babic sbabic@denx.de
Best regards, Stefano Babic
Dear Stefano Babic,
On 19/04/2012 10:55, Timo Ketola wrote:
The USB controller in i.MX25 has a PORTSCx registers which should be set. In this regard it is similar to the controller in i.MX31. As this file is compiled only with i.MX25 and -31, #ifdef check can be removed.
Signed-off-by: Timo Ketola timo@exertus.fi
Acked-by: Stefano Babic sbabic@denx.de
Stefano, will you apply these two USB patches please?
Best regards, Stefano Babic
Best regards, Marek Vasut
On 19/04/2012 10:55, Timo Ketola wrote:
The USB controller in i.MX25 has a PORTSCx registers which should be set. In this regard it is similar to the controller in i.MX31. As this file is compiled only with i.MX25 and -31, #ifdef check can be removed.
Signed-off-by: Timo Ketola timo@exertus.fi
Changes in v4:
- Reworded subject to shorten it
- Added commit message
- Changed the fix from adding i.MX25 to removing the check altogether
Changes in v2:
- Dropped patches 2, 3 and 6 so this one changed from 8 to 5
- Rebased to u-boot-imx next
drivers/usb/host/ehci-mxc.c | 2 -- 1 files changed, 0 insertions(+), 2 deletions(-)
Applied to u-boot-imx, thanks.
Best regards, Stefano Babic
The reference manual of i.MX25 (nor i.MX31) does not define such register. This seems to access read only UH2_CAPLENGTH register (if CONFIG_MXC_USB_PORT is zero).
Signed-off-by: Timo Ketola timo@exertus.fi ---
Changes in v4: - Rewrapped commit message
Changes in v2: - New patch in this series
drivers/usb/host/ehci-mxc.c | 2 -- 1 files changed, 0 insertions(+), 2 deletions(-)
diff --git a/drivers/usb/host/ehci-mxc.c b/drivers/usb/host/ehci-mxc.c index 7384580..45cbd18 100644 --- a/drivers/usb/host/ehci-mxc.c +++ b/drivers/usb/host/ehci-mxc.c @@ -125,8 +125,6 @@ int ehci_hcd_init(void) hcor = (struct ehci_hcor *)((uint32_t) hccr + HC_LENGTH(ehci_readl(&hccr->cr_capbase))); setbits_le32(&ehci->usbmode, CM_HOST); - setbits_le32(&ehci->control, USB_EN); - __raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc); mxc_set_usbcontrol(CONFIG_MXC_USB_PORT, CONFIG_MXC_USB_FLAGS);
On 19/04/2012 10:55, Timo Ketola wrote:
The reference manual of i.MX25 (nor i.MX31) does not define such register. This seems to access read only UH2_CAPLENGTH register (if CONFIG_MXC_USB_PORT is zero).
Signed-off-by: Timo Ketola timo@exertus.fi
Changes in v4:
- Rewrapped commit message
Changes in v2:
- New patch in this series
drivers/usb/host/ehci-mxc.c | 2 -- 1 files changed, 0 insertions(+), 2 deletions(-)
diff --git a/drivers/usb/host/ehci-mxc.c b/drivers/usb/host/ehci-mxc.c index 7384580..45cbd18 100644 --- a/drivers/usb/host/ehci-mxc.c +++ b/drivers/usb/host/ehci-mxc.c @@ -125,8 +125,6 @@ int ehci_hcd_init(void) hcor = (struct ehci_hcor *)((uint32_t) hccr + HC_LENGTH(ehci_readl(&hccr->cr_capbase))); setbits_le32(&ehci->usbmode, CM_HOST);
- setbits_le32(&ehci->control, USB_EN);
- __raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc); mxc_set_usbcontrol(CONFIG_MXC_USB_PORT, CONFIG_MXC_USB_FLAGS);
Acked-by: Stefano Babic sbabic@denx.de
Best regards, Stefano Babic
On 19/04/2012 10:55, Timo Ketola wrote:
The reference manual of i.MX25 (nor i.MX31) does not define such register. This seems to access read only UH2_CAPLENGTH register (if CONFIG_MXC_USB_PORT is zero).
Signed-off-by: Timo Ketola timo@exertus.fi
Applied to u-boot-imx, thanks.
Best regards, Stefano Babic
types.h must be included in imx-regs.h if one wants to include imx-regs.h in a board configuration file. That for one's part is necessary, if one wants to use addresses defined in imx-regs.h.
For example, fsl_esdhc.c needs CONFIG_SYS_FSL_ESDHC_ADDR defined and a proper thing is to define it with IMX_MMC_SDHCx_BASE in board configuration file. This patch fixes the build in that case.
Signed-off-by: Timo Ketola timo@exertus.fi ---
Changes in v4: - Proper fix was found so this patch changes altogether - subject, message and touched file
Changes in v2: - New patch in this series
arch/arm/include/asm/arch-mx25/imx-regs.h | 3 +++ 1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/arch/arm/include/asm/arch-mx25/imx-regs.h b/arch/arm/include/asm/arch-mx25/imx-regs.h index 7f9449b..cf925d7 100644 --- a/arch/arm/include/asm/arch-mx25/imx-regs.h +++ b/arch/arm/include/asm/arch-mx25/imx-regs.h @@ -34,6 +34,9 @@ #define _IMX_REGS_H
#ifndef __ASSEMBLY__ + +#include <asm/types.h> + #ifdef CONFIG_FEC_MXC extern void mx25_fec_init_pins(void); #endif
On 19/04/2012 10:55, Timo Ketola wrote:
types.h must be included in imx-regs.h if one wants to include imx-regs.h in a board configuration file. That for one's part is necessary, if one wants to use addresses defined in imx-regs.h.
For example, fsl_esdhc.c needs CONFIG_SYS_FSL_ESDHC_ADDR defined and a proper thing is to define it with IMX_MMC_SDHCx_BASE in board configuration file. This patch fixes the build in that case.
Signed-off-by: Timo Ketola timo@exertus.fi
Changes in v4:
- Proper fix was found so this patch changes altogether - subject, message and touched file
Changes in v2:
- New patch in this series
arch/arm/include/asm/arch-mx25/imx-regs.h | 3 +++ 1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/arch/arm/include/asm/arch-mx25/imx-regs.h b/arch/arm/include/asm/arch-mx25/imx-regs.h index 7f9449b..cf925d7 100644 --- a/arch/arm/include/asm/arch-mx25/imx-regs.h +++ b/arch/arm/include/asm/arch-mx25/imx-regs.h @@ -34,6 +34,9 @@ #define _IMX_REGS_H
#ifndef __ASSEMBLY__
+#include <asm/types.h>
#ifdef CONFIG_FEC_MXC extern void mx25_fec_init_pins(void); #endif
Acked-by: Stefano Babic sbabic@denx.de
Best regards, Stefano Babic
On 19/04/2012 10:55, Timo Ketola wrote:
types.h must be included in imx-regs.h if one wants to include imx-regs.h in a board configuration file. That for one's part is necessary, if one wants to use addresses defined in imx-regs.h.
For example, fsl_esdhc.c needs CONFIG_SYS_FSL_ESDHC_ADDR defined and a proper thing is to define it with IMX_MMC_SDHCx_BASE in board configuration file. This patch fixes the build in that case.
Signed-off-by: Timo Ketola timo@exertus.fi
Applied to u-boot-imx, thanks.
Best regards, Stefano Babic
Signed-off-by: Timo Ketola timo@exertus.fi ---
Changes in v3: - Dropped old patch number 8 "imx: nand: Don't invent new..." so this one changed from 9 to 8
Changes in v2: - New patch in this series - Add .imx target in the spirit of commit 303838
arch/arm/cpu/arm926ejs/config.mk | 6 ++++++ 1 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/config.mk b/arch/arm/cpu/arm926ejs/config.mk index ffb2e6c..6a3a1bb 100644 --- a/arch/arm/cpu/arm926ejs/config.mk +++ b/arch/arm/cpu/arm926ejs/config.mk @@ -31,3 +31,9 @@ PLATFORM_CPPFLAGS += -march=armv5te # ========================================================================= PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT) + +ifneq ($(CONFIG_IMX_CONFIG),) + +ALL-y += $(obj)u-boot.imx + +endif
On 19/04/2012 10:55, Timo Ketola wrote:
Signed-off-by: Timo Ketola timo@exertus.fi
Changes in v3:
- Dropped old patch number 8 "imx: nand: Don't invent new..." so this one changed from 9 to 8
Changes in v2:
- New patch in this series
- Add .imx target in the spirit of commit 303838
arch/arm/cpu/arm926ejs/config.mk | 6 ++++++ 1 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/config.mk b/arch/arm/cpu/arm926ejs/config.mk index ffb2e6c..6a3a1bb 100644 --- a/arch/arm/cpu/arm926ejs/config.mk +++ b/arch/arm/cpu/arm926ejs/config.mk @@ -31,3 +31,9 @@ PLATFORM_CPPFLAGS += -march=armv5te # ========================================================================= PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT)
+ifneq ($(CONFIG_IMX_CONFIG),)
+ALL-y += $(obj)u-boot.imx
+endif
Acked-by: Stefano Babic sbabic@denx.de
Best regards, Stefano Babic
participants (8)
-
Detlev Zundel -
Fabio Estevam -
Marek Vasut -
Scott Wood -
Stefano Babic -
Timo Ketola -
Troy Kisky -
Wolfgang Denk