New subject: [U-Boot] [PATCH V3] imx: i.mx6q: add the initial support for LogicPD i.MX6Q SOM

4 Apr 2017

Logic PD has an i.MX6Q system on module (SOM) with a development kit. The
SOM has a built-in microSD socket, DDR and NAND flash.  The development kit
has an SMSC Ethernet PHY, serial debug port and a variety of peripherals.
This have been verified to boot the i.MX6Q version over either SD
on the development kit or NAND built into the SOM.
Signed-off-by: Adam Ford aford173@gmail.com
---
Changes in V3:
  - Add OF_CONTROL and device tree
  - Switch to DM_I2C
  - Switch to DM_ETH
  - Switch to DM_MMC
  - Switch to DM_PMIC
  - Switch to DM_REGULATOR
  - Switch to DM_GPIO
  - Fix Ethernet reset to play nicely with DM_GPIO and DM_ETH
  - Remove more unnecessary code with DM enabled.
Changes in V2:
  - Alphabetize the modified Kconfig file
  - Clean up README file.
  - Elminate fdt_high and initrd_high and add bootm_size
  - Changed MTDPARTS_DEFAULT to increase the kernel size to 16MB
  - Cleaned up the mx6q_2x_MT41K512M16HA.cfg to include headers,
    replace hard-coded addresses with human-readable ones, and
    remove dead code
  - Updated mx6q_2x_MT41K512M16HA.cfg to use BOOT_OFFSET since SD
    and NAND have the same offset
  - Removed 'ifdef' references that were always true.
  - Removed CPU references that didn't exist.
  - And made local variables static
  - Add reference to worked used to derrive this code

diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig
index 190e5c6..18241d0 100644
--- a/arch/arm/cpu/armv7/mx6/Kconfig
+++ b/arch/arm/cpu/armv7/mx6/Kconfig
@@ -155,6 +155,20 @@ config TARGET_MX6CUBOXI
    select BOARD_LATE_INIT
    select SUPPORT_SPL
+config TARGET_MX6LOGICPD
+	bool "Logic PD i.MX6 SOM"
+	select BOARD_EARLY_INIT_F
+	select BOARD_LATE_INIT
+	select DM
+	select DM_ETH
+	select DM_GPIO
+	select DM_I2C
+	select DM_MMC
+	select DM_PMIC
+	select DM_REGULATOR
+	select DM_THERMAL
+	select OF_CONTROL
+
 config TARGET_MX6QARM2
    bool "mx6qarm2"
@@ -404,6 +418,7 @@ source "board/gateworks/gw_ventana/Kconfig"
 source "board/kosagi/novena/Kconfig"
 source "board/samtec/vining_2000/Kconfig"
 source "board/liebherr/mccmon6/Kconfig"
+source "board/logicpd/imx6/Kconfig"
 source "board/seco/Kconfig"
 source "board/solidrun/mx6cuboxi/Kconfig"
 source "board/technexion/pico-imx6ul/Kconfig"
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 0fbbb9b..a95f2db 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -319,6 +319,7 @@ dtb-$(CONFIG_MX6) += imx6ull-14x14-evk.dtb \
    imx6dl-icore-rqs.dtb \
    imx6q-icore.dtb \
    imx6q-icore-rqs.dtb \
+	imx6q-logicpd.dtb \
    imx6sx-sabreauto.dtb \
    imx6ul-geam-kit.dtb \
    imx6ul-isiot-emmc.dtb \
diff --git a/arch/arm/dts/imx6q-logicpd.dts b/arch/arm/dts/imx6q-logicpd.dts
new file mode 100644
index 0000000..f5ac5d9
--- /dev/null
+++ b/arch/arm/dts/imx6q-logicpd.dts
@@ -0,0 +1,220 @@
+/*
+ * Copyright 2017 Logic PD, Inc.
+ * Based on SabreSD, Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "imx6qdl-logicpd.dtsi"
+
+/ {
+	model = "Logic PD i.MX6QDL SOM";
+	compatible = "fsl,imx6q";
+
+	leds {
+		compatible = "gpio-leds";
+
+		gen_led0 {
+			label = "cpu0";
+			gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "cpu0";
+		};
+
+		gen_led1 {
+			label = "cpu1";
+			gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "cpu1";
+		};
+
+		gen_led2 {
+			label = "heartbeat";
+			gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "heartbeat";
+		};
+
+		gen_led3 {
+			label = "Always On";
+			gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "default-on";
+		};
+	};
+
+	reg_usb_otg_vbus: regulator-otg-vbus@0 {
+		compatible = "regulator-fixed";
+		regulator-name = "usb_otg_vbus";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+
+	reg_usb_h1_vbus: regulator-usbh1vbus@1 {
+		compatible = "regulator-fixed";
+		regulator-name = "usb_h1_vbus";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		enable-active-high;
+		regulator-always-on;
+		gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>;
+	};
+
+	reg_3v3: regulator-3v3@2 {
+		compatible = "regulator-fixed";
+		regulator-name = "reg_3v3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+};
+
+&uart3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart3>;
+	status = "okay";
+};
+
+&usbh1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usbh1>;
+	vbus-supply = <&reg_usb_h1_vbus>;
+	status = "okay";
+};
+
+&usbh2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usbh2>;
+	phy_type = "hsic";
+	disable-over-current;
+	status = "okay";
+};
+
+&usbotg {
+	vbus-supply = <&reg_usb_otg_vbus>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usbotg>;
+	disable-over-current;
+	status = "okay";
+};
+
+&fec {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_enet>;
+	phy-mode = "rmii";
+	phy-speed = <10>;
+	status = "okay";
+};
+
+&usdhc2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc2>;
+	cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
+	no-1-8-v;
+	keep-power-in-suspend;
+	status = "okay";
+};
+
+&iomuxc {
+	pinctrl_uart3: uart3grp {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_D23__UART3_CTS_B	0x1b0b1
+			MX6QDL_PAD_EIM_D24__UART3_TX_DATA	0x1b0b1
+			MX6QDL_PAD_EIM_D25__UART3_RX_DATA	0x1b0b1
+			MX6QDL_PAD_EIM_EB3__UART3_RTS_B	0x1b0b1
+		>;
+	};
+
+	pinctrl_usbotg: usbotggrp {
+	fsl,pins = <
+		MX6QDL_PAD_GPIO_1__USB_OTG_ID	0x17059
+		MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x130b0	/* USB_OTG_PWR_EN */
+		>;
+	};
+
+	pinctrl_usbh1: usbh1grp {
+		fsl,pins = <
+			MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0	/* USB_H1_PWR_EN */
+		>;
+	};
+
+	pinctrl_usbh2: usbh2grp {
+		fsl,pins = <
+			MX6QDL_PAD_RGMII_TXC__USB_H2_DATA      0x13030
+			MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x17030
+		>;
+	};
+
+	pinctrl_usdhc2: usdhc2grp {
+		fsl,pins = <
+			MX6QDL_PAD_SD2_CLK__SD2_CLK    0x10059
+			MX6QDL_PAD_SD2_CMD__SD2_CMD    0x17059
+			MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
+			MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
+			MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
+			MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
+		>;
+	};
+
+	pinctrl_enet: enetgrp {
+		fsl,pins = <
+			MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN	0x1b0b0
+			MX6QDL_PAD_ENET_MDIO__ENET_MDIO	0x1b0b0
+			MX6QDL_PAD_ENET_MDC__ENET_MDC	0x1b0b0
+			MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER	0x1b0b0
+			MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0	0x1b0b0
+			MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1	0x1b0b0
+			MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN	0x1b0b0
+			MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0	0x1b0b0
+			MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1	0x1b0b0
+			MX6QDL_PAD_GPIO_16__ENET_REF_CLK	0x4001b0a8
+			MX6QDL_PAD_KEY_ROW0__GPIO4_IO07		0x1b0b0 /* nINT */
+			MX6QDL_PAD_KEY_ROW1__GPIO4_IO09		0x1b0b0 /* Ethernet Reset */
+		>;
+	};
+
+	pinctrl_gpio_leds: gpioledsgrp {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_D19__GPIO3_IO19	0x130b0
+			MX6QDL_PAD_EIM_D20__GPIO3_IO20	0x130b0
+			MX6QDL_PAD_EIM_D21__GPIO3_IO21	0x130b0
+			MX6QDL_PAD_EIM_D22__GPIO3_IO22	0x130b0
+		>;
+	};
+};
+
diff --git a/arch/arm/dts/imx6qdl-logicpd.dtsi b/arch/arm/dts/imx6qdl-logicpd.dtsi
new file mode 100644
index 0000000..592ad05
--- /dev/null
+++ b/arch/arm/dts/imx6qdl-logicpd.dtsi
@@ -0,0 +1,418 @@
+/*
+ * Copyright 2016 Logic PD
+ * This file is adapted from imx6qdl-sabresd.dtsi.
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include "imx6q.dtsi"
+
+/ {
+	chosen {
+		stdout-path = &uart1;
+	};
+
+	memory {
+		reg = <0x10000000 0x80000000>;
+	};
+};
+
+/* Reroute power feeding the CPU to come from the external PMIC */
+&reg_arm
+{
+	vin-supply = <&sw1a_reg>;
+};
+
+&reg_soc
+{
+	vin-supply = <&sw1c_reg>;
+};
+
+&clks {
+	assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
+			  <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
+	assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
+				 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
+};
+
+&gpmi {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_gpmi_nand>;
+	status = "okay";
+	nand-on-flash-bbt;
+};
+
+&i2c3 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c3>;
+	status = "okay";
+
+	pmic: pfuze100@08 {
+		compatible = "fsl,pfuze100";
+		reg = <0x08>;
+
+		regulators {
+			sw1a_reg: sw1ab {
+				regulator-min-microvolt = <725000>;
+				regulator-max-microvolt = <1450000>;
+				regulator-name = "vddcore";
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <6250>;
+			};
+
+			sw1c_reg: sw1c {
+				regulator-min-microvolt = <725000>;
+				regulator-max-microvolt = <1450000>;
+				regulator-name = "vddsoc";
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <6250>;
+			};
+
+			sw2_reg: sw2 {
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "gen_3v3";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			sw3a_reg: sw3a {
+				regulator-min-microvolt = <400000>;
+				regulator-max-microvolt = <1975000>;
+				regulator-name = "sw3a_vddr";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			sw3b_reg: sw3b {
+				regulator-min-microvolt = <400000>;
+				regulator-max-microvolt = <1975000>;
+				regulator-name = "sw3b_vddr";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			sw4_reg: sw4 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "gen_rgmii";
+			};
+
+
+			swbst_reg: swbst {
+				regulator-min-microvolt = <5000000>;
+				regulator-max-microvolt = <5150000>;
+				regulator-name = "gen_5v0";
+			};
+
+			snvs_reg: vsnvs {
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-name = "gen_vsns";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			vref_reg: vrefddr {
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			vgen1_reg: vgen1 {
+				regulator-min-microvolt = <1500000>;
+				regulator-max-microvolt = <1500000>;
+				regulator-name = "gen_1v5";
+			};
+
+			vgen2_reg: vgen2 {
+				regulator-name = "vgen2";
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1550000>;
+			};
+
+			vgen3_reg: vgen3 {
+				regulator-name = "gen_vadj_0";
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3000000>;
+			};
+
+			vgen4_reg: vgen4 {
+				regulator-name = "gen_1v8";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-always-on;
+			};
+
+			vgen5_reg: vgen5 {
+				regulator-name = "gen_adj_1";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen6_reg: vgen6 {
+				regulator-name = "gen_2v5";
+				regulator-min-microvolt = <2500000>;
+				regulator-max-microvolt = <2500000>;
+				regulator-always-on;
+			};
+		};
+	};
+
+	temp_sense0: tmp102@4a {
+		compatible = "ti,tmp102";
+		reg = <0x4a>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_tempsense>;
+		interrupt-parent = <&gpio6>;
+		interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
+		#thermal-sensor-cells = <1>;
+	};
+
+	temp_sense1: tmp102@49 {
+		compatible = "ti,tmp102";
+		reg = <0x49>;
+		interrupt-parent = <&gpio6>;
+		interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
+		#thermal-sensor-cells = <1>;
+	};
+
+	mfg_eeprom: at24@51 {
+		compatible = "atmel,24c64";
+		pagesize = <32>;
+		read-only;
+		reg = <0x51>;
+	};
+
+	user_eeprom: at24@52 {
+		compatible = "atmel,24c64";
+		pagesize = <32>;
+		reg = <0x52>;
+	};
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hog>;
+
+	pinctrl_hog: hoggrp {
+		fsl,pins = <
+			MX6QDL_PAD_CSI0_MCLK__ARM_TRACE_CTL		0x1b0b0
+			MX6QDL_PAD_CSI0_DATA_EN__ARM_TRACE_CLK	0x1b0b0
+			MX6QDL_PAD_CSI0_VSYNC__ARM_TRACE00		0x1b0b0
+			MX6QDL_PAD_CSI0_DAT4__ARM_TRACE01		0x1b0b0
+			MX6QDL_PAD_CSI0_DAT5__ARM_TRACE02		0x1b0b0
+			MX6QDL_PAD_CSI0_DAT6__ARM_TRACE03		0x1b0b0
+			MX6QDL_PAD_CSI0_DAT7__ARM_TRACE04		0x1b0b0
+			MX6QDL_PAD_CSI0_DAT8__ARM_TRACE05		0x1b0b0
+			MX6QDL_PAD_CSI0_DAT9__ARM_TRACE06		0x1b0b0
+			MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07		0x1b0b0
+			MX6QDL_PAD_CSI0_DAT11__ARM_TRACE08		0x1b0b0
+			MX6QDL_PAD_CSI0_DAT12__ARM_TRACE09		0x1b0b0
+			MX6QDL_PAD_CSI0_DAT13__ARM_TRACE10		0x1b0b0
+			MX6QDL_PAD_CSI0_DAT14__ARM_TRACE11		0x1b0b0
+			MX6QDL_PAD_CSI0_DAT15__ARM_TRACE12		0x1b0b0
+			MX6QDL_PAD_CSI0_DAT16__ARM_TRACE13		0x1b0b0
+			MX6QDL_PAD_CSI0_DAT17__ARM_TRACE14		0x1b0b0
+			MX6QDL_PAD_CSI0_DAT18__ARM_TRACE15		0x1b0b0
+			MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05	0x1b0b0
+			MX6QDL_PAD_EIM_LBA__GPIO2_IO27	0x80000000
+			MX6QDL_PAD_EIM_OE__GPIO2_IO25	0x80000000
+			MX6QDL_PAD_EIM_RW__GPIO2_IO26	0x80000000
+			MX6QDL_PAD_EIM_CS0__GPIO2_IO23	0x80000000
+			MX6QDL_PAD_EIM_CS1__GPIO2_IO24	0x80000000
+			MX6QDL_PAD_EIM_A16__GPIO2_IO22	0x80000000
+			MX6QDL_PAD_EIM_A17__GPIO2_IO21	0x80000000
+			MX6QDL_PAD_EIM_A18__GPIO2_IO20	0x80000000
+			MX6QDL_PAD_EIM_A19__GPIO2_IO19	0x80000000
+			MX6QDL_PAD_EIM_A20__GPIO2_IO18	0x80000000
+			MX6QDL_PAD_EIM_A21__GPIO2_IO17	0x80000000
+			MX6QDL_PAD_EIM_A22__GPIO2_IO16	0x80000000
+			MX6QDL_PAD_EIM_A23__GPIO6_IO06	0x80000000
+			MX6QDL_PAD_EIM_A24__GPIO5_IO04	0x80000000
+			MX6QDL_PAD_EIM_A25__GPIO5_IO02	0x80000000
+			MX6QDL_PAD_EIM_DA0__GPIO3_IO00	0x80000000
+			MX6QDL_PAD_EIM_DA1__GPIO3_IO01	0x80000000
+			MX6QDL_PAD_EIM_DA2__GPIO3_IO02	0x80000000
+			MX6QDL_PAD_EIM_DA3__GPIO3_IO03	0x80000000
+			MX6QDL_PAD_EIM_DA4__GPIO3_IO04	0x80000000
+			MX6QDL_PAD_EIM_DA5__GPIO3_IO05	0x80000000
+			MX6QDL_PAD_EIM_DA6__GPIO3_IO06	0x80000000
+			MX6QDL_PAD_EIM_DA7__GPIO3_IO07	0x80000000
+			MX6QDL_PAD_EIM_DA8__GPIO3_IO08	0x80000000
+			MX6QDL_PAD_EIM_DA9__GPIO3_IO09	0x80000000
+			MX6QDL_PAD_EIM_DA10__GPIO3_IO10	0x80000000
+			MX6QDL_PAD_EIM_DA11__GPIO3_IO11	0x80000000
+			MX6QDL_PAD_EIM_DA12__GPIO3_IO12	0x80000000
+			MX6QDL_PAD_EIM_DA13__GPIO3_IO13	0x80000000
+			MX6QDL_PAD_EIM_DA14__GPIO3_IO14	0x80000000
+			MX6QDL_PAD_EIM_DA15__GPIO3_IO15	0x80000000
+			MX6QDL_PAD_EIM_D16__GPIO3_IO16	0x80000000
+			MX6QDL_PAD_EIM_D19__GPIO3_IO19	0x80000000
+			MX6QDL_PAD_EIM_D20__GPIO3_IO20	0x80000000
+			MX6QDL_PAD_EIM_D21__GPIO3_IO21	0x80000000
+			MX6QDL_PAD_EIM_D22__GPIO3_IO22	0x80000000
+			MX6QDL_PAD_EIM_D26__GPIO3_IO26	0x80000000
+			MX6QDL_PAD_EIM_D27__GPIO3_IO27	0x80000000
+			MX6QDL_PAD_EIM_EB0__GPIO2_IO28	0x80000000
+			MX6QDL_PAD_EIM_EB1__GPIO2_IO29	0x80000000
+			MX6QDL_PAD_EIM_EB2__GPIO2_IO30	0x80000000
+			MX6QDL_PAD_EIM_BCLK__GPIO6_IO31	0x80000000
+			MX6QDL_PAD_EIM_WAIT__GPIO5_IO00	0x80000000
+			MX6QDL_PAD_GPIO_2__GPIO1_IO02	0x80000000
+			MX6QDL_PAD_GPIO_4__GPIO1_IO04	0x80000000
+			MX6QDL_PAD_GPIO_7__GPIO1_IO07	0x80000000
+			MX6QDL_PAD_GPIO_8__GPIO1_IO08	0x80000000
+			MX6QDL_PAD_GPIO_9__GPIO1_IO09	0x80000000
+			MX6QDL_PAD_GPIO_17__GPIO7_IO12	0x80000000
+			MX6QDL_PAD_GPIO_18__GPIO7_IO13	0x80000000
+			MX6QDL_PAD_GPIO_19__GPIO4_IO05	0x80000000
+			MX6QDL_PAD_KEY_COL0__GPIO4_IO06	0x80000000
+			MX6QDL_PAD_KEY_ROW0__GPIO4_IO07	0x80000000
+			MX6QDL_PAD_KEY_COL1__GPIO4_IO08	0x80000000
+			MX6QDL_PAD_NANDF_CS1__GPIO6_IO14	0x80000000
+			MX6QDL_PAD_NANDF_CS3__GPIO6_IO16	0x80000000
+			MX6QDL_PAD_RGMII_TD0__GPIO6_IO20	0x80000000
+			MX6QDL_PAD_RGMII_TD1__GPIO6_IO21	0x80000000
+			MX6QDL_PAD_RGMII_TD2__GPIO6_IO22	0x80000000
+			MX6QDL_PAD_RGMII_TD3__GPIO6_IO23	0x80000000
+			MX6QDL_PAD_RGMII_RD0__GPIO6_IO25	0x80000000
+			MX6QDL_PAD_RGMII_RD1__GPIO6_IO27	0x80000000
+			MX6QDL_PAD_RGMII_RD2__GPIO6_IO28	0x80000000
+			MX6QDL_PAD_RGMII_RD3__GPIO6_IO29	0x80000000
+			MX6QDL_PAD_SD4_DAT0__GPIO2_IO08	0x80000000
+			MX6QDL_PAD_SD4_DAT3__GPIO2_IO11	0x80000000
+		>;
+	};
+
+	pinctrl_gpmi_nand: gpminandgrp {
+		fsl,pins = <
+			MX6QDL_PAD_NANDF_CLE__NAND_CLE		0x0b0b1
+			MX6QDL_PAD_NANDF_ALE__NAND_ALE		0x0b0b1
+			MX6QDL_PAD_NANDF_WP_B__NAND_WP_B	0x0b0b1
+			MX6QDL_PAD_NANDF_RB0__NAND_READY_B	0x0b000
+			MX6QDL_PAD_NANDF_CS0__NAND_CE0_B	0x0b0b1
+			MX6QDL_PAD_SD4_CMD__NAND_RE_B		0x0b0b1
+			MX6QDL_PAD_SD4_CLK__NAND_WE_B		0x0b0b1
+			MX6QDL_PAD_NANDF_D0__NAND_DATA00	0x0b0b1
+			MX6QDL_PAD_NANDF_D1__NAND_DATA01	0x0b0b1
+			MX6QDL_PAD_NANDF_D2__NAND_DATA02	0x0b0b1
+			MX6QDL_PAD_NANDF_D3__NAND_DATA03	0x0b0b1
+			MX6QDL_PAD_NANDF_D4__NAND_DATA04	0x0b0b1
+			MX6QDL_PAD_NANDF_D5__NAND_DATA05	0x0b0b1
+			MX6QDL_PAD_NANDF_D6__NAND_DATA06	0x0b0b1
+			MX6QDL_PAD_NANDF_D7__NAND_DATA07	0x0b0b1
+		>;
+	};
+
+
+	pinctrl_i2c3: i2c3grp {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_D17__I2C3_SCL		0x4001b8b1
+			MX6QDL_PAD_EIM_D18__I2C3_SDA		0x4001b8b1
+		>;
+	};
+
+	pinctrl_uart1: uart1grp {
+		fsl,pins = <
+			MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA	0x1b0b1
+			MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA	0x1b0b1
+		>;
+	};
+
+	pinctrl_uart2: uart2grp {
+		fsl,pins = <
+			MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA	0x1b0b1
+			MX6QDL_PAD_SD4_DAT5__UART2_RTS_B	0x1b0b1
+			MX6QDL_PAD_SD4_DAT6__UART2_CTS_B	0x1b0b1
+			MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA	0x1b0b1
+		>;
+	};
+
+	pinctrl_usdhc1: usdhc1grp {
+		fsl,pins = <
+			MX6QDL_PAD_SD1_CMD__SD1_CMD    0x17071
+			MX6QDL_PAD_SD1_CLK__SD1_CLK    0x10071
+			MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071
+			MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071
+			MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071
+			MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071
+		>;
+	};
+
+	pinctrl_usdhc3: usdhc3grp {
+		fsl,pins = <
+			MX6QDL_PAD_SD3_CMD__SD3_CMD    0x17059
+			MX6QDL_PAD_SD3_CLK__SD3_CLK    0x10059
+			MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
+			MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
+			MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
+			MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
+			MX6QDL_PAD_SD3_DAT4__GPIO7_IO01	0x1f0b0 /* WL_IRQ */
+			MX6QDL_PAD_SD3_DAT5__GPIO7_IO00	0x1f0b0 /* WLAN_EN */
+			MX6QDL_PAD_SD3_RST__GPIO7_IO08	0x1f0b0	/* BT_EN */
+		>;
+	};
+
+	pinctrl_tempsense: tempsensegrp {
+		fsl,pins = <
+			MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0	/* Temp Sense Alert */
+		>;
+	};
+};
+
+&snvs_poweroff {
+	status = "okay";
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1>;
+	status = "okay";
+};
+
+&uart2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart2>;
+	status = "okay";
+};
+
+&usdhc1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc1>;
+	cd-gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>;
+	keep-power-in-suspend;
+	enable-sdio-wakeup;
+	status = "okay";
+};
+
+&usdhc3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc3>;
+	non-removable;
+	keep-power-in-suspend;
+	enable-sdio-wakeup;
+	vmmc-supply = <&sw2_reg>;
+	status = "okay";
+	#address-cells = <1>;
+	#size-cells = <0>;
+	wlcore: wlcore@0 {
+		  compatible = "ti,wl1837";
+		  reg = <2>;
+		  interrupt-parent = <&gpio7>;
+		  interrupts = <1 GPIO_ACTIVE_HIGH>;
+	};
+};
+
diff --git a/board/logicpd/imx6/Kconfig b/board/logicpd/imx6/Kconfig
new file mode 100644
index 0000000..f5e2f58
--- /dev/null
+++ b/board/logicpd/imx6/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MX6LOGICPD
+
+config SYS_BOARD
+       default "imx6"
+
+config SYS_VENDOR
+       default "logicpd"
+
+config SYS_CONFIG_NAME
+       default "imx6_logic"
+
+endif
diff --git a/board/logicpd/imx6/MAINTAINERS b/board/logicpd/imx6/MAINTAINERS
new file mode 100644
index 0000000..5db7d2c
--- /dev/null
+++ b/board/logicpd/imx6/MAINTAINERS
@@ -0,0 +1,6 @@
+MX6LOGICPD BOARD
+M:     Adam Ford aford173@gmail.com
+S:     Maintained
+F:     board/logicpd/imx6/
+F:     include/configs/imx6_logic.h
+F:     configs/imx6q_logic_defconfig
diff --git a/board/logicpd/imx6/Makefile b/board/logicpd/imx6/Makefile
new file mode 100644
index 0000000..337df92
--- /dev/null
+++ b/board/logicpd/imx6/Makefile
@@ -0,0 +1,10 @@
+#
+# Copyright (C) 2007, Guennadi Liakhovetski lg@denx.de
+#
+# (C) Copyright 2011 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y  := imx6logic.o
+
diff --git a/board/logicpd/imx6/README b/board/logicpd/imx6/README
new file mode 100644
index 0000000..7c9b6bd
--- /dev/null
+++ b/board/logicpd/imx6/README
@@ -0,0 +1,37 @@
+U-Boot for LogicPD i.MX6 Development Kit
+----------------------------------------
+
+This file contains information for the port of U-Boot to the Logic PD Development kit.
+
+Logic PD has an i.MX6 System On Module (SOM) and a correspondong development
+board.  SOM has a built-in microSD socket, DDR and NAND flash.  The development kit has
+an SMSC Ethernet PHY, serial debug port and a variety of peripherals.
+
+On the intial release, the SOM came with an i.MX6D and i.MX6Q.
+
+For more details about Logic PD i.MX6 Development kit, visit:
+https://www.logicpd.com/
+
+Building U-Boot for Logic PD Development Kit
+--------------------------------------------
+To build U-Boot for the Dual and Quad variants:
+
+ make imx6q_logic_defconfig
+ make u-boot.imx ARCH=arm CROSS_COMPILE=arm-linux-
+
+
+Flashing U-Boot into the SD card
+--------------------------------
+
+See README.imximage for details on booting from SD
+
+Flashing U-Boot into NAND
+-------------------------
+Once in Linux with MTD support for the NAND on /dev/mtd0, program U-Boot with the following:
+with:
+
+  kobs-ng init -v -x u-boot.imx
+
+Additional Support Documentation can be found at:
+https://support.logicpd.com/
+
diff --git a/board/logicpd/imx6/imx6logic.c b/board/logicpd/imx6/imx6logic.c
new file mode 100644
index 0000000..fd8f330
--- /dev/null
+++ b/board/logicpd/imx6/imx6logic.c
@@ -0,0 +1,190 @@
+/*
+ * Copyright (C) 2017 Logic PD, Inc.
+ *
+ * Author: Adam Ford aford173@gmail.com
+ *
+ * Based on SabreSD by Fabio Estevam fabio.estevam@nxp.com
+ * and updates by Jagan Teki jagan@amarulasolutions.com
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <linux/sizes.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mxc_hdmi.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/imx-common/boot_mode.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |            \
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
+	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define NAND_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |            \
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   |             \
+	PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
+
+int dram_init(void)
+{
+	gd->ram_size = imx_ddr_size();
+	return 0;
+}
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+	MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const uart2_pads[] = {
+	MX6_PAD_SD4_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_SD4_DAT5__UART2_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_SD4_DAT6__UART2_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_SD4_DAT7__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const uart3_pads[] = {
+	MX6_PAD_EIM_D23__UART3_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_EIM_EB3__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static void fixup_enet_clock(void)
+{
+	struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+	struct gpio_desc nint;
+	struct gpio_desc reset;
+	int ret;
+
+	/* Set GPIO_16 as ENET_REF_CLK_OUT */
+	setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
+
+	/* Request GPIO Pins to reset Ethernet with new clock */
+	ret = dm_gpio_lookup_name("GPIO4_7", &nint);
+	if (ret) {
+		printf("Unable to lookup GPIO4_7\n");
+		return;
+	}
+
+	ret = dm_gpio_request(&nint, "eth0_nInt");
+	if (ret) {
+		printf("Unable to request eth0_nInt\n");
+		return;
+	}
+	/* Ensure nINT is input or PHY won't startup */
+	dm_gpio_set_dir_flags(&nint, GPIOD_IS_IN);
+
+	ret = dm_gpio_lookup_name("GPIO4_9", &reset);
+	if (ret) {
+		printf("Unable to lookup GPIO4_9\n");
+		return;
+	}
+
+	ret = dm_gpio_request(&reset, "eth0_reset");
+	if (ret) {
+		printf("Unable to request eth0_reset\n");
+		return;
+	}
+
+	/* Reset LAN8710A PHY */
+	dm_gpio_set_dir_flags(&reset, GPIOD_IS_OUT);
+	dm_gpio_set_value(&reset, 0);
+	udelay(150);
+	dm_gpio_set_value(&reset, 1);
+	mdelay(50);
+}
+
+static void setup_iomux_uart(void)
+{
+	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+	imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
+	imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
+}
+
+static iomux_v3_cfg_t const nand_pads[] = {
+	MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_NANDF_ALE__NAND_ALE  | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_NANDF_CLE__NAND_CLE  | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_NANDF_WP_B__NAND_WP_B  | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_NANDF_RB0__NAND_READY_B   | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_NANDF_D0__NAND_DATA00    | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_NANDF_D1__NAND_DATA01    | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_NANDF_D2__NAND_DATA02    | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_NANDF_D3__NAND_DATA03    | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_NANDF_D4__NAND_DATA04    | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_NANDF_D5__NAND_DATA05    | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_NANDF_D6__NAND_DATA06    | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_NANDF_D7__NAND_DATA07    | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_SD4_CLK__NAND_WE_B    | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_SD4_CMD__NAND_RE_B    | MUX_PAD_CTRL(NAND_PAD_CTRL),
+};
+
+static void setup_nand_pins(void)
+{
+	imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	fixup_enet_clock();
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+
+/*
+ * Do not overwrite the console
+ * Use always serial for U-Boot console
+ */
+int overwrite_console(void)
+{
+	return 1;
+}
+
+int board_early_init_f(void)
+{
+	setup_iomux_uart();
+	setup_nand_pins();
+	return 0;
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+	enable_fec_anatop_clock(0, ENET_50MHZ);
+	return 0;
+}
+
+static const struct boot_mode board_boot_modes[] = {
+	/* 4 bit bus width */
+	/* 4 bit bus width */
+	{"sd1",  MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
+	{"sd2",  MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
+	{NULL,   0},
+};
+
+int board_late_init(void)
+{
+	add_board_boot_modes(board_boot_modes);
+	setenv("board_name", "imx6logic");
+
+	if (is_mx6dq()) {
+		setenv("board_rev", "MX6DQ");
+		setenv("fdt_file", "imx6q-logicpd.dtb");
+	}
+	return 0;
+}
diff --git a/board/logicpd/imx6/mx6q_2x_MT41K512M16HA.cfg b/board/logicpd/imx6/mx6q_2x_MT41K512M16HA.cfg
new file mode 100644
index 0000000..b206548
--- /dev/null
+++ b/board/logicpd/imx6/mx6q_2x_MT41K512M16HA.cfg
@@ -0,0 +1,112 @@
+/*
+ * Copyright (C) 2017 Logic PD, Inc.
+ * Adam Ford aford173@gmail.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#include <asm/imx-common/imximage.cfg>
+
+/* image version */
+IMAGE_VERSION 2
+
+BOOT_OFFSET FLASH_OFFSET_STANDARD
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *      Addr-type register length (1,2 or 4 bytes)
+ *      Address   absolute address of the register
+ *      value     value to be stored in the register
+ */
+
+#define __ASSEMBLY__
+#include <config.h>
+#include "asm/arch-mx6/mx6-ddr.h"
+#include "asm/arch-mx6/iomux.h"
+#include "asm/arch-mx6/crm_regs.h"
+
+DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000
+DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
+DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00000030
+DATA 4, MX6_IOM_DRAM_CAS, 0x00000030
+DATA 4, MX6_IOM_DRAM_RAS, 0x00000030
+DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030
+DATA 4, MX6_IOM_DRAM_RESET, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
+DATA 4, MX6_IOM_DRAM_SDODT0, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDODT1, 0x00000030
+DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030
+DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
+DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030
+DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
+DATA 4, MX6_IOM_GRP_B0DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B1DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B2DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B3DS, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM0, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM1, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM2, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM3, 0x00000030
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
+DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003
+DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x002D003A
+DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x0038002B
+DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x03340338
+DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x0334032C
+DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4036383C
+DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x2E384038
+DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
+DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036
+DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040
+DATA 4, MX6_MMDC_P0_MDCFG0, 0xB8BE7955
+DATA 4, MX6_MMDC_P0_MDCFG1, 0xFF328F64
+DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
+DATA 4, MX6_MMDC_P0_MDMISC, 0x00011740
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
+DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
+DATA 4, MX6_MMDC_P0_MDOR, 0x00BE1023
+DATA 4, MX6_MMDC_P0_MDASP, 0x00000047
+DATA 4, MX6_MMDC_P0_MDCTL, 0x85190000
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00888032
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008031
+DATA 4, MX6_MMDC_P0_MDSCR, 0x19408030
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
+DATA 4, MX6_MMDC_P0_MDREF, 0x00007800
+DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00000007
+DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576
+DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
+
+/* set the default clock gate to save power */
+DATA 4, CCM_CCGR0, 0x00C03F3F
+DATA 4, CCM_CCGR1, 0x0030FC03
+DATA 4, CCM_CCGR2, 0x0FFFC000
+DATA 4, CCM_CCGR3, 0x3FF00000
+DATA 4, CCM_CCGR4, 0xFFFFF300
+DATA 4, CCM_CCGR5, 0x0F0000F3
+DATA 4, CCM_CCGR6, 0x00000FFF
+
+/* enable AXI cache for VDOA/VPU/IPU */
+DATA 4 MX6_IOMUXC_GPR4 0xF00000CF
+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+DATA 4 MX6_IOMUXC_GPR6 0x007F007F
+DATA 4 MX6_IOMUXC_GPR7 0x007F007F
diff --git a/configs/imx6q_logic_defconfig b/configs/imx6q_logic_defconfig
new file mode 100644
index 0000000..828adde
--- /dev/null
+++ b/configs/imx6q_logic_defconfig
@@ -0,0 +1,39 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_TARGET_MX6LOGICPD=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6q-logicpd"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/logicpd/imx6/mx6q_2x_MT41K512M16HA.cfg,MX6Q"
+CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="i.MX6 Logic # "
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_NAND_MXS=y
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_OF_LIBFDT=y
+# CONFIG_BLK is not set
+# CONFIG_DM_MMC_OPS is not set
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_FEC_MXC=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+
diff --git a/include/configs/imx6_logic.h b/include/configs/imx6_logic.h
new file mode 100644
index 0000000..7c23ff4
--- /dev/null
+++ b/include/configs/imx6_logic.h
@@ -0,0 +1,186 @@
+/*
+ * Copyright (C) 2017 Logic PD, Inc.
+ *
+ * Configuration settings for the LogicPD i.MX6 SOM.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __IMX6LOGIC_CONFIG_H
+#define __IMX6LOGIC_CONFIG_H
+
+#define CONFIG_MXC_UART_BASE   UART1_BASE
+#define CONSOLE_DEV            "ttymxc0"
+
+#include <config_distro_defaults.h>
+#include "mx6_common.h"
+
+#define CONFIG_IMX_THERMAL
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN          (10 * SZ_1M)
+
+#define CONFIG_MXC_UART
+
+/* MMC Configs */
+#define CONFIG_SYS_FSL_ESDHC_ADDR      0
+#define CONFIG_SYS_FSL_USDHC_NUM       2
+#define CONFIG_MMCROOT         "/dev/mmcblk1p2" /* Dev kit SD card */
+
+/* Ethernet Configs */
+#define CONFIG_MII
+#define IMX_FEC_BASE                   ENET_BASE_ADDR
+#define CONFIG_FEC_XCV_TYPE            RMII
+#define CONFIG_ETHPRIME                "FEC"
+#define CONFIG_FEC_MXC_PHYADDR         0
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_SMSC
+
+/* Command definition */
+#define CONFIG_CMD_BMODE
+
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"script=boot.scr\0" \
+	"image=zImage\0" \
+	"bootm_size=0x10000000\0" \
+	"fdt_addr_r=0x18000000\0" \
+	"fdt_addr=0x18000000\0" \
+	"ramdisk_addr_r=0x13000000\0" \
+	"ramdiskaddr=0x13000000\0" \
+	"kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
+	"ramdisk_file=rootfs.cpio.uboot\0" \
+	"boot_fdt=try\0" \
+	"ip_dyn=yes\0" \
+	"console=" CONSOLE_DEV "\0" \
+	"mmcdev=1\0" \
+	"mmcpart=1\0" \
+	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+	"nandroot=ubi0:rootfs rootfstype=ubifs\0" \
+	"mmcargs=setenv bootargs console=${console},${baudrate}" \
+	" root=${mmcroot} ${mtdparts}\0" \
+	"nandargs=setenv bootargs console=${console},${baudrate}" \
+	" ubi.mtd=fs root=${nandroot} ${mtdparts}\0" \
+	"ramargs=setenv bootargs console=${console},${baudrate}" \
+	" root=/dev/ram rw ${mtdparts}\0"                    \
+	"loadbootscript=" \
+	"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...;" \
+	" source\0" \
+	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image};" \
+	" setenv kernelsize ${filesize}\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+	"loadramdisk=fatload mmc ${mmcdev}:${mmcpart} ${ramdiskaddr} ${ramdisk_file};" \
+	" setenv ramdisksize ${filesize}\0" \
+	"mmcboot=echo Booting from mmc...; run mmcargs; run loadimage;" \
+	" run loadfdt; bootz ${loadaddr} - ${fdt_addr}\0" \
+	"mmcramboot=run ramargs; run loadimage;" \
+	" run loadfdt; run loadramdisk;" \
+	" bootz ${loadaddr} ${ramdiskaddr} ${fdt_addr}\0" \
+	"nandboot=echo Booting from nand ...; " \
+	" run nandargs;" \
+	" nand read ${loadaddr} kernel ${kernelsize};" \
+	" nand read ${fdt_addr} dtb;" \
+	" bootz ${loadaddr} - ${fdt_addr}\0" \
+	"nandramboot=echo Booting RAMdisk from nand ...; " \
+	" nand read ${ramdiskaddr} fs ${ramdisksize};" \
+	" nand read ${loadaddr} kernel ${kernelsize};" \
+	" nand read ${fdt_addr} dtb;" \
+	" run ramargs;" \
+	" bootz ${loadaddr} ${ramdiskaddr} ${fdt_addr}\0" \
+	"netargs=setenv bootargs console=${console},${baudrate} " \
+	"root=/dev/nfs" \
+	" ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+	"netboot=echo Booting from net ...; " \
+	"run netargs; " \
+	"if test ${ip_dyn} = yes; then " \
+		"setenv get_cmd dhcp; " \
+	"else " \
+		"setenv get_cmd tftp; " \
+	"fi; " \
+	"${get_cmd} ${image}; " \
+	"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+		"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+			"bootz ${loadaddr} - ${fdt_addr}; " \
+		"else " \
+			"if test ${boot_fdt} = try; then " \
+				"bootz; " \
+				"else " \
+				"echo WARN: Cannot load the DT; " \
+			"fi; " \
+		"fi; " \
+	"else " \
+	       "bootz; " \
+	"fi;\0" \
+	"autoboot=mmc dev ${mmcdev};" \
+	"if mmc rescan; then " \
+		"if run loadbootscript; then " \
+			"run bootscript; " \
+		"else " \
+		"if run loadimage; then " \
+			"run mmcboot; " \
+		"else run netboot; " \
+		"fi; " \
+	"fi; " \
+	"else run netboot; fi"
+#define CONFIG_BOOTCOMMAND \
+	"run autoboot"
+
+#define CONFIG_ARP_TIMEOUT     200UL
+
+#define CONFIG_SYS_MEMTEST_START       0x10000000
+#define CONFIG_SYS_MEMTEST_END         0x10010000
+#define CONFIG_SYS_MEMTEST_SCRATCH     0x10800000
+
+#define CONFIG_STACKSIZE               (128 * 1024)
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS           1
+#define PHYS_SDRAM                     MMDC0_ARB_BASE_ADDR
+#define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR       IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE       IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* Environment organization */
+#define CONFIG_ENV_SIZE                        (8 * 1024)
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET             0x400000
+#define CONFIG_ENV_SECT_SIZE          CONFIG_ENV_SIZE
+
+/* NAND flash command */
+
+#define CONFIG_CMD_NAND_TRIMFFS
+
+/* NAND stuff */
+#define CONFIG_SYS_MAX_NAND_DEVICE     1
+#define CONFIG_SYS_NAND_BASE           0x40000000
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x200000
+
+/* MTD device */
+# define CONFIG_MTD_DEVICE
+# define CONFIG_CMD_MTDPARTS
+# define CONFIG_MTD_PARTITIONS
+# define MTDIDS_DEFAULT		"nand0=gpmi-nand"
+# define MTDPARTS_DEFAULT	"mtdparts=gpmi-nand:4m(uboot)," \
+					"1m(env),16m(kernel),1m(dtb),-(fs)"
+
+/* DMA stuff, needed for GPMI/MXS NAND support */
+#define CONFIG_APBH_DMA
+#define CONFIG_APBH_DMA_BURST
+#define CONFIG_APBH_DMA_BURST8
+
+/* PMIC */
+#define CONFIG_DM_REGULATOR_PFUZE100
+#define CONFIG_CMD_PMIC
+#define CONFIG_CMD_REGULATOR
+
+#endif                         /* __IMX6LOGIC_CONFIG_H */
-- 
2.7.4


    

[U-Boot] [PATCH V3] imx: i.mx6q: add the initial support for LogicPD i.MX6Q SOM

Adam Ford

Tom Rini

Jagan Teki

Signed-off-by: Adam Ford aford173@gmail.com

tags (0)

participants (3)