-----Original Message----- From: Dylan Hung kobedylan@gmail.com Sent: Thursday, July 27, 2023 9:58 AM To: Ryan Chen ryan_chen@aspeedtech.com; ChiaWei Wang chiawei_wang@aspeedtech.com; BMC-SW BMC-SW@aspeedtech.com; joel@jms.id.au; joe.hershberger@ni.com; rfried.dev@gmail.com; u-boot@lists.denx.de Cc: kobedylan@gmail.com; Dylan Hung dylan_hung@aspeedtech.com Subject: [PATCH] net: ftgmac100: Add reset control

Add optional reset control, especially for the Aspeed SOC. For the hardware without a reset line, the reset assertion/deassertion will be skipped.

Signed-off-by: Dylan Hung dylan_hung@aspeedtech.com

Reviewed-by: Ryan Chen ryan_chen@aspeedtech.com

---

drivers/net/ftgmac100.c | 12 ++++++++++++ 1 file changed, 12 insertions(+)

diff --git a/drivers/net/ftgmac100.c b/drivers/net/ftgmac100.c index a50cde338a..886b97119d 100644 --- a/drivers/net/ftgmac100.c +++ b/drivers/net/ftgmac100.c @@ -13,6 +13,7 @@

#include <common.h> #include <clk.h> +#include <reset.h> #include <cpu_func.h> #include <dm.h> #include <log.h> @@ -90,6 +91,7 @@ struct ftgmac100_data { u32 max_speed;

struct clk_bulk clks;

• struct reset_ctl *reset_ctl;

  /* End of RX/TX ring buffer bits. Depend on model */ u32 rxdes0_edorr_mask;

@@ -568,6 +570,8 @@ static int ftgmac100_of_to_plat(struct udevice *dev) priv->txdes0_edotr_mask = BIT(15); }

• priv->reset_ctl = devm_reset_control_get_optional(dev, NULL);
• return clk_get_bulk(dev, &priv->clks); }

@@ -593,6 +597,12 @@ static int ftgmac100_probe(struct udevice *dev) if (ret) goto out;

• if (priv->reset_ctl) {

• ret = reset_deassert(priv->reset_ctl);
  

• if (ret)
  

• 	goto out;
  

• }
• /*
  • If DM MDIO is enabled, the MDIO bus will be initialized later in
  • dm_eth_phy_connect

@@ -628,6 +638,8 @@ static int ftgmac100_remove(struct udevice *dev) free(priv->phydev); mdio_unregister(priv->bus); mdio_free(priv->bus);

• if (priv->reset_ctl)

• reset_assert(priv->reset_ctl);
  

  clk_release_bulk(&priv->clks);

  return 0;

-- 2.25.1