[U-Boot] [PATCH 1/4] powerpc/p1010rdb: remove unused cpld_show
Function cpld_show() was for debug and not called, so clean it.
Signed-off-by: Shengzhou Liu Shengzhou.Liu@freescale.com --- board/freescale/p1010rdb/p1010rdb.c | 35 ----------------------------------- 1 file changed, 35 deletions(-)
diff --git a/board/freescale/p1010rdb/p1010rdb.c b/board/freescale/p1010rdb/p1010rdb.c index 06aa800..42153e6 100644 --- a/board/freescale/p1010rdb/p1010rdb.c +++ b/board/freescale/p1010rdb/p1010rdb.c @@ -52,41 +52,6 @@ struct cpld_data { u8 por2; /* POR Options */ u8 por3; /* POR Options */ }; - -void cpld_show(void) -{ - struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); - - printf("CPLD: V%x.%x PCBA: V%x.0\n", - in_8(&cpld_data->cpld_ver) & 0xF0, - in_8(&cpld_data->cpld_ver) & 0x0F, - in_8(&cpld_data->pcba_ver) & 0x0F); - -#ifdef CONFIG_DEBUG - printf("twindie_ddr =%x\n", - in_8(&cpld_data->twindie_ddr3)); - printf("bank_sel =%x\n", - in_8(&cpld_data->bank_sel)); - printf("usb2_sel =%x\n", - in_8(&cpld_data->usb2_sel)); - printf("porsw_sel =%x\n", - in_8(&cpld_data->porsw_sel)); - printf("tdm_can_sel =%x\n", - in_8(&cpld_data->tdm_can_sel)); - printf("tdm_can_sel =%x\n", - in_8(&cpld_data->tdm_can_sel)); - printf("spi_cs0_sel =%x\n", - in_8(&cpld_data->spi_cs0_sel)); - printf("bcsr0 =%x\n", - in_8(&cpld_data->bcsr0)); - printf("bcsr1 =%x\n", - in_8(&cpld_data->bcsr1)); - printf("bcsr2 =%x\n", - in_8(&cpld_data->bcsr2)); - printf("bcsr3 =%x\n", - in_8(&cpld_data->bcsr3)); -#endif -} #endif
int board_early_init_f(void)
Some boards use System EEPROM with 128-bytes instead of 256-bytes. Since we regard 256-bytes EEPROM as standard EEPROM with default value for MAX_NUM_PORTS. For those non-256-bytes EEPROM, we can redefine MAX_NUM_PORTS in board-specific file to override the default MAX_NUM_PORTS.
This patch doesn't impact on previous existing boards.
Signed-off-by: Shengzhou Liu Shengzhou.Liu@freescale.com --- Verified with 128B and 256B EEPROM, CRC works.
board/freescale/common/sys_eeprom.c | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/board/freescale/common/sys_eeprom.c b/board/freescale/common/sys_eeprom.c index d789364..9c18dd8 100644 --- a/board/freescale/common/sys_eeprom.c +++ b/board/freescale/common/sys_eeprom.c @@ -18,7 +18,11 @@ #endif
#ifdef CONFIG_SYS_I2C_EEPROM_NXID +/* some boards with non-256-bytes EEPROM have special define */ +/* for MAX_NUM_PORTS in board-specific file */ +#ifndef MAX_NUM_PORTS #define MAX_NUM_PORTS 23 +#endif #define NXID_VERSION 1 #endif
On 09/12/2013 11:46 PM, Shengzhou Liu wrote:
Some boards use System EEPROM with 128-bytes instead of 256-bytes. Since we regard 256-bytes EEPROM as standard EEPROM with default value for MAX_NUM_PORTS. For those non-256-bytes EEPROM, we can redefine MAX_NUM_PORTS in board-specific file to override the default MAX_NUM_PORTS.
This patch doesn't impact on previous existing boards.
Signed-off-by: Shengzhou Liu Shengzhou.Liu@freescale.com
Verified with 128B and 256B EEPROM, CRC works.
I would appreciate it if you update the version number and put a change log under the --- line, even there is no change. With a clear version number and change log, reviewers will be able to identify this is a resend and not spending much time on it.
You are also encouraged to mark previous patch as "superseded".
York
-----Original Message----- From: sun york-R58495 Sent: Friday, September 13, 2013 11:13 PM To: Liu Shengzhou-B36685 Cc: u-boot@lists.denx.de Subject: Re: [PATCH 2/4] powerpc/eeprom: update MAX_NUM_PORTS to adapt non-256- bytes EEPROM
I would appreciate it if you update the version number and put a change log under the --- line, even there is no change. With a clear version number and change log, reviewers will be able to identify this is a resend and not spending much time on it.
You are also encouraged to mark previous patch as "superseded".
York
Sorry for missing the updated version number, will keep it later. Previous patch has been marked as "superseded". Thanks, Shengzhou
Since pins multiplexing, SDHC shares signals with IFC, with this patch: To enable SDHC in case of NOR/NAND/SPI boot a) For temporary use case in runtime without reboot system run 'mux sdhc' in u-boot to validate SDHC with invalidating IFC. b) For long-term use case set 'esdhc' in hwconfig and save it. To enable IFC in case of SD boot a) For temporary use case in runtime without reboot system run 'mux ifc' in u-boot to validate IFC with invalidating SDHC. b) For long-term use case set 'ifc' in hwconfig and save it.
Signed-off-by: Shengzhou Liu Shengzhou.Liu@freescale.com --- board/freescale/p1010rdb/law.c | 2 - board/freescale/p1010rdb/p1010rdb.c | 119 +++++++++++++++++++++++++++++++----- board/freescale/p1010rdb/tlb.c | 4 -- include/configs/P1010RDB.h | 15 +---- 4 files changed, 107 insertions(+), 33 deletions(-)
diff --git a/board/freescale/p1010rdb/law.c b/board/freescale/p1010rdb/law.c index 0045127..ed41a05 100644 --- a/board/freescale/p1010rdb/law.c +++ b/board/freescale/p1010rdb/law.c @@ -9,11 +9,9 @@ #include <asm/mmu.h>
struct law_entry law_table[] = { -#ifndef CONFIG_SDCARD SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_IFC), SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_IFC), SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC), -#endif };
int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/p1010rdb/p1010rdb.c b/board/freescale/p1010rdb/p1010rdb.c index 42153e6..ae8ba45 100644 --- a/board/freescale/p1010rdb/p1010rdb.c +++ b/board/freescale/p1010rdb/p1010rdb.c @@ -21,10 +21,8 @@ #include <asm/fsl_serdes.h> #include <asm/fsl_ifc.h> #include <asm/fsl_pci.h> - -#ifndef CONFIG_SDCARD #include <hwconfig.h> -#endif +#include <i2c.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -33,8 +31,17 @@ DECLARE_GLOBAL_DATA_PTR; #define MUX_CPLD_TDM 0x01 #define MUX_CPLD_SPICS0_FLASH 0x00 #define MUX_CPLD_SPICS0_SLIC 0x02 +#define PMUXCR1_IFC_MASK 0x00ffff00 +#define PMUXCR1_SDHC_MASK 0x00fff000 +#define PMUXCR1_SDHC_ENABLE 0x00555000 + +enum { + MUX_TYPE_IFC, + MUX_TYPE_SDHC, +}; + +static uint sd_ifc_mux;
-#ifndef CONFIG_SDCARD struct cpld_data { u8 cpld_ver; /* cpld revision */ u8 pcba_ver; /* pcb revision number */ @@ -52,17 +59,14 @@ struct cpld_data { u8 por2; /* POR Options */ u8 por3; /* POR Options */ }; -#endif
int board_early_init_f(void) { ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); -#ifndef CONFIG_SDCARD struct fsl_ifc *ifc = (void *)CONFIG_SYS_IFC_ADDR;
/* Clock configuration to access CPLD using IFC(GPCM) */ setbits_be32(&ifc->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT); -#endif /* * Reset PCIe slots via GPIO4 */ @@ -74,7 +78,6 @@ int board_early_init_f(void)
int board_early_init_r(void) { -#ifndef CONFIG_SDCARD const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
@@ -98,7 +101,6 @@ int board_early_init_r(void) CONFIG_SYS_FLASH_BASE_PHYS + 0x1000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, flash_esel+1, BOOKE_PAGESZ_16M, 1); -#endif return 0; }
@@ -109,6 +111,38 @@ void pci_init_board(void) } #endif /* ifdef CONFIG_PCI */
+int config_board_mux(int ctrl_type) +{ + ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u8 tmp; + + switch (ctrl_type) { + case MUX_TYPE_IFC: + i2c_set_bus_num(I2C_PCA9557_BUS_NUM); + tmp = 0xf0; + i2c_write(I2C_PCA9557_ADDR1, 3, 1, &tmp, 1); + tmp = 0x01; + i2c_write(I2C_PCA9557_ADDR1, 1, 1, &tmp, 1); + sd_ifc_mux = MUX_TYPE_IFC; + clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK); + break; + case MUX_TYPE_SDHC: + i2c_set_bus_num(I2C_PCA9557_BUS_NUM); + tmp = 0xf0; + i2c_write(I2C_PCA9557_ADDR1, 3, 1, &tmp, 1); + tmp = 0x05; + i2c_write(I2C_PCA9557_ADDR1, 1, 1, &tmp, 1); + sd_ifc_mux = MUX_TYPE_SDHC; + clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK, + PMUXCR1_SDHC_ENABLE); + break; + default: + break; + } + + return 0; +} + int checkboard(void) { struct cpu_type *cpu; @@ -116,6 +150,11 @@ int checkboard(void) cpu = gd->arch.cpu; printf("Board: %sRDB\n", cpu->name);
+#ifdef CONFIG_SDCARD + /* switch to IFC to read info from CPLD */ + config_board_mux(MUX_TYPE_IFC); +#endif + return 0; }
@@ -211,6 +250,16 @@ void fdt_del_sdhc(void *blob) } }
+void fdt_del_ifc(void *blob) +{ + int nodeoff = 0; + + while ((nodeoff = fdt_node_offset_by_compatible(blob, 0, + "fsl,ifc")) >= 0) { + fdt_del_node(blob, nodeoff); + } +} + void fdt_disable_uart1(void *blob) { int nodeoff; @@ -254,9 +303,13 @@ void ft_board_setup(void *blob, bd_t *bd) fdt_del_flexcan(blob); fdt_del_node_and_alias(blob, "ethernet2"); } -#ifndef CONFIG_SDCARD - /* disable sdhc due to sdhc bug */ - fdt_del_sdhc(blob); + + /* Delete IFC node as IFC pins are multiplexing with SDHC */ + if (sd_ifc_mux != MUX_TYPE_IFC) + fdt_del_ifc(blob); + else + fdt_del_sdhc(blob); + if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "can")) { fdt_del_tdm(blob); fdt_del_spi_slic(blob); @@ -274,11 +327,25 @@ void ft_board_setup(void *blob, bd_t *bd) fdt_del_flexcan(blob); fdt_disable_uart1(blob); } +} #endif + +#ifdef CONFIG_SDCARD +int board_mmc_init(bd_t *bis) +{ + config_board_mux(MUX_TYPE_SDHC); + return -1; +} +#else +void board_reset(void) +{ + /* mux to IFC to enable CPLD for reset */ + if (sd_ifc_mux != MUX_TYPE_IFC) + config_board_mux(MUX_TYPE_IFC); } #endif
-#ifndef CONFIG_SDCARD + int misc_init_r(void) { struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); @@ -304,6 +371,30 @@ int misc_init_r(void) out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_FLASH); }
+ if (hwconfig("esdhc")) + config_board_mux(MUX_TYPE_SDHC); + else if (hwconfig("ifc")) + config_board_mux(MUX_TYPE_IFC); + return 0; } -#endif + +static int pin_mux_cmd(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + if (argc < 2) + return CMD_RET_USAGE; + if (strcmp(argv[1], "ifc") == 0) + config_board_mux(MUX_TYPE_IFC); + else if (strcmp(argv[1], "sdhc") == 0) + config_board_mux(MUX_TYPE_SDHC); + else + return CMD_RET_USAGE; + return 0; +} + +U_BOOT_CMD( + mux, 2, 0, pin_mux_cmd, + "configure multiplexing pin for IFC/SDHC bus in runtime", + "bus_type (e.g. mux sdhc)" +); diff --git a/board/freescale/p1010rdb/tlb.c b/board/freescale/p1010rdb/tlb.c index 77a8043..a7af0f6 100644 --- a/board/freescale/p1010rdb/tlb.c +++ b/board/freescale/p1010rdb/tlb.c @@ -42,7 +42,6 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 1, BOOKE_PAGESZ_1M, 1),
#ifndef CONFIG_SPL_BUILD -#ifndef CONFIG_SDCARD SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 0, 2, BOOKE_PAGESZ_16M, 1), @@ -51,7 +50,6 @@ struct fsl_e_tlb_entry tlb_table[] = { CONFIG_SYS_FLASH_BASE_PHYS + 0x1000000, MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 0, 3, BOOKE_PAGESZ_16M, 1), -#endif
#ifdef CONFIG_PCI /* *I*G* - PCI */ @@ -66,7 +64,6 @@ struct fsl_e_tlb_entry tlb_table[] = { #endif #endif
-#ifndef CONFIG_SDCARD /* *I*G - Board CPLD */ SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS, MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, @@ -75,7 +72,6 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 7, BOOKE_PAGESZ_1M, 1), -#endif
#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL) SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index ba3f7c2..4dfcc51 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -152,10 +152,7 @@ #define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on P1010 RDB */ #define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for P1010 RDB */
-#ifndef CONFIG_SDCARD #define CONFIG_MISC_INIT_R -#endif - #define CONFIG_HWCONFIG /* * These can be toggled for performance analysis, otherwise use default. @@ -256,10 +253,6 @@ extern unsigned long get_sdram_size(void); * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable */
-/* In case of SD card boot, IFC interface is not available because of muxing */ -#ifdef CONFIG_SDCARD -#define CONFIG_SYS_NO_FLASH -#else /* * IFC Definitions */ @@ -410,7 +403,6 @@ extern unsigned long get_sdram_size(void); FTIM2_GPCM_TCH(0x0) | \ FTIM2_GPCM_TWP(0x1f)) #define CONFIG_SYS_CS3_FTIM3 0x0 -#endif /* CONFIG_SDCARD */
#if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) #define CONFIG_SYS_RAMBOOT @@ -482,6 +474,8 @@ extern unsigned long get_sdram_size(void); #define CONFIG_SYS_FSL_I2C2_SPEED 400000 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 +#define I2C_PCA9557_ADDR1 0x18 +#define I2C_PCA9557_BUS_NUM 0
/* I2C EEPROM */ #undef CONFIG_ID_EEPROM @@ -567,12 +561,7 @@ extern unsigned long get_sdram_size(void); #define CONFIG_LBA48 #endif /* #ifdef CONFIG_FSL_SATA */
-/* SD interface will only be available in case of SD boot */ -#ifdef CONFIG_SDCARD #define CONFIG_MMC -#define CONFIG_DEF_HWCONFIG esdhc -#endif - #ifdef CONFIG_MMC #define CONFIG_CMD_MMC #define CONFIG_DOS_PARTITION
- Rename old P1010RDB board as P1010RDB-PA. - Add support for new P1010RDB-PB board. - Some optimization.
For more details, see board/freescale/p1010rdb/README.
Signed-off-by: Shengzhou Liu Shengzhou.Liu@freescale.com --- board/freescale/p1010rdb/p1010rdb.c | 176 ++++++++++++++++++++++++++++++++++-- boards.cfg | 40 +++++--- include/configs/P1010RDB.h | 101 ++++++++++++++++++--- 3 files changed, 283 insertions(+), 34 deletions(-)
diff --git a/board/freescale/p1010rdb/p1010rdb.c b/board/freescale/p1010rdb/p1010rdb.c index ae8ba45..e940d22 100644 --- a/board/freescale/p1010rdb/p1010rdb.c +++ b/board/freescale/p1010rdb/p1010rdb.c @@ -38,12 +38,23 @@ DECLARE_GLOBAL_DATA_PTR; enum { MUX_TYPE_IFC, MUX_TYPE_SDHC, + MUX_TYPE_SPIFLASH, + MUX_TYPE_TDM, + MUX_TYPE_CAN, + MUX_TYPE_CS0_NOR, + MUX_TYPE_CS0_NAND, +}; + +enum { + I2C_READ_BANK, + I2C_READ_PCB_VER, };
static uint sd_ifc_mux;
struct cpld_data { u8 cpld_ver; /* cpld revision */ +#if defined(CONFIG_P1010RDB_PA) u8 pcba_ver; /* pcb revision number */ u8 twindie_ddr3; u8 res1[6]; @@ -58,6 +69,9 @@ struct cpld_data { u8 por1; /* POR Options */ u8 por2; /* POR Options */ u8 por3; /* POR Options */ +#elif defined(CONFIG_P1010RDB_PB) + u8 rom_loc; +#endif };
int board_early_init_f(void) @@ -116,6 +130,9 @@ int config_board_mux(int ctrl_type) ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); u8 tmp;
+#if defined(CONFIG_P1010RDB_PA) + struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); + switch (ctrl_type) { case MUX_TYPE_IFC: i2c_set_bus_num(I2C_PCA9557_BUS_NUM); @@ -136,25 +153,171 @@ int config_board_mux(int ctrl_type) clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK, PMUXCR1_SDHC_ENABLE); break; + case MUX_TYPE_SPIFLASH: + out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_FLASH); + break; + case MUX_TYPE_TDM: + out_8(&cpld_data->tdm_can_sel, MUX_CPLD_TDM); + out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_SLIC); + break; + case MUX_TYPE_CAN: + out_8(&cpld_data->tdm_can_sel, MUX_CPLD_CAN_UART); + break; default: break; } +#elif defined(CONFIG_P1010RDB_PB) + uint orig_bus = i2c_get_bus_num(); + i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
+ switch (ctrl_type) { + case MUX_TYPE_IFC: + i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1); + clrbits_8(&tmp, 0x04); + i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1); + i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); + clrbits_8(&tmp, 0x04); + i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); + sd_ifc_mux = MUX_TYPE_IFC; + clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK); + break; + case MUX_TYPE_SDHC: + i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1); + setbits_8(&tmp, 0x04); + i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1); + i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); + clrbits_8(&tmp, 0x04); + i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); + sd_ifc_mux = MUX_TYPE_SDHC; + clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK, + PMUXCR1_SDHC_ENABLE); + break; + case MUX_TYPE_SPIFLASH: + i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1); + clrbits_8(&tmp, 0x80); + i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1); + i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); + clrbits_8(&tmp, 0x80); + i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); + break; + case MUX_TYPE_TDM: + i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1); + setbits_8(&tmp, 0x82); + i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1); + i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); + clrbits_8(&tmp, 0x82); + i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); + break; + case MUX_TYPE_CAN: + i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1); + clrbits_8(&tmp, 0x02); + i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1); + i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); + clrbits_8(&tmp, 0x02); + i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); + break; + case MUX_TYPE_CS0_NOR: + i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1); + clrbits_8(&tmp, 0x08); + i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1); + i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); + clrbits_8(&tmp, 0x08); + i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); + break; + case MUX_TYPE_CS0_NAND: + i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1); + setbits_8(&tmp, 0x08); + i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1); + i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); + clrbits_8(&tmp, 0x08); + i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); + break; + default: + break; + } + i2c_set_bus_num(orig_bus); +#endif return 0; }
+#ifdef CONFIG_P1010RDB_PB +int i2c_pca9557_read(int type) +{ + u8 val; + + i2c_set_bus_num(I2C_PCA9557_BUS_NUM); + i2c_read(I2C_PCA9557_ADDR2, 0, 1, &val, 1); + + switch (type) { + case I2C_READ_BANK: + val = (val & 0x10) >> 4; + break; + case I2C_READ_PCB_VER: + val = ((val & 0x60) >> 5) + 1; + break; + default: + break; + } + + return val; +} +#endif + int checkboard(void) { struct cpu_type *cpu; + struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); + u8 val;
cpu = gd->arch.cpu; - printf("Board: %sRDB\n", cpu->name); +#if defined(CONFIG_P1010RDB_PA) + printf("Board: %sRDB-PA, ", cpu->name); +#elif defined(CONFIG_P1010RDB_PB) + printf("Board: %sRDB-PB, ", cpu->name); + i2c_set_bus_num(I2C_PCA9557_BUS_NUM); + i2c_init(CONFIG_SYS_FSL_I2C_SPEED, CONFIG_SYS_FSL_I2C_SLAVE); + val = 0x0; /* no polarity inversion */ + i2c_write(I2C_PCA9557_ADDR2, 2, 1, &val, 1); +#endif
#ifdef CONFIG_SDCARD /* switch to IFC to read info from CPLD */ config_board_mux(MUX_TYPE_IFC); #endif
+#if defined(CONFIG_P1010RDB_PA) + val = (in_8(&cpld_data->pcba_ver) & 0xf); + printf("PCB: v%x.0\n", val); +#elif defined(CONFIG_P1010RDB_PB) + val = in_8(&cpld_data->cpld_ver); + printf("CPLD: v%x.%x, ", val >> 4, val & 0xf); + printf("PCB: v%x.0, ", i2c_pca9557_read(I2C_READ_PCB_VER)); + val = in_8(&cpld_data->rom_loc) & 0xf; + puts("Boot from: "); + switch (val) { + case 0xf: + config_board_mux(MUX_TYPE_CS0_NOR); + printf("NOR vBank%d\n", i2c_pca9557_read(I2C_READ_BANK)); + break; + case 0xe: + puts("SDHC\n"); + val = 0x60; /* set pca9557 pin input/output */ + i2c_write(I2C_PCA9557_ADDR2, 3, 1, &val, 1); + break; + case 0x5: + config_board_mux(MUX_TYPE_IFC); + config_board_mux(MUX_TYPE_CS0_NAND); + puts("NAND\n"); + break; + case 0x6: + config_board_mux(MUX_TYPE_IFC); + puts("SPI\n"); + break; + default: + puts("unknown\n"); + break; + } +#endif return 0; }
@@ -348,7 +511,6 @@ void board_reset(void)
int misc_init_r(void) { - struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "can")) { @@ -356,7 +518,7 @@ int misc_init_r(void) MPC85xx_PMUXCR_CAN1_UART | MPC85xx_PMUXCR_CAN2_TDM | MPC85xx_PMUXCR_CAN2_UART); - out_8(&cpld_data->tdm_can_sel, MUX_CPLD_CAN_UART); + config_board_mux(MUX_TYPE_CAN); } else if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "tdm")) { clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN2_UART | MPC85xx_PMUXCR_CAN1_UART); @@ -364,11 +526,10 @@ int misc_init_r(void) MPC85xx_PMUXCR_CAN1_TDM); clrbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_GPIO); setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_TDM); - out_8(&cpld_data->tdm_can_sel, MUX_CPLD_TDM); - out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_SLIC); + config_board_mux(MUX_TYPE_TDM); } else { /* defaultly spi_cs_sel to flash */ - out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_FLASH); + config_board_mux(MUX_TYPE_SPIFLASH); }
if (hwconfig("esdhc")) @@ -376,6 +537,9 @@ int misc_init_r(void) else if (hwconfig("ifc")) config_board_mux(MUX_TYPE_IFC);
+#ifdef CONFIG_P1010RDB_PB + setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_GPIO01_DRVVBUS); +#endif return 0; }
diff --git a/boards.cfg b/boards.cfg index 48aa0bf..e3457d8 100644 --- a/boards.cfg +++ b/boards.cfg @@ -787,20 +787,32 @@ MPC8572DS_36BIT powerpc mpc85xx mpc8572ds freesca MPC8572DS_NAND powerpc mpc85xx mpc8572ds freescale - MPC8572DS:NAND C29XPCIE powerpc mpc85xx c29xpcie freescale - C29XPCIE:C29XPCIE,36BIT C29XPCIE_SPIFLASH powerpc mpc85xx c29xpcie freescale - C29XPCIE:C29XPCIE,36BIT,SPIFLASH -P1010RDB_36BIT_NAND powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB,36BIT,NAND -P1010RDB_36BIT_NAND_SECBOOT powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB,36BIT,NAND_SECBOOT,SECURE_BOOT -P1010RDB_36BIT_NOR powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB,36BIT -P1010RDB_36BIT_NOR_SECBOOT powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB,36BIT,SECURE_BOOT -P1010RDB_36BIT_SDCARD powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB,36BIT,SDCARD -P1010RDB_36BIT_SPIFLASH powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB,36BIT,SPIFLASH -P1010RDB_36BIT_SPIFLASH_SECBOOT powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB,36BIT,SPIFLASH,SECURE_BOOT -P1010RDB_NAND powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB,NAND -P1010RDB_NAND_SECBOOT powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB,NAND_SECBOOT,SECURE_BOOT -P1010RDB_NOR powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB -P1010RDB_NOR_SECBOOT powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB,SECURE_BOOT -P1010RDB_SDCARD powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB,SDCARD -P1010RDB_SPIFLASH powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB,SPIFLASH -P1010RDB_SPIFLASH_SECBOOT powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB,SPIFLASH,SECURE_BOOT +P1010RDB-PA_36BIT_NAND powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB_PA,36BIT,NAND +P1010RDB-PA_36BIT_NAND_SECBOOT powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB_PA,36BIT,NAND_SECBOOT,SECURE_BOOT +P1010RDB-PA_36BIT_NOR powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB_PA,36BIT +P1010RDB-PA_36BIT_NOR_SECBOOT powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB_PA,36BIT,SECURE_BOOT +P1010RDB-PA_36BIT_SDCARD powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB_PA,36BIT,SDCARD +P1010RDB-PA_36BIT_SPIFLASH powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB_PA,36BIT,SPIFLASH +P1010RDB-PA_36BIT_SPIFLASH_SECBOOT powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB_PA,36BIT,SPIFLASH,SECURE_BOOT +P1010RDB-PA_NAND powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB_PA,NAND +P1010RDB-PA_NOR powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB_PA +P1010RDB-PA_SDCARD powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB_PA,SDCARD +P1010RDB-PA_SPIFLASH powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB_PA,SPIFLASH +P1010RDB-PA_SPIFLASH_SECBOOT powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB_PA,SPIFLASH,SECURE_BOOT +P1010RDB-PB_NOR powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB_PB +P1010RDB-PB_NAND powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB_PB,NAND +P1010RDB-PB_SDCARD powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB_PB,SDCARD +P1010RDB-PB_SPIFLASH powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB_PB,SPIFLASH +P1010RDB-PB_NOR_SECBOOT powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB_PB,SECURE_BOOT +P1010RDB-PB_NAND_SECBOOT powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB_PB,NAND_SECBOOT,SECURE_BOOT +P1010RDB-PB_SPIFLASH_SECBOOT powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB_PB,SPIFLASH,SECURE_BOOT +P1010RDB-PB_36BIT_NOR powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB_PB,36BIT +P1010RDB-PB_36BIT_NOR_SECBOOT powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB_PB,36BIT,SECURE_BOOT +P1010RDB-PB_36BIT_NAND powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB_PB,36BIT,NAND +P1010RDB-PB_36BIT_NAND_SECBOOT powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB_PB,36BIT,NAND_SECBOOT,SECURE_BOOT +P1010RDB-PB_36BIT_SDCARD powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB_PB,36BIT,SDCARD +P1010RDB-PB_36BIT_SPIFLASH powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB_PB,36BIT,SPIFLASH +P1010RDB-PB_36BIT_SPIFLASH_SECBOOT powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB_PB,36BIT,SPIFLASH,SECURE_BOOT P1011RDB powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011RDB P1011RDB_36BIT powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011RDB,36BIT P1011RDB_36BIT_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011RDB,36BIT,SDCARD diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index 4dfcc51..f866794 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -120,7 +120,11 @@ #endif
/* controller 2, Slot 2, tgtid 2, Base address 9000 */ +#if defined(CONFIG_P1010RDB_PA) #define CONFIG_SYS_PCIE2_NAME "PCIe Slot" +#elif defined(CONFIG_P1010RDB_PB) +#define CONFIG_SYS_PCIE2_NAME "mini PCIe Slot" +#endif #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 @@ -200,25 +204,24 @@ extern unsigned long get_sdram_size(void); #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 - #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 #define CONFIG_SYS_DDR_RCW_1 0x00000000 #define CONFIG_SYS_DDR_RCW_2 0x00000000 -#define CONFIG_SYS_DDR_CONTROL 0x470C0000 /* Type = DDR3 */ -#define CONFIG_SYS_DDR_CONTROL_2 0x04401010 +#define CONFIG_SYS_DDR_CONTROL 0xc70c0008 /* Type = DDR3 */ +#define CONFIG_SYS_DDR_CONTROL_2 0x24401000 #define CONFIG_SYS_DDR_TIMING_4 0x00000001 #define CONFIG_SYS_DDR_TIMING_5 0x03402400
-#define CONFIG_SYS_DDR_TIMING_3_800 0x00020000 -#define CONFIG_SYS_DDR_TIMING_0_800 0x00330004 -#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6B4644 +#define CONFIG_SYS_DDR_TIMING_3_800 0x00030000 +#define CONFIG_SYS_DDR_TIMING_0_800 0x00110104 +#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644 #define CONFIG_SYS_DDR_TIMING_2_800 0x0FA888CF #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000 -#define CONFIG_SYS_DDR_MODE_1_800 0x40461520 -#define CONFIG_SYS_DDR_MODE_2_800 0x8000c000 +#define CONFIG_SYS_DDR_MODE_1_800 0x00441420 +#define CONFIG_SYS_DDR_MODE_2_800 0x00000000 #define CONFIG_SYS_DDR_INTERVAL_800 0x0C300100 -#define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8655A608 +#define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608
/* settings for DDR3 at 667MT/s */ #define CONFIG_SYS_DDR_TIMING_3_667 0x00010000 @@ -315,6 +318,8 @@ extern unsigned long get_sdram_size(void); | CSPR_MSEL_NAND \ | CSPR_V) #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) + +#if defined(CONFIG_P1010RDB_PA) #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ @@ -322,13 +327,26 @@ extern unsigned long get_sdram_size(void); | CSOR_NAND_PGS_512 /* Page Size = 512b */ \ | CSOR_NAND_SPRZ_16 /* Spare size = 16 */ \ | CSOR_NAND_PB(32)) /* 32 Pages Per Block */ +#define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) + +#elif defined(CONFIG_P1010RDB_PB) +#define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ + | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ + | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ + | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ + | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ + | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ + | CSOR_NAND_PB(128)) /*Pages Per Block = 128 */ +#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) +#endif
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_MTD_NAND_VERIFY_WRITE #define CONFIG_CMD_NAND -#define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
+#if defined(CONFIG_P1010RDB_PA) /* NAND Flash Timing Params */ #define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \ FTIM0_NAND_TWP(0x0C) | \ @@ -343,6 +361,23 @@ extern unsigned long get_sdram_size(void); FTIM2_NAND_TWHRE(0x0f) #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04)
+#elif defined(CONFIG_P1010RDB_PB) +/* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */ +/* ONFI NAND Flash mode0 Timing Params */ +#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07)| \ + FTIM0_NAND_TWP(0x18) | \ + FTIM0_NAND_TWCHT(0x07) | \ + FTIM0_NAND_TWH(0x0a)) +#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32)| \ + FTIM1_NAND_TWBE(0x39) | \ + FTIM1_NAND_TRR(0x0e) | \ + FTIM1_NAND_TRP(0x18)) +#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ + FTIM2_NAND_TREH(0x0a) | \ + FTIM2_NAND_TWHRE(0x1e)) +#define CONFIG_SYS_NAND_FTIM3 0x0 +#endif + #define CONFIG_SYS_NAND_DDR_LAW 11
/* Set up IFC registers for boot location NOR/NAND */ @@ -475,10 +510,20 @@ extern unsigned long get_sdram_size(void); #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 #define I2C_PCA9557_ADDR1 0x18 +#define I2C_PCA9557_ADDR2 0x19 #define I2C_PCA9557_BUS_NUM 0
/* I2C EEPROM */ -#undef CONFIG_ID_EEPROM +#if defined(CONFIG_P1010RDB_PB) +#define CONFIG_ID_EEPROM +#ifdef CONFIG_ID_EEPROM +#define CONFIG_SYS_I2C_EEPROM_NXID +#endif +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 +#define CONFIG_SYS_EEPROM_BUS_NUM 0 +#define MAX_NUM_PORTS 9 /* for 128Bytes EEPROM */ +#endif /* enable read and write access to EEPROM */ #define CONFIG_CMD_EEPROM #define CONFIG_SYS_I2C_MULTI_EEPROMS @@ -602,9 +647,14 @@ extern unsigned long get_sdram_size(void); #define CONFIG_ENV_SIZE 0x2000 #elif defined(CONFIG_NAND) #define CONFIG_ENV_IS_IN_NAND +#if defined(CONFIG_P1010RDB_PA) #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE +#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */ +#elif defined(CONFIG_P1010RDB_PB) +#define CONFIG_ENV_SIZE (16 * 1024) +#define CONFIG_ENV_RANGE (32 * CONFIG_ENV_SIZE) /* new block size 512K */ +#endif #define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) -#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) #elif defined(CONFIG_SYS_RAMBOOT) #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) @@ -697,7 +747,6 @@ extern unsigned long get_sdram_size(void); #define CONFIG_HAS_ETH2 #endif
-#define CONFIG_HOSTNAME P1010RDB #define CONFIG_ROOTPATH "/opt/nfsroot" #define CONFIG_BOOTFILE "uImage" #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */ @@ -736,7 +785,31 @@ extern unsigned long get_sdram_size(void); "ext2load usb 0:4 $loadaddr $bootfile;" \ "ext2load usb 0:4 $fdtaddr $fdtfile;" \ "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ + CONFIG_BOOTMODE + +#if defined(CONFIG_P1010RDB_PA) +#define CONFIG_BOOTMODE \ + "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \ + "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \ + "boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \ + "mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \ + "boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \ + "mw.b ffb00011 0; mw.b ffb00017 1; reset\0" + +#elif defined(CONFIG_P1010RDB_PB) +#define CONFIG_BOOTMODE \ + "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \ + "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \ + "boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \ + "i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \ + "boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0;" \ + "i2c mw 19 1 8; i2c mw 19 3 f7; reset\0" \ + "boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0;" \ + "i2c mw 19 1 0; i2c mw 19 3 f7; reset\0" \ + "boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0;" \ + "i2c mw 19 1 4; i2c mw 19 3 f3; reset\0" +#endif
#define CONFIG_RAMBOOTCOMMAND \ "setenv bootargs root=/dev/ram rw " \
Hi everyone,
I want to implement a minimal secure boot architecture into u-boot by letting the u-boot.img be decrypted during SPL execution. Thus, the u-boot.img is present on the MMC in an encrypted version. I already implemented a basic AES-128 en-/decryption algorithm into the SPL.
Everything will be implement on a PandaBoard (OMAP4460). Now my questions are:
1.) What would be the general architecture? u-boot.img is loaded into external memory (DRAM)at address 0x80100000. To decrypt it, the whole file needs to be processed by SPL, which will not be able to load the data since the SPL can not exceed a certain size (~49 kByte I guess).
-> Thus, would it be somehow possible to implement the algorithm in the SPL but let the u-boot.img data be stored in DRAM for processing?
2.) Furthermore, where could be a good place to put the actual algorithm in? I figured that in my situation the function call flow is something like this:
... > omap_boot_device() > boot_device() > spl_mmc_load_image() > mmc_load_image_fat > file_fat_read() > do_fat_read()
_jump_to_image_noargs() where u-boot.img is eventually called using the
image_entry() function.
Thanks a lot, -b
Hi
On Fri, Sep 13, 2013 at 4:57 PM, bin4ry 0xbin4ry@gmail.com wrote:
Hi everyone,
I want to implement a minimal secure boot architecture into u-boot by letting the u-boot.img be decrypted during SPL execution. Thus, the u-boot.img is present on the MMC in an encrypted version. I already implemented a basic AES-128 en-/decryption algorithm into the SPL.
Everything will be implement on a PandaBoard (OMAP4460). Now my questions are:
1.) What would be the general architecture? u-boot.img is loaded into external memory (DRAM)at address 0x80100000. To decrypt it, the whole file needs to be processed by SPL, which will not be able to load the data since the SPL can not exceed a certain size (~49 kByte I guess).
-> Thus, would it be somehow possible to implement the algorithm inthe SPL but let the u-boot.img data be stored in DRAM for processing?
2.) Furthermore, where could be a good place to put the actual algorithm in? I figured that in my situation the function call flow is something like this:
... > omap_boot_device() > boot_device() > spl_mmc_load_image() > mmc_load_image_fat > file_fat_read() > do_fat_read()
... > omap_boot_device() > boot_device() > spl_mmc_load_image()
file_fat_read() > do_fat_read()
I don't understand you can decrypt it after load. Why just verify the signature?
Michael
_jump_to_image_noargs() where u-boot.img is eventually called using the
image_entry() function.
Thanks a lot, -b
U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Am 13.09.2013 19:28, schrieb Michael Trimarchi:
Hi I don't understand you can decrypt it after load. Why just verify the signature?
Michael
This is a proof-of-concept for a technique, which involves de-/encrypting the u-boot.img with a key derived from a hardware fingerprint. This is why I can not just verify the signature.
Yes, I want to decrypt it after load. However, I am not sure about the correct position in the SPL source code to this, i.e. the position after loading the u-boot.img and before executing it. I assume after do_fat_read() the u-boot.img is loaded into internal memory and jump_to_image_no_args() executes the u-boot.img. Thus, the decryption routine should be implemented between both functions?
Hi bin4ry,
On Fri, 13 Sep 2013 16:57:20 +0200, bin4ry 0xbin4ry@gmail.com wrote:
Hi everyone,
I want to implement a minimal secure boot architecture into u-boot by letting the u-boot.img be decrypted during SPL execution. Thus, the u-boot.img is present on the MMC in an encrypted version. I already implemented a basic AES-128 en-/decryption algorithm into the SPL.
What's the point of encrypting the whole binary? Secure boot usually uses authentication, not encryption, of the payload that is to be secured: instead of decrypting several hundreds of KBs, you hash them (which is faster) and decrypt only the few hundreds bits of the encrypted hash in order to compare both hashes (but trust chain remains the same of course).
Note: if you chose payload encryption over authentication (hash encryption) because you are worried about collision, preimage or even second preimage resistance, then you should just go with use a stronger hash function. Besides, for a small and compact payload such as a bootloader, the risks of collisions are reduced because there is less room in the input space.
Amicalement,
Hi Albert,
so if I get you right the workflow for payload authentication is the following:
Encryption process:
1. Create hash value H for u-boot.img 2. Encrypt the hash value H with secret K to get encrypted hash values H_enc 3. Store H_enc
Decryption process:
1. Read H_enc 2. Decrypt H_enc using secret K to get plain hash values H 3. Create Hash values H' of u-boot.img 4. Compare H and H'
Did I get you right?
Thanks and best regards, -b
Am 15.09.2013 08:08, schrieb Albert ARIBAUD:
What's the point of encrypting the whole binary? Secure boot usually uses authentication, not encryption, of the payload that is to be secured: instead of decrypting several hundreds of KBs, you hash them (which is faster) and decrypt only the few hundreds bits of the encrypted hash in order to compare both hashes (but trust chain remains the same of course).
Note: if you chose payload encryption over authentication (hash encryption) because you are worried about collision, preimage or even second preimage resistance, then you should just go with use a stronger hash function. Besides, for a small and compact payload such as a bootloader, the risks of collisions are reduced because there is less room in the input space.
Amicalement,
Hi bin4ry,
Sorry for the delay in answering.
On Mon, 30 Sep 2013 09:51:54 +0200, bin4ry 0xbin4ry@gmail.com wrote:
Hi Albert,
so if I get you right the workflow for payload authentication is the following:
Encryption process:
(you really should not talk about "encryption process" if your goal is authentication rather than encryption. The correct term would be somehting like "signature process" and "signature verification process")
- Create hash value H for u-boot.img
- Encrypt the hash value H with secret K to get encrypted hash values H_enc
- Store H_enc
Decryption process:
- Read H_enc
- Decrypt H_enc using secret K to get plain hash values H
- Create Hash values H' of u-boot.img
- Compare H and H'
Did I get you right?
Almost, but not quite.
The most important problem is that you seem to assume use of symmetric encryption , since your 'K' seems to be both the encryption and decryption key. That is not good, because K is needed on the target for the verification phase, and thus, could then be used by an attacker to encrypt the hash of a malicious payload that would then pass verification. You need asymetric encryption, with a pair of public and private keys. The private key is used in the signing process, for encrypting the hash. The public key is on the device and is used in the verification process, for decrypting the encrypted hash.
But then, of course, you can't simply have the public key in Flash, because the attacker could generate a new pair of keys, then sign the malicious payload hash with the new private key and flash the new public key. Therefore, you need a way to secure the public key. One way is to have it in ROM, but this could be against silicon or manufacter budget. Fuses are usually not big enough, but you could fuse a hash of the key.
Note that, in any case, authentication only makes senses if you can trust the piece of software on the arget that will check the key and verify the payload hash... Which means you need some secure mode on the device to boot (pun intended). And that mode will probably already include a way of signing the payloads.
Thanks and best regards,
You're welcome.
-b
Amicalement,
participants (6)
-
Albert ARIBAUD -
bin4ry -
Liu Shengzhou-B36685 -
Michael Trimarchi -
Shengzhou Liu -
York Sun