[U-Boot] [PATCH v2 1/3] net: zynq: Extend register description with offsets
Extend comments with register offset to help with debuggging.
Signed-off-by: Michal Simek michal.simek@xilinx.com Acked-by: Joe Hershberger joe.hershberger@ni.com ---
Changes in v2: None
drivers/net/zynq_gem.c | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-)
diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index 72f1332c8008..d98c229f4330 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -108,28 +108,28 @@
/* Device registers */ struct zynq_gem_regs { - u32 nwctrl; /* Network Control reg */ - u32 nwcfg; /* Network Config reg */ - u32 nwsr; /* Network Status reg */ + u32 nwctrl; /* 0x0 - Network Control reg */ + u32 nwcfg; /* 0x4 - Network Config reg */ + u32 nwsr; /* 0x8 - Network Status reg */ u32 reserved1; - u32 dmacr; /* DMA Control reg */ - u32 txsr; /* TX Status reg */ - u32 rxqbase; /* RX Q Base address reg */ - u32 txqbase; /* TX Q Base address reg */ - u32 rxsr; /* RX Status reg */ + u32 dmacr; /* 0x10 - DMA Control reg */ + u32 txsr; /* 0x14 - TX Status reg */ + u32 rxqbase; /* 0x18 - RX Q Base address reg */ + u32 txqbase; /* 0x1c - TX Q Base address reg */ + u32 rxsr; /* 0x20 - RX Status reg */ u32 reserved2[2]; - u32 idr; /* Interrupt Disable reg */ + u32 idr; /* 0x2c - Interrupt Disable reg */ u32 reserved3; - u32 phymntnc; /* Phy Maintaince reg */ + u32 phymntnc; /* 0x34 - Phy Maintaince reg */ u32 reserved4[18]; - u32 hashl; /* Hash Low address reg */ - u32 hashh; /* Hash High address reg */ + u32 hashl; /* 0x80 - Hash Low address reg */ + u32 hashh; /* 0x84 - Hash High address reg */ #define LADDR_LOW 0 #define LADDR_HIGH 1 - u32 laddr[4][LADDR_HIGH + 1]; /* Specific1 addr low/high reg */ - u32 match[4]; /* Type ID1 Match reg */ + u32 laddr[4][LADDR_HIGH + 1]; /* 0x8c - Specific1 addr low/high reg */ + u32 match[4]; /* 0xa8 - Type ID1 Match reg */ u32 reserved6[18]; - u32 stat[44]; /* Octects transmitted Low reg - stat start */ + u32 stat[44]; /* 0x100 - Octects transmitted Low reg - stat start */ };
/* BD descriptors */
Previous loop was completely bogus. Iterration should go just over statistic counters.
Signed-off-by: Michal Simek michal.simek@xilinx.com Acked-by: Joe Hershberger joe.hershberger@ni.com ---
Changes in v2: None
drivers/net/zynq_gem.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index d98c229f4330..f32862fd0b2e 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -129,7 +129,8 @@ struct zynq_gem_regs { u32 laddr[4][LADDR_HIGH + 1]; /* 0x8c - Specific1 addr low/high reg */ u32 match[4]; /* 0xa8 - Type ID1 Match reg */ u32 reserved6[18]; - u32 stat[44]; /* 0x100 - Octects transmitted Low reg - stat start */ +#define STAT_SIZE 44 + u32 stat[STAT_SIZE]; /* 0x100 - Octects transmitted Low reg */ };
/* BD descriptors */ @@ -301,8 +302,6 @@ static int zynq_gem_init(struct eth_device *dev, bd_t * bis) u32 i; unsigned long clk_rate = 0; struct phy_device *phydev; - const u32 stat_size = (sizeof(struct zynq_gem_regs) - - offsetof(struct zynq_gem_regs, stat)) / 4; struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; struct zynq_gem_priv *priv = dev->priv; const u32 supported = SUPPORTED_10baseT_Half | @@ -330,7 +329,7 @@ static int zynq_gem_init(struct eth_device *dev, bd_t * bis) writel(0x0, ®s->hashh);
/* Clear all counters */ - for (i = 0; i <= stat_size; i++) + for (i = 0; i < STAT_SIZE; i++) readl(®s->stat[i]);
/* Setup RxBD space */
From: "Edgar E. Iglesias" edgar.iglesias@xilinx.com
Zynq has no priority queues. ZynqMP has one priority queue and this change is required to get ethernet working. This patch was not needed on ep108 for uknown reason even it should be used. Tested on Zynq and ZynqMP.
Signed-off-by: Edgar E. Iglesias edgar.iglesias@xilinx.com Signed-off-by: Michal Simek michal.simek@xilinx.com ---
Changes in v2: - Fix commit message - Remove FIXME from the driver - Add macro for the first free TX descriptor - 0 is used by send, 1 is used by other patch
drivers/net/zynq_gem.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+)
diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index f32862fd0b2e..29073fbd6633 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -131,6 +131,10 @@ struct zynq_gem_regs { u32 reserved6[18]; #define STAT_SIZE 44 u32 stat[STAT_SIZE]; /* 0x100 - Octects transmitted Low reg */ + u32 reserved7[164]; + u32 transmit_q1_ptr; /* 0x440 - Transmit priority queue 1 */ + u32 reserved8[15]; + u32 receive_q1_ptr; /* 0x480 - Receive priority queue 1 */ };
/* BD descriptors */ @@ -147,6 +151,9 @@ struct emac_bd { /* BD separation space */ #define BD_SEPRN_SPACE 64
+/* Setup the first free TX descriptor */ +#define TX_FREE_DESC 2 + /* Initialized, rxbd_current, rx_first_buf must be 0 after init */ struct zynq_gem_priv { struct emac_bd *tx_bd; @@ -304,6 +311,8 @@ static int zynq_gem_init(struct eth_device *dev, bd_t * bis) struct phy_device *phydev; struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; struct zynq_gem_priv *priv = dev->priv; + struct emac_bd *dummy_tx_bd = &priv->tx_bd[TX_FREE_DESC]; + struct emac_bd *dummy_rx_bd = &priv->tx_bd[TX_FREE_DESC + 2]; const u32 supported = SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Half | @@ -352,6 +361,23 @@ static int zynq_gem_init(struct eth_device *dev, bd_t * bis) /* Setup for Network Control register, MDIO, Rx and Tx enable */ setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_MDEN_MASK);
+ /* Disable the second priority queue */ + dummy_tx_bd->addr = 0; + dummy_tx_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK | + ZYNQ_GEM_TXBUF_LAST_MASK| + ZYNQ_GEM_TXBUF_USED_MASK; + + dummy_rx_bd->addr = ZYNQ_GEM_RXBUF_WRAP_MASK | + ZYNQ_GEM_RXBUF_NEW_MASK; + dummy_rx_bd->status = 0; + flush_dcache_range((ulong)&dummy_tx_bd, (ulong)&dummy_tx_bd + + sizeof(dummy_tx_bd)); + flush_dcache_range((ulong)&dummy_rx_bd, (ulong)&dummy_rx_bd + + sizeof(dummy_rx_bd)); + + writel((u32)dummy_tx_bd, ®s->transmit_q1_ptr); + writel((u32)dummy_rx_bd, ®s->receive_q1_ptr); + priv->init++; }
Hi Michal,
On Thu, Nov 12, 2015 at 7:43 AM, Michal Simek michal.simek@xilinx.com wrote:
From: "Edgar E. Iglesias" edgar.iglesias@xilinx.com
Zynq has no priority queues. ZynqMP has one priority queue and this change is required to get ethernet working. This patch was not needed on ep108 for uknown reason even it should be used. Tested on Zynq and ZynqMP.
Signed-off-by: Edgar E. Iglesias edgar.iglesias@xilinx.com Signed-off-by: Michal Simek michal.simek@xilinx.com
Acked-by: Joe Hershberger joe.hershberger@ni.com
participants (2)
-
Joe Hershberger -
Michal Simek