[U-Boot] [PATCH 0/6] Add support for hi6220 SoC and HiKey 96boards CE board.
This series adds support for the first 96boards consumer edition HiKey board.
More information can be found about this board at the following link https://www.96boards.org/products/hikey/.
This initial port adds support for: - 1) Serial 2) eMMC and sd card 3) USB 4) GPIO
It has been tested with Arm Trusted Firmware running u-boot as the BL33 executable.
Some (slightly old) instructions on exactly how to compile everything (l-loader, with Arm Trusted Firmware, which then loads u-boot are available here: -
http://people.linaro.org/~peter.griffin/hikey/hikey-u-boot-release_r1/u-boot....
One thing I'm fairly sure is wrong but can't see how to fix is the header definitions are currently in arch/arm/include/asm/arch-armv8/*.h and I suspect they should be in a directory something like arch/arm/include/asm/arch-hi6220. However so far what makes this magic happen and how to fix it has aluded me.
Notes:
eMMC has been tested with basic reading of eMMC partition into DDR. I have not tested writing / erasing. I suspect due to lack of clock control it won't be running in the most performant high speed mode.
SD card slot has been tested for reading and booting kernels into DDR. It is also currently used for saving the u-boot enviroment.
USB has been tested with ASIX networking adapter to tftpboot kernels into DDR. USB mass storage device enumeration does not currently work for an unknown reason (leads to a hang).
GPIO has been tested using gpio toggle command GPIO4_1-3 to flash LEDs.
A basic SoC datasheet can be found here: - https://github.com/96boards/documentation/blob/master/hikey/ Hi6220V100_Multi-Mode_Application_Processor_Function_Description.pdf
Board schematic can be found here: - https://github.com/96boards/documentation/blob/master/hikey/ 96Boards-Hikey-Rev-A1.pdf
kind regards,
Peter.
Peter Griffin (6): usb: dwc2: Add support for v3 snpsid value dm: gpio: hi6220: Add a hi6220 GPIO driver model driver. ARM: hi6220: Add register and bitfield definition header files. hi6553: Add register definition and bitfield header for 6553 pmic mmc: hi6220_dw_mmc: Add hi6220 glue code for dw_mmc controller. ARM64: HiKey: hi6220: Add u-boot support for the 96boards CE HiKey board.
arch/arm/Kconfig | 5 + arch/arm/include/asm/arch-armv8/dwmmc.h | 8 + arch/arm/include/asm/arch-armv8/gpio.h | 47 +++ arch/arm/include/asm/arch-armv8/hi6220.h | 324 +++++++++++++++ .../include/asm/arch-armv8/hi6220_regs_alwayson.h | 349 ++++++++++++++++ arch/arm/include/asm/arch-armv8/hi6553.h | 75 ++++ board/96boards/hikey64/Kconfig | 12 + board/96boards/hikey64/Makefile | 8 + board/96boards/hikey64/hikey.c | 439 +++++++++++++++++++++ configs/hikey_aemv8a_defconfig | 5 + drivers/gpio/Makefile | 2 + drivers/gpio/hi6220_gpio.c | 95 +++++ drivers/mmc/Makefile | 1 + drivers/mmc/hi6220_dw_mmc.c | 63 +++ drivers/usb/host/dwc2.c | 3 +- drivers/usb/host/dwc2.h | 1 + include/configs/hikey_aemv8a.h | 187 +++++++++ 17 files changed, 1623 insertions(+), 1 deletion(-) create mode 100644 arch/arm/include/asm/arch-armv8/dwmmc.h create mode 100644 arch/arm/include/asm/arch-armv8/gpio.h create mode 100644 arch/arm/include/asm/arch-armv8/hi6220.h create mode 100644 arch/arm/include/asm/arch-armv8/hi6220_regs_alwayson.h create mode 100644 arch/arm/include/asm/arch-armv8/hi6553.h create mode 100644 board/96boards/hikey64/Kconfig create mode 100644 board/96boards/hikey64/Makefile create mode 100644 board/96boards/hikey64/hikey.c create mode 100644 configs/hikey_aemv8a_defconfig create mode 100644 drivers/gpio/hi6220_gpio.c create mode 100644 drivers/mmc/hi6220_dw_mmc.c create mode 100644 include/configs/hikey_aemv8a.h
This has been tested to the extent that I can enumerate a asix usb networking adapter and boot a kernel over usb on the 96boards hikey u-boot port I'm currently doing.
Signed-off-by: Peter Griffin peter.griffin@linaro.org --- drivers/usb/host/dwc2.c | 3 ++- drivers/usb/host/dwc2.h | 1 + 2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/usb/host/dwc2.c b/drivers/usb/host/dwc2.c index e8142ac..19a6007 100644 --- a/drivers/usb/host/dwc2.c +++ b/drivers/usb/host/dwc2.c @@ -1015,7 +1015,8 @@ int usb_lowlevel_init(int index, enum usb_init_type init, void **controller) snpsid = readl(®s->gsnpsid); printf("Core Release: %x.%03x\n", snpsid >> 12 & 0xf, snpsid & 0xfff);
- if ((snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_2xx) { + if ((snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_2xx && + (snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_3xx) { printf("SNPSID invalid (not DWC2 OTG device): %08x\n", snpsid); return -ENODEV; } diff --git a/drivers/usb/host/dwc2.h b/drivers/usb/host/dwc2.h index ba08fd5..1e0f502 100644 --- a/drivers/usb/host/dwc2.h +++ b/drivers/usb/host/dwc2.h @@ -729,6 +729,7 @@ struct dwc2_core_regs { #define DWC2_PCGCCTL_DEEP_SLEEP (1 << 7) #define DWC2_PCGCCTL_DEEP_SLEEP_OFFSET 7 #define DWC2_SNPSID_DEVID_VER_2xx (0x4f542 << 12) +#define DWC2_SNPSID_DEVID_VER_3xx (0x4f543 << 12) #define DWC2_SNPSID_DEVID_MASK (0xfffff << 12) #define DWC2_SNPSID_DEVID_OFFSET 12
This patch adds support for the GPIO perif found on hi6220 SoC.
Signed-off-by: Peter Griffin peter.griffin@linaro.org --- arch/arm/include/asm/arch-armv8/gpio.h | 47 +++++++++++++++++ drivers/gpio/Makefile | 2 + drivers/gpio/hi6220_gpio.c | 95 ++++++++++++++++++++++++++++++++++ 3 files changed, 144 insertions(+) create mode 100644 arch/arm/include/asm/arch-armv8/gpio.h create mode 100644 drivers/gpio/hi6220_gpio.c
diff --git a/arch/arm/include/asm/arch-armv8/gpio.h b/arch/arm/include/asm/arch-armv8/gpio.h new file mode 100644 index 0000000..162c2d9 --- /dev/null +++ b/arch/arm/include/asm/arch-armv8/gpio.h @@ -0,0 +1,47 @@ +/* + * Copyright (C) 2015 Linaro + * Peter Griffin peter.griffin@linaro.org + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _HI6220_GPIO_H_ +#define _HI6220_GPIO_H_ + +#define HI6220_GPIO0_BASE (void *)0xf8011000 +#define HI6220_GPIO1_BASE (void *)0xf8012000 +#define HI6220_GPIO2_BASE (void *)0xf8013000 +#define HI6220_GPIO3_BASE (void *)0xf8014000 +#define HI6220_GPIO4_BASE (void *)0xf7020000 +#define HI6220_GPIO5_BASE (void *)0xf7021000 +#define HI6220_GPIO6_BASE (void *)0xf7022000 +#define HI6220_GPIO7_BASE (void *)0xf7023000 +#define HI6220_GPIO8_BASE (void *)0xf7024000 +#define HI6220_GPIO9_BASE (void *)0xf7025000 +#define HI6220_GPIO10_BASE (void *)0xf7026000 +#define HI6220_GPIO11_BASE (void *)0xf7027000 +#define HI6220_GPIO12_BASE (void *)0xf7028000 +#define HI6220_GPIO13_BASE (void *)0xf7029000 +#define HI6220_GPIO14_BASE (void *)0xf702a000 +#define HI6220_GPIO15_BASE (void *)0xf702b000 +#define HI6220_GPIO16_BASE (void *)0xf702c000 +#define HI6220_GPIO17_BASE (void *)0xf702d000 +#define HI6220_GPIO18_BASE (void *)0xf702e000 +#define HI6220_GPIO19_BASE (void *)0xf702f000 + +#define BIT(x) (1 << (x)) + +#define HI6220_GPIO_PER_BANK 8 +#define HI6220_GPIO_DIR 0x400 + +struct gpio_bank { + u8 *base; /* address of registers in physical memory */ +}; + +/* Information about a GPIO bank */ +struct hikey_gpio_platdata { + int bank_index; + void *base; /* address of registers in physical memory */ +}; + +#endif /* _HI6220_GPIO_H_ */ diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 85f71c5..470fabd 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -42,3 +42,5 @@ obj-$(CONFIG_TCA642X) += tca642x.o oby-$(CONFIG_SX151X) += sx151x.o obj-$(CONFIG_SUNXI_GPIO) += sunxi_gpio.o obj-$(CONFIG_LPC32XX_GPIO) += lpc32xx_gpio.o +obj-$(CONFIG_HIKEY_GPIO) += hi6220_gpio.o + diff --git a/drivers/gpio/hi6220_gpio.c b/drivers/gpio/hi6220_gpio.c new file mode 100644 index 0000000..3f41bff --- /dev/null +++ b/drivers/gpio/hi6220_gpio.c @@ -0,0 +1,95 @@ +/* + * Copyright (C) 2015 Linaro + * Peter Griffin peter.griffin@linaro.org + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <asm/gpio.h> +#include <asm/io.h> +#include <errno.h> + +static int hi6220_gpio_direction_input(struct udevice *dev, unsigned int gpio) +{ + struct gpio_bank *bank = dev_get_priv(dev); + u8 data; + + data = readb(bank->base + HI6220_GPIO_DIR); + data &= ~(1 << gpio); + writeb(data, bank->base + HI6220_GPIO_DIR); + + return 0; +} + +static int hi6220_gpio_set_value(struct udevice *dev, unsigned gpio, + int value) +{ + struct gpio_bank *bank = dev_get_priv(dev); + + writeb(!!value << gpio, bank->base + (BIT(gpio + 2))); + return 0; +} + +static int hi6220_gpio_direction_output(struct udevice *dev, unsigned gpio, + int value) +{ + struct gpio_bank *bank = dev_get_priv(dev); + u8 data; + + data = readb(bank->base + HI6220_GPIO_DIR); + data |= 1 << gpio; + writeb(data, bank->base + HI6220_GPIO_DIR); + + hi6220_gpio_set_value(dev, gpio, value); + + return 0; +} + +static int hi6220_gpio_get_value(struct udevice *dev, unsigned gpio) +{ + struct gpio_bank *bank = dev_get_priv(dev); + + return !!readb(bank->base + (BIT(gpio + 2))); +} + + + +static const struct dm_gpio_ops gpio_hi6220_ops = { + .direction_input = hi6220_gpio_direction_input, + .direction_output = hi6220_gpio_direction_output, + .get_value = hi6220_gpio_get_value, + .set_value = hi6220_gpio_set_value, +}; + +static int hi6220_gpio_probe(struct udevice *dev) +{ + struct gpio_bank *bank = dev_get_priv(dev); + struct hikey_gpio_platdata *plat = dev_get_platdata(dev); + struct gpio_dev_priv *uc_priv = dev->uclass_priv; + char name[18], *str; + + sprintf(name, "GPIO%d_", plat->bank_index); + + str = strdup(name); + if (!str) + return -ENOMEM; + + uc_priv->bank_name = str; + uc_priv->gpio_count = HI6220_GPIO_PER_BANK; + + bank->base = (u8 *)plat->base; + + return 0; +} + +U_BOOT_DRIVER(gpio_hi6220) = { + .name = "gpio_hi6220", + .id = UCLASS_GPIO, + .ops = &gpio_hi6220_ops, + .probe = hi6220_gpio_probe, + .priv_auto_alloc_size = sizeof(struct gpio_bank), +}; + +
Hi Peter,
On 12 May 2015 at 07:25, Peter Griffin peter.griffin@linaro.org wrote:
This patch adds support for the GPIO perif found on hi6220 SoC.
Signed-off-by: Peter Griffin peter.griffin@linaro.org
arch/arm/include/asm/arch-armv8/gpio.h | 47 +++++++++++++++++ drivers/gpio/Makefile | 2 + drivers/gpio/hi6220_gpio.c | 95 ++++++++++++++++++++++++++++++++++ 3 files changed, 144 insertions(+) create mode 100644 arch/arm/include/asm/arch-armv8/gpio.h create mode 100644 drivers/gpio/hi6220_gpio.c
diff --git a/arch/arm/include/asm/arch-armv8/gpio.h b/arch/arm/include/asm/arch-armv8/gpio.h new file mode 100644 index 0000000..162c2d9 --- /dev/null +++ b/arch/arm/include/asm/arch-armv8/gpio.h @@ -0,0 +1,47 @@ +/*
- Copyright (C) 2015 Linaro
- Peter Griffin peter.griffin@linaro.org
- SPDX-License-Identifier: GPL-2.0+
- */
+#ifndef _HI6220_GPIO_H_ +#define _HI6220_GPIO_H_
+#define HI6220_GPIO0_BASE (void *)0xf8011000 +#define HI6220_GPIO1_BASE (void *)0xf8012000 +#define HI6220_GPIO2_BASE (void *)0xf8013000 +#define HI6220_GPIO3_BASE (void *)0xf8014000 +#define HI6220_GPIO4_BASE (void *)0xf7020000 +#define HI6220_GPIO5_BASE (void *)0xf7021000 +#define HI6220_GPIO6_BASE (void *)0xf7022000 +#define HI6220_GPIO7_BASE (void *)0xf7023000 +#define HI6220_GPIO8_BASE (void *)0xf7024000 +#define HI6220_GPIO9_BASE (void *)0xf7025000 +#define HI6220_GPIO10_BASE (void *)0xf7026000 +#define HI6220_GPIO11_BASE (void *)0xf7027000 +#define HI6220_GPIO12_BASE (void *)0xf7028000 +#define HI6220_GPIO13_BASE (void *)0xf7029000 +#define HI6220_GPIO14_BASE (void *)0xf702a000 +#define HI6220_GPIO15_BASE (void *)0xf702b000 +#define HI6220_GPIO16_BASE (void *)0xf702c000 +#define HI6220_GPIO17_BASE (void *)0xf702d000 +#define HI6220_GPIO18_BASE (void *)0xf702e000 +#define HI6220_GPIO19_BASE (void *)0xf702f000
I see device tree patches for this SoC - so is it possible to use device tree for this driver and avoid including these addresses?
[snip]
Regards, Simon
This patch adds the header files which will be used in the subsquent board / drivers to enable support for hi6220 hikey board.
Signed-off-by: Peter Griffin peter.griffin@linaro.org --- arch/arm/include/asm/arch-armv8/hi6220.h | 324 +++++++++++++++++++ .../include/asm/arch-armv8/hi6220_regs_alwayson.h | 349 +++++++++++++++++++++ 2 files changed, 673 insertions(+) create mode 100644 arch/arm/include/asm/arch-armv8/hi6220.h create mode 100644 arch/arm/include/asm/arch-armv8/hi6220_regs_alwayson.h
diff --git a/arch/arm/include/asm/arch-armv8/hi6220.h b/arch/arm/include/asm/arch-armv8/hi6220.h new file mode 100644 index 0000000..3ddec91 --- /dev/null +++ b/arch/arm/include/asm/arch-armv8/hi6220.h @@ -0,0 +1,324 @@ +/* + * (C) Copyright 2015 Linaro + * Peter Griffin peter.griffin@linaro.org + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __HI6220_H__ +#define __HI6220_H__ + +#include "hi6220_regs_alwayson.h" + +#define HI6220_MMC0_BASE 0xF723D000 +#define HI6220_MMC1_BASE 0xF723E000 + +#define HI6220_PMUSSI_BASE 0xF8000000 + +#define HI6220_PERI_BASE 0xF7030000 + +#define PERI_SC_PERIPH_CTRL1 (HI6220_PERI_BASE + 0x000) + +#define PERI_CTRL1_ETR_AXI_CSYSREQ_N (1 << 0) +#define PERI_CTRL1_HIFI_INT_MASK (1 << 1) +#define PERI_CTRL1_HIFI_ALL_INT_MASK (1 << 2) +#define PERI_CTRL1_ETR_AXI_CSYSREQ_N_MSK (1 << 16) +#define PERI_CTRL1_HIFI_INT_MASK_MSK (1 << 17) +#define PERI_CTRL1_HIFI_ALL_INT_MASK_MSK (1 << 18) + + +#define PERI_SC_PERIPH_CTRL2 (HI6220_PERI_BASE + 0x004) + +#define PERI_CTRL2_MMC_CLK_PHASE_BYPASS_EN_MMC0 (1 << 0) +#define PERI_CTRL2_MMC_CLK_PHASE_BYPASS_EN_MMC1 (1 << 2) +#define PERI_CTRL2_NAND_SYS_MEM_SEL (1 << 6) +#define PERI_CTRL2_G3D_DDRT_AXI_SEL (1 << 7) +#define PERI_CTRL2_GU_MDM_BBP_TESTPIN_SEL (1 << 8) +#define PERI_CTRL2_CODEC_SSI_MASTER_CHECK (1 << 9) +#define PERI_CTRL2_FUNC_TEST_SOFT (1 << 12) +#define PERI_CTRL2_CSSYS_TS_ENABLE (1 << 15) +#define PERI_CTRL2_HIFI_RAMCTRL_S_EMA (1 << 16) +#define PERI_CTRL2_HIFI_RAMCTRL_S_EMAW (1 << 20) +#define PERI_CTRL2_HIFI_RAMCTRL_S_EMAS (1 << 22) +#define PERI_CTRL2_HIFI_RAMCTRL_S_RET1N (1 << 26) +#define PERI_CTRL2_HIFI_RAMCTRL_S_RET2N (1 << 27) +#define PERI_CTRL2_HIFI_RAMCTRL_S_PGEN (1 << 28) + +#define PERI_SC_PERIPH_CTRL3 (HI6220_PERI_BASE + 0x008) + +#define PERI_CTRL3_HIFI_DDR_HARQMEM_ADDR (1 << 0) +#define PERI_CTRL3_HIFI_HARQMEMRMP_EN (1 << 12) +#define PERI_CTRL3_HARQMEM_SYS_MED_SEL (1 << 13) +#define PERI_CTRL3_SOC_AP_OCCUPY_GRP1 (1 << 14) +#define PERI_CTRL3_SOC_AP_OCCUPY_GRP2 (1 << 16) +#define PERI_CTRL3_SOC_AP_OCCUPY_GRP3 (1 << 18) +#define PERI_CTRL3_SOC_AP_OCCUPY_GRP4 (1 << 20) +#define PERI_CTRL3_SOC_AP_OCCUPY_GRP5 (1 << 22) +#define PERI_CTRL3_SOC_AP_OCCUPY_GRP6 (1 << 24) + +#define PERI_SC_PERIPH_CTRL4 (HI6220_PERI_BASE + 0x00c) + +#define PERI_CTRL4_PICO_FSELV (1 << 0) +#define PERI_CTRL4_FPGA_EXT_PHY_SEL (1 << 3) +#define PERI_CTRL4_PICO_REFCLKSEL (1 << 4) +#define PERI_CTRL4_PICO_SIDDQ (1 << 6) +#define PERI_CTRL4_PICO_SUSPENDM_SLEEPM (1 << 7) +#define PERI_CTRL4_PICO_OGDISABLE (1 << 8) +#define PERI_CTRL4_PICO_COMMONONN (1 << 9) +#define PERI_CTRL4_PICO_VBUSVLDEXT (1 << 10) +#define PERI_CTRL4_PICO_VBUSVLDEXTSEL (1 << 11) +#define PERI_CTRL4_PICO_VATESTENB (1 << 12) +#define PERI_CTRL4_PICO_SUSPENDM (1 << 14) +#define PERI_CTRL4_PICO_SLEEPM (1 << 15) +#define PERI_CTRL4_BC11_C (1 << 16) +#define PERI_CTRL4_BC11_B (1 << 17) +#define PERI_CTRL4_BC11_A (1 << 18) +#define PERI_CTRL4_BC11_GND (1 << 19) +#define PERI_CTRL4_BC11_FLOAT (1 << 20) +#define PERI_CTRL4_OTG_PHY_SEL (1 << 21) +#define PERI_CTRL4_USB_OTG_SS_SCALEDOWN_MODE (1 << 22) +#define PERI_CTRL4_OTG_DM_PULLDOWN (1 << 24) +#define PERI_CTRL4_OTG_DP_PULLDOWN (1 << 25) +#define PERI_CTRL4_OTG_IDPULLUP (1 << 26) +#define PERI_CTRL4_OTG_DRVBUS (1 << 27) +#define PERI_CTRL4_OTG_SESSEND (1 << 28) +#define PERI_CTRL4_OTG_BVALID (1 << 29) +#define PERI_CTRL4_OTG_AVALID (1 << 30) +#define PERI_CTRL4_OTG_VBUSVALID (1 << 31) + +#define PERI_SC_PERIPH_CTRL5 (HI6220_PERI_BASE + 0x010) + +#define PERI_CTRL5_USBOTG_RES_SEL (1 << 3) +#define PERI_CTRL5_PICOPHY_ACAENB (1 << 4) +#define PERI_CTRL5_PICOPHY_BC_MODE (1 << 5) +#define PERI_CTRL5_PICOPHY_CHRGSEL (1 << 6) +#define PERI_CTRL5_PICOPHY_VDATSRCEND (1 << 7) +#define PERI_CTRL5_PICOPHY_VDATDETENB (1 << 8) +#define PERI_CTRL5_PICOPHY_DCDENB (1 << 9) +#define PERI_CTRL5_PICOPHY_IDDIG (1 << 10) +#define PERI_CTRL5_DBG_MUX (1 << 11) + +#define PERI_SC_PERIPH_CTRL6 (HI6220_PERI_BASE + 0x014) + +#define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_EMA (1 << 0) +#define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_EMAW (1 << 4) +#define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_EMAS (1 << 6) +#define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_RET1N (1 << 10) +#define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_RET2N (1 << 11) +#define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_PGEN (1 << 12) + +#define PERI_SC_PERIPH_CTRL8 (HI6220_PERI_BASE + 0x018) + +#define PERI_CTRL8_PICOPHY_TXRISETUNE0 (1 << 0) +#define PERI_CTRL8_PICOPHY_TXPREEMPAMPTUNE0 (1 << 2) +#define PERI_CTRL8_PICOPHY_TXRESTUNE0 (1 << 4) +#define PERI_CTRL8_PICOPHY_TXHSSVTUNE0 (1 << 6) +#define PERI_CTRL8_PICOPHY_COMPDISTUNE0 (1 << 8) +#define PERI_CTRL8_PICOPHY_TXPREEMPPULSETUNE0 (1 << 11) +#define PERI_CTRL8_PICOPHY_OTGTUNE0 (1 << 12) +#define PERI_CTRL8_PICOPHY_SQRXTUNE0 (1 << 16) +#define PERI_CTRL8_PICOPHY_TXVREFTUNE0 (1 << 20) +#define PERI_CTRL8_PICOPHY_TXFSLSTUNE0 (1 << 28) + +#define PERI_SC_PERIPH_CTRL9 (HI6220_PERI_BASE + 0x01c) + +#define PERI_CTRL9_PICOPLY_TESTCLKEN (1 << 0) +#define PERI_CTRL9_PICOPLY_TESTDATAOUTSEL (1 << 1) +#define PERI_CTRL9_PICOPLY_TESTADDR (1 << 4) +#define PERI_CTRL9_PICOPLY_TESTDATAIN (1 << 8) + +#define PERI_SC_PERIPH_CTRL10 (HI6220_PERI_BASE + 0x020) +#define PERI_SC_PERIPH_CTRL12 (HI6220_PERI_BASE + 0x024) +#define PERI_SC_PERIPH_CTRL13 (HI6220_PERI_BASE + 0x028) +#define PERI_SC_PERIPH_CTRL14 (HI6220_PERI_BASE + 0x02c) + +#define PERI_SC_DDR_CTRL0 (HI6220_PERI_BASE + 0x050) +#define PERI_SC_PERIPH_STAT1 (HI6220_PERI_BASE + 0x094) + +#define PERI_SC_PERIPH_CLK0_EN (HI6220_PERI_BASE + 0x200) +#define PERI_SC_PERIPH_CLK0_DIS (HI6220_PERI_BASE + 0x204) +#define PERI_SC_PERIPH_CLK0_STAT (HI6220_PERI_BASE + 0x208) + +#define PERI_CLK0_MMC0 (1 << 0) +#define PERI_CLK0_MMC1 (1 << 1) +#define PERI_CLK0_MMC2 (1 << 2) +#define PERI_CLK0_NANDC (1 << 3) +#define PERI_CLK0_USBOTG (1 << 4) +#define PERI_CLK0_PICOPHY (1 << 5) +#define PERI_CLK0_PLL (1 << 6) + +#define PERI_SC_PERIPH_CLK1_EN (HI6220_PERI_BASE + 0x210) +#define PERI_SC_PERIPH_CLK1_DIS (HI6220_PERI_BASE + 0x214) +#define PERI_SC_PERIPH_CLK1_STAT (HI6220_PERI_BASE + 0x218) + +#define PERI_CLK1_HIFI (1 << 0) +#define PERI_CLK1_DIGACODEC (1 << 5) + + +#define PERI_SC_PERIPH_CLK2_EN (HI6220_PERI_BASE + 0x220) +#define PERI_SC_PERIPH_CLK2_DIS (HI6220_PERI_BASE + 0x224) +#define PERI_SC_PERIPH_CLK2_STAT (HI6220_PERI_BASE + 0x228) + +#define PERI_CLK2_IPF (1 << 0) +#define PERI_CLK2_SOCP (1 << 1) +#define PERI_CLK2_DMAC (1 << 2) +#define PERI_CLK2_SECENG (1 << 3) +#define PERI_CLK2_HPM0 (1 << 5) +#define PERI_CLK2_HPM1 (1 << 6) +#define PERI_CLK2_HPM2 (1 << 7) +#define PERI_CLK2_HPM3 (1 << 8) + + +#define PERI_SC_PERIPH_CLK3_EN (HI6220_PERI_BASE + 0x230) +#define PERI_SC_PERIPH_CLK3_DIS (HI6220_PERI_BASE + 0x234) +#define PERI_SC_PERIPH_CLK3_STAT (HI6220_PERI_BASE + 0x238) + + + + +#define PERI_SC_PERIPH_CLK8_EN (HI6220_PERI_BASE + 0x240) +#define PERI_SC_PERIPH_CLK8_DIS (HI6220_PERI_BASE + 0x244) +#define PERI_SC_PERIPH_CLK8_STAT (HI6220_PERI_BASE + 0x248) + +#define PERI_CLK8_RS0 (1 << 0) +#define PERI_CLK8_RS2 (1 << 1) +#define PERI_CLK8_RS3 (1 << 2) +#define PERI_CLK8_MS0 (1 << 3) +#define PERI_CLK8_MS2 (1 << 5) +#define PERI_CLK8_XG2RAM0 (1 << 6) +#define PERI_CLK8_X2SRAM (1 << 7) +#define PERI_CLK8_SRAM (1 << 8) +#define PERI_CLK8_ROM (1 << 9) +#define PERI_CLK8_HARQ (1 << 10) +#define PERI_CLK8_MMU (1 << 11) +#define PERI_CLK8_DDRC (1 << 12) +#define PERI_CLK8_DDRPHY (1 << 13) +#define PERI_CLK8_DDRPHY_REF (1 << 14) +#define PERI_CLK8_X2X_SYSNOC (1 << 15) +#define PERI_CLK8_X2X_CCPU (1 << 16) +#define PERI_CLK8_DDRT (1 << 17) +#define PERI_CLK8_DDRPACK_RS (1 << 18) + + +#define PERI_SC_PERIPH_CLK9_EN (HI6220_PERI_BASE + 0x250) +#define PERI_SC_PERIPH_CLK9_DIS (HI6220_PERI_BASE + 0x254) +#define PERI_SC_PERIPH_CLK9_STAT (HI6220_PERI_BASE + 0x258) + +#define PERI_CLK9_CARM_DAP (1 << 0) +#define PERI_CLK9_CARM_ATB (1 << 1) +#define PERI_CLK9_CARM_LBUS (1 << 2) +#define PERI_CLK9_CARM_KERNEL (1 << 3) + + +#define PERI_SC_PERIPH_CLK10_EN (HI6220_PERI_BASE + 0x260) +#define PERI_SC_PERIPH_CLK10_DIS (HI6220_PERI_BASE + 0x264) +#define PERI_SC_PERIPH_CLK10_STAT (HI6220_PERI_BASE + 0x268) + +#define PERI_CLK10_IPF_CCPU (1 << 0) +#define PERI_CLK10_SOCP_CCPU (1 << 1) +#define PERI_CLK10_SECENG_CCPU (1 << 2) +#define PERI_CLK10_HARQ_CCPU (1 << 3) +#define PERI_CLK10_IPF_MCU (1 << 16) +#define PERI_CLK10_SOCP_MCU (1 << 17) +#define PERI_CLK10_SECENG_MCU (1 << 18) +#define PERI_CLK10_HARQ_MCU (1 << 19) + +#define PERI_SC_PERIPH_CLK12_EN (HI6220_PERI_BASE + 0x270) +#define PERI_SC_PERIPH_CLK12_DIS (HI6220_PERI_BASE + 0x274) +#define PERI_SC_PERIPH_CLK12_STAT (HI6220_PERI_BASE + 0x278) + +#define PERI_CLK12_HIFI_SRC (1 << 0) +#define PERI_CLK12_MMC0_SRC (1 << 1) +#define PERI_CLK12_MMC1_SRC (1 << 2) +#define PERI_CLK12_MMC2_SRC (1 << 3) +#define PERI_CLK12_SYSPLL_DIV (1 << 4) +#define PERI_CLK12_TPIU_SRC (1 << 5) +#define PERI_CLK12_MMC0_HF (1 << 6) +#define PERI_CLK12_MMC1_HF (1 << 7) +#define PERI_CLK12_PLL_TEST_SRC (1 << 8) +#define PERI_CLK12_CODEC_SOC (1 << 9) +#define PERI_CLK12_MEDIA (1 << 10) + +#define PERI_SC_PERIPH_RST0_EN (HI6220_PERI_BASE + 0x300) +#define PERI_SC_PERIPH_RST0_DIS (HI6220_PERI_BASE + 0x304) +#define PERI_SC_PERIPH_RST0_STAT (HI6220_PERI_BASE + 0x308) + +#define PERI_RST0_MMC0 (1 << 0) +#define PERI_RST0_MMC1 (1 << 1) +#define PERI_RST0_MMC2 (1 << 2) +#define PERI_RST0_NANDC (1 << 3) +#define PERI_RST0_USBOTG_BUS (1 << 4) +#define PERI_RST0_POR_PICOPHY (1 << 5) +#define PERI_RST0_USBOTG (1 << 6) +#define PERI_RST0_USBOTG_32K (1 << 7) + + +#define PERI_SC_PERIPH_RST1_EN (HI6220_PERI_BASE + 0x310) +#define PERI_SC_PERIPH_RST1_DIS (HI6220_PERI_BASE + 0x314) +#define PERI_SC_PERIPH_RST1_STAT (HI6220_PERI_BASE + 0x318) + +#define PERI_RST1_HIFI (1 << 0) +#define PERI_RST1_DIGACODEC (1 << 5) + + +#define PERI_SC_PERIPH_RST2_EN (HI6220_PERI_BASE + 0x320) +#define PERI_SC_PERIPH_RST2_DIS (HI6220_PERI_BASE + 0x324) +#define PERI_SC_PERIPH_RST2_STAT (HI6220_PERI_BASE + 0x328) + +#define PERI_RST2_IPF (1 << 0) +#define PERI_RST2_SOCP (1 << 1) +#define PERI_RST2_DMAC (1 << 2) +#define PERI_RST2_SECENG (1 << 3) +#define PERI_RST2_ABB (1 << 4) +#define PERI_RST2_HPM0 (1 << 5) +#define PERI_RST2_HPM1 (1 << 6) +#define PERI_RST2_HPM2 (1 << 7) +#define PERI_RST2_HPM3 (1 << 8) + + +#define PERI_SC_PERIPH_RST3_EN (HI6220_PERI_BASE + 0x330) +#define PERI_SC_PERIPH_RST3_DIS (HI6220_PERI_BASE + 0x334) +#define PERI_SC_PERIPH_RST3_STAT (HI6220_PERI_BASE + 0x338) + +#define PERI_RST3_CSSYS (1 << 0) +#define PERI_RST3_I2C0 (1 << 1) +#define PERI_RST3_I2C1 (1 << 2) +#define PERI_RST3_I2C2 (1 << 3) +#define PERI_RST3_I2C3 (1 << 4) +#define PERI_RST3_UART1 (1 << 5) +#define PERI_RST3_UART2 (1 << 6) +#define PERI_RST3_UART3 (1 << 7) +#define PERI_RST3_UART4 (1 << 8) +#define PERI_RST3_SSP (1 << 9) +#define PERI_RST3_PWM (1 << 10) +#define PERI_RST3_BLPWM (1 << 11) +#define PERI_RST3_TSENSOR (1 << 12) +#define PERI_RST3_DAPB (1 << 18) +#define PERI_RST3_HKADC (1 << 19) +#define PERI_RST3_CODEC (1 << 20) + + +#define PERI_SC_PERIPH_RST8_EN (HI6220_PERI_BASE + 0x340) +#define PERI_SC_PERIPH_RST8_DIS (HI6220_PERI_BASE + 0x344) +#define PERI_SC_PERIPH_RST8_STAT (HI6220_PERI_BASE + 0x338) + +#define PERI_RST8_RS0 (1 << 0) +#define PERI_RST8_RS2 (1 << 1) +#define PERI_RST8_RS3 (1 << 2) +#define PERI_RST8_MS0 (1 << 3) +#define PERI_RST8_MS2 (1 << 5) +#define PERI_RST8_XG2RAM0 (1 << 6) +#define PERI_RST8_X2SRAM_TZMA (1 << 7) +#define PERI_RST8_SRAM (1 << 8) +#define PERI_RST8_HARQ (1 << 10) +#define PERI_RST8_DDRC (1 << 12) +#define PERI_RST8_DDRC_APB (1 << 13) +#define PERI_RST8_DDRPACK_APB (1 << 14) +#define PERI_RST8_DDRT (1 << 17) + +#define PERI_SC_CLK0_SEL (HI6220_PERI_BASE + 0x400) +#define PERI_SC_CLKCFG8BIT1 (HI6220_PERI_BASE + 0x494) +#define PERI_SC_CLKCFG8BIT2 (HI6220_PERI_BASE + 0x498) +#define PERI_SC_RESERVED8_ADDR (HI6220_PERI_BASE + 0xd04) + +#endif /*__HI62220_H__*/ diff --git a/arch/arm/include/asm/arch-armv8/hi6220_regs_alwayson.h b/arch/arm/include/asm/arch-armv8/hi6220_regs_alwayson.h new file mode 100644 index 0000000..3f0205a --- /dev/null +++ b/arch/arm/include/asm/arch-armv8/hi6220_regs_alwayson.h @@ -0,0 +1,349 @@ +/* + * (C) Copyright 2015 Linaro + * Peter Griffin peter.griffin@linaro.org + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __HI6220_ALWAYSON_H__ +#define __HI6220_ALWAYSON_H__ + +#define ALWAYSON_CTRL_BASE 0xF7800000 + +#define ALWAYSON_SC_SYS_CTRL0 (ALWAYSON_CTRL_BASE + 0x000) + +#define ALWAYSON_SC_SYS_CTRL0_MODE_NORMAL 0x004 +#define ALWAYSON_SC_SYS_CTRL0_MODE_MASK 0x007 + +#define ALWAYSON_SC_SYS_CTRL1 (ALWAYSON_CTRL_BASE + 0x004) + +#define ALWAYSON_SC_SYS_CTRL1_AARM_WD_RST_CFG (1 << 0) +#define ALWAYSON_SC_SYS_CTRL1_REMAP_SRAM_AARM (1 << 1) +#define ALWAYSON_SC_SYS_CTRL1_EFUSEC_REMAP (1 << 2) +#define ALWAYSON_SC_SYS_CTRL1_EXT_PLL_SEL (1 << 3) +#define ALWAYSON_SC_SYS_CTRL1_MCU_WDG0_RSTMCU_CFG (1 << 4) +#define ALWAYSON_SC_SYS_CTRL1_USIM0_HPD_DE_BOUNCE_CFG (1 << 6) +#define ALWAYSON_SC_SYS_CTRL1_USIM0_HPD_OE_CFG (1 << 7) +#define ALWAYSON_SC_SYS_CTRL1_USIM1_HPD_DE_BOUNCE_CFG (1 << 8) +#define ALWAYSON_SC_SYS_CTRL1_USIM1_HPD_OE_CFG (1 << 9) +#define ALWAYSON_SC_SYS_CTRL1_BUS_DFS_FORE_HD_CFG (1 << 10) +#define ALWAYSON_SC_SYS_CTRL1_BUS_DFS_FORE_HD_CFG1 (1 << 11) +#define ALWAYSON_SC_SYS_CTRL1_USIM0_HPD_OE_SFT (1 << 12) +#define ALWAYSON_SC_SYS_CTRL1_USIM1_HPD_OE_SFT (1 << 13) +#define ALWAYSON_SC_SYS_CTRL1_MCU_CLKEN_HARDCFG (1 << 15) +#define ALWAYSON_SC_SYS_CTRL1_AARM_WD_RST_CFG_MSK (1 << 16) +#define ALWAYSON_SC_SYS_CTRL1_REMAP_SRAM_AARM_MSK (1 << 17) +#define ALWAYSON_SC_SYS_CTRL1_EFUSEC_REMAP_MSK (1 << 18) +#define ALWAYSON_SC_SYS_CTRL1_EXT_PLL_SEL_MSK (1 << 19) +#define ALWAYSON_SC_SYS_CTRL1_MCU_WDG0_RSTMCU_CFG_MSK (1 << 20) +#define ALWAYSON_SC_SYS_CTRL1_USIM0_HPD_DE_BOUNCE_CFG_MSK (1 << 22) +#define ALWAYSON_SC_SYS_CTRL1_USIM0_HPD_OE_CFG_MSK (1 << 23) +#define ALWAYSON_SC_SYS_CTRL1_USIM1_HPD_DE_BOUNCE_CFG_MSK (1 << 24) +#define ALWAYSON_SC_SYS_CTRL1_USIM1_HPD_OE_CFG_MSK (1 << 25) +#define ALWAYSON_SC_SYS_CTRL1_BUS_DFS_FORE_HD_CFG_MSK (1 << 26) +#define ALWAYSON_SC_SYS_CTRL1_BUS_DFS_FORE_HD_CFG1_MSK (1 << 27) +#define ALWAYSON_SC_SYS_CTRL1_USIM0_HPD_OE_SFT_MSK (1 << 28) +#define ALWAYSON_SC_SYS_CTRL1_USIM1_HPD_OE_SFT_MSK (1 << 29) +#define ALWAYSON_SC_SYS_CTRL1_MCU_CLKEN_HARDCFG_MSK (1 << 31) + +#define ALWAYSON_SC_SYS_CTRL2 (ALWAYSON_CTRL_BASE + 0x008) + +#define ALWAYSON_SC_SYS_CTRL2_MCU_SFT_RST_STAT_CLEAR (1 << 26) +#define ALWAYSON_SC_SYS_CTRL2_MCU_WDG0_RST_STAT_CLEAR (1 << 27) +#define ALWAYSON_SC_SYS_CTRL2_TSENSOR_RST_STAT_CLEAR (1 << 28) +#define ALWAYSON_SC_SYS_CTRL2_ACPU_WDG_RST_STAT_CLEAR (1 << 29) +#define ALWAYSON_SC_SYS_CTRL2_MCU_WDG1_RST_STAT_CLEAR (1 << 30) +#define ALWAYSON_SC_SYS_CTRL2_GLB_SRST_STAT_CLEAR (1 << 31) + +#define ALWAYSON_SC_SYS_STAT0 (ALWAYSON_CTRL_BASE + 0x010) + +#define ALWAYSON_SC_SYS_STAT0_MCU_RST_STAT (1 << 25) +#define ALWAYSON_SC_SYS_STAT0_MCU_SOFTRST_STAT (1 << 26) +#define ALWAYSON_SC_SYS_STAT0_MCU_WDGRST_STAT (1 << 27) +#define ALWAYSON_SC_SYS_STAT0_TSENSOR_HARDRST_STAT (1 << 28) +#define ALWAYSON_SC_SYS_STAT0_ACPU_WD_GLB_RST_STAT (1 << 29) +#define ALWAYSON_SC_SYS_STAT0_CM3_WDG1_RST_STAT (1 << 30) +#define ALWAYSON_SC_SYS_STAT0_GLB_SRST_STAT (1 << 31) + +#define ALWAYSON_SC_SYS_STAT1 (ALWAYSON_CTRL_BASE + 0x014) + +#define ALWAYSON_SC_SYS_STAT1_MODE_STATUS (1 << 0) +#define ALWAYSON_SC_SYS_STAT1_BOOT_SEL_LOCK (1 << 16) +#define ALWAYSON_SC_SYS_STAT1_FUNC_MODE_LOCK (1 << 17) +#define ALWAYSON_SC_SYS_STAT1_BOOT_MODE_LOCK (1 << 19) +#define ALWAYSON_SC_SYS_STAT1_FUN_JTAG_MODE_OUT (1 << 20) +#define ALWAYSON_SC_SYS_STAT1_SECURITY_BOOT_FLG (1 << 27) +#define ALWAYSON_SC_SYS_STAT1_EFUSE_NANDBOOT_MSK (1 << 28) +#define ALWAYSON_SC_SYS_STAT1_EFUSE_NAND_BITWIDE (1 << 29) + +#define ALWAYSON_SC_MCU_IMCTRL (ALWAYSON_CTRL_BASE + 0x018) +#define ALWAYSON_SC_MCU_IMSTAT (ALWAYSON_CTRL_BASE + 0x01C) +#define ALWAYSON_SC_SECONDRY_INT_EN0 (ALWAYSON_CTRL_BASE + 0x044) +#define ALWAYSON_SC_SECONDRY_INT_STATR0 (ALWAYSON_CTRL_BASE + 0x048) +#define ALWAYSON_SC_SECONDRY_INT_STATM0 (ALWAYSON_CTRL_BASE + 0x04C) +#define ALWAYSON_SC_MCU_WKUP_INT_EN6 (ALWAYSON_CTRL_BASE + 0x054) +#define ALWAYSON_SC_MCU_WKUP_INT_STATR6 (ALWAYSON_CTRL_BASE + 0x058) +#define ALWAYSON_SC_MCU_WKUP_INT_STATM6 (ALWAYSON_CTRL_BASE + 0x05C) +#define ALWAYSON_SC_MCU_WKUP_INT_EN5 (ALWAYSON_CTRL_BASE + 0x064) +#define ALWAYSON_SC_MCU_WKUP_INT_STATR5 (ALWAYSON_CTRL_BASE + 0x068) +#define ALWAYSON_SC_MCU_WKUP_INT_STATM5 (ALWAYSON_CTRL_BASE + 0x06C) +#define ALWAYSON_SC_MCU_WKUP_INT_EN4 (ALWAYSON_CTRL_BASE + 0x094) +#define ALWAYSON_SC_MCU_WKUP_INT_STATR4 (ALWAYSON_CTRL_BASE + 0x098) +#define ALWAYSON_SC_MCU_WKUP_INT_STATM4 (ALWAYSON_CTRL_BASE + 0x09C) +#define ALWAYSON_SC_MCU_WKUP_INT_EN0 (ALWAYSON_CTRL_BASE + 0x0A8) +#define ALWAYSON_SC_MCU_WKUP_INT_STATR0 (ALWAYSON_CTRL_BASE + 0x0AC) +#define ALWAYSON_SC_MCU_WKUP_INT_STATM0 (ALWAYSON_CTRL_BASE + 0x0B0) +#define ALWAYSON_SC_MCU_WKUP_INT_EN1 (ALWAYSON_CTRL_BASE + 0x0B4) +#define ALWAYSON_SC_MCU_WKUP_INT_STATR1 (ALWAYSON_CTRL_BASE + 0x0B8) +#define ALWAYSON_SC_MCU_WKUP_INT_STATM1 (ALWAYSON_CTRL_BASE + 0x0BC) +#define ALWAYSON_SC_INT_STATR (ALWAYSON_CTRL_BASE + 0x0C4) +#define ALWAYSON_SC_INT_STATM (ALWAYSON_CTRL_BASE + 0x0C8) +#define ALWAYSON_SC_INT_CLEAR (ALWAYSON_CTRL_BASE + 0x0CC) +#define ALWAYSON_SC_INT_EN_SET (ALWAYSON_CTRL_BASE + 0x0D0) +#define ALWAYSON_SC_INT_EN_DIS (ALWAYSON_CTRL_BASE + 0x0D4) +#define ALWAYSON_SC_INT_EN_STAT (ALWAYSON_CTRL_BASE + 0x0D8) +#define ALWAYSON_SC_INT_STATR1 (ALWAYSON_CTRL_BASE + 0x0E4) +#define ALWAYSON_SC_INT_STATM1 (ALWAYSON_CTRL_BASE + 0x0E8) +#define ALWAYSON_SC_INT_CLEAR1 (ALWAYSON_CTRL_BASE + 0x0EC) +#define ALWAYSON_SC_INT_EN_SET1 (ALWAYSON_CTRL_BASE + 0x0F0) +#define ALWAYSON_SC_INT_EN_DIS1 (ALWAYSON_CTRL_BASE + 0x0F4) +#define ALWAYSON_SC_INT_EN_STAT1 (ALWAYSON_CTRL_BASE + 0x0F8) +#define ALWAYSON_SC_TIMER_EN0 (ALWAYSON_CTRL_BASE + 0x1D0) +#define ALWAYSON_SC_TIMER_EN1 (ALWAYSON_CTRL_BASE + 0x1D4) +#define ALWAYSON_SC_TIMER_EN4 (ALWAYSON_CTRL_BASE + 0x1F0) +#define ALWAYSON_SC_TIMER_EN5 (ALWAYSON_CTRL_BASE + 0x1F4) +#define ALWAYSON_SC_MCU_SUBSYS_CTRL0 (ALWAYSON_CTRL_BASE + 0x400) +#define ALWAYSON_SC_MCU_SUBSYS_CTRL1 (ALWAYSON_CTRL_BASE + 0x404) +#define ALWAYSON_SC_MCU_SUBSYS_CTRL2 (ALWAYSON_CTRL_BASE + 0x408) +#define ALWAYSON_SC_MCU_SUBSYS_CTRL3 (ALWAYSON_CTRL_BASE + 0x40C) + +#define ALWAYSON_SC_MCU_SUBSYS_CTRL3_RCLK_3 0x003 +#define ALWAYSON_SC_MCU_SUBSYS_CTRL3_RCLK_MASK 0x007 +#define ALWAYSON_SC_MCU_SUBSYS_CTRL3_CSSYS_CTRL_PROT (1 << 3) +#define ALWAYSON_SC_MCU_SUBSYS_CTRL3_TCXO_AFC_OEN_CRG (1 << 4) +#define ALWAYSON_SC_MCU_SUBSYS_CTRL3_AOB_IO_SEL18_USIM1 (1 << 8) +#define ALWAYSON_SC_MCU_SUBSYS_CTRL3_AOB_IO_SEL18_USIM0 (1 << 9) +#define ALWAYSON_SC_MCU_SUBSYS_CTRL3_AOB_IO_SEL18_SD (1 << 10) +#define ALWAYSON_SC_MCU_SUBSYS_CTRL3_MCU_SUBSYS_CTRL3_RESERVED (1 << 11) + +#define ALWAYSON_SC_MCU_SUBSYS_CTRL4 (ALWAYSON_CTRL_BASE + 0x410) +#define ALWAYSON_SC_MCU_SUBSYS_CTRL5 (ALWAYSON_CTRL_BASE + 0x414) +#define ALWAYSON_SC_MCU_SUBSYS_CTRL6 (ALWAYSON_CTRL_BASE + 0x418) +#define ALWAYSON_SC_MCU_SUBSYS_CTRL7 (ALWAYSON_CTRL_BASE + 0x41C) +#define ALWAYSON_SC_MCU_SUBSYS_STAT0 (ALWAYSON_CTRL_BASE + 0x440) +#define ALWAYSON_SC_MCU_SUBSYS_STAT1 (ALWAYSON_CTRL_BASE + 0x444) +#define ALWAYSON_SC_MCU_SUBSYS_STAT2 (ALWAYSON_CTRL_BASE + 0x448) +#define ALWAYSON_SC_MCU_SUBSYS_STAT3 (ALWAYSON_CTRL_BASE + 0x44C) +#define ALWAYSON_SC_MCU_SUBSYS_STAT4 (ALWAYSON_CTRL_BASE + 0x450) +#define ALWAYSON_SC_MCU_SUBSYS_STAT5 (ALWAYSON_CTRL_BASE + 0x454) +#define ALWAYSON_SC_MCU_SUBSYS_STAT6 (ALWAYSON_CTRL_BASE + 0x458) +#define ALWAYSON_SC_MCU_SUBSYS_STAT7 (ALWAYSON_CTRL_BASE + 0x45C) + +#define ALWAYSON_SC_PERIPH_CLK4_EN (ALWAYSON_CTRL_BASE + 0x630) + +#define ALWAYSON_SC_PERIPH_CLK4_EN_HCLK_MCU (1 << 0) +#define ALWAYSON_SC_PERIPH_CLK4_EN_CLK_MCU_DAP (1 << 3) +#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_CM3_TIMER0 (1 << 4) +#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_CM3_TIMER1 (1 << 5) +#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_CM3_WDT0 (1 << 6) +#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_CM3_WDT1 (1 << 7) +#define ALWAYSON_SC_PERIPH_CLK4_EN_HCLK_IPC_S (1 << 8) +#define ALWAYSON_SC_PERIPH_CLK4_EN_HCLK_IPC_NS (1 << 9) +#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_EFUSEC (1 << 10) +#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TZPC (1 << 11) +#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_WDT0 (1 << 12) +#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_WDT1 (1 << 13) +#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_WDT2 (1 << 14) +#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER0 (1 << 15) +#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER1 (1 << 16) +#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER2 (1 << 17) +#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER3 (1 << 18) +#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER4 (1 << 19) +#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER5 (1 << 20) +#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER6 (1 << 21) +#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER7 (1 << 22) +#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER8 (1 << 23) +#define ALWAYSON_SC_PERIPH_CLK4_EN_CLK_UART0 (1 << 24) +#define ALWAYSON_SC_PERIPH_CLK4_EN_CLK_RTC0 (1 << 25) +#define ALWAYSON_SC_PERIPH_CLK4_EN_CLK_RTC1 (1 << 26) +#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_PMUSSI (1 << 27) +#define ALWAYSON_SC_PERIPH_CLK4_EN_CLK_JTAG_AUTH (1 << 28) +#define ALWAYSON_SC_PERIPH_CLK4_EN_CLK_CS_DAPB_ON (1 << 29) +#define ALWAYSON_SC_PERIPH_CLK4_EN_CLK_PDM (1 << 30) +#define ALWAYSON_SC_PERIPH_CLK4_EN_CLK_SSI_PAD (1 << 31) + +#define ALWAYSON_SC_PERIPH_CLK4_DIS (ALWAYSON_CTRL_BASE + 0x634) +#define ALWAYSON_SC_PERIPH_CLK4_STAT (ALWAYSON_CTRL_BASE + 0x638) + +#define ALWAYSON_SC_PERIPH_CLK5_EN (ALWAYSON_CTRL_BASE + 0x63C) + +#define ALWAYSON_SC_PERIPH_CLK5_EN_PCLK_PMUSSI_CCPU (1 << 0) +#define ALWAYSON_SC_PERIPH_CLK5_EN_PCLK_EFUSEC_CCPU (1 << 1) +#define ALWAYSON_SC_PERIPH_CLK5_EN_HCLK_IPC_CCPU (1 << 2) +#define ALWAYSON_SC_PERIPH_CLK5_EN_HCLK_IPC_NS_CCPU (1 << 3) +#define ALWAYSON_SC_PERIPH_CLK5_EN_PCLK_PMUSSI_MCU (1 << 16) +#define ALWAYSON_SC_PERIPH_CLK5_EN_PCLK_EFUSEC_MCU (1 << 17) +#define ALWAYSON_SC_PERIPH_CLK5_EN_HCLK_IPC_MCU (1 << 18) +#define ALWAYSON_SC_PERIPH_CLK5_EN_HCLK_IPC_NS_MCU (1 << 19) + +#define ALWAYSON_SC_PERIPH_CLK5_DIS (ALWAYSON_CTRL_BASE + 0x640) +#define ALWAYSON_SC_PERIPH_CLK5_STAT (ALWAYSON_CTRL_BASE + 0x644) + +#define ALWAYSON_SC_PERIPH_RST4_EN (ALWAYSON_CTRL_BASE + 0x6F0) +#define ALWAYSON_SC_PERIPH_RST4_DIS (ALWAYSON_CTRL_BASE + 0x6F4) + +#define ALWAYSON_SC_PERIPH_RST4_DIS_RESET_MCU_ECTR_N (1 << 0) +#define ALWAYSON_SC_PERIPH_RST4_DIS_RESET_MCU_SYS_N (1 << 1) +#define ALWAYSON_SC_PERIPH_RST4_DIS_RESET_MCU_POR_N (1 << 2) +#define ALWAYSON_SC_PERIPH_RST4_DIS_RESET_MCU_DAP_N (1 << 3) +#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_CM3_TIMER0_N (1 << 4) +#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_CM3_TIMER1_N (1 << 5) +#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_CM3_WDT0_N (1 << 6) +#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_CM3_WDT1_N (1 << 7) +#define ALWAYSON_SC_PERIPH_RST4_DIS_HRESET_IPC_S_N (1 << 8) +#define ALWAYSON_SC_PERIPH_RST4_DIS_HRESET_IPC_NS_N (1 << 9) +#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_EFUSEC_N (1 << 10) +#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_WDT0_N (1 << 12) +#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_WDT1_N (1 << 13) +#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_WDT2_N (1 << 14) +#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER0_N (1 << 15) +#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER1_N (1 << 16) +#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER2_N (1 << 17) +#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER3_N (1 << 18) +#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER4_N (1 << 19) +#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER5_N (1 << 20) +#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER6_N (1 << 21) +#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER7_N (1 << 22) +#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER8_N (1 << 23) +#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_UART0_N (1 << 24) +#define ALWAYSON_SC_PERIPH_RST4_DIS_RESET_RTC0_N (1 << 25) +#define ALWAYSON_SC_PERIPH_RST4_DIS_RESET_RTC1_N (1 << 26) +#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_PMUSSI_N (1 << 27) +#define ALWAYSON_SC_PERIPH_RST4_DIS_RESET_JTAG_AUTH_N (1 << 28) +#define ALWAYSON_SC_PERIPH_RST4_DIS_RESET_CS_DAPB_ON_N (1 << 29) +#define ALWAYSON_SC_PERIPH_RST4_DIS_MDM_SUBSYS_GLB (1 << 30) + +#define ALWAYSON_SC_PERIPH_RST4_STAT (ALWAYSON_CTRL_BASE + 0x6F8) + +#define ALWAYSON_SC_PERIPH_RST5_EN (ALWAYSON_CTRL_BASE + 0x6FC) +#define ALWAYSON_SC_PERIPH_RST5_DIS (ALWAYSON_CTRL_BASE + 0x700) +#define ALWAYSON_SC_PERIPH_RST5_STAT (ALWAYSON_CTRL_BASE + 0x704) + +#define ALWAYSON_SC_PW_CLK0_EN (ALWAYSON_CTRL_BASE + 0x800) +#define ALWAYSON_SC_PW_CLK0_DIS (ALWAYSON_CTRL_BASE + 0x804) +#define ALWAYSON_SC_PW_CLK0_STAT (ALWAYSON_CTRL_BASE + 0x808) + +#define ALWAYSON_SC_PW_RST0_EN (ALWAYSON_CTRL_BASE + 0x810) +#define ALWAYSON_SC_PW_RST0_DIS (ALWAYSON_CTRL_BASE + 0x814) +#define ALWAYSON_SC_PW_RST0_STAT0 (ALWAYSON_CTRL_BASE + 0x818) + +#define ALWAYSON_SC_PW_ISOEN0 (ALWAYSON_CTRL_BASE + 0x820) +#define ALWAYSON_SC_PW_ISODIS0 (ALWAYSON_CTRL_BASE + 0x824) +#define ALWAYSON_SC_PW_ISO_STAT0 (ALWAYSON_CTRL_BASE + 0x828) +#define ALWAYSON_SC_PW_MTCMOS_EN0 (ALWAYSON_CTRL_BASE + 0x830) +#define ALWAYSON_SC_PW_MTCMOS_DIS0 (ALWAYSON_CTRL_BASE + 0x834) +#define ALWAYSON_SC_PW_MTCMOS_STAT0 (ALWAYSON_CTRL_BASE + 0x838) +#define ALWAYSON_SC_PW_MTCMOS_ACK_STAT0 (ALWAYSON_CTRL_BASE + 0x83C) +#define ALWAYSON_SC_PW_MTCMOS_TIMEOUT_STAT0 (ALWAYSON_CTRL_BASE + 0x840) +#define ALWAYSON_SC_PW_STAT0 (ALWAYSON_CTRL_BASE + 0x850) +#define ALWAYSON_SC_PW_STAT1 (ALWAYSON_CTRL_BASE + 0x854) +#define ALWAYSON_SC_SYSTEST_STAT (ALWAYSON_CTRL_BASE + 0x880) +#define ALWAYSON_SC_SYSTEST_SLICER_CNT0 (ALWAYSON_CTRL_BASE + 0x890) +#define ALWAYSON_SC_SYSTEST_SLICER_CNT1 (ALWAYSON_CTRL_BASE + 0x894) +#define ALWAYSON_SC_PW_CTRL1 (ALWAYSON_CTRL_BASE + 0x8C8) +#define ALWAYSON_SC_PW_CTRL (ALWAYSON_CTRL_BASE + 0x8CC) +#define ALWAYSON_SC_MCPU_VOTEEN (ALWAYSON_CTRL_BASE + 0x8D0) +#define ALWAYSON_SC_MCPU_VOTEDIS (ALWAYSON_CTRL_BASE + 0x8D4) +#define ALWAYSON_SC_MCPU_VOTESTAT (ALWAYSON_CTRL_BASE + 0x8D8) +#define ALWAYSON_SC_MCPU_VOTE_MSK0 (ALWAYSON_CTRL_BASE + 0x8E0) +#define ALWAYSON_SC_MCPU_VOTE_MSK1 (ALWAYSON_CTRL_BASE + 0x8E4) +#define ALWAYSON_SC_MCPU_VOTESTAT0_MSK (ALWAYSON_CTRL_BASE + 0x8E8) +#define ALWAYSON_SC_MCPU_VOTESTAT1_MSK (ALWAYSON_CTRL_BASE + 0x8EC) +#define ALWAYSON_SC_PERI_VOTEEN (ALWAYSON_CTRL_BASE + 0x8F0) +#define ALWAYSON_SC_PERI_VOTEDIS (ALWAYSON_CTRL_BASE + 0x8F4) +#define ALWAYSON_SC_PERI_VOTESTAT (ALWAYSON_CTRL_BASE + 0x8F8) +#define ALWAYSON_SC_PERI_VOTE_MSK0 (ALWAYSON_CTRL_BASE + 0x900) +#define ALWAYSON_SC_PERI_VOTE_MSK1 (ALWAYSON_CTRL_BASE + 0x904) +#define ALWAYSON_SC_PERI_VOTESTAT0_MSK (ALWAYSON_CTRL_BASE + 0x908) +#define ALWAYSON_SC_PERI_VOTESTAT1_MSK (ALWAYSON_CTRL_BASE + 0x90C) +#define ALWAYSON_SC_ACPU_VOTEEN (ALWAYSON_CTRL_BASE + 0x910) +#define ALWAYSON_SC_ACPU_VOTEDIS (ALWAYSON_CTRL_BASE + 0x914) +#define ALWAYSON_SC_ACPU_VOTESTAT (ALWAYSON_CTRL_BASE + 0x918) +#define ALWAYSON_SC_ACPU_VOTE_MSK0 (ALWAYSON_CTRL_BASE + 0x920) +#define ALWAYSON_SC_ACPU_VOTE_MSK1 (ALWAYSON_CTRL_BASE + 0x924) +#define ALWAYSON_SC_ACPU_VOTESTAT0_MSK (ALWAYSON_CTRL_BASE + 0x928) +#define ALWAYSON_SC_ACPU_VOTESTAT1_MSK (ALWAYSON_CTRL_BASE + 0x92C) +#define ALWAYSON_SC_MCU_VOTEEN (ALWAYSON_CTRL_BASE + 0x930) +#define ALWAYSON_SC_MCU_VOTEDIS (ALWAYSON_CTRL_BASE + 0x934) +#define ALWAYSON_SC_MCU_VOTESTAT (ALWAYSON_CTRL_BASE + 0x938) +#define ALWAYSON_SC_MCU_VOTE_MSK0 (ALWAYSON_CTRL_BASE + 0x940) +#define ALWAYSON_SC_MCU_VOTE_MSK1 (ALWAYSON_CTRL_BASE + 0x944) +#define ALWAYSON_SC_MCU_VOTESTAT0_MSK (ALWAYSON_CTRL_BASE + 0x948) +#define ALWAYSON_SC_MCU_VOTESTAT1_MSK (ALWAYSON_CTRL_BASE + 0x94C) +#define ALWAYSON_SC_MCU_VOTE1EN (ALWAYSON_CTRL_BASE + 0x960) +#define ALWAYSON_SC_MCU_VOTE1DIS (ALWAYSON_CTRL_BASE + 0x964) +#define ALWAYSON_SC_MCU_VOTE1STAT (ALWAYSON_CTRL_BASE + 0x968) +#define ALWAYSON_SC_MCU_VOTE1_MSK0 (ALWAYSON_CTRL_BASE + 0x970) +#define ALWAYSON_SC_MCU_VOTE1_MSK1 (ALWAYSON_CTRL_BASE + 0x974) +#define ALWAYSON_SC_MCU_VOTE1STAT0_MSK (ALWAYSON_CTRL_BASE + 0x978) +#define ALWAYSON_SC_MCU_VOTE1STAT1_MSK (ALWAYSON_CTRL_BASE + 0x97C) +#define ALWAYSON_SC_MCU_VOTE2EN (ALWAYSON_CTRL_BASE + 0x980) +#define ALWAYSON_SC_MCU_VOTE2DIS (ALWAYSON_CTRL_BASE + 0x984) +#define ALWAYSON_SC_MCU_VOTE2STAT (ALWAYSON_CTRL_BASE + 0x988) +#define ALWAYSON_SC_MCU_VOTE2_MSK0 (ALWAYSON_CTRL_BASE + 0x990) +#define ALWAYSON_SC_MCU_VOTE2_MSK1 (ALWAYSON_CTRL_BASE + 0x994) +#define ALWAYSON_SC_MCU_VOTE2STAT0_MSK (ALWAYSON_CTRL_BASE + 0x998) +#define ALWAYSON_SC_MCU_VOTE2STAT1_MSK (ALWAYSON_CTRL_BASE + 0x99C) +#define ALWAYSON_SC_VOTE_CTRL (ALWAYSON_CTRL_BASE + 0x9A0) +#define ALWAYSON_SC_VOTE_STAT (ALWAYSON_CTRL_BASE + 0x9A4) +#define ALWAYSON_SC_ECONUM (ALWAYSON_CTRL_BASE + 0xF00) +#define ALWAYSON_SCCHIPID (ALWAYSON_CTRL_BASE + 0xF10) +#define ALWAYSON_SCSOCID (ALWAYSON_CTRL_BASE + 0xF1C) +#define ALWAYSON_SC_SOC_FPGA_RTL_DEF (ALWAYSON_CTRL_BASE + 0xFE0) +#define ALWAYSON_SC_SOC_FPGA_PR_DEF (ALWAYSON_CTRL_BASE + 0xFE4) +#define ALWAYSON_SC_SOC_FPGA_RES_DEF0 (ALWAYSON_CTRL_BASE + 0xFE8) +#define ALWAYSON_SC_SOC_FPGA_RES_DEF1 (ALWAYSON_CTRL_BASE + 0xFEC) +#define ALWAYSON_SC_XTAL_CTRL0 (ALWAYSON_CTRL_BASE + 0x102) +#define ALWAYSON_SC_XTAL_CTRL1 (ALWAYSON_CTRL_BASE + 0x102) +#define ALWAYSON_SC_XTAL_CTRL3 (ALWAYSON_CTRL_BASE + 0x103) +#define ALWAYSON_SC_XTAL_CTRL5 (ALWAYSON_CTRL_BASE + 0x103) +#define ALWAYSON_SC_XTAL_STAT0 (ALWAYSON_CTRL_BASE + 0x106) +#define ALWAYSON_SC_XTAL_STAT1 (ALWAYSON_CTRL_BASE + 0x107) +#define ALWAYSON_SC_EFUSE_CHIPID0 (ALWAYSON_CTRL_BASE + 0x108) +#define ALWAYSON_SC_EFUSE_CHIPID1 (ALWAYSON_CTRL_BASE + 0x108) +#define ALWAYSON_SC_EFUSE_SYS_CTRL (ALWAYSON_CTRL_BASE + 0x108) +#define ALWAYSON_SC_DEBUG_CTRL1 (ALWAYSON_CTRL_BASE + 0x128) +#define ALWAYSON_SC_DBG_STAT (ALWAYSON_CTRL_BASE + 0x12B) +#define ALWAYSON_SC_ARM_DBG_KEY0 (ALWAYSON_CTRL_BASE + 0x12B) +#define ALWAYSON_SC_RESERVED31 (ALWAYSON_CTRL_BASE + 0x13A) +#define ALWAYSON_SC_RESERVED32 (ALWAYSON_CTRL_BASE + 0x13A) +#define ALWAYSON_SC_RESERVED33 (ALWAYSON_CTRL_BASE + 0x13A) +#define ALWAYSON_SC_RESERVED34 (ALWAYSON_CTRL_BASE + 0x13A) +#define ALWAYSON_SC_RESERVED35 (ALWAYSON_CTRL_BASE + 0x13B) +#define ALWAYSON_SC_RESERVED36 (ALWAYSON_CTRL_BASE + 0x13B) +#define ALWAYSON_SC_RESERVED37 (ALWAYSON_CTRL_BASE + 0x13B) +#define ALWAYSON_SC_RESERVED38 (ALWAYSON_CTRL_BASE + 0x13B) +#define ALWAYSON_SC_ALWAYSON_SYS_CTRL0 (ALWAYSON_CTRL_BASE + 0x148) +#define ALWAYSON_SC_ALWAYSON_SYS_CTRL1 (ALWAYSON_CTRL_BASE + 0x148) +#define ALWAYSON_SC_ALWAYSON_SYS_CTRL2 (ALWAYSON_CTRL_BASE + 0x148) +#define ALWAYSON_SC_ALWAYSON_SYS_CTRL3 (ALWAYSON_CTRL_BASE + 0x148) +#define ALWAYSON_SC_ALWAYSON_SYS_CTRL10 (ALWAYSON_CTRL_BASE + 0x14A) +#define ALWAYSON_SC_ALWAYSON_SYS_CTRL11 (ALWAYSON_CTRL_BASE + 0x14A) +#define ALWAYSON_SC_ALWAYSON_SYS_STAT0 (ALWAYSON_CTRL_BASE + 0x14C) +#define ALWAYSON_SC_ALWAYSON_SYS_STAT1 (ALWAYSON_CTRL_BASE + 0x14C) +#define ALWAYSON_SC_ALWAYSON_SYS_STAT2 (ALWAYSON_CTRL_BASE + 0x14C) +#define ALWAYSON_SC_ALWAYSON_SYS_STAT3 (ALWAYSON_CTRL_BASE + 0x14C) +#define ALWAYSON_SC_PWUP_TIME0 (ALWAYSON_CTRL_BASE + 0x188) +#define ALWAYSON_SC_PWUP_TIME1 (ALWAYSON_CTRL_BASE + 0x188) +#define ALWAYSON_SC_PWUP_TIME2 (ALWAYSON_CTRL_BASE + 0x188) +#define ALWAYSON_SC_PWUP_TIME3 (ALWAYSON_CTRL_BASE + 0x188) +#define ALWAYSON_SC_PWUP_TIME4 (ALWAYSON_CTRL_BASE + 0x189) +#define ALWAYSON_SC_PWUP_TIME5 (ALWAYSON_CTRL_BASE + 0x189) +#define ALWAYSON_SC_PWUP_TIME6 (ALWAYSON_CTRL_BASE + 0x189) +#define ALWAYSON_SC_PWUP_TIME7 (ALWAYSON_CTRL_BASE + 0x189) +#define ALWAYSON_SC_SECURITY_CTRL1 (ALWAYSON_CTRL_BASE + 0x1C0) + +#define PCLK_TIMER1 (1 << 16) +#define PCLK_TIMER0 (1 << 15) + +#endif /* __HI6220_ALWAYSON_H__ */
This pmic is used on the 96boards consumer edition HiKey board.
Signed-off-by: Peter Griffin peter.griffin@linaro.org --- arch/arm/include/asm/arch-armv8/hi6553.h | 75 ++++++++++++++++++++++++++++++++ 1 file changed, 75 insertions(+) create mode 100644 arch/arm/include/asm/arch-armv8/hi6553.h
diff --git a/arch/arm/include/asm/arch-armv8/hi6553.h b/arch/arm/include/asm/arch-armv8/hi6553.h new file mode 100644 index 0000000..d0770e1 --- /dev/null +++ b/arch/arm/include/asm/arch-armv8/hi6553.h @@ -0,0 +1,75 @@ +/* + * (C) Copyright 2015 Linaro + * Peter Griffin peter.griffin@linaro.org + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __HI6553_PMIC_H__ +#define __HI6553_PMIC_H__ + +#define HI6553_DISABLE6_XO_CLK 0x036 + +#define HI6553_DISABLE6_XO_CLK_BB (1 << 0) +#define HI6553_DISABLE6_XO_CLK_CONN (1 << 1) +#define HI6553_DISABLE6_XO_CLK_NFC (1 << 2) +#define HI6553_DISABLE6_XO_CLK_RF1 (1 << 3) +#define HI6553_DISABLE6_XO_CLK_RF2 (1 << 4) + +#define HI6553_VERSION_REG 0x000 +#define HI6553_ENABLE2_LDO1_8 0x029 +#define HI6553_DISABLE2_LDO1_8 0x02a +#define HI6553_ONOFF_STATUS2_LDO1_8 0x02b +#define HI6553_ENABLE3_LDO9_16 0x02c +#define HI6553_DISABLE3_LDO9_16 0x02d +#define HI6553_ONOFF_STATUS3_LDO9_16 0x02e +#define HI6553_PERI_EN_MARK 0x040 +#define HI6553_BUCK2_REG1 0x04a +#define HI6553_BUCK2_REG5 0x04e +#define HI6553_BUCK2_REG6 0x04f +#define HI6553_BUCK3_REG3 0x054 +#define HI6553_BUCK3_REG5 0x056 +#define HI6553_BUCK3_REG6 0x057 +#define HI6553_BUCK4_REG2 0x05b +#define HI6553_BUCK4_REG5 0x05e +#define HI6553_BUCK4_REG6 0x05f +#define HI6553_CLK_TOP0 0x063 +#define HI6553_CLK_TOP3 0x066 +#define HI6553_CLK_TOP4 0x067 +#define HI6553_VSET_BUCK2_ADJ 0x06d +#define HI6553_VSET_BUCK3_ADJ 0x06e +#define HI6553_LDO7_REG_ADJ 0x078 +#define HI6553_LDO10_REG_ADJ 0x07b +#define HI6553_LDO19_REG_ADJ 0x084 +#define HI6553_LDO20_REG_ADJ 0x085 +#define HI6553_DR_LED_CTRL 0x098 +#define HI6553_DR_OUT_CTRL 0x099 +#define HI6553_DR3_ISET 0x09a +#define HI6553_DR3_START_DEL 0x09b +#define HI6553_DR4_ISET 0x09c +#define HI6553_DR4_START_DEL 0x09d +#define HI6553_DR345_TIM_CONF0 0x0a0 +#define HI6553_NP_REG_ADJ1 0x0be +#define HI6553_NP_REG_CHG 0x0c0 +#define HI6553_BUCK01_CTRL2 0x0d9 +#define HI6553_BUCK0_CTRL1 0x0dd +#define HI6553_BUCK0_CTRL5 0x0e1 +#define HI6553_BUCK0_CTRL7 0x0e3 +#define HI6553_BUCK1_CTRL1 0x0e8 +#define HI6553_BUCK1_CTRL5 0x0ec +#define HI6553_BUCK1_CTRL7 0x0ef +#define HI6553_CLK19M2_600_586_EN 0x0fe + +#define HI6553_LED_START_DELAY_TIME 0x00 +#define HI6553_LED_ELEC_VALUE 0x07 +#define HI6553_LED_LIGHT_TIME 0xf0 +#define HI6553_LED_GREEN_ENABLE (1 << 1) +#define HI6553_LED_OUT_CTRL 0x00 + +#define HI6553_PMU_V300 0x30 +#define HI6553_PMU_V310 0x31 + +unsigned char hi6553_read_8(unsigned int offset); +void hi6553_write_8(unsigned int offset, unsigned char value); + +#endif /* __HI6553_PMIC_H__ */
This patch adds the glue code for hi6220 SoC which has 2x synopsis dw_mmc controllers. This will be used by the hikey board support in subsequent patches.
Signed-off-by: Peter Griffin peter.griffin@linaro.org --- arch/arm/include/asm/arch-armv8/dwmmc.h | 8 +++++ drivers/mmc/Makefile | 1 + drivers/mmc/hi6220_dw_mmc.c | 63 +++++++++++++++++++++++++++++++++ 3 files changed, 72 insertions(+) create mode 100644 arch/arm/include/asm/arch-armv8/dwmmc.h create mode 100644 drivers/mmc/hi6220_dw_mmc.c
diff --git a/arch/arm/include/asm/arch-armv8/dwmmc.h b/arch/arm/include/asm/arch-armv8/dwmmc.h new file mode 100644 index 0000000..c747383 --- /dev/null +++ b/arch/arm/include/asm/arch-armv8/dwmmc.h @@ -0,0 +1,8 @@ +/* + * (C) Copyright 2015 Linaro + * Peter Griffin peter.griffin@linaro.org + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +int hi6220_dwmci_add_port(int index, u32 regbase, int bus_width); diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index ed73687..81a1a8f 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -11,6 +11,7 @@ obj-$(CONFIG_BFIN_SDH) += bfin_sdh.o obj-$(CONFIG_DAVINCI_MMC) += davinci_mmc.o obj-$(CONFIG_DWMMC) += dw_mmc.o obj-$(CONFIG_EXYNOS_DWMMC) += exynos_dw_mmc.o +obj-$(CONFIG_HIKEY_DWMMC) += hi6220_dw_mmc.o obj-$(CONFIG_FSL_ESDHC) += fsl_esdhc.o obj-$(CONFIG_FTSDC010) += ftsdc010_mci.o obj-$(CONFIG_FTSDC021) += ftsdc021_sdhci.o diff --git a/drivers/mmc/hi6220_dw_mmc.c b/drivers/mmc/hi6220_dw_mmc.c new file mode 100644 index 0000000..a3880a3 --- /dev/null +++ b/drivers/mmc/hi6220_dw_mmc.c @@ -0,0 +1,63 @@ +/* + * (C) Copyright 2015 Linaro + * peter.griffin peter.griffin@linaro.org + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dwmmc.h> +#include <malloc.h> +#include <asm-generic/errno.h> + +#define DWMMC_MAX_CH_NUM 4 + +/* +#define DWMMC_MAX_FREQ 52000000 +#define DWMMC_MIN_FREQ 400000 +*/ + +/*TODO we should probably use the frequencies above, but ATF uses + the ones below so stick with that for the moment */ +#define DWMMC_MAX_FREQ 50000000 +#define DWMMC_MIN_FREQ 378000 + +/* Source clock is configured to 100Mhz by ATF bl1*/ +#define MMC0_DEFAULT_FREQ 100000000 + +static int hi6220_dwmci_core_init(struct dwmci_host *host, int index) +{ + host->name = "HiKey DWMMC"; + + host->dev_index = index; + + /* Add the mmc channel to be registered with mmc core */ + if (add_dwmci(host, DWMMC_MAX_FREQ, DWMMC_MIN_FREQ)) { + printf("DWMMC%d registration failed\n", index); + return -1; + } + return 0; +} + +/* + * This function adds the mmc channel to be registered with mmc core. + * index - mmc channel number. + * regbase - register base address of mmc channel specified in 'index'. + * bus_width - operating bus width of mmc channel specified in 'index'. + */ +int hi6220_dwmci_add_port(int index, u32 regbase, int bus_width) +{ + struct dwmci_host *host = NULL; + + host = malloc(sizeof(struct dwmci_host)); + if (!host) { + error("dwmci_host malloc fail!\n"); + return -ENOMEM; + } + + host->ioaddr = (void *)regbase; + host->buswidth = bus_width; + host->bus_hz = MMC0_DEFAULT_FREQ; + + return hi6220_dwmci_core_init(host, index); +}
HiKey is the first 96boards consumer edition compliant board. It features a hi6220 SoC which has eight ARM A53 cpu's.
This initial port adds support for: - 1) Serial 2) eMMC / sd card 3) USB 4) GPIO
It has been tested with Arm Trusted Firmware running u-boot as the BL33 executable.
Notes:
eMMC has been tested with basic reading of eMMC partition intto DDR. I have not tested writing / erasing. I suspect due to lack of clock control it won't be running in the most performant high speed mode.
SD card slot has been tested for reading and booting kernels into DDR. It is also currently used for saving the u-boot enviroment.
USB has been tested with ASIX networking adapter to tftpboot kernels into DDR. USB mass storage device enumeration doesn't currently work for an unkown reason.
GPIO has been tested using gpio toggle GPIO4_1-3 to flash LEDs.
Basic SoC datasheet can be found here: - https://github.com/96boards/documentation/blob/master/hikey/ Hi6220V100_Multi-Mode_Application_Processor_Function_Description.pdf
Board schematic can be found here: - https://github.com/96boards/documentation/blob/master/hikey/ 96Boards-Hikey-Rev-A1.pdf
Signed-off-by: Peter Griffin peter.griffin@linaro.org --- arch/arm/Kconfig | 5 + board/96boards/hikey64/Kconfig | 12 ++ board/96boards/hikey64/Makefile | 8 + board/96boards/hikey64/hikey.c | 439 ++++++++++++++++++++++++++++++++++++++++ configs/hikey_aemv8a_defconfig | 5 + include/configs/hikey_aemv8a.h | 187 +++++++++++++++++ 6 files changed, 656 insertions(+) create mode 100644 board/96boards/hikey64/Kconfig create mode 100644 board/96boards/hikey64/Makefile create mode 100644 board/96boards/hikey64/hikey.c create mode 100644 configs/hikey_aemv8a_defconfig create mode 100644 include/configs/hikey_aemv8a.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 7ed0e20..0b6de5d 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -656,6 +656,10 @@ config TARGET_LS2085A_SIMU select ARM64 select ARMV8_MULTIENTRY
+config TARGET_96BOARDS_HIKEY + bool "Support HiKey 96boards Consumer Edition Platform" + select ARM64 + config TARGET_LS1021AQDS bool "Support ls1021aqds" select CPU_V7 @@ -787,6 +791,7 @@ source "board/armadeus/apf27/Kconfig" source "board/armltd/integrator/Kconfig" source "board/armltd/vexpress/Kconfig" source "board/armltd/vexpress64/Kconfig" +source "board/96boards/hikey64/Kconfig" source "board/bachmann/ot1200/Kconfig" source "board/balloon3/Kconfig" source "board/barco/platinum/Kconfig" diff --git a/board/96boards/hikey64/Kconfig b/board/96boards/hikey64/Kconfig new file mode 100644 index 0000000..eb1709b --- /dev/null +++ b/board/96boards/hikey64/Kconfig @@ -0,0 +1,12 @@ +if TARGET_96BOARDS_HIKEY + +config SYS_BOARD + default "hikey64" + +config SYS_VENDOR + default "96boards" + +config SYS_CONFIG_NAME + default "hikey_aemv8a" + +endif diff --git a/board/96boards/hikey64/Makefile b/board/96boards/hikey64/Makefile new file mode 100644 index 0000000..d4ec8c7 --- /dev/null +++ b/board/96boards/hikey64/Makefile @@ -0,0 +1,8 @@ +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := hikey.o diff --git a/board/96boards/hikey64/hikey.c b/board/96boards/hikey64/hikey.c new file mode 100644 index 0000000..91e8e6b --- /dev/null +++ b/board/96boards/hikey64/hikey.c @@ -0,0 +1,439 @@ +/* + * (C) Copyright 2015 Linaro + * Peter Griffin peter.griffin@linaro.org + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> +#include <dm.h> +#include <malloc.h> +#include <errno.h> +#include <netdev.h> +#include <asm/io.h> +#include <asm-generic/gpio.h> +#include <asm/arch/gpio.h> +#include <asm/arch/dwmmc.h> +#include <asm/arch/hi6220.h> +#include <asm/arch/hi6553.h> + +#ifdef CONFIG_DM_GPIO +static const struct hikey_gpio_platdata hi6220_gpio[] = { + { 0, HI6220_GPIO0_BASE}, + { 1, HI6220_GPIO1_BASE}, + { 2, HI6220_GPIO2_BASE}, + { 3, HI6220_GPIO3_BASE}, + { 4, HI6220_GPIO4_BASE}, + { 5, HI6220_GPIO5_BASE}, + { 6, HI6220_GPIO6_BASE}, + { 7, HI6220_GPIO7_BASE}, + { 8, HI6220_GPIO8_BASE}, + { 9, HI6220_GPIO9_BASE}, + { 10, HI6220_GPIO10_BASE}, + { 11, HI6220_GPIO11_BASE}, + { 12, HI6220_GPIO12_BASE}, + { 13, HI6220_GPIO13_BASE}, + { 14, HI6220_GPIO14_BASE}, + { 15, HI6220_GPIO15_BASE}, + { 16, HI6220_GPIO16_BASE}, + { 17, HI6220_GPIO17_BASE}, + { 18, HI6220_GPIO18_BASE}, + { 19, HI6220_GPIO19_BASE}, + +}; + +U_BOOT_DEVICES(hi6220_gpios) = { + { "gpio_hi6220", &hi6220_gpio[0] }, + { "gpio_hi6220", &hi6220_gpio[1] }, + { "gpio_hi6220", &hi6220_gpio[2] }, + { "gpio_hi6220", &hi6220_gpio[3] }, + { "gpio_hi6220", &hi6220_gpio[4] }, + { "gpio_hi6220", &hi6220_gpio[5] }, + { "gpio_hi6220", &hi6220_gpio[6] }, + { "gpio_hi6220", &hi6220_gpio[7] }, + { "gpio_hi6220", &hi6220_gpio[8] }, + { "gpio_hi6220", &hi6220_gpio[9] }, + { "gpio_hi6220", &hi6220_gpio[10] }, + { "gpio_hi6220", &hi6220_gpio[11] }, + { "gpio_hi6220", &hi6220_gpio[12] }, + { "gpio_hi6220", &hi6220_gpio[13] }, + { "gpio_hi6220", &hi6220_gpio[14] }, + { "gpio_hi6220", &hi6220_gpio[15] }, + { "gpio_hi6220", &hi6220_gpio[16] }, + { "gpio_hi6220", &hi6220_gpio[17] }, + { "gpio_hi6220", &hi6220_gpio[18] }, + { "gpio_hi6220", &hi6220_gpio[19] }, +}; +#endif + +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_SHOW_BOOT_PROGRESS) +void show_boot_progress(int progress) +{ + printf("Boot reached stage %d\n", progress); +} +#endif + +static inline void delay(ulong loops) +{ + __asm__ volatile ("1:\n" + "subs %0, %1, #1\n" + "bne 1b" : "=r" (loops) : "0" (loops)); +} + + +#define EYE_PATTERN 0x70533483 + +static void init_usb_and_picophy(void) +{ + unsigned int data; + + /* enable USB clock */ + writel(PERI_CLK0_USBOTG, PERI_SC_PERIPH_CLK0_EN); + do { + data = readl(PERI_SC_PERIPH_CLK0_STAT); + } while ((data & PERI_CLK0_USBOTG) == 0); + + /* take usb IPs out of reset */ + writel(PERI_RST0_USBOTG_BUS | PERI_RST0_POR_PICOPHY | + PERI_RST0_USBOTG | PERI_RST0_USBOTG_32K, + PERI_SC_PERIPH_RST0_DIS); + do { + data = readl(PERI_SC_PERIPH_RST0_STAT); + data &= PERI_RST0_USBOTG_BUS | PERI_RST0_POR_PICOPHY | + PERI_RST0_USBOTG | PERI_RST0_USBOTG_32K; + } while (data); + + /*CTRL 5*/ + data = readl(PERI_SC_PERIPH_CTRL5); + data &= ~PERI_CTRL5_PICOPHY_BC_MODE; + data |= PERI_CTRL5_USBOTG_RES_SEL | PERI_CTRL5_PICOPHY_ACAENB; + data |= 0x300; + writel(data, PERI_SC_PERIPH_CTRL5); + + /*CTRL 4*/ + + /* configure USB PHY */ + data = readl(PERI_SC_PERIPH_CTRL4); + + /* make PHY out of low power mode */ + data &= ~PERI_CTRL4_PICO_SIDDQ; + data &= ~PERI_CTRL4_PICO_OGDISABLE; + data |= PERI_CTRL4_PICO_VBUSVLDEXTSEL | PERI_CTRL4_PICO_VBUSVLDEXT; + writel(data, PERI_SC_PERIPH_CTRL4); + + writel(EYE_PATTERN, PERI_SC_PERIPH_CTRL8); + + delay(20000); +} + +static int sd_card_detect(void) +{ + int ret; + + /* configure GPIO8 as nopull */ + writel(0, 0xf8001830); + + gpio_request(8, "SD CD"); + + gpio_direction_input(8); + ret = gpio_get_value(8); + + if (!ret) { + printf("%s: SD card present\n", __func__); + return 1; + } + + printf("%s: SD card not present\n", __func__); + return 0; +} + +static void mmc1_setup_pinmux(void) +{ + /* switch pinmux to SD */ + writel(0, 0xf701000c); + writel(0, 0xf7010010); + writel(0, 0xf7010014); + writel(0, 0xf7010018); + writel(0, 0xf701001c); + writel(0, 0xf7010020); + + /* input, 16mA or 12mA */ + writel(0x64, 0xf701080c); + writel(0x54, 0xf7010810); + writel(0x54, 0xf7010814); + writel(0x54, 0xf7010818); + writel(0x54, 0xf701081c); + writel(0x54, 0xf7010820); + + sd_card_detect(); +} + +static void mmc1_init_pll(void) +{ + uint32_t data; + + /* select SYSPLL as the source of MMC1 */ + /* select SYSPLL as the source of MUX1 (SC_CLK_SEL0) */ + writel(1 << 11 | 1 << 27, PERI_SC_CLK0_SEL); + do { + data = readl(PERI_SC_CLK0_SEL); + } while (!(data & (1 << 11))); + + /* select MUX1 as the source of MUX2 (SC_CLK_SEL0) */ + writel(1 << 30, PERI_SC_CLK0_SEL); + do { + data = readl(PERI_SC_CLK0_SEL); + } while (data & (1 << 14)); + + writel((1 << 1), PERI_SC_PERIPH_CLK0_EN); + do { + data = readl(PERI_SC_PERIPH_CLK0_STAT); + } while (!(data & (1 << 1))); + + data = readl(PERI_SC_PERIPH_CLK12_EN); + data |= 1 << 2; + writel(data, PERI_SC_PERIPH_CLK12_EN); + + do { + /* 1.2GHz / 50 = 24MHz */ + writel(0x31 | (1 << 7), PERI_SC_CLKCFG8BIT2); + data = readl(PERI_SC_CLKCFG8BIT2); + } while ((data & 0x31) != 0x31); +} + +static void mmc1_reset_clk(void) +{ + unsigned int data; + + /* disable mmc1 bus clock */ + writel(PERI_CLK0_MMC1, PERI_SC_PERIPH_CLK0_DIS); + do { + data = readl(PERI_SC_PERIPH_CLK0_STAT); + } while (data & PERI_CLK0_MMC1); + + /* enable mmc1 bus clock */ + writel(PERI_CLK0_MMC1, PERI_SC_PERIPH_CLK0_EN); + do { + data = readl(PERI_SC_PERIPH_CLK0_STAT); + } while (!(data & PERI_CLK0_MMC1)); + + /* reset mmc1 clock domain */ + writel(PERI_RST0_MMC1, PERI_SC_PERIPH_RST0_EN); + + /* bypass mmc1 clock phase */ + data = readl(PERI_SC_PERIPH_CTRL2); + data |= 3 << 2; + writel(data, PERI_SC_PERIPH_CTRL2); + + /* disable low power */ + data = readl(PERI_SC_PERIPH_CTRL13); + data |= 1 << 4; + writel(data, PERI_SC_PERIPH_CTRL13); + do { + data = readl(PERI_SC_PERIPH_RST0_STAT); + } while (!(data & PERI_RST0_MMC1)); + + /* unreset mmc0 clock domain */ + writel(PERI_RST0_MMC1, PERI_SC_PERIPH_RST0_DIS); + do { + data = readl(PERI_SC_PERIPH_RST0_STAT); + } while (data & PERI_RST0_MMC1); +} + +/* PMU SSI is the IP that maps the external PMU hi6553 registers as IO */ +static void hi6220_pmussi_init(void) +{ + uint32_t data; + + /* Take PMUSSI out of reset */ + writel(ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_PMUSSI_N, + ALWAYSON_SC_PERIPH_RST4_DIS); + do { + data = readl(ALWAYSON_SC_PERIPH_RST4_STAT); + } while (data & ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_PMUSSI_N); + + /* set PMU SSI clock latency for read operation */ + data = readl(ALWAYSON_SC_MCU_SUBSYS_CTRL3); + data &= ~ALWAYSON_SC_MCU_SUBSYS_CTRL3_RCLK_MASK; + data |= ALWAYSON_SC_MCU_SUBSYS_CTRL3_RCLK_3; + writel(data, ALWAYSON_SC_MCU_SUBSYS_CTRL3); + + /* enable PMUSSI clock */ + data = ALWAYSON_SC_PERIPH_CLK5_EN_PCLK_PMUSSI_CCPU | + ALWAYSON_SC_PERIPH_CLK5_EN_PCLK_PMUSSI_MCU; + writel(data, ALWAYSON_SC_PERIPH_CLK5_EN); + data = ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_PMUSSI; + writel(data, ALWAYSON_SC_PERIPH_CLK4_EN); + + /* Output high to PMIC on PWR_HOLD_GPIO0_0 */ + gpio_request(0, "PWR_HOLD_GPIO0_0"); + gpio_direction_output(0, 1); +} + +uint8_t hi6553_readb(unsigned int offset) +{ + return readb((u8 *)(unsigned long)HI6220_PMUSSI_BASE + (offset << 2)); +} + +void hi6553_writeb(unsigned int offset, uint8_t value) +{ + writeb(value, (u8 *)(unsigned long)HI6220_PMUSSI_BASE + (offset << 2)); +} + +static void hikey_hi6553_init(void) +{ + int data; + + hi6553_writeb(HI6553_PERI_EN_MARK, 0x1e); + hi6553_writeb(HI6553_NP_REG_ADJ1, 0); + data = HI6553_DISABLE6_XO_CLK_CONN | HI6553_DISABLE6_XO_CLK_NFC | + HI6553_DISABLE6_XO_CLK_RF1 | HI6553_DISABLE6_XO_CLK_RF2; + hi6553_writeb(HI6553_DISABLE6_XO_CLK, data); + + /* configure BUCK0 & BUCK1 */ + hi6553_writeb(HI6553_BUCK01_CTRL2, 0x5e); + hi6553_writeb(HI6553_BUCK0_CTRL7, 0x10); + hi6553_writeb(HI6553_BUCK1_CTRL7, 0x10); + hi6553_writeb(HI6553_BUCK0_CTRL5, 0x1e); + hi6553_writeb(HI6553_BUCK1_CTRL5, 0x1e); + hi6553_writeb(HI6553_BUCK0_CTRL1, 0xfc); + hi6553_writeb(HI6553_BUCK1_CTRL1, 0xfc); + + /* configure BUCK2 */ + hi6553_writeb(HI6553_BUCK2_REG1, 0x4f); + hi6553_writeb(HI6553_BUCK2_REG5, 0x99); + hi6553_writeb(HI6553_BUCK2_REG6, 0x45); + mdelay(1); + hi6553_writeb(HI6553_VSET_BUCK2_ADJ, 0x22); + mdelay(1); + + /* configure BUCK3 */ + hi6553_writeb(HI6553_BUCK3_REG3, 0x02); + hi6553_writeb(HI6553_BUCK3_REG5, 0x99); + hi6553_writeb(HI6553_BUCK3_REG6, 0x41); + hi6553_writeb(HI6553_VSET_BUCK3_ADJ, 0x02); + mdelay(1); + + /* configure BUCK4 */ + hi6553_writeb(HI6553_BUCK4_REG2, 0x9a); + hi6553_writeb(HI6553_BUCK4_REG5, 0x99); + hi6553_writeb(HI6553_BUCK4_REG6, 0x45); + + /* configure LDO20 */ + hi6553_writeb(HI6553_LDO20_REG_ADJ, 0x50); + + hi6553_writeb(HI6553_NP_REG_CHG, 0x0f); + hi6553_writeb(HI6553_CLK_TOP0, 0x06); + hi6553_writeb(HI6553_CLK_TOP3, 0xc0); + hi6553_writeb(HI6553_CLK_TOP4, 0x00); + + /* configure LDO7 & LDO10 for SD slot */ + data = hi6553_readb(HI6553_LDO7_REG_ADJ); + data = (data & 0xf8) | 0x2; + hi6553_writeb(HI6553_LDO7_REG_ADJ, data); + mdelay(5); + /* enable LDO7 */ + hi6553_writeb(HI6553_ENABLE2_LDO1_8, 1 << 6); + mdelay(5); + data = hi6553_readb(HI6553_LDO10_REG_ADJ); + data = (data & 0xf8) | 0x5; + hi6553_writeb(HI6553_LDO10_REG_ADJ, data); + mdelay(5); + /* enable LDO10 */ + hi6553_writeb(HI6553_ENABLE3_LDO9_16, 1 << 1); + mdelay(5); + + /* select 32.764KHz */ + hi6553_writeb(HI6553_CLK19M2_600_586_EN, 0x01); +} + +/* + * Routine: misc_init_r + * Description: A basic misc_init_r + */ +int __weak misc_init_r(void) +{ + init_usb_and_picophy(); + + return 0; +} + +int board_init(void) +{ + gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; + gd->flags = 0; + + icache_enable(); + + return 0; +} + +#ifdef CONFIG_GENERIC_MMC + +static int init_dwmmc(void) +{ + int ret; + +#ifdef CONFIG_DWMMC + + + /* mmc0 pinmux and clocks are already configured by ATF */ + ret = hi6220_dwmci_add_port(0, HI6220_MMC0_BASE, 8); + + if (ret) + printf("%s: Error adding eMMC port\n", __func__); + + /* take mmc1 (sd slot) out of reset, configure clocks and pinmuxing */ + + mmc1_init_pll(); + mmc1_reset_clk(); + mmc1_setup_pinmux(); + + ret |= hi6220_dwmci_add_port(1, HI6220_MMC1_BASE, 4); + + if (ret) + printf("%s: Error adding SD port\n", __func__); +#endif + return ret; +} + +int board_mmc_init(bd_t *bis) +{ + int ret; + + /* init the pmussi ip */ + hi6220_pmussi_init(); + + /* init the hi6553 pmic */ + hikey_hi6553_init(); + + /* add the eMMC and sd ports */ + ret = init_dwmmc(); + + if (ret) + debug("init_dwmmc failed\n"); + + return ret; +} +#endif + +int dram_init(void) +{ + gd->ram_size = + get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, PHYS_SDRAM_1_SIZE); + return 0; +} + +void dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = + get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); +} + +/* Use the Watchdog to cause reset */ +void reset_cpu(ulong addr) +{ + /* TODO program the watchdog */ +} diff --git a/configs/hikey_aemv8a_defconfig b/configs/hikey_aemv8a_defconfig new file mode 100644 index 0000000..3bbb2c5 --- /dev/null +++ b/configs/hikey_aemv8a_defconfig @@ -0,0 +1,5 @@ +# 96boards HiKey +CONFIG_ARM=y +CONFIG_TARGET_96BOARDS_HIKEY=y +CONFIG_DEFAULT_DEVICE_TREE="hikey" +CONFIG_SHOW_BOOT_PROGRESS=y diff --git a/include/configs/hikey_aemv8a.h b/include/configs/hikey_aemv8a.h new file mode 100644 index 0000000..7c0012f --- /dev/null +++ b/include/configs/hikey_aemv8a.h @@ -0,0 +1,187 @@ +/* + * (C) Copyright 2015 Linaro + * + * Peter Griffin peter.griffin@linaro.org + * + * Configuration for HiKey 96boards CE. Parts were derived from other ARM + * configurations. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __HIKEY_AEMV8A_H +#define __HIKEY_AEMV8A_H + +/* We use generic board for hikey */ +#define CONFIG_SYS_GENERIC_BOARD + +#define CONFIG_REMAKE_ELF + +#define CONFIG_SUPPORT_RAW_INITRD + +/* Cache Definitions */ +#define CONFIG_SYS_DCACHE_OFF +#define CONFIG_SYS_ICACHE_OFF + +#define CONFIG_IDENT_STRING " hikey_aemv8a" +#define CONFIG_BOOTP_VCI_STRING "U-boot.armv8.hikey_aemv8a" + +/* Flat Device Tree Definitions */ +#define CONFIG_OF_LIBFDT + +/* Physical Memory Map */ + +#define CONFIG_SYS_TEXT_BASE 0x37000000 +/* RAM debug builds */ +/*#define CONFIG_SYS_TEXT_BASE 0x27000000*/ + +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 0x00000000 +#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1024 MB */ +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 + +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 + +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) + +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x8000) +#define LINUX_BOOT_PARAM_ADDR (CONFIG_SYS_SDRAM_BASE + 0x2000) + +/* Generic Timer Definitions */ +#define COUNTER_FREQUENCY (0x1300000) /* 19MHz */ + +/* Generic Interrupt Controller Definitions */ +#define GICD_BASE (0xf6801000) +#define GICC_BASE (0xf6802000) + +#define CONFIG_SYS_MEMTEST_START V2M_BASE +#define CONFIG_SYS_MEMTEST_END (V2M_BASE + 0x40000000) + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (8 << 20)) + +/* PL011 Serial Configuration */ +#define CONFIG_PL011_SERIAL + +#define CONFIG_PL011_CLOCK 19200000 +#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0} +#define CONFIG_CONS_INDEX 0 + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_SERIAL0 0xF8015000 + +#define CONFIG_CMD_USB +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_DWC2 +#define CONFIG_USB_DWC2_REG_ADDR 0xF72C0000 +/*#define CONFIG_DWC2_DFLT_SPEED_FULL*/ +#define CONFIG_DWC2_ENABLE_DYNAMIC_FIFO + +#define CONFIG_USB_STORAGE +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_SMSC95XX +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_MISC_INIT_R +#endif + +#define CONFIG_HIKEY_GPIO +#define CONFIG_DM_GPIO +#define CONFIG_CMD_GPIO +#define CONFIG_DM + +/* SD/MMC configuration */ +#define CONFIG_GENERIC_MMC +#define CONFIG_MMC +#define CONFIG_DWMMC +#define CONFIG_HIKEY_DWMMC +#define CONFIG_BOUNCE_BUFFER +#define CONFIG_CMD_MMC + +#define CONFIG_FS_EXT4 +#define CONFIG_FS_FAT + +/* Command line configuration */ +#define CONFIG_MENU +/*#define CONFIG_MENU_SHOW*/ +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_BDI +#define CONFIG_CMD_BOOTI +#define CONFIG_CMD_UNZIP +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PXE +#define CONFIG_CMD_ENV +#define CONFIG_CMD_IMI +#define CONFIG_CMD_LOADB +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_CMD_PING +#define CONFIG_CMD_SAVEENV +#define CONFIG_CMD_RUN +#define CONFIG_CMD_BOOTD +#define CONFIG_CMD_ECHO +#define CONFIG_CMD_SOURCE +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_FS_GENERIC + +#define CONFIG_DOS_PARTITION +#define CONFIG_EFI_PARTITION +#define CONFIG_MAC_PARTITION +#define CONFIG_MTD_PARTITIONS + +/* BOOTP options */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_PXE +#define CONFIG_BOOTP_PXE_CLIENTARCH 0x100 + +/* Initial environment variables */ + +/* + * Defines where the kernel and FDT exist in NOR flash and where it will + * be copied into DRAM + */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "kernel_name=Image\0" \ + "kernel_addr=0x0000000\0" \ + "fdt_name=hi6220-hikey.dtb\0" \ + "fdt_addr=0x0300000\0" \ + "max_fdt=0x100000\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "initrd_high=0xffffffffffffffff\0" \ + +/* Assume we boot with root on the first partition of a USB stick */ +#define CONFIG_BOOTARGS "console=ttyAMA0,115200n8 /dev/mmcblk0p7 rw " + +/* Copy the kernel and FDT to DRAM memory and boot */ +#define CONFIG_BOOTCOMMAND "booti $kernel_addr_r - $fdt_addr_r" + +#define CONFIG_BOOTDELAY 2 + +/* Preserve enviroment onto sd card */ +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 1 +#define CONFIG_SYS_MMC_ENV_PART 0 +#define CONFIG_ENV_OFFSET 0x0 +#define CONFIG_ENV_SIZE 0x1000 +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT + +/* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PROMPT "HiKey64# " +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_LONGHELP +#define CONFIG_CMDLINE_EDITING +#define CONFIG_SYS_MAXARGS 64 /* max command args */ + +#define CONFIG_SYS_NO_FLASH + +#endif /* __HIKEY_AEMV8A_H */
On Tue, May 12, 2015 at 8:25 AM, Peter Griffin peter.griffin@linaro.org wrote:
HiKey is the first 96boards consumer edition compliant board. It features a hi6220 SoC which has eight ARM A53 cpu's.
This initial port adds support for: -
- Serial
- eMMC / sd card
- USB
- GPIO
It has been tested with Arm Trusted Firmware running u-boot as the BL33 executable.
Notes:
eMMC has been tested with basic reading of eMMC partition intto DDR. I have not tested writing / erasing. I suspect due to lack of clock control it won't be running in the most performant high speed mode.
SD card slot has been tested for reading and booting kernels into DDR. It is also currently used for saving the u-boot enviroment.
USB has been tested with ASIX networking adapter to tftpboot kernels into DDR. USB mass storage device enumeration doesn't currently work for an unkown reason.
GPIO has been tested using gpio toggle GPIO4_1-3 to flash LEDs.
Basic SoC datasheet can be found here: - https://github.com/96boards/documentation/blob/master/hikey/ Hi6220V100_Multi-Mode_Application_Processor_Function_Description.pdf
Board schematic can be found here: - https://github.com/96boards/documentation/blob/master/hikey/ 96Boards-Hikey-Rev-A1.pdf
Signed-off-by: Peter Griffin peter.griffin@linaro.org
arch/arm/Kconfig | 5 + board/96boards/hikey64/Kconfig | 12 ++ board/96boards/hikey64/Makefile | 8 + board/96boards/hikey64/hikey.c | 439 ++++++++++++++++++++++++++++++++++++++++
This is more likely to have common parts with other HiSi boards than other 96boards compliant boards.
configs/hikey_aemv8a_defconfig | 5 + include/configs/hikey_aemv8a.h | 187 +++++++++++++++++
aemv8a seems to be leftover from VExpress. Just hikey should be enough.
6 files changed, 656 insertions(+) create mode 100644 board/96boards/hikey64/Kconfig create mode 100644 board/96boards/hikey64/Makefile create mode 100644 board/96boards/hikey64/hikey.c create mode 100644 configs/hikey_aemv8a_defconfig create mode 100644 include/configs/hikey_aemv8a.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 7ed0e20..0b6de5d 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -656,6 +656,10 @@ config TARGET_LS2085A_SIMU select ARM64 select ARMV8_MULTIENTRY
+config TARGET_96BOARDS_HIKEY
bool "Support HiKey 96boards Consumer Edition Platform"select ARM64config TARGET_LS1021AQDS bool "Support ls1021aqds" select CPU_V7 @@ -787,6 +791,7 @@ source "board/armadeus/apf27/Kconfig" source "board/armltd/integrator/Kconfig" source "board/armltd/vexpress/Kconfig" source "board/armltd/vexpress64/Kconfig" +source "board/96boards/hikey64/Kconfig" source "board/bachmann/ot1200/Kconfig" source "board/balloon3/Kconfig" source "board/barco/platinum/Kconfig" diff --git a/board/96boards/hikey64/Kconfig b/board/96boards/hikey64/Kconfig new file mode 100644 index 0000000..eb1709b --- /dev/null +++ b/board/96boards/hikey64/Kconfig @@ -0,0 +1,12 @@ +if TARGET_96BOARDS_HIKEY
+config SYS_BOARD
default "hikey64"+config SYS_VENDOR
default "96boards"
96boards doesn't really make boards. This should be CircuitCo or HiSilicon.
+config SYS_CONFIG_NAME
default "hikey_aemv8a"+endif diff --git a/board/96boards/hikey64/Makefile b/board/96boards/hikey64/Makefile new file mode 100644 index 0000000..d4ec8c7 --- /dev/null +++ b/board/96boards/hikey64/Makefile @@ -0,0 +1,8 @@ +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# SPDX-License-Identifier: GPL-2.0+ +#
+obj-y := hikey.o diff --git a/board/96boards/hikey64/hikey.c b/board/96boards/hikey64/hikey.c new file mode 100644 index 0000000..91e8e6b --- /dev/null +++ b/board/96boards/hikey64/hikey.c @@ -0,0 +1,439 @@ +/*
- (C) Copyright 2015 Linaro
- Peter Griffin peter.griffin@linaro.org
- SPDX-License-Identifier: GPL-2.0+
- */
+#include <common.h> +#include <dm.h> +#include <malloc.h> +#include <errno.h> +#include <netdev.h> +#include <asm/io.h> +#include <asm-generic/gpio.h> +#include <asm/arch/gpio.h> +#include <asm/arch/dwmmc.h> +#include <asm/arch/hi6220.h> +#include <asm/arch/hi6553.h>
+#ifdef CONFIG_DM_GPIO +static const struct hikey_gpio_platdata hi6220_gpio[] = {
{ 0, HI6220_GPIO0_BASE},{ 1, HI6220_GPIO1_BASE},{ 2, HI6220_GPIO2_BASE},{ 3, HI6220_GPIO3_BASE},{ 4, HI6220_GPIO4_BASE},{ 5, HI6220_GPIO5_BASE},{ 6, HI6220_GPIO6_BASE},{ 7, HI6220_GPIO7_BASE},{ 8, HI6220_GPIO8_BASE},{ 9, HI6220_GPIO9_BASE},{ 10, HI6220_GPIO10_BASE},{ 11, HI6220_GPIO11_BASE},{ 12, HI6220_GPIO12_BASE},{ 13, HI6220_GPIO13_BASE},{ 14, HI6220_GPIO14_BASE},{ 15, HI6220_GPIO15_BASE},{ 16, HI6220_GPIO16_BASE},{ 17, HI6220_GPIO17_BASE},{ 18, HI6220_GPIO18_BASE},{ 19, HI6220_GPIO19_BASE},+};
+U_BOOT_DEVICES(hi6220_gpios) = {
{ "gpio_hi6220", &hi6220_gpio[0] },{ "gpio_hi6220", &hi6220_gpio[1] },{ "gpio_hi6220", &hi6220_gpio[2] },{ "gpio_hi6220", &hi6220_gpio[3] },{ "gpio_hi6220", &hi6220_gpio[4] },{ "gpio_hi6220", &hi6220_gpio[5] },{ "gpio_hi6220", &hi6220_gpio[6] },{ "gpio_hi6220", &hi6220_gpio[7] },{ "gpio_hi6220", &hi6220_gpio[8] },{ "gpio_hi6220", &hi6220_gpio[9] },{ "gpio_hi6220", &hi6220_gpio[10] },{ "gpio_hi6220", &hi6220_gpio[11] },{ "gpio_hi6220", &hi6220_gpio[12] },{ "gpio_hi6220", &hi6220_gpio[13] },{ "gpio_hi6220", &hi6220_gpio[14] },{ "gpio_hi6220", &hi6220_gpio[15] },{ "gpio_hi6220", &hi6220_gpio[16] },{ "gpio_hi6220", &hi6220_gpio[17] },{ "gpio_hi6220", &hi6220_gpio[18] },{ "gpio_hi6220", &hi6220_gpio[19] },+}; +#endif
+DECLARE_GLOBAL_DATA_PTR;
+#if defined(CONFIG_SHOW_BOOT_PROGRESS) +void show_boot_progress(int progress) +{
printf("Boot reached stage %d\n", progress);
Nothing h/w specific here. I'd remove or make this be the default (weak) implementation.
+} +#endif
+static inline void delay(ulong loops)
udelay/mdelay does not work for you?
+{
__asm__ volatile ("1:\n""subs %0, %1, #1\n""bne 1b" : "=r" (loops) : "0" (loops));+}
+#define EYE_PATTERN 0x70533483
+static void init_usb_and_picophy(void) +{
unsigned int data;/* enable USB clock */writel(PERI_CLK0_USBOTG, PERI_SC_PERIPH_CLK0_EN);do {data = readl(PERI_SC_PERIPH_CLK0_STAT);} while ((data & PERI_CLK0_USBOTG) == 0);/* take usb IPs out of reset */writel(PERI_RST0_USBOTG_BUS | PERI_RST0_POR_PICOPHY |PERI_RST0_USBOTG | PERI_RST0_USBOTG_32K,PERI_SC_PERIPH_RST0_DIS);do {data = readl(PERI_SC_PERIPH_RST0_STAT);data &= PERI_RST0_USBOTG_BUS | PERI_RST0_POR_PICOPHY |PERI_RST0_USBOTG | PERI_RST0_USBOTG_32K;} while (data);/*CTRL 5*/data = readl(PERI_SC_PERIPH_CTRL5);data &= ~PERI_CTRL5_PICOPHY_BC_MODE;data |= PERI_CTRL5_USBOTG_RES_SEL | PERI_CTRL5_PICOPHY_ACAENB;data |= 0x300;writel(data, PERI_SC_PERIPH_CTRL5);/*CTRL 4*//* configure USB PHY */data = readl(PERI_SC_PERIPH_CTRL4);/* make PHY out of low power mode */data &= ~PERI_CTRL4_PICO_SIDDQ;data &= ~PERI_CTRL4_PICO_OGDISABLE;data |= PERI_CTRL4_PICO_VBUSVLDEXTSEL | PERI_CTRL4_PICO_VBUSVLDEXT;writel(data, PERI_SC_PERIPH_CTRL4);writel(EYE_PATTERN, PERI_SC_PERIPH_CTRL8);delay(20000);+}
+static int sd_card_detect(void) +{
int ret;/* configure GPIO8 as nopull */writel(0, 0xf8001830);gpio_request(8, "SD CD");gpio_direction_input(8);ret = gpio_get_value(8);if (!ret) {printf("%s: SD card present\n", __func__);return 1;}printf("%s: SD card not present\n", __func__);return 0;+}
+static void mmc1_setup_pinmux(void) +{
/* switch pinmux to SD */writel(0, 0xf701000c);writel(0, 0xf7010010);writel(0, 0xf7010014);writel(0, 0xf7010018);writel(0, 0xf701001c);writel(0, 0xf7010020);/* input, 16mA or 12mA */writel(0x64, 0xf701080c);writel(0x54, 0xf7010810);writel(0x54, 0xf7010814);writel(0x54, 0xf7010818);writel(0x54, 0xf701081c);writel(0x54, 0xf7010820);sd_card_detect();+}
+static void mmc1_init_pll(void) +{
uint32_t data;/* select SYSPLL as the source of MMC1 *//* select SYSPLL as the source of MUX1 (SC_CLK_SEL0) */writel(1 << 11 | 1 << 27, PERI_SC_CLK0_SEL);do {data = readl(PERI_SC_CLK0_SEL);} while (!(data & (1 << 11)));/* select MUX1 as the source of MUX2 (SC_CLK_SEL0) */writel(1 << 30, PERI_SC_CLK0_SEL);do {data = readl(PERI_SC_CLK0_SEL);} while (data & (1 << 14));writel((1 << 1), PERI_SC_PERIPH_CLK0_EN);do {data = readl(PERI_SC_PERIPH_CLK0_STAT);} while (!(data & (1 << 1)));data = readl(PERI_SC_PERIPH_CLK12_EN);data |= 1 << 2;writel(data, PERI_SC_PERIPH_CLK12_EN);do {/* 1.2GHz / 50 = 24MHz */writel(0x31 | (1 << 7), PERI_SC_CLKCFG8BIT2);data = readl(PERI_SC_CLKCFG8BIT2);} while ((data & 0x31) != 0x31);+}
+static void mmc1_reset_clk(void) +{
unsigned int data;/* disable mmc1 bus clock */writel(PERI_CLK0_MMC1, PERI_SC_PERIPH_CLK0_DIS);do {data = readl(PERI_SC_PERIPH_CLK0_STAT);} while (data & PERI_CLK0_MMC1);/* enable mmc1 bus clock */writel(PERI_CLK0_MMC1, PERI_SC_PERIPH_CLK0_EN);do {data = readl(PERI_SC_PERIPH_CLK0_STAT);} while (!(data & PERI_CLK0_MMC1));/* reset mmc1 clock domain */writel(PERI_RST0_MMC1, PERI_SC_PERIPH_RST0_EN);/* bypass mmc1 clock phase */data = readl(PERI_SC_PERIPH_CTRL2);data |= 3 << 2;writel(data, PERI_SC_PERIPH_CTRL2);/* disable low power */data = readl(PERI_SC_PERIPH_CTRL13);data |= 1 << 4;writel(data, PERI_SC_PERIPH_CTRL13);do {data = readl(PERI_SC_PERIPH_RST0_STAT);} while (!(data & PERI_RST0_MMC1));/* unreset mmc0 clock domain */writel(PERI_RST0_MMC1, PERI_SC_PERIPH_RST0_DIS);do {data = readl(PERI_SC_PERIPH_RST0_STAT);} while (data & PERI_RST0_MMC1);+}
+/* PMU SSI is the IP that maps the external PMU hi6553 registers as IO */ +static void hi6220_pmussi_init(void) +{
uint32_t data;/* Take PMUSSI out of reset */writel(ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_PMUSSI_N,ALWAYSON_SC_PERIPH_RST4_DIS);do {data = readl(ALWAYSON_SC_PERIPH_RST4_STAT);} while (data & ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_PMUSSI_N);/* set PMU SSI clock latency for read operation */data = readl(ALWAYSON_SC_MCU_SUBSYS_CTRL3);data &= ~ALWAYSON_SC_MCU_SUBSYS_CTRL3_RCLK_MASK;data |= ALWAYSON_SC_MCU_SUBSYS_CTRL3_RCLK_3;writel(data, ALWAYSON_SC_MCU_SUBSYS_CTRL3);/* enable PMUSSI clock */data = ALWAYSON_SC_PERIPH_CLK5_EN_PCLK_PMUSSI_CCPU |ALWAYSON_SC_PERIPH_CLK5_EN_PCLK_PMUSSI_MCU;writel(data, ALWAYSON_SC_PERIPH_CLK5_EN);data = ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_PMUSSI;writel(data, ALWAYSON_SC_PERIPH_CLK4_EN);/* Output high to PMIC on PWR_HOLD_GPIO0_0 */gpio_request(0, "PWR_HOLD_GPIO0_0");gpio_direction_output(0, 1);+}
+uint8_t hi6553_readb(unsigned int offset) +{
return readb((u8 *)(unsigned long)HI6220_PMUSSI_BASE + (offset << 2));+}
+void hi6553_writeb(unsigned int offset, uint8_t value) +{
writeb(value, (u8 *)(unsigned long)HI6220_PMUSSI_BASE + (offset << 2));+}
+static void hikey_hi6553_init(void) +{
int data;hi6553_writeb(HI6553_PERI_EN_MARK, 0x1e);hi6553_writeb(HI6553_NP_REG_ADJ1, 0);data = HI6553_DISABLE6_XO_CLK_CONN | HI6553_DISABLE6_XO_CLK_NFC |HI6553_DISABLE6_XO_CLK_RF1 | HI6553_DISABLE6_XO_CLK_RF2;hi6553_writeb(HI6553_DISABLE6_XO_CLK, data);/* configure BUCK0 & BUCK1 */hi6553_writeb(HI6553_BUCK01_CTRL2, 0x5e);hi6553_writeb(HI6553_BUCK0_CTRL7, 0x10);hi6553_writeb(HI6553_BUCK1_CTRL7, 0x10);hi6553_writeb(HI6553_BUCK0_CTRL5, 0x1e);hi6553_writeb(HI6553_BUCK1_CTRL5, 0x1e);hi6553_writeb(HI6553_BUCK0_CTRL1, 0xfc);hi6553_writeb(HI6553_BUCK1_CTRL1, 0xfc);/* configure BUCK2 */hi6553_writeb(HI6553_BUCK2_REG1, 0x4f);hi6553_writeb(HI6553_BUCK2_REG5, 0x99);hi6553_writeb(HI6553_BUCK2_REG6, 0x45);mdelay(1);hi6553_writeb(HI6553_VSET_BUCK2_ADJ, 0x22);mdelay(1);/* configure BUCK3 */hi6553_writeb(HI6553_BUCK3_REG3, 0x02);hi6553_writeb(HI6553_BUCK3_REG5, 0x99);hi6553_writeb(HI6553_BUCK3_REG6, 0x41);hi6553_writeb(HI6553_VSET_BUCK3_ADJ, 0x02);mdelay(1);/* configure BUCK4 */hi6553_writeb(HI6553_BUCK4_REG2, 0x9a);hi6553_writeb(HI6553_BUCK4_REG5, 0x99);hi6553_writeb(HI6553_BUCK4_REG6, 0x45);/* configure LDO20 */hi6553_writeb(HI6553_LDO20_REG_ADJ, 0x50);hi6553_writeb(HI6553_NP_REG_CHG, 0x0f);hi6553_writeb(HI6553_CLK_TOP0, 0x06);hi6553_writeb(HI6553_CLK_TOP3, 0xc0);hi6553_writeb(HI6553_CLK_TOP4, 0x00);/* configure LDO7 & LDO10 for SD slot */data = hi6553_readb(HI6553_LDO7_REG_ADJ);data = (data & 0xf8) | 0x2;hi6553_writeb(HI6553_LDO7_REG_ADJ, data);mdelay(5);/* enable LDO7 */hi6553_writeb(HI6553_ENABLE2_LDO1_8, 1 << 6);mdelay(5);data = hi6553_readb(HI6553_LDO10_REG_ADJ);data = (data & 0xf8) | 0x5;hi6553_writeb(HI6553_LDO10_REG_ADJ, data);mdelay(5);/* enable LDO10 */hi6553_writeb(HI6553_ENABLE3_LDO9_16, 1 << 1);mdelay(5);/* select 32.764KHz */hi6553_writeb(HI6553_CLK19M2_600_586_EN, 0x01);+}
+/*
- Routine: misc_init_r
- Description: A basic misc_init_r
Pretty worthless comments.
- */
+int __weak misc_init_r(void)
Why weak?
+{
init_usb_and_picophy();return 0;+}
+int board_init(void) +{
gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;gd->flags = 0;icache_enable();return 0;+}
+#ifdef CONFIG_GENERIC_MMC
+static int init_dwmmc(void) +{
int ret;+#ifdef CONFIG_DWMMC
Extra blank lines.
/* mmc0 pinmux and clocks are already configured by ATF */ret = hi6220_dwmci_add_port(0, HI6220_MMC0_BASE, 8);if (ret)printf("%s: Error adding eMMC port\n", __func__);/* take mmc1 (sd slot) out of reset, configure clocks and pinmuxing */mmc1_init_pll();mmc1_reset_clk();mmc1_setup_pinmux();ret |= hi6220_dwmci_add_port(1, HI6220_MMC1_BASE, 4);if (ret)printf("%s: Error adding SD port\n", __func__);+#endif
return ret;+}
+int board_mmc_init(bd_t *bis) +{
int ret;/* init the pmussi ip */hi6220_pmussi_init();/* init the hi6553 pmic */hikey_hi6553_init();/* add the eMMC and sd ports */ret = init_dwmmc();if (ret)debug("init_dwmmc failed\n");return ret;+} +#endif
+int dram_init(void) +{
gd->ram_size =get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, PHYS_SDRAM_1_SIZE);return 0;+}
+void dram_init_banksize(void) +{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;gd->bd->bi_dram[0].size =get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);+}
+/* Use the Watchdog to cause reset */ +void reset_cpu(ulong addr) +{
/* TODO program the watchdog */+} diff --git a/configs/hikey_aemv8a_defconfig b/configs/hikey_aemv8a_defconfig new file mode 100644 index 0000000..3bbb2c5 --- /dev/null +++ b/configs/hikey_aemv8a_defconfig @@ -0,0 +1,5 @@ +# 96boards HiKey +CONFIG_ARM=y +CONFIG_TARGET_96BOARDS_HIKEY=y +CONFIG_DEFAULT_DEVICE_TREE="hikey" +CONFIG_SHOW_BOOT_PROGRESS=y diff --git a/include/configs/hikey_aemv8a.h b/include/configs/hikey_aemv8a.h new file mode 100644 index 0000000..7c0012f --- /dev/null +++ b/include/configs/hikey_aemv8a.h @@ -0,0 +1,187 @@ +/*
- (C) Copyright 2015 Linaro
- Peter Griffin peter.griffin@linaro.org
- Configuration for HiKey 96boards CE. Parts were derived from other ARM
- configurations.
- SPDX-License-Identifier: GPL-2.0+
- */
+#ifndef __HIKEY_AEMV8A_H +#define __HIKEY_AEMV8A_H
+/* We use generic board for hikey */ +#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_REMAKE_ELF
+#define CONFIG_SUPPORT_RAW_INITRD
+/* Cache Definitions */ +#define CONFIG_SYS_DCACHE_OFF +#define CONFIG_SYS_ICACHE_OFF
I-cache at least should be simple to enable.
+#define CONFIG_IDENT_STRING " hikey_aemv8a" +#define CONFIG_BOOTP_VCI_STRING "U-boot.armv8.hikey_aemv8a"
+/* Flat Device Tree Definitions */ +#define CONFIG_OF_LIBFDT
+/* Physical Memory Map */
+#define CONFIG_SYS_TEXT_BASE 0x37000000 +/* RAM debug builds */ +/*#define CONFIG_SYS_TEXT_BASE 0x27000000*/
+#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 0x00000000 +#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1024 MB */ +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
+#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x8000)
This is the kernel address? This is ideally 0x80000 for Image files.
+#define LINUX_BOOT_PARAM_ADDR (CONFIG_SYS_SDRAM_BASE + 0x2000)
What is this for?
+/* Generic Timer Definitions */ +#define COUNTER_FREQUENCY (0x1300000) /* 19MHz */
Write as decimal and then you don't need the comment.
+/* Generic Interrupt Controller Definitions */ +#define GICD_BASE (0xf6801000) +#define GICC_BASE (0xf6802000)
+#define CONFIG_SYS_MEMTEST_START V2M_BASE +#define CONFIG_SYS_MEMTEST_END (V2M_BASE + 0x40000000)
V2M is a VExpress thing.
+/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (8 << 20))
Why is this related to CONFIG_ENV_SIZE?
+/* PL011 Serial Configuration */ +#define CONFIG_PL011_SERIAL
+#define CONFIG_PL011_CLOCK 19200000 +#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0} +#define CONFIG_CONS_INDEX 0
+#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_SERIAL0 0xF8015000
+#define CONFIG_CMD_USB +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_DWC2 +#define CONFIG_USB_DWC2_REG_ADDR 0xF72C0000 +/*#define CONFIG_DWC2_DFLT_SPEED_FULL*/ +#define CONFIG_DWC2_ENABLE_DYNAMIC_FIFO
+#define CONFIG_USB_STORAGE +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_SMSC95XX +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_MISC_INIT_R +#endif
+#define CONFIG_HIKEY_GPIO +#define CONFIG_DM_GPIO +#define CONFIG_CMD_GPIO +#define CONFIG_DM
+/* SD/MMC configuration */ +#define CONFIG_GENERIC_MMC +#define CONFIG_MMC +#define CONFIG_DWMMC +#define CONFIG_HIKEY_DWMMC +#define CONFIG_BOUNCE_BUFFER +#define CONFIG_CMD_MMC
+#define CONFIG_FS_EXT4 +#define CONFIG_FS_FAT
+/* Command line configuration */ +#define CONFIG_MENU +/*#define CONFIG_MENU_SHOW*/ +#define CONFIG_CMD_CACHE
But you've disabled caches...
+#define CONFIG_CMD_BDI +#define CONFIG_CMD_BOOTI +#define CONFIG_CMD_UNZIP +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PXE +#define CONFIG_CMD_ENV +#define CONFIG_CMD_IMI +#define CONFIG_CMD_LOADB +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_CMD_PING +#define CONFIG_CMD_SAVEENV +#define CONFIG_CMD_RUN +#define CONFIG_CMD_BOOTD +#define CONFIG_CMD_ECHO +#define CONFIG_CMD_SOURCE +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_FS_GENERIC
+#define CONFIG_DOS_PARTITION +#define CONFIG_EFI_PARTITION +#define CONFIG_MAC_PARTITION +#define CONFIG_MTD_PARTITIONS
Use config_distro_defaults.h and you can drop lots of these.
+/* BOOTP options */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_PXE +#define CONFIG_BOOTP_PXE_CLIENTARCH 0x100
+/* Initial environment variables */
+/*
- Defines where the kernel and FDT exist in NOR flash and where it will
- be copied into DRAM
- */
+#define CONFIG_EXTRA_ENV_SETTINGS \
"kernel_name=Image\0" \"kernel_addr=0x0000000\0" \"fdt_name=hi6220-hikey.dtb\0" \"fdt_addr=0x0300000\0" \"max_fdt=0x100000\0" \"fdt_high=0xffffffffffffffff\0" \"initrd_high=0xffffffffffffffff\0" \+/* Assume we boot with root on the first partition of a USB stick */ +#define CONFIG_BOOTARGS "console=ttyAMA0,115200n8 /dev/mmcblk0p7 rw "
+/* Copy the kernel and FDT to DRAM memory and boot */ +#define CONFIG_BOOTCOMMAND "booti $kernel_addr_r - $fdt_addr_r"
+#define CONFIG_BOOTDELAY 2
+/* Preserve enviroment onto sd card */ +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 1 +#define CONFIG_SYS_MMC_ENV_PART 0 +#define CONFIG_ENV_OFFSET 0x0 +#define CONFIG_ENV_SIZE 0x1000 +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
Looks like a typo here.
+/* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PROMPT "HiKey64# "
Do we really need a custom prompt?
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)+#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_LONGHELP +#define CONFIG_CMDLINE_EDITING +#define CONFIG_SYS_MAXARGS 64 /* max command args */
+#define CONFIG_SYS_NO_FLASH
+#endif /* __HIKEY_AEMV8A_H */
1.9.1
U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Hi Rob,
On 12 May 2015 at 19:29, Rob Herring robherring2@gmail.com wrote:
On Tue, May 12, 2015 at 8:25 AM, Peter Griffin peter.griffin@linaro.org wrote:
HiKey is the first 96boards consumer edition compliant board. It
features a hi6220
SoC which has eight ARM A53 cpu's.
Thanks for reviewing the patches. Also sorry for the long lag in replying to you. I have been a bit busy on other activities recently.
<snip>
arch/arm/Kconfig | 5 + board/96boards/hikey64/Kconfig | 12 ++ board/96boards/hikey64/Makefile | 8 + board/96boards/hikey64/hikey.c | 439
++++++++++++++++++++++++++++++++++++++++
This is more likely to have common parts with other HiSi boards than
other 96boards compliant boards.
OK, I've renamed the directory hisilicon in v2 which seems to match with how other semi vendors have done it e.g. ti, samsung and broadcom
configs/hikey_aemv8a_defconfig | 5 + include/configs/hikey_aemv8a.h | 187 +++++++++++++++++
aemv8a seems to be leftover from VExpress. Just hikey should be enough.
Yes your right, I've removed it in v2
6 files changed, 656 insertions(+) create mode 100644 board/96boards/hikey64/Kconfig create mode 100644 board/96boards/hikey64/Makefile create mode 100644 board/96boards/hikey64/hikey.c create mode 100644 configs/hikey_aemv8a_defconfig create mode 100644 include/configs/hikey_aemv8a.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 7ed0e20..0b6de5d 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -656,6 +656,10 @@ config TARGET_LS2085A_SIMU select ARM64 select ARMV8_MULTIENTRY
+config TARGET_96BOARDS_HIKEY
bool "Support HiKey 96boards Consumer Edition Platform"select ARM64config TARGET_LS1021AQDS bool "Support ls1021aqds" select CPU_V7 @@ -787,6 +791,7 @@ source "board/armadeus/apf27/Kconfig" source "board/armltd/integrator/Kconfig" source "board/armltd/vexpress/Kconfig" source "board/armltd/vexpress64/Kconfig" +source "board/96boards/hikey64/Kconfig" source "board/bachmann/ot1200/Kconfig" source "board/balloon3/Kconfig" source "board/barco/platinum/Kconfig" diff --git a/board/96boards/hikey64/Kconfig
b/board/96boards/hikey64/Kconfig
new file mode 100644 index 0000000..eb1709b --- /dev/null +++ b/board/96boards/hikey64/Kconfig @@ -0,0 +1,12 @@ +if TARGET_96BOARDS_HIKEY
+config SYS_BOARD
default "hikey64"+config SYS_VENDOR
default "96boards"96boards doesn't really make boards. This should be CircuitCo or HiSilicon.
Renamed to be HiSilicon in v2
+config SYS_CONFIG_NAME
default "hikey_aemv8a"+endif diff --git a/board/96boards/hikey64/Makefile
b/board/96boards/hikey64/Makefile
new file mode 100644 index 0000000..d4ec8c7
<snip>
+#endif
+DECLARE_GLOBAL_DATA_PTR;
+#if defined(CONFIG_SHOW_BOOT_PROGRESS) +void show_boot_progress(int progress) +{
printf("Boot reached stage %d\n", progress);Nothing h/w specific here. I'd remove or make this be the default (weak) implementation.
I've removed it in v2
+} +#endif
+static inline void delay(ulong loops)
udelay/mdelay does not work for you?
This was left over from vexpress. I will remove in v2 (after double checking that udelay and mdelay are indeed working properly).
+{
__asm__ volatile ("1:\n""subs %0, %1, #1\n""bne 1b" : "=r" (loops) : "0" (loops));+}
+#define EYE_PATTERN 0x70533483
+static void init_usb_and_picophy(void) +{
unsigned int data;/* enable USB clock */writel(PERI_CLK0_USBOTG, PERI_SC_PERIPH_CLK0_EN);do {data = readl(PERI_SC_PERIPH_CLK0_STAT);} while ((data & PERI_CLK0_USBOTG) == 0);/* take usb IPs out of reset */writel(PERI_RST0_USBOTG_BUS | PERI_RST0_POR_PICOPHY |PERI_RST0_USBOTG | PERI_RST0_USBOTG_32K,PERI_SC_PERIPH_RST0_DIS);do {data = readl(PERI_SC_PERIPH_RST0_STAT);data &= PERI_RST0_USBOTG_BUS | PERI_RST0_POR_PICOPHY |PERI_RST0_USBOTG | PERI_RST0_USBOTG_32K;} while (data);/*CTRL 5*/data = readl(PERI_SC_PERIPH_CTRL5);data &= ~PERI_CTRL5_PICOPHY_BC_MODE;data |= PERI_CTRL5_USBOTG_RES_SEL | PERI_CTRL5_PICOPHY_ACAENB;data |= 0x300;writel(data, PERI_SC_PERIPH_CTRL5);/*CTRL 4*//* configure USB PHY */data = readl(PERI_SC_PERIPH_CTRL4);/* make PHY out of low power mode */data &= ~PERI_CTRL4_PICO_SIDDQ;data &= ~PERI_CTRL4_PICO_OGDISABLE;data |= PERI_CTRL4_PICO_VBUSVLDEXTSEL |
PERI_CTRL4_PICO_VBUSVLDEXT;
writel(data, PERI_SC_PERIPH_CTRL4);writel(EYE_PATTERN, PERI_SC_PERIPH_CTRL8);delay(20000);+}
+static int sd_card_detect(void) +{
int ret;/* configure GPIO8 as nopull */writel(0, 0xf8001830);gpio_request(8, "SD CD");gpio_direction_input(8);ret = gpio_get_value(8);if (!ret) {printf("%s: SD card present\n", __func__);return 1;}printf("%s: SD card not present\n", __func__);return 0;+}
+static void mmc1_setup_pinmux(void) +{
/* switch pinmux to SD */writel(0, 0xf701000c);writel(0, 0xf7010010);writel(0, 0xf7010014);writel(0, 0xf7010018);writel(0, 0xf701001c);writel(0, 0xf7010020);/* input, 16mA or 12mA */writel(0x64, 0xf701080c);writel(0x54, 0xf7010810);writel(0x54, 0xf7010814);writel(0x54, 0xf7010818);writel(0x54, 0xf701081c);writel(0x54, 0xf7010820);sd_card_detect();+}
+static void mmc1_init_pll(void) +{
uint32_t data;/* select SYSPLL as the source of MMC1 *//* select SYSPLL as the source of MUX1 (SC_CLK_SEL0) */writel(1 << 11 | 1 << 27, PERI_SC_CLK0_SEL);do {data = readl(PERI_SC_CLK0_SEL);} while (!(data & (1 << 11)));/* select MUX1 as the source of MUX2 (SC_CLK_SEL0) */writel(1 << 30, PERI_SC_CLK0_SEL);do {data = readl(PERI_SC_CLK0_SEL);} while (data & (1 << 14));writel((1 << 1), PERI_SC_PERIPH_CLK0_EN);do {data = readl(PERI_SC_PERIPH_CLK0_STAT);} while (!(data & (1 << 1)));data = readl(PERI_SC_PERIPH_CLK12_EN);data |= 1 << 2;writel(data, PERI_SC_PERIPH_CLK12_EN);do {/* 1.2GHz / 50 = 24MHz */writel(0x31 | (1 << 7), PERI_SC_CLKCFG8BIT2);data = readl(PERI_SC_CLKCFG8BIT2);} while ((data & 0x31) != 0x31);+}
+static void mmc1_reset_clk(void) +{
unsigned int data;/* disable mmc1 bus clock */writel(PERI_CLK0_MMC1, PERI_SC_PERIPH_CLK0_DIS);do {data = readl(PERI_SC_PERIPH_CLK0_STAT);} while (data & PERI_CLK0_MMC1);/* enable mmc1 bus clock */writel(PERI_CLK0_MMC1, PERI_SC_PERIPH_CLK0_EN);do {data = readl(PERI_SC_PERIPH_CLK0_STAT);} while (!(data & PERI_CLK0_MMC1));/* reset mmc1 clock domain */writel(PERI_RST0_MMC1, PERI_SC_PERIPH_RST0_EN);/* bypass mmc1 clock phase */data = readl(PERI_SC_PERIPH_CTRL2);data |= 3 << 2;writel(data, PERI_SC_PERIPH_CTRL2);/* disable low power */data = readl(PERI_SC_PERIPH_CTRL13);data |= 1 << 4;writel(data, PERI_SC_PERIPH_CTRL13);do {data = readl(PERI_SC_PERIPH_RST0_STAT);} while (!(data & PERI_RST0_MMC1));/* unreset mmc0 clock domain */writel(PERI_RST0_MMC1, PERI_SC_PERIPH_RST0_DIS);do {data = readl(PERI_SC_PERIPH_RST0_STAT);} while (data & PERI_RST0_MMC1);+}
+/* PMU SSI is the IP that maps the external PMU hi6553 registers as IO */ +static void hi6220_pmussi_init(void) +{
uint32_t data;/* Take PMUSSI out of reset */writel(ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_PMUSSI_N,ALWAYSON_SC_PERIPH_RST4_DIS);do {data = readl(ALWAYSON_SC_PERIPH_RST4_STAT);} while (data & ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_PMUSSI_N);/* set PMU SSI clock latency for read operation */data = readl(ALWAYSON_SC_MCU_SUBSYS_CTRL3);data &= ~ALWAYSON_SC_MCU_SUBSYS_CTRL3_RCLK_MASK;data |= ALWAYSON_SC_MCU_SUBSYS_CTRL3_RCLK_3;writel(data, ALWAYSON_SC_MCU_SUBSYS_CTRL3);/* enable PMUSSI clock */data = ALWAYSON_SC_PERIPH_CLK5_EN_PCLK_PMUSSI_CCPU |ALWAYSON_SC_PERIPH_CLK5_EN_PCLK_PMUSSI_MCU;writel(data, ALWAYSON_SC_PERIPH_CLK5_EN);data = ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_PMUSSI;writel(data, ALWAYSON_SC_PERIPH_CLK4_EN);/* Output high to PMIC on PWR_HOLD_GPIO0_0 */gpio_request(0, "PWR_HOLD_GPIO0_0");gpio_direction_output(0, 1);+}
+uint8_t hi6553_readb(unsigned int offset) +{
return readb((u8 *)(unsigned long)HI6220_PMUSSI_BASE + (offset <<
2));
+}
+void hi6553_writeb(unsigned int offset, uint8_t value) +{
writeb(value, (u8 *)(unsigned long)HI6220_PMUSSI_BASE + (offset
<< 2));
+}
+static void hikey_hi6553_init(void) +{
int data;hi6553_writeb(HI6553_PERI_EN_MARK, 0x1e);hi6553_writeb(HI6553_NP_REG_ADJ1, 0);data = HI6553_DISABLE6_XO_CLK_CONN | HI6553_DISABLE6_XO_CLK_NFC |HI6553_DISABLE6_XO_CLK_RF1 | HI6553_DISABLE6_XO_CLK_RF2;hi6553_writeb(HI6553_DISABLE6_XO_CLK, data);/* configure BUCK0 & BUCK1 */hi6553_writeb(HI6553_BUCK01_CTRL2, 0x5e);hi6553_writeb(HI6553_BUCK0_CTRL7, 0x10);hi6553_writeb(HI6553_BUCK1_CTRL7, 0x10);hi6553_writeb(HI6553_BUCK0_CTRL5, 0x1e);hi6553_writeb(HI6553_BUCK1_CTRL5, 0x1e);hi6553_writeb(HI6553_BUCK0_CTRL1, 0xfc);hi6553_writeb(HI6553_BUCK1_CTRL1, 0xfc);/* configure BUCK2 */hi6553_writeb(HI6553_BUCK2_REG1, 0x4f);hi6553_writeb(HI6553_BUCK2_REG5, 0x99);hi6553_writeb(HI6553_BUCK2_REG6, 0x45);mdelay(1);hi6553_writeb(HI6553_VSET_BUCK2_ADJ, 0x22);mdelay(1);/* configure BUCK3 */hi6553_writeb(HI6553_BUCK3_REG3, 0x02);hi6553_writeb(HI6553_BUCK3_REG5, 0x99);hi6553_writeb(HI6553_BUCK3_REG6, 0x41);hi6553_writeb(HI6553_VSET_BUCK3_ADJ, 0x02);mdelay(1);/* configure BUCK4 */hi6553_writeb(HI6553_BUCK4_REG2, 0x9a);hi6553_writeb(HI6553_BUCK4_REG5, 0x99);hi6553_writeb(HI6553_BUCK4_REG6, 0x45);/* configure LDO20 */hi6553_writeb(HI6553_LDO20_REG_ADJ, 0x50);hi6553_writeb(HI6553_NP_REG_CHG, 0x0f);hi6553_writeb(HI6553_CLK_TOP0, 0x06);hi6553_writeb(HI6553_CLK_TOP3, 0xc0);hi6553_writeb(HI6553_CLK_TOP4, 0x00);/* configure LDO7 & LDO10 for SD slot */data = hi6553_readb(HI6553_LDO7_REG_ADJ);data = (data & 0xf8) | 0x2;hi6553_writeb(HI6553_LDO7_REG_ADJ, data);mdelay(5);/* enable LDO7 */hi6553_writeb(HI6553_ENABLE2_LDO1_8, 1 << 6);mdelay(5);data = hi6553_readb(HI6553_LDO10_REG_ADJ);data = (data & 0xf8) | 0x5;hi6553_writeb(HI6553_LDO10_REG_ADJ, data);mdelay(5);/* enable LDO10 */hi6553_writeb(HI6553_ENABLE3_LDO9_16, 1 << 1);mdelay(5);/* select 32.764KHz */hi6553_writeb(HI6553_CLK19M2_600_586_EN, 0x01);+}
+/*
- Routine: misc_init_r
- Description: A basic misc_init_r
Pretty worthless comments.
OK, removed in v2
- */
+int __weak misc_init_r(void)
Why weak?
It shouldn't have been weak, __weak removed in v2
+{
init_usb_and_picophy();return 0;+}
+int board_init(void) +{
gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;gd->flags = 0;icache_enable();return 0;+}
+#ifdef CONFIG_GENERIC_MMC
+static int init_dwmmc(void) +{
int ret;+#ifdef CONFIG_DWMMC
Extra blank lines.
Removed in v2
/* mmc0 pinmux and clocks are already configured by ATF */ret = hi6220_dwmci_add_port(0, HI6220_MMC0_BASE, 8);if (ret)printf("%s: Error adding eMMC port\n", __func__);/* take mmc1 (sd slot) out of reset, configure clocks andpinmuxing */
mmc1_init_pll();mmc1_reset_clk();mmc1_setup_pinmux();ret |= hi6220_dwmci_add_port(1, HI6220_MMC1_BASE, 4);if (ret)printf("%s: Error adding SD port\n", __func__);+#endif
return ret;+}
+int board_mmc_init(bd_t *bis) +{
int ret;/* init the pmussi ip */hi6220_pmussi_init();/* init the hi6553 pmic */hikey_hi6553_init();/* add the eMMC and sd ports */ret = init_dwmmc();if (ret)debug("init_dwmmc failed\n");return ret;+} +#endif
+int dram_init(void) +{
gd->ram_size =get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,PHYS_SDRAM_1_SIZE);
return 0;+}
+void dram_init_banksize(void) +{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;gd->bd->bi_dram[0].size =get_ram_size((long *)PHYS_SDRAM_1,PHYS_SDRAM_1_SIZE);
+}
+/* Use the Watchdog to cause reset */ +void reset_cpu(ulong addr) +{
/* TODO program the watchdog */+} diff --git a/configs/hikey_aemv8a_defconfig
b/configs/hikey_aemv8a_defconfig
new file mode 100644 index 0000000..3bbb2c5 --- /dev/null +++ b/configs/hikey_aemv8a_defconfig @@ -0,0 +1,5 @@ +# 96boards HiKey +CONFIG_ARM=y +CONFIG_TARGET_96BOARDS_HIKEY=y +CONFIG_DEFAULT_DEVICE_TREE="hikey" +CONFIG_SHOW_BOOT_PROGRESS=y diff --git a/include/configs/hikey_aemv8a.h
b/include/configs/hikey_aemv8a.h
new file mode 100644 index 0000000..7c0012f --- /dev/null +++ b/include/configs/hikey_aemv8a.h @@ -0,0 +1,187 @@ +/*
- (C) Copyright 2015 Linaro
- Peter Griffin peter.griffin@linaro.org
- Configuration for HiKey 96boards CE. Parts were derived from other
ARM
- configurations.
- SPDX-License-Identifier: GPL-2.0+
- */
+#ifndef __HIKEY_AEMV8A_H +#define __HIKEY_AEMV8A_H
+/* We use generic board for hikey */ +#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_REMAKE_ELF
+#define CONFIG_SUPPORT_RAW_INITRD
+/* Cache Definitions */ +#define CONFIG_SYS_DCACHE_OFF +#define CONFIG_SYS_ICACHE_OFF
I-cache at least should be simple to enable.
Good spot. I will try enabling both dcache and icache, and if it works will have it enabled in v2.
+#define CONFIG_IDENT_STRING " hikey_aemv8a" +#define CONFIG_BOOTP_VCI_STRING
"U-boot.armv8.hikey_aemv8a"
+/* Flat Device Tree Definitions */ +#define CONFIG_OF_LIBFDT
+/* Physical Memory Map */
+#define CONFIG_SYS_TEXT_BASE 0x37000000 +/* RAM debug builds */ +/*#define CONFIG_SYS_TEXT_BASE 0x27000000*/
+#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 0x00000000 +#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1024 MB */ +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE +
0x7fff0)
+#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x8000)
This is the kernel address? This is ideally 0x80000 for Image files.
Yes it is the default kernel load address. I can update to 0x80000 in v2. Just for my own curiosity what is special about 0x80000?
+#define LINUX_BOOT_PARAM_ADDR (CONFIG_SYS_SDRAM_BASE + 0x2000)
What is this for?
This is assigned to bi_boot_params, which is used by the bootm function for armv7. However on armv8 it appears not to be used so I think it can be removed.
+/* Generic Timer Definitions */ +#define COUNTER_FREQUENCY (0x1300000) /* 19MHz */
Write as decimal and then you don't need the comment.
OK, will fix in v2
+/* Generic Interrupt Controller Definitions */ +#define GICD_BASE (0xf6801000) +#define GICC_BASE (0xf6802000)
+#define CONFIG_SYS_MEMTEST_START V2M_BASE +#define CONFIG_SYS_MEMTEST_END (V2M_BASE + 0x40000000)
V2M is a VExpress thing.
Yes your right, I will remove in v2
+/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (8 << 20))
Why is this related to CONFIG_ENV_SIZE?
I will confess this is left over from vexpress. However judging by the number of other boards which declare CONFIG_SYS_MALLOC_LEN to be CONFIG_ENV_SIZE plus some additional memory. I can only assume that there must be a command or build configuration which requires the enviroment to be malloc'ed.
git grep CONFIG_SYS_MALLOC_LEN | grep CONFIG_ENV_SIZE | wc -l 78
Either that or there has been a lot of copy and paste, and your the first to notice ;-)
+/* PL011 Serial Configuration */ +#define CONFIG_PL011_SERIAL
+#define CONFIG_PL011_CLOCK 19200000 +#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0} +#define CONFIG_CONS_INDEX 0
+#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_SERIAL0 0xF8015000
+#define CONFIG_CMD_USB +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_DWC2 +#define CONFIG_USB_DWC2_REG_ADDR 0xF72C0000 +/*#define CONFIG_DWC2_DFLT_SPEED_FULL*/ +#define CONFIG_DWC2_ENABLE_DYNAMIC_FIFO
+#define CONFIG_USB_STORAGE +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_SMSC95XX +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_MISC_INIT_R +#endif
+#define CONFIG_HIKEY_GPIO +#define CONFIG_DM_GPIO +#define CONFIG_CMD_GPIO +#define CONFIG_DM
+/* SD/MMC configuration */ +#define CONFIG_GENERIC_MMC +#define CONFIG_MMC +#define CONFIG_DWMMC +#define CONFIG_HIKEY_DWMMC +#define CONFIG_BOUNCE_BUFFER +#define CONFIG_CMD_MMC
+#define CONFIG_FS_EXT4 +#define CONFIG_FS_FAT
+/* Command line configuration */ +#define CONFIG_MENU +/*#define CONFIG_MENU_SHOW*/ +#define CONFIG_CMD_CACHE
But you've disabled caches...
As mentioned above I will try enabling caches for V2
+#define CONFIG_CMD_BDI +#define CONFIG_CMD_BOOTI +#define CONFIG_CMD_UNZIP +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PXE +#define CONFIG_CMD_ENV +#define CONFIG_CMD_IMI +#define CONFIG_CMD_LOADB +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_CMD_PING +#define CONFIG_CMD_SAVEENV +#define CONFIG_CMD_RUN +#define CONFIG_CMD_BOOTD +#define CONFIG_CMD_ECHO +#define CONFIG_CMD_SOURCE +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_FS_GENERIC
+#define CONFIG_DOS_PARTITION +#define CONFIG_EFI_PARTITION +#define CONFIG_MAC_PARTITION +#define CONFIG_MTD_PARTITIONS
Use config_distro_defaults.h and you can drop lots of these.
OK thanks, I wasn't aware of that I will look at using config_distro_defaults.h for V2.
+/* BOOTP options */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_PXE +#define CONFIG_BOOTP_PXE_CLIENTARCH 0x100
+/* Initial environment variables */
+/*
- Defines where the kernel and FDT exist in NOR flash and where it will
- be copied into DRAM
- */
+#define CONFIG_EXTRA_ENV_SETTINGS \
"kernel_name=Image\0" \"kernel_addr=0x0000000\0" \"fdt_name=hi6220-hikey.dtb\0" \"fdt_addr=0x0300000\0" \"max_fdt=0x100000\0" \"fdt_high=0xffffffffffffffff\0" \"initrd_high=0xffffffffffffffff\0" \+/* Assume we boot with root on the first partition of a USB stick */ +#define CONFIG_BOOTARGS "console=ttyAMA0,115200n8
/dev/mmcblk0p7 rw "
+/* Copy the kernel and FDT to DRAM memory and boot */ +#define CONFIG_BOOTCOMMAND "booti $kernel_addr_r - $fdt_addr_r"
+#define CONFIG_BOOTDELAY 2
+/* Preserve enviroment onto sd card */ +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 1 +#define CONFIG_SYS_MMC_ENV_PART 0 +#define CONFIG_ENV_OFFSET 0x0 +#define CONFIG_ENV_SIZE 0x1000 +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET +
CONFIG_ENV_SIZE)
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
Looks like a typo here.
Surprisingly not, that is just what it is called.
+/* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer
Size */
+#define CONFIG_SYS_PROMPT "HiKey64# "
Do we really need a custom prompt?
No I guess not. It did bring a smile to my face the first time u-boot booted on HiKey though :-) I will remove it in V2.
regards,
Peter.
Hi Peter,
On 12 May 2015 at 07:25, Peter Griffin peter.griffin@linaro.org wrote:
HiKey is the first 96boards consumer edition compliant board. It features a hi6220 SoC which has eight ARM A53 cpu's.
This initial port adds support for: -
- Serial
- eMMC / sd card
- USB
- GPIO
It has been tested with Arm Trusted Firmware running u-boot as the BL33 executable.
Are there instructions somewhere on how to do this? Perhaps add a README with details or a few links?
Notes:
eMMC has been tested with basic reading of eMMC partition intto DDR. I have not tested writing / erasing. I suspect due to lack of clock control it won't be running in the most performant high speed mode.
SD card slot has been tested for reading and booting kernels into DDR. It is also currently used for saving the u-boot enviroment.
USB has been tested with ASIX networking adapter to tftpboot kernels into DDR. USB mass storage device enumeration doesn't currently work for an unkown reason.
GPIO has been tested using gpio toggle GPIO4_1-3 to flash LEDs.
Basic SoC datasheet can be found here: - https://github.com/96boards/documentation/blob/master/hikey/ Hi6220V100_Multi-Mode_Application_Processor_Function_Description.pdf
Board schematic can be found here: - https://github.com/96boards/documentation/blob/master/hikey/ 96Boards-Hikey-Rev-A1.pdf
Signed-off-by: Peter Griffin peter.griffin@linaro.org
arch/arm/Kconfig | 5 + board/96boards/hikey64/Kconfig | 12 ++ board/96boards/hikey64/Makefile | 8 + board/96boards/hikey64/hikey.c | 439 ++++++++++++++++++++++++++++++++++++++++ configs/hikey_aemv8a_defconfig | 5 + include/configs/hikey_aemv8a.h | 187 +++++++++++++++++ 6 files changed, 656 insertions(+) create mode 100644 board/96boards/hikey64/Kconfig create mode 100644 board/96boards/hikey64/Makefile create mode 100644 board/96boards/hikey64/hikey.c create mode 100644 configs/hikey_aemv8a_defconfig create mode 100644 include/configs/hikey_aemv8a.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 7ed0e20..0b6de5d 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -656,6 +656,10 @@ config TARGET_LS2085A_SIMU select ARM64 select ARMV8_MULTIENTRY
+config TARGET_96BOARDS_HIKEY
bool "Support HiKey 96boards Consumer Edition Platform"select ARM64config TARGET_LS1021AQDS bool "Support ls1021aqds" select CPU_V7 @@ -787,6 +791,7 @@ source "board/armadeus/apf27/Kconfig" source "board/armltd/integrator/Kconfig" source "board/armltd/vexpress/Kconfig" source "board/armltd/vexpress64/Kconfig" +source "board/96boards/hikey64/Kconfig" source "board/bachmann/ot1200/Kconfig" source "board/balloon3/Kconfig" source "board/barco/platinum/Kconfig" diff --git a/board/96boards/hikey64/Kconfig b/board/96boards/hikey64/Kconfig new file mode 100644 index 0000000..eb1709b --- /dev/null +++ b/board/96boards/hikey64/Kconfig @@ -0,0 +1,12 @@ +if TARGET_96BOARDS_HIKEY
+config SYS_BOARD
default "hikey64"+config SYS_VENDOR
default "96boards"+config SYS_CONFIG_NAME
default "hikey_aemv8a"+endif diff --git a/board/96boards/hikey64/Makefile b/board/96boards/hikey64/Makefile new file mode 100644 index 0000000..d4ec8c7 --- /dev/null +++ b/board/96boards/hikey64/Makefile @@ -0,0 +1,8 @@ +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# SPDX-License-Identifier: GPL-2.0+ +#
+obj-y := hikey.o diff --git a/board/96boards/hikey64/hikey.c b/board/96boards/hikey64/hikey.c new file mode 100644 index 0000000..91e8e6b --- /dev/null +++ b/board/96boards/hikey64/hikey.c @@ -0,0 +1,439 @@ +/*
- (C) Copyright 2015 Linaro
- Peter Griffin peter.griffin@linaro.org
- SPDX-License-Identifier: GPL-2.0+
- */
+#include <common.h> +#include <dm.h> +#include <malloc.h> +#include <errno.h> +#include <netdev.h> +#include <asm/io.h> +#include <asm-generic/gpio.h> +#include <asm/arch/gpio.h> +#include <asm/arch/dwmmc.h> +#include <asm/arch/hi6220.h> +#include <asm/arch/hi6553.h>
+#ifdef CONFIG_DM_GPIO +static const struct hikey_gpio_platdata hi6220_gpio[] = {
{ 0, HI6220_GPIO0_BASE},{ 1, HI6220_GPIO1_BASE},{ 2, HI6220_GPIO2_BASE},{ 3, HI6220_GPIO3_BASE},{ 4, HI6220_GPIO4_BASE},{ 5, HI6220_GPIO5_BASE},{ 6, HI6220_GPIO6_BASE},{ 7, HI6220_GPIO7_BASE},{ 8, HI6220_GPIO8_BASE},{ 9, HI6220_GPIO9_BASE},{ 10, HI6220_GPIO10_BASE},{ 11, HI6220_GPIO11_BASE},{ 12, HI6220_GPIO12_BASE},{ 13, HI6220_GPIO13_BASE},{ 14, HI6220_GPIO14_BASE},{ 15, HI6220_GPIO15_BASE},{ 16, HI6220_GPIO16_BASE},{ 17, HI6220_GPIO17_BASE},{ 18, HI6220_GPIO18_BASE},{ 19, HI6220_GPIO19_BASE},+};
+U_BOOT_DEVICES(hi6220_gpios) = {
{ "gpio_hi6220", &hi6220_gpio[0] },{ "gpio_hi6220", &hi6220_gpio[1] },{ "gpio_hi6220", &hi6220_gpio[2] },{ "gpio_hi6220", &hi6220_gpio[3] },{ "gpio_hi6220", &hi6220_gpio[4] },{ "gpio_hi6220", &hi6220_gpio[5] },{ "gpio_hi6220", &hi6220_gpio[6] },{ "gpio_hi6220", &hi6220_gpio[7] },{ "gpio_hi6220", &hi6220_gpio[8] },{ "gpio_hi6220", &hi6220_gpio[9] },{ "gpio_hi6220", &hi6220_gpio[10] },{ "gpio_hi6220", &hi6220_gpio[11] },{ "gpio_hi6220", &hi6220_gpio[12] },{ "gpio_hi6220", &hi6220_gpio[13] },{ "gpio_hi6220", &hi6220_gpio[14] },{ "gpio_hi6220", &hi6220_gpio[15] },{ "gpio_hi6220", &hi6220_gpio[16] },{ "gpio_hi6220", &hi6220_gpio[17] },{ "gpio_hi6220", &hi6220_gpio[18] },{ "gpio_hi6220", &hi6220_gpio[19] },+}; +#endif
Can we use device tree for this board? I have just received one so if you don't have the time for this I could give it a try (once I figure out how to get U-Boot onto the board).
Also, do you know anything about the SDRAM controller? I don't see mention of it in the docs and we would need it to create an SPL for this board.
[snip]
Regards, Simon
Hi Simon,
It has been tested with Arm Trusted Firmware running u-boot as the BL33
executable.
Are there instructions somewhere on how to do this? Perhaps add a README with details or a few links?
There are some slightly old instructions here http://people.linaro.org/~peter.griffin/hikey/hikey-u-boot-release_r1/u-boot...
Are there instructions somewhere on how to do this? Perhaps add a README with details or a few links?
Yes good idea, I will include a README with the v2 patchset which includes some of this info.
Notes:
eMMC has been tested with basic reading of eMMC partition intto DDR. I
have not
tested writing / erasing. I suspect due to lack of clock control it
won't be
running in the most performant high speed mode.
SD card slot has been tested for reading and booting kernels into DDR. It is also currently used for saving the u-boot enviroment.
USB has been tested with ASIX networking adapter to tftpboot kernels into DDR. USB mass storage device enumeration doesn't currently work for an unkown reason.
GPIO has been tested using gpio toggle GPIO4_1-3 to flash LEDs.
Basic SoC datasheet can be found here: - https://github.com/96boards/documentation/blob/master/hikey/ Hi6220V100_Multi-Mode_Application_Processor_Function_Description.pdf
Board schematic can be found here: - https://github.com/96boards/documentation/blob/master/hikey/ 96Boards-Hikey-Rev-A1.pdf
Signed-off-by: Peter Griffin peter.griffin@linaro.org
arch/arm/Kconfig | 5 + board/96boards/hikey64/Kconfig | 12 ++ board/96boards/hikey64/Makefile | 8 + board/96boards/hikey64/hikey.c | 439
++++++++++++++++++++++++++++++++++++++++
configs/hikey_aemv8a_defconfig | 5 + include/configs/hikey_aemv8a.h | 187 +++++++++++++++++ 6 files changed, 656 insertions(+) create mode 100644 board/96boards/hikey64/Kconfig create mode 100644 board/96boards/hikey64/Makefile create mode 100644 board/96boards/hikey64/hikey.c create mode 100644 configs/hikey_aemv8a_defconfig create mode 100644 include/configs/hikey_aemv8a.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 7ed0e20..0b6de5d 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -656,6 +656,10 @@ config TARGET_LS2085A_SIMU select ARM64 select ARMV8_MULTIENTRY
+config TARGET_96BOARDS_HIKEY
bool "Support HiKey 96boards Consumer Edition Platform"select ARM64config TARGET_LS1021AQDS bool "Support ls1021aqds" select CPU_V7 @@ -787,6 +791,7 @@ source "board/armadeus/apf27/Kconfig" source "board/armltd/integrator/Kconfig" source "board/armltd/vexpress/Kconfig" source "board/armltd/vexpress64/Kconfig" +source "board/96boards/hikey64/Kconfig" source "board/bachmann/ot1200/Kconfig" source "board/balloon3/Kconfig" source "board/barco/platinum/Kconfig" diff --git a/board/96boards/hikey64/Kconfig
b/board/96boards/hikey64/Kconfig
new file mode 100644 index 0000000..eb1709b --- /dev/null +++ b/board/96boards/hikey64/Kconfig @@ -0,0 +1,12 @@ +if TARGET_96BOARDS_HIKEY
+config SYS_BOARD
default "hikey64"+config SYS_VENDOR
default "96boards"+config SYS_CONFIG_NAME
default "hikey_aemv8a"+endif diff --git a/board/96boards/hikey64/Makefile
b/board/96boards/hikey64/Makefile
new file mode 100644 index 0000000..d4ec8c7 --- /dev/null +++ b/board/96boards/hikey64/Makefile @@ -0,0 +1,8 @@ +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# SPDX-License-Identifier: GPL-2.0+ +#
+obj-y := hikey.o diff --git a/board/96boards/hikey64/hikey.c
b/board/96boards/hikey64/hikey.c
new file mode 100644 index 0000000..91e8e6b --- /dev/null +++ b/board/96boards/hikey64/hikey.c @@ -0,0 +1,439 @@ +/*
- (C) Copyright 2015 Linaro
- Peter Griffin peter.griffin@linaro.org
- SPDX-License-Identifier: GPL-2.0+
- */
+#include <common.h> +#include <dm.h> +#include <malloc.h> +#include <errno.h> +#include <netdev.h> +#include <asm/io.h> +#include <asm-generic/gpio.h> +#include <asm/arch/gpio.h> +#include <asm/arch/dwmmc.h> +#include <asm/arch/hi6220.h> +#include <asm/arch/hi6553.h>
+#ifdef CONFIG_DM_GPIO +static const struct hikey_gpio_platdata hi6220_gpio[] = {
{ 0, HI6220_GPIO0_BASE},{ 1, HI6220_GPIO1_BASE},{ 2, HI6220_GPIO2_BASE},{ 3, HI6220_GPIO3_BASE},{ 4, HI6220_GPIO4_BASE},{ 5, HI6220_GPIO5_BASE},{ 6, HI6220_GPIO6_BASE},{ 7, HI6220_GPIO7_BASE},{ 8, HI6220_GPIO8_BASE},{ 9, HI6220_GPIO9_BASE},{ 10, HI6220_GPIO10_BASE},{ 11, HI6220_GPIO11_BASE},{ 12, HI6220_GPIO12_BASE},{ 13, HI6220_GPIO13_BASE},{ 14, HI6220_GPIO14_BASE},{ 15, HI6220_GPIO15_BASE},{ 16, HI6220_GPIO16_BASE},{ 17, HI6220_GPIO17_BASE},{ 18, HI6220_GPIO18_BASE},{ 19, HI6220_GPIO19_BASE},+};
+U_BOOT_DEVICES(hi6220_gpios) = {
{ "gpio_hi6220", &hi6220_gpio[0] },{ "gpio_hi6220", &hi6220_gpio[1] },{ "gpio_hi6220", &hi6220_gpio[2] },{ "gpio_hi6220", &hi6220_gpio[3] },{ "gpio_hi6220", &hi6220_gpio[4] },{ "gpio_hi6220", &hi6220_gpio[5] },{ "gpio_hi6220", &hi6220_gpio[6] },{ "gpio_hi6220", &hi6220_gpio[7] },{ "gpio_hi6220", &hi6220_gpio[8] },{ "gpio_hi6220", &hi6220_gpio[9] },{ "gpio_hi6220", &hi6220_gpio[10] },{ "gpio_hi6220", &hi6220_gpio[11] },{ "gpio_hi6220", &hi6220_gpio[12] },{ "gpio_hi6220", &hi6220_gpio[13] },{ "gpio_hi6220", &hi6220_gpio[14] },{ "gpio_hi6220", &hi6220_gpio[15] },{ "gpio_hi6220", &hi6220_gpio[16] },{ "gpio_hi6220", &hi6220_gpio[17] },{ "gpio_hi6220", &hi6220_gpio[18] },{ "gpio_hi6220", &hi6220_gpio[19] },+}; +#endif
Can we use device tree for this board? I have just received one so if you don't have the time for this I could give it a try (once I figure out how to get U-Boot onto the board).
Do you mean using device tree for configuring u-boot? If so that would be a useful addition. If you want to do it then please do :-)
Also, do you know anything about the SDRAM controller? I don't see mention of it in the docs and we would need it to create an SPL for this board.
No I'm afraid not. The datasheet released so far is sadly rather sparse on details.
There is some code in ATF for configuring ddr clocks which could be used as a reference though see arm-trusted-firmware/plat/hikey/pll.c.
regards,
Peter.
Hi Peter,
On 6 July 2015 at 05:50, Peter Griffin peter.griffin@linaro.org wrote:
Hi Simon,
It has been tested with Arm Trusted Firmware running u-boot as the BL33 executable.
Are there instructions somewhere on how to do this? Perhaps add a README with details or a few links?
There are some slightly old instructions here http://people.linaro.org/~peter.griffin/hikey/hikey-u-boot-release_r1/u-boot...
Are there instructions somewhere on how to do this? Perhaps add a README with details or a few links?
Yes good idea, I will include a README with the v2 patchset which includes some of this info.
Notes:
eMMC has been tested with basic reading of eMMC partition intto DDR. I have not tested writing / erasing. I suspect due to lack of clock control it won't be running in the most performant high speed mode.
SD card slot has been tested for reading and booting kernels into DDR. It is also currently used for saving the u-boot enviroment.
USB has been tested with ASIX networking adapter to tftpboot kernels into DDR. USB mass storage device enumeration doesn't currently work for an unkown reason.
GPIO has been tested using gpio toggle GPIO4_1-3 to flash LEDs.
Basic SoC datasheet can be found here: - https://github.com/96boards/documentation/blob/master/hikey/ Hi6220V100_Multi-Mode_Application_Processor_Function_Description.pdf
Board schematic can be found here: - https://github.com/96boards/documentation/blob/master/hikey/ 96Boards-Hikey-Rev-A1.pdf
Signed-off-by: Peter Griffin peter.griffin@linaro.org
arch/arm/Kconfig | 5 + board/96boards/hikey64/Kconfig | 12 ++ board/96boards/hikey64/Makefile | 8 + board/96boards/hikey64/hikey.c | 439 ++++++++++++++++++++++++++++++++++++++++ configs/hikey_aemv8a_defconfig | 5 + include/configs/hikey_aemv8a.h | 187 +++++++++++++++++ 6 files changed, 656 insertions(+) create mode 100644 board/96boards/hikey64/Kconfig create mode 100644 board/96boards/hikey64/Makefile create mode 100644 board/96boards/hikey64/hikey.c create mode 100644 configs/hikey_aemv8a_defconfig create mode 100644 include/configs/hikey_aemv8a.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 7ed0e20..0b6de5d 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -656,6 +656,10 @@ config TARGET_LS2085A_SIMU select ARM64 select ARMV8_MULTIENTRY
+config TARGET_96BOARDS_HIKEY
bool "Support HiKey 96boards Consumer Edition Platform"select ARM64config TARGET_LS1021AQDS bool "Support ls1021aqds" select CPU_V7 @@ -787,6 +791,7 @@ source "board/armadeus/apf27/Kconfig" source "board/armltd/integrator/Kconfig" source "board/armltd/vexpress/Kconfig" source "board/armltd/vexpress64/Kconfig" +source "board/96boards/hikey64/Kconfig" source "board/bachmann/ot1200/Kconfig" source "board/balloon3/Kconfig" source "board/barco/platinum/Kconfig" diff --git a/board/96boards/hikey64/Kconfig b/board/96boards/hikey64/Kconfig new file mode 100644 index 0000000..eb1709b --- /dev/null +++ b/board/96boards/hikey64/Kconfig @@ -0,0 +1,12 @@ +if TARGET_96BOARDS_HIKEY
+config SYS_BOARD
default "hikey64"+config SYS_VENDOR
default "96boards"+config SYS_CONFIG_NAME
default "hikey_aemv8a"+endif diff --git a/board/96boards/hikey64/Makefile b/board/96boards/hikey64/Makefile new file mode 100644 index 0000000..d4ec8c7 --- /dev/null +++ b/board/96boards/hikey64/Makefile @@ -0,0 +1,8 @@ +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# SPDX-License-Identifier: GPL-2.0+ +#
+obj-y := hikey.o diff --git a/board/96boards/hikey64/hikey.c b/board/96boards/hikey64/hikey.c new file mode 100644 index 0000000..91e8e6b --- /dev/null +++ b/board/96boards/hikey64/hikey.c @@ -0,0 +1,439 @@ +/*
- (C) Copyright 2015 Linaro
- Peter Griffin peter.griffin@linaro.org
- SPDX-License-Identifier: GPL-2.0+
- */
+#include <common.h> +#include <dm.h> +#include <malloc.h> +#include <errno.h> +#include <netdev.h> +#include <asm/io.h> +#include <asm-generic/gpio.h> +#include <asm/arch/gpio.h> +#include <asm/arch/dwmmc.h> +#include <asm/arch/hi6220.h> +#include <asm/arch/hi6553.h>
+#ifdef CONFIG_DM_GPIO +static const struct hikey_gpio_platdata hi6220_gpio[] = {
{ 0, HI6220_GPIO0_BASE},{ 1, HI6220_GPIO1_BASE},{ 2, HI6220_GPIO2_BASE},{ 3, HI6220_GPIO3_BASE},{ 4, HI6220_GPIO4_BASE},{ 5, HI6220_GPIO5_BASE},{ 6, HI6220_GPIO6_BASE},{ 7, HI6220_GPIO7_BASE},{ 8, HI6220_GPIO8_BASE},{ 9, HI6220_GPIO9_BASE},{ 10, HI6220_GPIO10_BASE},{ 11, HI6220_GPIO11_BASE},{ 12, HI6220_GPIO12_BASE},{ 13, HI6220_GPIO13_BASE},{ 14, HI6220_GPIO14_BASE},{ 15, HI6220_GPIO15_BASE},{ 16, HI6220_GPIO16_BASE},{ 17, HI6220_GPIO17_BASE},{ 18, HI6220_GPIO18_BASE},{ 19, HI6220_GPIO19_BASE},+};
+U_BOOT_DEVICES(hi6220_gpios) = {
{ "gpio_hi6220", &hi6220_gpio[0] },{ "gpio_hi6220", &hi6220_gpio[1] },{ "gpio_hi6220", &hi6220_gpio[2] },{ "gpio_hi6220", &hi6220_gpio[3] },{ "gpio_hi6220", &hi6220_gpio[4] },{ "gpio_hi6220", &hi6220_gpio[5] },{ "gpio_hi6220", &hi6220_gpio[6] },{ "gpio_hi6220", &hi6220_gpio[7] },{ "gpio_hi6220", &hi6220_gpio[8] },{ "gpio_hi6220", &hi6220_gpio[9] },{ "gpio_hi6220", &hi6220_gpio[10] },{ "gpio_hi6220", &hi6220_gpio[11] },{ "gpio_hi6220", &hi6220_gpio[12] },{ "gpio_hi6220", &hi6220_gpio[13] },{ "gpio_hi6220", &hi6220_gpio[14] },{ "gpio_hi6220", &hi6220_gpio[15] },{ "gpio_hi6220", &hi6220_gpio[16] },{ "gpio_hi6220", &hi6220_gpio[17] },{ "gpio_hi6220", &hi6220_gpio[18] },{ "gpio_hi6220", &hi6220_gpio[19] },+}; +#endif
Can we use device tree for this board? I have just received one so if you don't have the time for this I could give it a try (once I figure out how to get U-Boot onto the board).
Do you mean using device tree for configuring u-boot? If so that would be a useful addition. If you want to do it then please do :-)
OK, I'll wait for your respin and then see if I can get it running.
Also, do you know anything about the SDRAM controller? I don't see mention of it in the docs and we would need it to create an SPL for this board.
No I'm afraid not. The datasheet released so far is sadly rather sparse on details.
There is some code in ATF for configuring ddr clocks which could be used as a reference though see arm-trusted-firmware/plat/hikey/pll.c.
Yes it looks like that has everything. Thanks for the pointer (although I'm not sure I will have the energy to get to that!)
Regards, Simon
participants (3)
-
Peter Griffin -
Rob Herring -
Simon Glass